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authorBen Dooks <ben.dooks@codethink.co.uk>2015-11-18 09:41:15 -0500
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2015-12-13 22:59:48 -0500
commit855ddcab352c15b8c4d0bd93759f821250c601fb (patch)
tree35de613695579da7f57a11b8e09060a84abdfe67 /drivers/tty
parent41788f054920d591c2d44838b73457e9d33ebd2c (diff)
ARM: meson: serial: only disable tx irq on stop
Since disabling the transmit state machine still allows characters to be transmitted when written to the UART write FIFO, simply disable the transmit interrupt when the UART port is stopped. This has not shown an improvement with the console issues when running systemd, but seems like it should be done. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Reported-by: Edward Cragg <ed.cragg@codethink.co.uk> Tested-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/tty')
-rw-r--r--drivers/tty/serial/meson_uart.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/tty/serial/meson_uart.c b/drivers/tty/serial/meson_uart.c
index c7bad2b5aa49..9327efd88918 100644
--- a/drivers/tty/serial/meson_uart.c
+++ b/drivers/tty/serial/meson_uart.c
@@ -110,7 +110,7 @@ static void meson_uart_stop_tx(struct uart_port *port)
110 u32 val; 110 u32 val;
111 111
112 val = readl(port->membase + AML_UART_CONTROL); 112 val = readl(port->membase + AML_UART_CONTROL);
113 val &= ~AML_UART_TX_EN; 113 val &= ~AML_UART_TX_INT_EN;
114 writel(val, port->membase + AML_UART_CONTROL); 114 writel(val, port->membase + AML_UART_CONTROL);
115} 115}
116 116
@@ -133,7 +133,7 @@ static void meson_uart_shutdown(struct uart_port *port)
133 spin_lock_irqsave(&port->lock, flags); 133 spin_lock_irqsave(&port->lock, flags);
134 134
135 val = readl(port->membase + AML_UART_CONTROL); 135 val = readl(port->membase + AML_UART_CONTROL);
136 val &= ~(AML_UART_RX_EN | AML_UART_TX_EN); 136 val &= ~AML_UART_RX_EN;
137 val &= ~(AML_UART_RX_INT_EN | AML_UART_TX_INT_EN); 137 val &= ~(AML_UART_RX_INT_EN | AML_UART_TX_INT_EN);
138 writel(val, port->membase + AML_UART_CONTROL); 138 writel(val, port->membase + AML_UART_CONTROL);
139 139