serial: imx: implement DSR irq handling for DTE mode

Enable reporting of DSR events (which is named DTR in the registers
because Freescale uses the names as seem from a DCE).

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

1 files changed, 17 insertions, 3 deletions

diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 161e9ed768e4..4b38392f4bd6 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -114,6 +114,7 @@
 #define UCR3_RXDSEN     (1<<6)  /* Receive status interrupt enable */
 #define UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
 #define UCR3_AWAKEN     (1<<4)  /* Async wake interrupt enable */
+#define UCR3_DTRDEN     (1<<3)  /* Data Terminal Ready Delta Enable. */
 #define IMX21_UCR3_RXDMUXSEL    (1<<2)  /* RXD Muxed Input Select */
 #define UCR3_INVT       (1<<1)  /* Inverted Infrared transmission */
 #define UCR3_BPEN       (1<<0)  /* Preset registers enable */
@@ -142,7 +143,7 @@
 #define USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
 #define USR1_RRDY       (1<<9)   /* Receiver ready interrupt/dma flag */
 #define USR1_AGTIM      (1<<8)   /* Ageing timer interrupt flag */
-#define USR1_TIMEOUT    (1<<7)   /* Receive timeout interrupt status */
+#define USR1_DTRD       (1<<7)   /* DTR Delta */
 #define USR1_RXDS        (1<<6)  /* Receiver idle interrupt flag */
 #define USR1_AIRINT      (1<<5)  /* Async IR wake interrupt flag */
 #define USR1_AWAKE       (1<<4)  /* Aysnc wake interrupt flag */
@@ -807,6 +808,19 @@ static irqreturn_t imx_int(int irq, void *dev_id)
                 ret = IRQ_HANDLED;
         }
 
+        if (sts & USR1_DTRD) {
+                unsigned long flags;
+
+                if (sts & USR1_DTRD)
+                        writel(USR1_DTRD, sport->port.membase + USR1);
+
+                spin_lock_irqsave(&sport->port.lock, flags);
+                imx_mctrl_check(sport);
+                spin_unlock_irqrestore(&sport->port.lock, flags);
+
+                ret = IRQ_HANDLED;
+        }
+
         if (sts & USR1_RTSD) {
                 imx_rtsint(irq, dev_id);
                 ret = IRQ_HANDLED;
@@ -1205,7 +1219,7 @@ static int imx_startup(struct uart_port *port)
         /*
          * Finally, clear and enable interrupts
          */
-        writel(USR1_RTSD, sport->port.membase + USR1);
+        writel(USR1_RTSD | USR1_DTRD, sport->port.membase + USR1);
         writel(USR2_ORE, sport->port.membase + USR2);
 
         if (sport->dma_is_inited && !sport->dma_is_enabled)
@@ -1245,7 +1259,7 @@ static int imx_startup(struct uart_port *port)
                  * now, too.
                  */
                 temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP |
-                        UCR3_RI | UCR3_DCD;
+                        UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
 
                 if (sport->dte_mode)
                         temp &= ~(UCR3_RI | UCR3_DCD);