Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver updates from Kevin Hilman:
 "Some of these are for drivers/soc, where we're now putting
  SoC-specific drivers these days.  Some are for other driver subsystems
  where we have received acks from the appropriate maintainers.

  Some highlights:

   - simple-mfd: document DT bindings and misc updates
   - migrate mach-berlin to simple-mfd for clock, pinctrl and reset
   - memory: support for Tegra132 SoC
   - memory: introduce tegra EMC driver for scaling memory frequency
   - misc. updates for ARM CCI and CCN busses"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (48 commits)
  drivers: soc: sunxi: Introduce SoC driver to map SRAMs
  arm-cci: Add aliases for PMU events
  arm-cci: Add CCI-500 PMU support
  arm-cci: Sanitise CCI400 PMU driver specific code
  arm-cci: Abstract handling for CCI events
  arm-cci: Abstract out the PMU counter details
  arm-cci: Cleanup PMU driver code
  arm-cci: Do not enable CCI-400 PMU by default
  firmware: qcom: scm: Add HDCP Support
  ARM: berlin: add an ADC node for the BG2Q
  ARM: berlin: remove useless chip and system ctrl compatibles
  clk: berlin: drop direct of_iomap of nodes reg property
  ARM: berlin: move BG2Q clock node
  ARM: berlin: move BG2CD clock node
  ARM: berlin: move BG2 clock node
  clk: berlin: prepare simple-mfd conversion
  pinctrl: berlin: drop SoC stub provided regmap
  ARM: berlin: move pinctrl to simple-mfd nodes
  pinctrl: berlin: prepare to use regmap provided by syscon
  reset: berlin: drop arch_initcall initialization
  ...

9 files changed, 711 insertions, 0 deletions

diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index d8bde82f0370..96ddecb92254 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -2,6 +2,7 @@ menu "SOC (System On Chip) specific Drivers"
 
 source "drivers/soc/mediatek/Kconfig"
 source "drivers/soc/qcom/Kconfig"
+source "drivers/soc/sunxi/Kconfig"
 source "drivers/soc/ti/Kconfig"
 source "drivers/soc/versatile/Kconfig"
 
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 70042b259744..7dc7c0d8a2c1 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -4,6 +4,7 @@
 
 obj-$(CONFIG_ARCH_MEDIATEK)     += mediatek/
 obj-$(CONFIG_ARCH_QCOM)         += qcom/
+obj-$(CONFIG_ARCH_SUNXI)        += sunxi/
 obj-$(CONFIG_ARCH_TEGRA)        += tegra/
 obj-$(CONFIG_SOC_TI)            += ti/
 obj-$(CONFIG_PLAT_VERSATILE)    += versatile/
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index 460b2dba109c..5eea374c8fa6 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -10,3 +10,10 @@ config QCOM_GSBI
           functions for connecting the underlying serial UART, SPI, and I2C
           devices to the output pins.
 
+config QCOM_PM
+        bool "Qualcomm Power Management"
+        depends on ARCH_QCOM && !ARM64
+        help
+          QCOM Platform specific power driver to manage cores and L2 low power
+          modes. It interface with various system drivers to put the cores in
+          low power modes.
diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
index 438901257ac1..931d385386c5 100644
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_QCOM_GSBI) +=      qcom_gsbi.o
+obj-$(CONFIG_QCOM_PM)   +=      spm.o
diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c
new file mode 100644
index 000000000000..b562af816c0a
--- /dev/null
+++ b/drivers/soc/qcom/spm.c
@@ -0,0 +1,385 @@
+/*
+ * Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014,2015, Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/cpuidle.h>
+#include <linux/cpu_pm.h>
+#include <linux/qcom_scm.h>
+
+#include <asm/cpuidle.h>
+#include <asm/proc-fns.h>
+#include <asm/suspend.h>
+
+#define MAX_PMIC_DATA           2
+#define MAX_SEQ_DATA            64
+#define SPM_CTL_INDEX           0x7f
+#define SPM_CTL_INDEX_SHIFT     4
+#define SPM_CTL_EN              BIT(0)
+
+enum pm_sleep_mode {
+        PM_SLEEP_MODE_STBY,
+        PM_SLEEP_MODE_RET,
+        PM_SLEEP_MODE_SPC,
+        PM_SLEEP_MODE_PC,
+        PM_SLEEP_MODE_NR,
+};
+
+enum spm_reg {
+        SPM_REG_CFG,
+        SPM_REG_SPM_CTL,
+        SPM_REG_DLY,
+        SPM_REG_PMIC_DLY,
+        SPM_REG_PMIC_DATA_0,
+        SPM_REG_PMIC_DATA_1,
+        SPM_REG_VCTL,
+        SPM_REG_SEQ_ENTRY,
+        SPM_REG_SPM_STS,
+        SPM_REG_PMIC_STS,
+        SPM_REG_NR,
+};
+
+struct spm_reg_data {
+        const u8 *reg_offset;
+        u32 spm_cfg;
+        u32 spm_dly;
+        u32 pmic_dly;
+        u32 pmic_data[MAX_PMIC_DATA];
+        u8 seq[MAX_SEQ_DATA];
+        u8 start_index[PM_SLEEP_MODE_NR];
+};
+
+struct spm_driver_data {
+        void __iomem *reg_base;
+        const struct spm_reg_data *reg_data;
+};
+
+static const u8 spm_reg_offset_v2_1[SPM_REG_NR] = {
+        [SPM_REG_CFG]           = 0x08,
+        [SPM_REG_SPM_CTL]       = 0x30,
+        [SPM_REG_DLY]           = 0x34,
+        [SPM_REG_SEQ_ENTRY]     = 0x80,
+};
+
+/* SPM register data for 8974, 8084 */
+static const struct spm_reg_data spm_reg_8974_8084_cpu  = {
+        .reg_offset = spm_reg_offset_v2_1,
+        .spm_cfg = 0x1,
+        .spm_dly = 0x3C102800,
+        .seq = { 0x03, 0x0B, 0x0F, 0x00, 0x20, 0x80, 0x10, 0xE8, 0x5B, 0x03,
+                0x3B, 0xE8, 0x5B, 0x82, 0x10, 0x0B, 0x30, 0x06, 0x26, 0x30,
+                0x0F },
+        .start_index[PM_SLEEP_MODE_STBY] = 0,
+        .start_index[PM_SLEEP_MODE_SPC] = 3,
+};
+
+static const u8 spm_reg_offset_v1_1[SPM_REG_NR] = {
+        [SPM_REG_CFG]           = 0x08,
+        [SPM_REG_SPM_CTL]       = 0x20,
+        [SPM_REG_PMIC_DLY]      = 0x24,
+        [SPM_REG_PMIC_DATA_0]   = 0x28,
+        [SPM_REG_PMIC_DATA_1]   = 0x2C,
+        [SPM_REG_SEQ_ENTRY]     = 0x80,
+};
+
+/* SPM register data for 8064 */
+static const struct spm_reg_data spm_reg_8064_cpu = {
+        .reg_offset = spm_reg_offset_v1_1,
+        .spm_cfg = 0x1F,
+        .pmic_dly = 0x02020004,
+        .pmic_data[0] = 0x0084009C,
+        .pmic_data[1] = 0x00A4001C,
+        .seq = { 0x03, 0x0F, 0x00, 0x24, 0x54, 0x10, 0x09, 0x03, 0x01,
+                0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F },
+        .start_index[PM_SLEEP_MODE_STBY] = 0,
+        .start_index[PM_SLEEP_MODE_SPC] = 2,
+};
+
+static DEFINE_PER_CPU(struct spm_driver_data *, cpu_spm_drv);
+
+typedef int (*idle_fn)(int);
+static DEFINE_PER_CPU(idle_fn*, qcom_idle_ops);
+
+static inline void spm_register_write(struct spm_driver_data *drv,
+                                        enum spm_reg reg, u32 val)
+{
+        if (drv->reg_data->reg_offset[reg])
+                writel_relaxed(val, drv->reg_base +
+                                drv->reg_data->reg_offset[reg]);
+}
+
+/* Ensure a guaranteed write, before return */
+static inline void spm_register_write_sync(struct spm_driver_data *drv,
+                                        enum spm_reg reg, u32 val)
+{
+        u32 ret;
+
+        if (!drv->reg_data->reg_offset[reg])
+                return;
+
+        do {
+                writel_relaxed(val, drv->reg_base +
+                                drv->reg_data->reg_offset[reg]);
+                ret = readl_relaxed(drv->reg_base +
+                                drv->reg_data->reg_offset[reg]);
+                if (ret == val)
+                        break;
+                cpu_relax();
+        } while (1);
+}
+
+static inline u32 spm_register_read(struct spm_driver_data *drv,
+                                        enum spm_reg reg)
+{
+        return readl_relaxed(drv->reg_base + drv->reg_data->reg_offset[reg]);
+}
+
+static void spm_set_low_power_mode(struct spm_driver_data *drv,
+                                        enum pm_sleep_mode mode)
+{
+        u32 start_index;
+        u32 ctl_val;
+
+        start_index = drv->reg_data->start_index[mode];
+
+        ctl_val = spm_register_read(drv, SPM_REG_SPM_CTL);
+        ctl_val &= ~(SPM_CTL_INDEX << SPM_CTL_INDEX_SHIFT);
+        ctl_val |= start_index << SPM_CTL_INDEX_SHIFT;
+        ctl_val |= SPM_CTL_EN;
+        spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val);
+}
+
+static int qcom_pm_collapse(unsigned long int unused)
+{
+        qcom_scm_cpu_power_down(QCOM_SCM_CPU_PWR_DOWN_L2_ON);
+
+        /*
+         * Returns here only if there was a pending interrupt and we did not
+         * power down as a result.
+         */
+        return -1;
+}
+
+static int qcom_cpu_spc(int cpu)
+{
+        int ret;
+        struct spm_driver_data *drv = per_cpu(cpu_spm_drv, cpu);
+
+        spm_set_low_power_mode(drv, PM_SLEEP_MODE_SPC);
+        ret = cpu_suspend(0, qcom_pm_collapse);
+        /*
+         * ARM common code executes WFI without calling into our driver and
+         * if the SPM mode is not reset, then we may accidently power down the
+         * cpu when we intended only to gate the cpu clock.
+         * Ensure the state is set to standby before returning.
+         */
+        spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY);
+
+        return ret;
+}
+
+static int qcom_idle_enter(int cpu, unsigned long index)
+{
+        return per_cpu(qcom_idle_ops, cpu)[index](cpu);
+}
+
+static const struct of_device_id qcom_idle_state_match[] __initconst = {
+        { .compatible = "qcom,idle-state-spc", .data = qcom_cpu_spc },
+        { },
+};
+
+static int __init qcom_cpuidle_init(struct device_node *cpu_node, int cpu)
+{
+        const struct of_device_id *match_id;
+        struct device_node *state_node;
+        int i;
+        int state_count = 1;
+        idle_fn idle_fns[CPUIDLE_STATE_MAX];
+        idle_fn *fns;
+        cpumask_t mask;
+        bool use_scm_power_down = false;
+
+        for (i = 0; ; i++) {
+                state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i);
+                if (!state_node)
+                        break;
+
+                if (!of_device_is_available(state_node))
+                        continue;
+
+                if (i == CPUIDLE_STATE_MAX) {
+                        pr_warn("%s: cpuidle states reached max possible\n",
+                                        __func__);
+                        break;
+                }
+
+                match_id = of_match_node(qcom_idle_state_match, state_node);
+                if (!match_id)
+                        return -ENODEV;
+
+                idle_fns[state_count] = match_id->data;
+
+                /* Check if any of the states allow power down */
+                if (match_id->data == qcom_cpu_spc)
+                        use_scm_power_down = true;
+
+                state_count++;
+        }
+
+        if (state_count == 1)
+                goto check_spm;
+
+        fns = devm_kcalloc(get_cpu_device(cpu), state_count, sizeof(*fns),
+                        GFP_KERNEL);
+        if (!fns)
+                return -ENOMEM;
+
+        for (i = 1; i < state_count; i++)
+                fns[i] = idle_fns[i];
+
+        if (use_scm_power_down) {
+                /* We have atleast one power down mode */
+                cpumask_clear(&mask);
+                cpumask_set_cpu(cpu, &mask);
+                qcom_scm_set_warm_boot_addr(cpu_resume, &mask);
+        }
+
+        per_cpu(qcom_idle_ops, cpu) = fns;
+
+        /*
+         * SPM probe for the cpu should have happened by now, if the
+         * SPM device does not exist, return -ENXIO to indicate that the
+         * cpu does not support idle states.
+         */
+check_spm:
+        return per_cpu(cpu_spm_drv, cpu) ? 0 : -ENXIO;
+}
+
+static struct cpuidle_ops qcom_cpuidle_ops __initdata = {
+        .suspend = qcom_idle_enter,
+        .init = qcom_cpuidle_init,
+};
+
+CPUIDLE_METHOD_OF_DECLARE(qcom_idle_v1, "qcom,kpss-acc-v1", &qcom_cpuidle_ops);
+CPUIDLE_METHOD_OF_DECLARE(qcom_idle_v2, "qcom,kpss-acc-v2", &qcom_cpuidle_ops);
+
+static struct spm_driver_data *spm_get_drv(struct platform_device *pdev,
+                int *spm_cpu)
+{
+        struct spm_driver_data *drv = NULL;
+        struct device_node *cpu_node, *saw_node;
+        int cpu;
+        bool found;
+
+        for_each_possible_cpu(cpu) {
+                cpu_node = of_cpu_device_node_get(cpu);
+                if (!cpu_node)
+                        continue;
+                saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0);
+                found = (saw_node == pdev->dev.of_node);
+                of_node_put(saw_node);
+                of_node_put(cpu_node);
+                if (found)
+                        break;
+        }
+
+        if (found) {
+                drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
+                if (drv)
+                        *spm_cpu = cpu;
+        }
+
+        return drv;
+}
+
+static const struct of_device_id spm_match_table[] = {
+        { .compatible = "qcom,msm8974-saw2-v2.1-cpu",
+          .data = &spm_reg_8974_8084_cpu },
+        { .compatible = "qcom,apq8084-saw2-v2.1-cpu",
+          .data = &spm_reg_8974_8084_cpu },
+        { .compatible = "qcom,apq8064-saw2-v1.1-cpu",
+          .data = &spm_reg_8064_cpu },
+        { },
+};
+
+static int spm_dev_probe(struct platform_device *pdev)
+{
+        struct spm_driver_data *drv;
+        struct resource *res;
+        const struct of_device_id *match_id;
+        void __iomem *addr;
+        int cpu;
+
+        drv = spm_get_drv(pdev, &cpu);
+        if (!drv)
+                return -EINVAL;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        drv->reg_base = devm_ioremap_resource(&pdev->dev, res);
+        if (IS_ERR(drv->reg_base))
+                return PTR_ERR(drv->reg_base);
+
+        match_id = of_match_node(spm_match_table, pdev->dev.of_node);
+        if (!match_id)
+                return -ENODEV;
+
+        drv->reg_data = match_id->data;
+
+        /* Write the SPM sequences first.. */
+        addr = drv->reg_base + drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY];
+        __iowrite32_copy(addr, drv->reg_data->seq,
+                        ARRAY_SIZE(drv->reg_data->seq) / 4);
+
+        /*
+         * ..and then the control registers.
+         * On some SoC if the control registers are written first and if the
+         * CPU was held in reset, the reset signal could trigger the SPM state
+         * machine, before the sequences are completely written.
+         */
+        spm_register_write(drv, SPM_REG_CFG, drv->reg_data->spm_cfg);
+        spm_register_write(drv, SPM_REG_DLY, drv->reg_data->spm_dly);
+        spm_register_write(drv, SPM_REG_PMIC_DLY, drv->reg_data->pmic_dly);
+        spm_register_write(drv, SPM_REG_PMIC_DATA_0,
+                                drv->reg_data->pmic_data[0]);
+        spm_register_write(drv, SPM_REG_PMIC_DATA_1,
+                                drv->reg_data->pmic_data[1]);
+
+        /* Set up Standby as the default low power mode */
+        spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY);
+
+        per_cpu(cpu_spm_drv, cpu) = drv;
+
+        return 0;
+}
+
+static struct platform_driver spm_driver = {
+        .probe = spm_dev_probe,
+        .driver = {
+                .name = "saw",
+                .of_match_table = spm_match_table,
+        },
+};
+module_platform_driver(spm_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("SAW power controller driver");
+MODULE_ALIAS("platform:saw");
diff --git a/drivers/soc/sunxi/Kconfig b/drivers/soc/sunxi/Kconfig
new file mode 100644
index 000000000000..353b07e40176
--- /dev/null
+++ b/drivers/soc/sunxi/Kconfig
@@ -0,0 +1,10 @@
+#
+# Allwinner sunXi SoC drivers
+#
+config SUNXI_SRAM
+        bool
+        default ARCH_SUNXI
+        help
+          Say y here to enable the SRAM controller support. This
+          device is responsible on mapping the SRAM in the sunXi SoCs
+          whether to the CPU/DMA, or to the devices.
diff --git a/drivers/soc/sunxi/Makefile b/drivers/soc/sunxi/Makefile
new file mode 100644
index 000000000000..4cf9dbdf346e
--- /dev/null
+++ b/drivers/soc/sunxi/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_SUNXI_SRAM) +=     sunxi_sram.o
diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c
new file mode 100644
index 000000000000..bc52670c8f4b
--- /dev/null
+++ b/drivers/soc/sunxi/sunxi_sram.c
@@ -0,0 +1,284 @@
+/*
+ * Allwinner SoCs SRAM Controller Driver
+ *
+ * Copyright (C) 2015 Maxime Ripard
+ *
+ * Author: Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/debugfs.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include <linux/soc/sunxi/sunxi_sram.h>
+
+struct sunxi_sram_func {
+        char    *func;
+        u8      val;
+};
+
+struct sunxi_sram_data {
+        char                    *name;
+        u8                      reg;
+        u8                      offset;
+        u8                      width;
+        struct sunxi_sram_func  *func;
+        struct list_head        list;
+};
+
+struct sunxi_sram_desc {
+        struct sunxi_sram_data  data;
+        bool                    claimed;
+};
+
+#define SUNXI_SRAM_MAP(_val, _func)                             \
+        {                                                       \
+                .func = _func,                                  \
+                .val = _val,                                    \
+        }
+
+#define SUNXI_SRAM_DATA(_name, _reg, _off, _width, ...)         \
+        {                                                       \
+                .name = _name,                                  \
+                .reg = _reg,                                    \
+                .offset = _off,                                 \
+                .width = _width,                                \
+                .func = (struct sunxi_sram_func[]){             \
+                        __VA_ARGS__, { } },                     \
+        }
+
+static struct sunxi_sram_desc sun4i_a10_sram_a3_a4 = {
+        .data   = SUNXI_SRAM_DATA("A3-A4", 0x4, 0x4, 2,
+                                  SUNXI_SRAM_MAP(0, "cpu"),
+                                  SUNXI_SRAM_MAP(1, "emac")),
+};
+
+static struct sunxi_sram_desc sun4i_a10_sram_d = {
+        .data   = SUNXI_SRAM_DATA("D", 0x4, 0x0, 1,
+                                  SUNXI_SRAM_MAP(0, "cpu"),
+                                  SUNXI_SRAM_MAP(1, "usb-otg")),
+};
+
+static const struct of_device_id sunxi_sram_dt_ids[] = {
+        {
+                .compatible     = "allwinner,sun4i-a10-sram-a3-a4",
+                .data           = &sun4i_a10_sram_a3_a4.data,
+        },
+        {
+                .compatible     = "allwinner,sun4i-a10-sram-d",
+                .data           = &sun4i_a10_sram_d.data,
+        },
+        {}
+};
+
+static struct device *sram_dev;
+static LIST_HEAD(claimed_sram);
+static DEFINE_SPINLOCK(sram_lock);
+static void __iomem *base;
+
+static int sunxi_sram_show(struct seq_file *s, void *data)
+{
+        struct device_node *sram_node, *section_node;
+        const struct sunxi_sram_data *sram_data;
+        const struct of_device_id *match;
+        struct sunxi_sram_func *func;
+        const __be32 *sram_addr_p, *section_addr_p;
+        u32 val;
+
+        seq_puts(s, "Allwinner sunXi SRAM\n");
+        seq_puts(s, "--------------------\n\n");
+
+        for_each_child_of_node(sram_dev->of_node, sram_node) {
+                sram_addr_p = of_get_address(sram_node, 0, NULL, NULL);
+
+                seq_printf(s, "sram@%08x\n",
+                           be32_to_cpu(*sram_addr_p));
+
+                for_each_child_of_node(sram_node, section_node) {
+                        match = of_match_node(sunxi_sram_dt_ids, section_node);
+                        if (!match)
+                                continue;
+                        sram_data = match->data;
+
+                        section_addr_p = of_get_address(section_node, 0,
+                                                        NULL, NULL);
+
+                        seq_printf(s, "\tsection@%04x\t(%s)\n",
+                                   be32_to_cpu(*section_addr_p),
+                                   sram_data->name);
+
+                        val = readl(base + sram_data->reg);
+                        val >>= sram_data->offset;
+                        val &= sram_data->width;
+
+                        for (func = sram_data->func; func->func; func++) {
+                                seq_printf(s, "\t\t%s%c\n", func->func,
+                                           func->val == val ? '*' : ' ');
+                        }
+                }
+
+                seq_puts(s, "\n");
+        }
+
+        return 0;
+}
+
+static int sunxi_sram_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, sunxi_sram_show, inode->i_private);
+}
+
+static const struct file_operations sunxi_sram_fops = {
+        .open = sunxi_sram_open,
+        .read = seq_read,
+        .llseek = seq_lseek,
+        .release = single_release,
+};
+
+static inline struct sunxi_sram_desc *to_sram_desc(const struct sunxi_sram_data *data)
+{
+        return container_of(data, struct sunxi_sram_desc, data);
+}
+
+static const struct sunxi_sram_data *sunxi_sram_of_parse(struct device_node *node,
+                                                         unsigned int *value)
+{
+        const struct of_device_id *match;
+        struct of_phandle_args args;
+        int ret;
+
+        ret = of_parse_phandle_with_fixed_args(node, "allwinner,sram", 1, 0,
+                                               &args);
+        if (ret)
+                return ERR_PTR(ret);
+
+        if (!of_device_is_available(args.np)) {
+                ret = -EBUSY;
+                goto err;
+        }
+
+        if (value)
+                *value = args.args[0];
+
+        match = of_match_node(sunxi_sram_dt_ids, args.np);
+        if (!match) {
+                ret = -EINVAL;
+                goto err;
+        }
+
+        of_node_put(args.np);
+        return match->data;
+
+err:
+        of_node_put(args.np);
+        return ERR_PTR(ret);
+}
+
+int sunxi_sram_claim(struct device *dev)
+{
+        const struct sunxi_sram_data *sram_data;
+        struct sunxi_sram_desc *sram_desc;
+        unsigned int device;
+        u32 val, mask;
+
+        if (IS_ERR(base))
+                return -EPROBE_DEFER;
+
+        if (!dev || !dev->of_node)
+                return -EINVAL;
+
+        sram_data = sunxi_sram_of_parse(dev->of_node, &device);
+        if (IS_ERR(sram_data))
+                return PTR_ERR(sram_data);
+
+        sram_desc = to_sram_desc(sram_data);
+
+        spin_lock(&sram_lock);
+
+        if (sram_desc->claimed) {
+                spin_unlock(&sram_lock);
+                return -EBUSY;
+        }
+
+        mask = GENMASK(sram_data->offset + sram_data->width, sram_data->offset);
+        val = readl(base + sram_data->reg);
+        val &= ~mask;
+        writel(val | ((device << sram_data->offset) & mask),
+               base + sram_data->reg);
+
+        spin_unlock(&sram_lock);
+
+        return 0;
+}
+EXPORT_SYMBOL(sunxi_sram_claim);
+
+int sunxi_sram_release(struct device *dev)
+{
+        const struct sunxi_sram_data *sram_data;
+        struct sunxi_sram_desc *sram_desc;
+
+        if (!dev || !dev->of_node)
+                return -EINVAL;
+
+        sram_data = sunxi_sram_of_parse(dev->of_node, NULL);
+        if (IS_ERR(sram_data))
+                return -EINVAL;
+
+        sram_desc = to_sram_desc(sram_data);
+
+        spin_lock(&sram_lock);
+        sram_desc->claimed = false;
+        spin_unlock(&sram_lock);
+
+        return 0;
+}
+EXPORT_SYMBOL(sunxi_sram_release);
+
+static int sunxi_sram_probe(struct platform_device *pdev)
+{
+        struct resource *res;
+        struct dentry *d;
+
+        sram_dev = &pdev->dev;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        base = devm_ioremap_resource(&pdev->dev, res);
+        if (IS_ERR(base))
+                return PTR_ERR(base);
+
+        of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
+
+        d = debugfs_create_file("sram", S_IRUGO, NULL, NULL,
+                                &sunxi_sram_fops);
+        if (!d)
+                return -ENOMEM;
+
+        return 0;
+}
+
+static const struct of_device_id sunxi_sram_dt_match[] = {
+        { .compatible = "allwinner,sun4i-a10-sram-controller" },
+        { },
+};
+MODULE_DEVICE_TABLE(of, sunxi_sram_dt_match);
+
+static struct platform_driver sunxi_sram_driver = {
+        .driver = {
+                .name           = "sunxi-sram",
+                .of_match_table = sunxi_sram_dt_match,
+        },
+        .probe  = sunxi_sram_probe,
+};
+module_platform_driver(sunxi_sram_driver);
+
+MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
+MODULE_DESCRIPTION("Allwinner sunXi SRAM Controller Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/soc/tegra/fuse/tegra-apbmisc.c b/drivers/soc/tegra/fuse/tegra-apbmisc.c
index 3bf5aba4caaa..73fad05d8f2c 100644
--- a/drivers/soc/tegra/fuse/tegra-apbmisc.c
+++ b/drivers/soc/tegra/fuse/tegra-apbmisc.c
@@ -28,8 +28,15 @@
 #define APBMISC_SIZE    0x64
 #define FUSE_SKU_INFO   0x10
 
+#define PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT      4
+#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG  \
+        (0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
+#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT \
+        (0x3 << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
+
 static void __iomem *apbmisc_base;
 static void __iomem *strapping_base;
+static bool long_ram_code;
 
 u32 tegra_read_chipid(void)
 {
@@ -54,6 +61,18 @@ u32 tegra_read_straps(void)
                 return 0;
 }
 
+u32 tegra_read_ram_code(void)
+{
+        u32 straps = tegra_read_straps();
+
+        if (long_ram_code)
+                straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG;
+        else
+                straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT;
+
+        return straps >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT;
+}
+
 static const struct of_device_id apbmisc_match[] __initconst = {
         { .compatible = "nvidia,tegra20-apbmisc", },
         {},
@@ -112,4 +131,6 @@ void __init tegra_init_apbmisc(void)
         strapping_base = of_iomap(np, 1);
         if (!strapping_base)
                 pr_err("ioremap tegra strapping_base failed\n");
+
+        long_ram_code = of_property_read_bool(np, "nvidia,long-ram-code");
 }