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authorArnd Bergmann <arnd@arndb.de>2016-04-26 04:21:57 -0400
committerArnd Bergmann <arnd@arndb.de>2016-04-26 04:21:57 -0400
commita183d7f846de1ea87b9010f0aab77d2f4915e064 (patch)
tree89473fdfb30faf7092bf2e22b0c74e325113f0b5 /drivers/soc
parent2b9cf18982b0ba7317f258663560e181594a9bf8 (diff)
parent23f1e2ecdecee9f2ec45de0a468b82bb1f7f3ca2 (diff)
Merge tag 'renesas-rcar-sysc2-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers
Merge "Second Round of Renesas ARM Based SoC R-Car SYSC Updates for v4.7" from Simon Horman: Introduce a DT-based driver for the R-Car System Controller, as found on Renesas R-Car H1, R-Car Gen2, and R-Car Gen3 SoCs. * tag 'renesas-rcar-sysc2-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (30 commits) soc: renesas: rcar-sysc: Add support for R-Car H3 power areas soc: renesas: rcar-sysc: Add support for R-Car E2 power areas soc: renesas: rcar-sysc: Add support for R-Car M2-N power areas soc: renesas: rcar-sysc: Add support for R-Car M2-W power areas soc: renesas: rcar-sysc: Add support for R-Car H2 power areas soc: renesas: rcar-sysc: Add support for R-Car H1 power areas soc: renesas: rcar-sysc: Enable Clock Domain for I/O devices soc: renesas: rcar-sysc: Make rcar_sysc_power_is_off() static soc: renesas: rcar-sysc: Add DT support for SYSC PM domains soc: renesas: rcar-sysc: Improve rcar_sysc_power() debug info soc: renesas: Move pm-rcar to drivers/soc/renesas/rcar-sysc clk: renesas: cpg-mssr: Export cpg_mssr_{at,de}tach_dev() clk: renesas: mstp: Provide dummy attach/detach_dev callbacks clk: renesas: Provide Kconfig symbols for CPG/MSSR and CPG/MSTP support soc: renesas: Add r8a7795 SYSC PM Domain Binding Definitions soc: renesas: Add r8a7794 SYSC PM Domain Binding Definitions soc: renesas: Add r8a7793 SYSC PM Domain Binding Definitions soc: renesas: Add r8a7791 SYSC PM Domain Binding Definitions soc: renesas: Add r8a7790 SYSC PM Domain Binding Definitions soc: renesas: Add r8a7779 SYSC PM Domain Binding Definitions ...
Diffstat (limited to 'drivers/soc')
-rw-r--r--drivers/soc/Makefile3
-rw-r--r--drivers/soc/renesas/Makefile7
-rw-r--r--drivers/soc/renesas/r8a7779-sysc.c34
-rw-r--r--drivers/soc/renesas/r8a7790-sysc.c48
-rw-r--r--drivers/soc/renesas/r8a7791-sysc.c33
-rw-r--r--drivers/soc/renesas/r8a7794-sysc.c33
-rw-r--r--drivers/soc/renesas/r8a7795-sysc.c56
-rw-r--r--drivers/soc/renesas/rcar-sysc.c401
-rw-r--r--drivers/soc/renesas/rcar-sysc.h58
9 files changed, 672 insertions, 1 deletions
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 5ade71306ee1..380230f03874 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -9,7 +9,8 @@ obj-$(CONFIG_MACH_DOVE) += dove/
9obj-y += fsl/ 9obj-y += fsl/
10obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ 10obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
11obj-$(CONFIG_ARCH_QCOM) += qcom/ 11obj-$(CONFIG_ARCH_QCOM) += qcom/
12obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ 12obj-$(CONFIG_ARCH_RENESAS) += renesas/
13obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
13obj-$(CONFIG_SOC_SAMSUNG) += samsung/ 14obj-$(CONFIG_SOC_SAMSUNG) += samsung/
14obj-$(CONFIG_ARCH_SUNXI) += sunxi/ 15obj-$(CONFIG_ARCH_SUNXI) += sunxi/
15obj-$(CONFIG_ARCH_TEGRA) += tegra/ 16obj-$(CONFIG_ARCH_TEGRA) += tegra/
diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
new file mode 100644
index 000000000000..151fcd3f025b
--- /dev/null
+++ b/drivers/soc/renesas/Makefile
@@ -0,0 +1,7 @@
1obj-$(CONFIG_ARCH_R8A7779) += rcar-sysc.o r8a7779-sysc.o
2obj-$(CONFIG_ARCH_R8A7790) += rcar-sysc.o r8a7790-sysc.o
3obj-$(CONFIG_ARCH_R8A7791) += rcar-sysc.o r8a7791-sysc.o
4# R-Car M2-N is identical to R-Car M2-W w.r.t. power domains.
5obj-$(CONFIG_ARCH_R8A7793) += rcar-sysc.o r8a7791-sysc.o
6obj-$(CONFIG_ARCH_R8A7794) += rcar-sysc.o r8a7794-sysc.o
7obj-$(CONFIG_ARCH_R8A7795) += rcar-sysc.o r8a7795-sysc.o
diff --git a/drivers/soc/renesas/r8a7779-sysc.c b/drivers/soc/renesas/r8a7779-sysc.c
new file mode 100644
index 000000000000..9e8e6b7faa04
--- /dev/null
+++ b/drivers/soc/renesas/r8a7779-sysc.c
@@ -0,0 +1,34 @@
1/*
2 * Renesas R-Car H1 System Controller
3 *
4 * Copyright (C) 2016 Glider bvba
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11#include <linux/bug.h>
12#include <linux/kernel.h>
13
14#include <dt-bindings/power/r8a7779-sysc.h>
15
16#include "rcar-sysc.h"
17
18static const struct rcar_sysc_area r8a7779_areas[] __initconst = {
19 { "always-on", 0, 0, R8A7779_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
20 { "arm1", 0x40, 1, R8A7779_PD_ARM1, R8A7779_PD_ALWAYS_ON,
21 PD_CPU_CR },
22 { "arm2", 0x40, 2, R8A7779_PD_ARM2, R8A7779_PD_ALWAYS_ON,
23 PD_CPU_CR },
24 { "arm3", 0x40, 3, R8A7779_PD_ARM3, R8A7779_PD_ALWAYS_ON,
25 PD_CPU_CR },
26 { "sgx", 0xc0, 0, R8A7779_PD_SGX, R8A7779_PD_ALWAYS_ON },
27 { "vdp", 0x100, 0, R8A7779_PD_VDP, R8A7779_PD_ALWAYS_ON },
28 { "imp", 0x140, 0, R8A7779_PD_IMP, R8A7779_PD_ALWAYS_ON },
29};
30
31const struct rcar_sysc_info r8a7779_sysc_info __initconst = {
32 .areas = r8a7779_areas,
33 .num_areas = ARRAY_SIZE(r8a7779_areas),
34};
diff --git a/drivers/soc/renesas/r8a7790-sysc.c b/drivers/soc/renesas/r8a7790-sysc.c
new file mode 100644
index 000000000000..7a567ad0ff73
--- /dev/null
+++ b/drivers/soc/renesas/r8a7790-sysc.c
@@ -0,0 +1,48 @@
1/*
2 * Renesas R-Car H2 System Controller
3 *
4 * Copyright (C) 2016 Glider bvba
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11#include <linux/bug.h>
12#include <linux/kernel.h>
13
14#include <dt-bindings/power/r8a7790-sysc.h>
15
16#include "rcar-sysc.h"
17
18static const struct rcar_sysc_area r8a7790_areas[] __initconst = {
19 { "always-on", 0, 0, R8A7790_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
20 { "ca15-scu", 0x180, 0, R8A7790_PD_CA15_SCU, R8A7790_PD_ALWAYS_ON,
21 PD_SCU },
22 { "ca15-cpu0", 0x40, 0, R8A7790_PD_CA15_CPU0, R8A7790_PD_CA15_SCU,
23 PD_CPU_NOCR },
24 { "ca15-cpu1", 0x40, 1, R8A7790_PD_CA15_CPU1, R8A7790_PD_CA15_SCU,
25 PD_CPU_NOCR },
26 { "ca15-cpu2", 0x40, 2, R8A7790_PD_CA15_CPU2, R8A7790_PD_CA15_SCU,
27 PD_CPU_NOCR },
28 { "ca15-cpu3", 0x40, 3, R8A7790_PD_CA15_CPU3, R8A7790_PD_CA15_SCU,
29 PD_CPU_NOCR },
30 { "ca7-scu", 0x100, 0, R8A7790_PD_CA7_SCU, R8A7790_PD_ALWAYS_ON,
31 PD_SCU },
32 { "ca7-cpu0", 0x1c0, 0, R8A7790_PD_CA7_CPU0, R8A7790_PD_CA7_SCU,
33 PD_CPU_NOCR },
34 { "ca7-cpu1", 0x1c0, 1, R8A7790_PD_CA7_CPU1, R8A7790_PD_CA7_SCU,
35 PD_CPU_NOCR },
36 { "ca7-cpu2", 0x1c0, 2, R8A7790_PD_CA7_CPU2, R8A7790_PD_CA7_SCU,
37 PD_CPU_NOCR },
38 { "ca7-cpu3", 0x1c0, 3, R8A7790_PD_CA7_CPU3, R8A7790_PD_CA7_SCU,
39 PD_CPU_NOCR },
40 { "sh-4a", 0x80, 0, R8A7790_PD_SH_4A, R8A7790_PD_ALWAYS_ON },
41 { "rgx", 0xc0, 0, R8A7790_PD_RGX, R8A7790_PD_ALWAYS_ON },
42 { "imp", 0x140, 0, R8A7790_PD_IMP, R8A7790_PD_ALWAYS_ON },
43};
44
45const struct rcar_sysc_info r8a7790_sysc_info __initconst = {
46 .areas = r8a7790_areas,
47 .num_areas = ARRAY_SIZE(r8a7790_areas),
48};
diff --git a/drivers/soc/renesas/r8a7791-sysc.c b/drivers/soc/renesas/r8a7791-sysc.c
new file mode 100644
index 000000000000..03b9f41a34e6
--- /dev/null
+++ b/drivers/soc/renesas/r8a7791-sysc.c
@@ -0,0 +1,33 @@
1/*
2 * Renesas R-Car M2-W/N System Controller
3 *
4 * Copyright (C) 2016 Glider bvba
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11#include <linux/bug.h>
12#include <linux/kernel.h>
13
14#include <dt-bindings/power/r8a7791-sysc.h>
15
16#include "rcar-sysc.h"
17
18static const struct rcar_sysc_area r8a7791_areas[] __initconst = {
19 { "always-on", 0, 0, R8A7791_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
20 { "ca15-scu", 0x180, 0, R8A7791_PD_CA15_SCU, R8A7791_PD_ALWAYS_ON,
21 PD_SCU },
22 { "ca15-cpu0", 0x40, 0, R8A7791_PD_CA15_CPU0, R8A7791_PD_CA15_SCU,
23 PD_CPU_NOCR },
24 { "ca15-cpu1", 0x40, 1, R8A7791_PD_CA15_CPU1, R8A7791_PD_CA15_SCU,
25 PD_CPU_NOCR },
26 { "sh-4a", 0x80, 0, R8A7791_PD_SH_4A, R8A7791_PD_ALWAYS_ON },
27 { "sgx", 0xc0, 0, R8A7791_PD_SGX, R8A7791_PD_ALWAYS_ON },
28};
29
30const struct rcar_sysc_info r8a7791_sysc_info __initconst = {
31 .areas = r8a7791_areas,
32 .num_areas = ARRAY_SIZE(r8a7791_areas),
33};
diff --git a/drivers/soc/renesas/r8a7794-sysc.c b/drivers/soc/renesas/r8a7794-sysc.c
new file mode 100644
index 000000000000..c4da2941e06c
--- /dev/null
+++ b/drivers/soc/renesas/r8a7794-sysc.c
@@ -0,0 +1,33 @@
1/*
2 * Renesas R-Car E2 System Controller
3 *
4 * Copyright (C) 2016 Glider bvba
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11#include <linux/bug.h>
12#include <linux/kernel.h>
13
14#include <dt-bindings/power/r8a7794-sysc.h>
15
16#include "rcar-sysc.h"
17
18static const struct rcar_sysc_area r8a7794_areas[] __initconst = {
19 { "always-on", 0, 0, R8A7794_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
20 { "ca7-scu", 0x100, 0, R8A7794_PD_CA7_SCU, R8A7794_PD_ALWAYS_ON,
21 PD_SCU },
22 { "ca7-cpu0", 0x1c0, 0, R8A7794_PD_CA7_CPU0, R8A7794_PD_CA7_SCU,
23 PD_CPU_NOCR },
24 { "ca7-cpu1", 0x1c0, 1, R8A7794_PD_CA7_CPU1, R8A7794_PD_CA7_SCU,
25 PD_CPU_NOCR },
26 { "sh-4a", 0x80, 0, R8A7794_PD_SH_4A, R8A7794_PD_ALWAYS_ON },
27 { "sgx", 0xc0, 0, R8A7794_PD_SGX, R8A7794_PD_ALWAYS_ON },
28};
29
30const struct rcar_sysc_info r8a7794_sysc_info __initconst = {
31 .areas = r8a7794_areas,
32 .num_areas = ARRAY_SIZE(r8a7794_areas),
33};
diff --git a/drivers/soc/renesas/r8a7795-sysc.c b/drivers/soc/renesas/r8a7795-sysc.c
new file mode 100644
index 000000000000..5e7537c96f7b
--- /dev/null
+++ b/drivers/soc/renesas/r8a7795-sysc.c
@@ -0,0 +1,56 @@
1/*
2 * Renesas R-Car H3 System Controller
3 *
4 * Copyright (C) 2016 Glider bvba
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11#include <linux/bug.h>
12#include <linux/kernel.h>
13
14#include <dt-bindings/power/r8a7795-sysc.h>
15
16#include "rcar-sysc.h"
17
18static const struct rcar_sysc_area r8a7795_areas[] __initconst = {
19 { "always-on", 0, 0, R8A7795_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
20 { "ca57-scu", 0x1c0, 0, R8A7795_PD_CA57_SCU, R8A7795_PD_ALWAYS_ON,
21 PD_SCU },
22 { "ca57-cpu0", 0x80, 0, R8A7795_PD_CA57_CPU0, R8A7795_PD_CA57_SCU,
23 PD_CPU_NOCR },
24 { "ca57-cpu1", 0x80, 1, R8A7795_PD_CA57_CPU1, R8A7795_PD_CA57_SCU,
25 PD_CPU_NOCR },
26 { "ca57-cpu2", 0x80, 2, R8A7795_PD_CA57_CPU2, R8A7795_PD_CA57_SCU,
27 PD_CPU_NOCR },
28 { "ca57-cpu3", 0x80, 3, R8A7795_PD_CA57_CPU3, R8A7795_PD_CA57_SCU,
29 PD_CPU_NOCR },
30 { "ca53-scu", 0x140, 0, R8A7795_PD_CA53_SCU, R8A7795_PD_ALWAYS_ON,
31 PD_SCU },
32 { "ca53-cpu0", 0x200, 0, R8A7795_PD_CA53_CPU0, R8A7795_PD_CA53_SCU,
33 PD_CPU_NOCR },
34 { "ca53-cpu1", 0x200, 1, R8A7795_PD_CA53_CPU1, R8A7795_PD_CA53_SCU,
35 PD_CPU_NOCR },
36 { "ca53-cpu2", 0x200, 2, R8A7795_PD_CA53_CPU2, R8A7795_PD_CA53_SCU,
37 PD_CPU_NOCR },
38 { "ca53-cpu3", 0x200, 3, R8A7795_PD_CA53_CPU3, R8A7795_PD_CA53_SCU,
39 PD_CPU_NOCR },
40 { "a3vp", 0x340, 0, R8A7795_PD_A3VP, R8A7795_PD_ALWAYS_ON },
41 { "cr7", 0x240, 0, R8A7795_PD_CR7, R8A7795_PD_ALWAYS_ON },
42 { "a3vc", 0x380, 0, R8A7795_PD_A3VC, R8A7795_PD_ALWAYS_ON },
43 { "a2vc0", 0x3c0, 0, R8A7795_PD_A2VC0, R8A7795_PD_A3VC },
44 { "a2vc1", 0x3c0, 1, R8A7795_PD_A2VC1, R8A7795_PD_A3VC },
45 { "3dg-a", 0x100, 0, R8A7795_PD_3DG_A, R8A7795_PD_ALWAYS_ON },
46 { "3dg-b", 0x100, 1, R8A7795_PD_3DG_B, R8A7795_PD_3DG_A },
47 { "3dg-c", 0x100, 2, R8A7795_PD_3DG_C, R8A7795_PD_3DG_B },
48 { "3dg-d", 0x100, 3, R8A7795_PD_3DG_D, R8A7795_PD_3DG_C },
49 { "3dg-e", 0x100, 4, R8A7795_PD_3DG_E, R8A7795_PD_3DG_D },
50 { "a3ir", 0x180, 0, R8A7795_PD_A3IR, R8A7795_PD_ALWAYS_ON },
51};
52
53const struct rcar_sysc_info r8a7795_sysc_info __initconst = {
54 .areas = r8a7795_areas,
55 .num_areas = ARRAY_SIZE(r8a7795_areas),
56};
diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c
new file mode 100644
index 000000000000..79dbc770895f
--- /dev/null
+++ b/drivers/soc/renesas/rcar-sysc.c
@@ -0,0 +1,401 @@
1/*
2 * R-Car SYSC Power management support
3 *
4 * Copyright (C) 2014 Magnus Damm
5 * Copyright (C) 2015-2016 Glider bvba
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11
12#include <linux/clk/renesas.h>
13#include <linux/delay.h>
14#include <linux/err.h>
15#include <linux/mm.h>
16#include <linux/of_address.h>
17#include <linux/pm_domain.h>
18#include <linux/slab.h>
19#include <linux/spinlock.h>
20#include <linux/io.h>
21#include <linux/soc/renesas/rcar-sysc.h>
22
23#include "rcar-sysc.h"
24
25/* SYSC Common */
26#define SYSCSR 0x00 /* SYSC Status Register */
27#define SYSCISR 0x04 /* Interrupt Status Register */
28#define SYSCISCR 0x08 /* Interrupt Status Clear Register */
29#define SYSCIER 0x0c /* Interrupt Enable Register */
30#define SYSCIMR 0x10 /* Interrupt Mask Register */
31
32/* SYSC Status Register */
33#define SYSCSR_PONENB 1 /* Ready for power resume requests */
34#define SYSCSR_POFFENB 0 /* Ready for power shutoff requests */
35
36/*
37 * Power Control Register Offsets inside the register block for each domain
38 * Note: The "CR" registers for ARM cores exist on H1 only
39 * Use WFI to power off, CPG/APMU to resume ARM cores on R-Car Gen2
40 * Use PSCI on R-Car Gen3
41 */
42#define PWRSR_OFFS 0x00 /* Power Status Register */
43#define PWROFFCR_OFFS 0x04 /* Power Shutoff Control Register */
44#define PWROFFSR_OFFS 0x08 /* Power Shutoff Status Register */
45#define PWRONCR_OFFS 0x0c /* Power Resume Control Register */
46#define PWRONSR_OFFS 0x10 /* Power Resume Status Register */
47#define PWRER_OFFS 0x14 /* Power Shutoff/Resume Error */
48
49
50#define SYSCSR_RETRIES 100
51#define SYSCSR_DELAY_US 1
52
53#define PWRER_RETRIES 100
54#define PWRER_DELAY_US 1
55
56#define SYSCISR_RETRIES 1000
57#define SYSCISR_DELAY_US 1
58
59#define RCAR_PD_ALWAYS_ON 32 /* Always-on power area */
60
61static void __iomem *rcar_sysc_base;
62static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */
63
64static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, bool on)
65{
66 unsigned int sr_bit, reg_offs;
67 int k;
68
69 if (on) {
70 sr_bit = SYSCSR_PONENB;
71 reg_offs = PWRONCR_OFFS;
72 } else {
73 sr_bit = SYSCSR_POFFENB;
74 reg_offs = PWROFFCR_OFFS;
75 }
76
77 /* Wait until SYSC is ready to accept a power request */
78 for (k = 0; k < SYSCSR_RETRIES; k++) {
79 if (ioread32(rcar_sysc_base + SYSCSR) & BIT(sr_bit))
80 break;
81 udelay(SYSCSR_DELAY_US);
82 }
83
84 if (k == SYSCSR_RETRIES)
85 return -EAGAIN;
86
87 /* Submit power shutoff or power resume request */
88 iowrite32(BIT(sysc_ch->chan_bit),
89 rcar_sysc_base + sysc_ch->chan_offs + reg_offs);
90
91 return 0;
92}
93
94static int rcar_sysc_power(const struct rcar_sysc_ch *sysc_ch, bool on)
95{
96 unsigned int isr_mask = BIT(sysc_ch->isr_bit);
97 unsigned int chan_mask = BIT(sysc_ch->chan_bit);
98 unsigned int status;
99 unsigned long flags;
100 int ret = 0;
101 int k;
102
103 spin_lock_irqsave(&rcar_sysc_lock, flags);
104
105 iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
106
107 /* Submit power shutoff or resume request until it was accepted */
108 for (k = 0; k < PWRER_RETRIES; k++) {
109 ret = rcar_sysc_pwr_on_off(sysc_ch, on);
110 if (ret)
111 goto out;
112
113 status = ioread32(rcar_sysc_base +
114 sysc_ch->chan_offs + PWRER_OFFS);
115 if (!(status & chan_mask))
116 break;
117
118 udelay(PWRER_DELAY_US);
119 }
120
121 if (k == PWRER_RETRIES) {
122 ret = -EIO;
123 goto out;
124 }
125
126 /* Wait until the power shutoff or resume request has completed * */
127 for (k = 0; k < SYSCISR_RETRIES; k++) {
128 if (ioread32(rcar_sysc_base + SYSCISR) & isr_mask)
129 break;
130 udelay(SYSCISR_DELAY_US);
131 }
132
133 if (k == SYSCISR_RETRIES)
134 ret = -EIO;
135
136 iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
137
138 out:
139 spin_unlock_irqrestore(&rcar_sysc_lock, flags);
140
141 pr_debug("sysc power %s domain %d: %08x -> %d\n", on ? "on" : "off",
142 sysc_ch->isr_bit, ioread32(rcar_sysc_base + SYSCISR), ret);
143 return ret;
144}
145
146int rcar_sysc_power_down(const struct rcar_sysc_ch *sysc_ch)
147{
148 return rcar_sysc_power(sysc_ch, false);
149}
150
151int rcar_sysc_power_up(const struct rcar_sysc_ch *sysc_ch)
152{
153 return rcar_sysc_power(sysc_ch, true);
154}
155
156static bool rcar_sysc_power_is_off(const struct rcar_sysc_ch *sysc_ch)
157{
158 unsigned int st;
159
160 st = ioread32(rcar_sysc_base + sysc_ch->chan_offs + PWRSR_OFFS);
161 if (st & BIT(sysc_ch->chan_bit))
162 return true;
163
164 return false;
165}
166
167void __iomem *rcar_sysc_init(phys_addr_t base)
168{
169 rcar_sysc_base = ioremap_nocache(base, PAGE_SIZE);
170 if (!rcar_sysc_base)
171 panic("unable to ioremap R-Car SYSC hardware block\n");
172
173 return rcar_sysc_base;
174}
175
176struct rcar_sysc_pd {
177 struct generic_pm_domain genpd;
178 struct rcar_sysc_ch ch;
179 unsigned int flags;
180 char name[0];
181};
182
183static inline struct rcar_sysc_pd *to_rcar_pd(struct generic_pm_domain *d)
184{
185 return container_of(d, struct rcar_sysc_pd, genpd);
186}
187
188static int rcar_sysc_pd_power_off(struct generic_pm_domain *genpd)
189{
190 struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
191
192 pr_debug("%s: %s\n", __func__, genpd->name);
193
194 if (pd->flags & PD_NO_CR) {
195 pr_debug("%s: Cannot control %s\n", __func__, genpd->name);
196 return -EBUSY;
197 }
198
199 if (pd->flags & PD_BUSY) {
200 pr_debug("%s: %s busy\n", __func__, genpd->name);
201 return -EBUSY;
202 }
203
204 return rcar_sysc_power_down(&pd->ch);
205}
206
207static int rcar_sysc_pd_power_on(struct generic_pm_domain *genpd)
208{
209 struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
210
211 pr_debug("%s: %s\n", __func__, genpd->name);
212
213 if (pd->flags & PD_NO_CR) {
214 pr_debug("%s: Cannot control %s\n", __func__, genpd->name);
215 return 0;
216 }
217
218 return rcar_sysc_power_up(&pd->ch);
219}
220
221static bool has_cpg_mstp;
222
223static void __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd)
224{
225 struct generic_pm_domain *genpd = &pd->genpd;
226 const char *name = pd->genpd.name;
227 struct dev_power_governor *gov = &simple_qos_governor;
228
229 if (pd->flags & PD_CPU) {
230 /*
231 * This domain contains a CPU core and therefore it should
232 * only be turned off if the CPU is not in use.
233 */
234 pr_debug("PM domain %s contains %s\n", name, "CPU");
235 pd->flags |= PD_BUSY;
236 gov = &pm_domain_always_on_gov;
237 } else if (pd->flags & PD_SCU) {
238 /*
239 * This domain contains an SCU and cache-controller, and
240 * therefore it should only be turned off if the CPU cores are
241 * not in use.
242 */
243 pr_debug("PM domain %s contains %s\n", name, "SCU");
244 pd->flags |= PD_BUSY;
245 gov = &pm_domain_always_on_gov;
246 } else if (pd->flags & PD_NO_CR) {
247 /*
248 * This domain cannot be turned off.
249 */
250 pd->flags |= PD_BUSY;
251 gov = &pm_domain_always_on_gov;
252 }
253
254 if (!(pd->flags & (PD_CPU | PD_SCU))) {
255 /* Enable Clock Domain for I/O devices */
256 genpd->flags = GENPD_FLAG_PM_CLK;
257 if (has_cpg_mstp) {
258 genpd->attach_dev = cpg_mstp_attach_dev;
259 genpd->detach_dev = cpg_mstp_detach_dev;
260 } else {
261 genpd->attach_dev = cpg_mssr_attach_dev;
262 genpd->detach_dev = cpg_mssr_detach_dev;
263 }
264 }
265
266 genpd->power_off = rcar_sysc_pd_power_off;
267 genpd->power_on = rcar_sysc_pd_power_on;
268
269 if (pd->flags & (PD_CPU | PD_NO_CR)) {
270 /* Skip CPUs (handled by SMP code) and areas without control */
271 pr_debug("%s: Not touching %s\n", __func__, genpd->name);
272 goto finalize;
273 }
274
275 if (!rcar_sysc_power_is_off(&pd->ch)) {
276 pr_debug("%s: %s is already powered\n", __func__, genpd->name);
277 goto finalize;
278 }
279
280 rcar_sysc_power_up(&pd->ch);
281
282finalize:
283 pm_genpd_init(genpd, gov, false);
284}
285
286static const struct of_device_id rcar_sysc_matches[] = {
287#ifdef CONFIG_ARCH_R8A7779
288 { .compatible = "renesas,r8a7779-sysc", .data = &r8a7779_sysc_info },
289#endif
290#ifdef CONFIG_ARCH_R8A7790
291 { .compatible = "renesas,r8a7790-sysc", .data = &r8a7790_sysc_info },
292#endif
293#ifdef CONFIG_ARCH_R8A7791
294 { .compatible = "renesas,r8a7791-sysc", .data = &r8a7791_sysc_info },
295#endif
296#ifdef CONFIG_ARCH_R8A7793
297 /* R-Car M2-N is identical to R-Car M2-W w.r.t. power domains. */
298 { .compatible = "renesas,r8a7793-sysc", .data = &r8a7791_sysc_info },
299#endif
300#ifdef CONFIG_ARCH_R8A7794
301 { .compatible = "renesas,r8a7794-sysc", .data = &r8a7794_sysc_info },
302#endif
303#ifdef CONFIG_ARCH_R8A7795
304 { .compatible = "renesas,r8a7795-sysc", .data = &r8a7795_sysc_info },
305#endif
306 { /* sentinel */ }
307};
308
309struct rcar_pm_domains {
310 struct genpd_onecell_data onecell_data;
311 struct generic_pm_domain *domains[RCAR_PD_ALWAYS_ON + 1];
312};
313
314static int __init rcar_sysc_pd_init(void)
315{
316 const struct rcar_sysc_info *info;
317 const struct of_device_id *match;
318 struct rcar_pm_domains *domains;
319 struct device_node *np;
320 u32 syscier, syscimr;
321 void __iomem *base;
322 unsigned int i;
323 int error;
324
325 np = of_find_matching_node_and_match(NULL, rcar_sysc_matches, &match);
326 if (!np)
327 return -ENODEV;
328
329 info = match->data;
330
331 has_cpg_mstp = of_find_compatible_node(NULL, NULL,
332 "renesas,cpg-mstp-clocks");
333
334 base = of_iomap(np, 0);
335 if (!base) {
336 pr_warn("%s: Cannot map regs\n", np->full_name);
337 error = -ENOMEM;
338 goto out_put;
339 }
340
341 rcar_sysc_base = base;
342
343 domains = kzalloc(sizeof(*domains), GFP_KERNEL);
344 if (!domains) {
345 error = -ENOMEM;
346 goto out_put;
347 }
348
349 domains->onecell_data.domains = domains->domains;
350 domains->onecell_data.num_domains = ARRAY_SIZE(domains->domains);
351
352 for (i = 0, syscier = 0; i < info->num_areas; i++)
353 syscier |= BIT(info->areas[i].isr_bit);
354
355 /*
356 * Mask all interrupt sources to prevent the CPU from receiving them.
357 * Make sure not to clear reserved bits that were set before.
358 */
359 syscimr = ioread32(base + SYSCIMR);
360 syscimr |= syscier;
361 pr_debug("%s: syscimr = 0x%08x\n", np->full_name, syscimr);
362 iowrite32(syscimr, base + SYSCIMR);
363
364 /*
365 * SYSC needs all interrupt sources enabled to control power.
366 */
367 pr_debug("%s: syscier = 0x%08x\n", np->full_name, syscier);
368 iowrite32(syscier, base + SYSCIER);
369
370 for (i = 0; i < info->num_areas; i++) {
371 const struct rcar_sysc_area *area = &info->areas[i];
372 struct rcar_sysc_pd *pd;
373
374 pd = kzalloc(sizeof(*pd) + strlen(area->name) + 1, GFP_KERNEL);
375 if (!pd) {
376 error = -ENOMEM;
377 goto out_put;
378 }
379
380 strcpy(pd->name, area->name);
381 pd->genpd.name = pd->name;
382 pd->ch.chan_offs = area->chan_offs;
383 pd->ch.chan_bit = area->chan_bit;
384 pd->ch.isr_bit = area->isr_bit;
385 pd->flags = area->flags;
386
387 rcar_sysc_pd_setup(pd);
388 if (area->parent >= 0)
389 pm_genpd_add_subdomain(domains->domains[area->parent],
390 &pd->genpd);
391
392 domains->domains[area->isr_bit] = &pd->genpd;
393 }
394
395 of_genpd_add_provider_onecell(np, &domains->onecell_data);
396
397out_put:
398 of_node_put(np);
399 return error;
400}
401early_initcall(rcar_sysc_pd_init);
diff --git a/drivers/soc/renesas/rcar-sysc.h b/drivers/soc/renesas/rcar-sysc.h
new file mode 100644
index 000000000000..5e766174c2f4
--- /dev/null
+++ b/drivers/soc/renesas/rcar-sysc.h
@@ -0,0 +1,58 @@
1/*
2 * Renesas R-Car System Controller
3 *
4 * Copyright (C) 2016 Glider bvba
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10#ifndef __SOC_RENESAS_RCAR_SYSC_H__
11#define __SOC_RENESAS_RCAR_SYSC_H__
12
13#include <linux/types.h>
14
15
16/*
17 * Power Domain flags
18 */
19#define PD_CPU BIT(0) /* Area contains main CPU core */
20#define PD_SCU BIT(1) /* Area contains SCU and L2 cache */
21#define PD_NO_CR BIT(2) /* Area lacks PWR{ON,OFF}CR registers */
22
23#define PD_BUSY BIT(3) /* Busy, for internal use only */
24
25#define PD_CPU_CR PD_CPU /* CPU area has CR (R-Car H1) */
26#define PD_CPU_NOCR PD_CPU | PD_NO_CR /* CPU area lacks CR (R-Car Gen2/3) */
27#define PD_ALWAYS_ON PD_NO_CR /* Always-on area */
28
29
30/*
31 * Description of a Power Area
32 */
33
34struct rcar_sysc_area {
35 const char *name;
36 u16 chan_offs; /* Offset of PWRSR register for this area */
37 u8 chan_bit; /* Bit in PWR* (except for PWRUP in PWRSR) */
38 u8 isr_bit; /* Bit in SYSCI*R */
39 int parent; /* -1 if none */
40 unsigned int flags; /* See PD_* */
41};
42
43
44/*
45 * SoC-specific Power Area Description
46 */
47
48struct rcar_sysc_info {
49 const struct rcar_sysc_area *areas;
50 unsigned int num_areas;
51};
52
53extern const struct rcar_sysc_info r8a7779_sysc_info;
54extern const struct rcar_sysc_info r8a7790_sysc_info;
55extern const struct rcar_sysc_info r8a7791_sysc_info;
56extern const struct rcar_sysc_info r8a7794_sysc_info;
57extern const struct rcar_sysc_info r8a7795_sysc_info;
58#endif /* __SOC_RENESAS_RCAR_SYSC_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-09 20:10:02 -0500