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authorBart Van Assche <bart.vanassche@sandisk.com>2015-07-09 10:24:50 -0400
committerJames Bottomley <JBottomley@Odin.com>2015-08-26 13:42:25 -0400
commit8dfa4b5a9b44714d7710f9f452f65763629f10df (patch)
tree5a26d650c7e02b235872fbe434b88b797833c44f /drivers/scsi/qla2xxx
parent118e2ef9df2297147706d21d2a1dfeefea878c5a (diff)
qla2xxx: Fix sparse annotations
This patch removes 21 casts between an __iomem pointer type and another data type but also introduces five new casts (see also the casts with "__force"). Although this patch does not change any functionality, IMHO the code with __force casts needs further review. Signed-off-by: Bart Van Assche <bart.vanassche@sandisk.com> Acked-by: Himanshu Madhani <himanshu.madhani@qlogic.com> Signed-off-by: James Bottomley <JBottomley@Odin.com>
Diffstat (limited to 'drivers/scsi/qla2xxx')
-rw-r--r--drivers/scsi/qla2xxx/qla_def.h6
-rw-r--r--drivers/scsi/qla2xxx/qla_iocb.c12
-rw-r--r--drivers/scsi/qla2xxx/qla_mbx.c2
-rw-r--r--drivers/scsi/qla2xxx/qla_mr.c6
-rw-r--r--drivers/scsi/qla2xxx/qla_nx.c107
-rw-r--r--drivers/scsi/qla2xxx/qla_tmpl.c20
6 files changed, 71 insertions, 82 deletions
diff --git a/drivers/scsi/qla2xxx/qla_def.h b/drivers/scsi/qla2xxx/qla_def.h
index e86201d3b8c6..ac88c4e7cf13 100644
--- a/drivers/scsi/qla2xxx/qla_def.h
+++ b/drivers/scsi/qla2xxx/qla_def.h
@@ -3418,9 +3418,9 @@ struct qla_hw_data {
3418 mempool_t *ctx_mempool; 3418 mempool_t *ctx_mempool;
3419#define FCP_CMND_DMA_POOL_SIZE 512 3419#define FCP_CMND_DMA_POOL_SIZE 512
3420 3420
3421 unsigned long nx_pcibase; /* Base I/O address */ 3421 void __iomem *nx_pcibase; /* Base I/O address */
3422 uint8_t *nxdb_rd_ptr; /* Doorbell read pointer */ 3422 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */
3423 unsigned long nxdb_wr_ptr; /* Door bell write pointer */ 3423 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */
3424 3424
3425 uint32_t crb_win; 3425 uint32_t crb_win;
3426 uint32_t curr_window; 3426 uint32_t curr_window;
diff --git a/drivers/scsi/qla2xxx/qla_iocb.c b/drivers/scsi/qla2xxx/qla_iocb.c
index 5c0bf290d5df..e07161c1eda1 100644
--- a/drivers/scsi/qla2xxx/qla_iocb.c
+++ b/drivers/scsi/qla2xxx/qla_iocb.c
@@ -2507,16 +2507,12 @@ sufficient_dsds:
2507 /* write, read and verify logic */ 2507 /* write, read and verify logic */
2508 dbval = dbval | (req->id << 8) | (req->ring_index << 16); 2508 dbval = dbval | (req->id << 8) | (req->ring_index << 16);
2509 if (ql2xdbwr) 2509 if (ql2xdbwr)
2510 qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval); 2510 qla82xx_wr_32(ha, (uintptr_t __force)ha->nxdb_wr_ptr, dbval);
2511 else { 2511 else {
2512 WRT_REG_DWORD( 2512 WRT_REG_DWORD(ha->nxdb_wr_ptr, dbval);
2513 (unsigned long __iomem *)ha->nxdb_wr_ptr,
2514 dbval);
2515 wmb(); 2513 wmb();
2516 while (RD_REG_DWORD((void __iomem *)ha->nxdb_rd_ptr) != dbval) { 2514 while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) {
2517 WRT_REG_DWORD( 2515 WRT_REG_DWORD(ha->nxdb_wr_ptr, dbval);
2518 (unsigned long __iomem *)ha->nxdb_wr_ptr,
2519 dbval);
2520 wmb(); 2516 wmb();
2521 } 2517 }
2522 } 2518 }
diff --git a/drivers/scsi/qla2xxx/qla_mbx.c b/drivers/scsi/qla2xxx/qla_mbx.c
index 0c5477f1bfba..26ca18c3fa6a 100644
--- a/drivers/scsi/qla2xxx/qla_mbx.c
+++ b/drivers/scsi/qla2xxx/qla_mbx.c
@@ -1239,7 +1239,7 @@ qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
1239 "Entered %s.\n", __func__); 1239 "Entered %s.\n", __func__);
1240 1240
1241 if (IS_P3P_TYPE(ha) && ql2xdbwr) 1241 if (IS_P3P_TYPE(ha) && ql2xdbwr)
1242 qla82xx_wr_32(ha, ha->nxdb_wr_ptr, 1242 qla82xx_wr_32(ha, (uintptr_t __force)ha->nxdb_wr_ptr,
1243 (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16))); 1243 (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16)));
1244 1244
1245 if (ha->flags.npiv_supported) 1245 if (ha->flags.npiv_supported)
diff --git a/drivers/scsi/qla2xxx/qla_mr.c b/drivers/scsi/qla2xxx/qla_mr.c
index 2d798e6fadb3..b5029e543b91 100644
--- a/drivers/scsi/qla2xxx/qla_mr.c
+++ b/drivers/scsi/qla2xxx/qla_mr.c
@@ -862,7 +862,7 @@ qlafx00_config_queues(struct scsi_qla_host *vha)
862 dma_addr_t bar2_hdl = pci_resource_start(ha->pdev, 2); 862 dma_addr_t bar2_hdl = pci_resource_start(ha->pdev, 2);
863 863
864 req->length = ha->req_que_len; 864 req->length = ha->req_que_len;
865 req->ring = (void *)ha->iobase + ha->req_que_off; 865 req->ring = (void __force *)ha->iobase + ha->req_que_off;
866 req->dma = bar2_hdl + ha->req_que_off; 866 req->dma = bar2_hdl + ha->req_que_off;
867 if ((!req->ring) || (req->length == 0)) { 867 if ((!req->ring) || (req->length == 0)) {
868 ql_log_pci(ql_log_info, ha->pdev, 0x012f, 868 ql_log_pci(ql_log_info, ha->pdev, 0x012f,
@@ -877,7 +877,7 @@ qlafx00_config_queues(struct scsi_qla_host *vha)
877 ha->req_que_off, (u64)req->dma); 877 ha->req_que_off, (u64)req->dma);
878 878
879 rsp->length = ha->rsp_que_len; 879 rsp->length = ha->rsp_que_len;
880 rsp->ring = (void *)ha->iobase + ha->rsp_que_off; 880 rsp->ring = (void __force *)ha->iobase + ha->rsp_que_off;
881 rsp->dma = bar2_hdl + ha->rsp_que_off; 881 rsp->dma = bar2_hdl + ha->rsp_que_off;
882 if ((!rsp->ring) || (rsp->length == 0)) { 882 if ((!rsp->ring) || (rsp->length == 0)) {
883 ql_log_pci(ql_log_info, ha->pdev, 0x0131, 883 ql_log_pci(ql_log_info, ha->pdev, 0x0131,
@@ -1425,7 +1425,7 @@ qlafx00_init_response_q_entries(struct rsp_que *rsp)
1425 pkt = rsp->ring_ptr; 1425 pkt = rsp->ring_ptr;
1426 for (cnt = 0; cnt < rsp->length; cnt++) { 1426 for (cnt = 0; cnt < rsp->length; cnt++) {
1427 pkt->signature = RESPONSE_PROCESSED; 1427 pkt->signature = RESPONSE_PROCESSED;
1428 WRT_REG_DWORD((void __iomem *)&pkt->signature, 1428 WRT_REG_DWORD((void __force __iomem *)&pkt->signature,
1429 RESPONSE_PROCESSED); 1429 RESPONSE_PROCESSED);
1430 pkt++; 1430 pkt++;
1431 } 1431 }
diff --git a/drivers/scsi/qla2xxx/qla_nx.c b/drivers/scsi/qla2xxx/qla_nx.c
index 264be49d0490..3d3ea84cca07 100644
--- a/drivers/scsi/qla2xxx/qla_nx.c
+++ b/drivers/scsi/qla2xxx/qla_nx.c
@@ -347,32 +347,31 @@ char *qdev_state(uint32_t dev_state)
347} 347}
348 348
349/* 349/*
350 * In: 'off' is offset from CRB space in 128M pci map 350 * In: 'off_in' is offset from CRB space in 128M pci map
351 * Out: 'off' is 2M pci map addr 351 * Out: 'off_out' is 2M pci map addr
352 * side effect: lock crb window 352 * side effect: lock crb window
353 */ 353 */
354static void 354static void
355qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off) 355qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong off_in,
356 void __iomem **off_out)
356{ 357{
357 u32 win_read; 358 u32 win_read;
358 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 359 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
359 360
360 ha->crb_win = CRB_HI(*off); 361 ha->crb_win = CRB_HI(off_in);
361 writel(ha->crb_win, 362 writel(ha->crb_win, CRB_WINDOW_2M + ha->nx_pcibase);
362 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
363 363
364 /* Read back value to make sure write has gone through before trying 364 /* Read back value to make sure write has gone through before trying
365 * to use it. 365 * to use it.
366 */ 366 */
367 win_read = RD_REG_DWORD((void __iomem *) 367 win_read = RD_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase);
368 (CRB_WINDOW_2M + ha->nx_pcibase));
369 if (win_read != ha->crb_win) { 368 if (win_read != ha->crb_win) {
370 ql_dbg(ql_dbg_p3p, vha, 0xb000, 369 ql_dbg(ql_dbg_p3p, vha, 0xb000,
371 "%s: Written crbwin (0x%x) " 370 "%s: Written crbwin (0x%x) "
372 "!= Read crbwin (0x%x), off=0x%lx.\n", 371 "!= Read crbwin (0x%x), off=0x%lx.\n",
373 __func__, ha->crb_win, win_read, *off); 372 __func__, ha->crb_win, win_read, off_in);
374 } 373 }
375 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 374 *off_out = (off_in & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
376} 375}
377 376
378static inline unsigned long 377static inline unsigned long
@@ -417,29 +416,30 @@ qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off)
417} 416}
418 417
419static int 418static int
420qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off) 419qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong off_in,
420 void __iomem **off_out)
421{ 421{
422 struct crb_128M_2M_sub_block_map *m; 422 struct crb_128M_2M_sub_block_map *m;
423 423
424 if (*off >= QLA82XX_CRB_MAX) 424 if (off_in >= QLA82XX_CRB_MAX)
425 return -1; 425 return -1;
426 426
427 if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) { 427 if (off_in >= QLA82XX_PCI_CAMQM && off_in < QLA82XX_PCI_CAMQM_2M_END) {
428 *off = (*off - QLA82XX_PCI_CAMQM) + 428 *off_out = (off_in - QLA82XX_PCI_CAMQM) +
429 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 429 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
430 return 0; 430 return 0;
431 } 431 }
432 432
433 if (*off < QLA82XX_PCI_CRBSPACE) 433 if (off_in < QLA82XX_PCI_CRBSPACE)
434 return -1; 434 return -1;
435 435
436 *off -= QLA82XX_PCI_CRBSPACE; 436 *off_out = (void __iomem *)(off_in - QLA82XX_PCI_CRBSPACE);
437 437
438 /* Try direct map */ 438 /* Try direct map */
439 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; 439 m = &crb_128M_2M_map[CRB_BLK(off_in)].sub_block[CRB_SUBBLK(off_in)];
440 440
441 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { 441 if (m->valid && (m->start_128M <= off_in) && (m->end_128M > off_in)) {
442 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; 442 *off_out = off_in + m->start_2M - m->start_128M + ha->nx_pcibase;
443 return 0; 443 return 0;
444 } 444 }
445 /* Not in direct map, use crb window */ 445 /* Not in direct map, use crb window */
@@ -465,19 +465,20 @@ static int qla82xx_crb_win_lock(struct qla_hw_data *ha)
465} 465}
466 466
467int 467int
468qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data) 468qla82xx_wr_32(struct qla_hw_data *ha, ulong off_in, u32 data)
469{ 469{
470 void __iomem *off;
470 unsigned long flags = 0; 471 unsigned long flags = 0;
471 int rv; 472 int rv;
472 473
473 rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 474 rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off);
474 475
475 BUG_ON(rv == -1); 476 BUG_ON(rv == -1);
476 477
477 if (rv == 1) { 478 if (rv == 1) {
478 write_lock_irqsave(&ha->hw_lock, flags); 479 write_lock_irqsave(&ha->hw_lock, flags);
479 qla82xx_crb_win_lock(ha); 480 qla82xx_crb_win_lock(ha);
480 qla82xx_pci_set_crbwindow_2M(ha, &off); 481 qla82xx_pci_set_crbwindow_2M(ha, off_in, &off);
481 } 482 }
482 483
483 writel(data, (void __iomem *)off); 484 writel(data, (void __iomem *)off);
@@ -490,22 +491,23 @@ qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data)
490} 491}
491 492
492int 493int
493qla82xx_rd_32(struct qla_hw_data *ha, ulong off) 494qla82xx_rd_32(struct qla_hw_data *ha, ulong off_in)
494{ 495{
496 void __iomem *off;
495 unsigned long flags = 0; 497 unsigned long flags = 0;
496 int rv; 498 int rv;
497 u32 data; 499 u32 data;
498 500
499 rv = qla82xx_pci_get_crb_addr_2M(ha, &off); 501 rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off);
500 502
501 BUG_ON(rv == -1); 503 BUG_ON(rv == -1);
502 504
503 if (rv == 1) { 505 if (rv == 1) {
504 write_lock_irqsave(&ha->hw_lock, flags); 506 write_lock_irqsave(&ha->hw_lock, flags);
505 qla82xx_crb_win_lock(ha); 507 qla82xx_crb_win_lock(ha);
506 qla82xx_pci_set_crbwindow_2M(ha, &off); 508 qla82xx_pci_set_crbwindow_2M(ha, off_in, &off);
507 } 509 }
508 data = RD_REG_DWORD((void __iomem *)off); 510 data = RD_REG_DWORD(off);
509 511
510 if (rv == 1) { 512 if (rv == 1) {
511 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 513 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
@@ -919,20 +921,18 @@ qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag)
919{ 921{
920 uint32_t off_value, rval = 0; 922 uint32_t off_value, rval = 0;
921 923
922 WRT_REG_DWORD((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase), 924 WRT_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase, off & 0xFFFF0000);
923 (off & 0xFFFF0000));
924 925
925 /* Read back value to make sure write has gone through */ 926 /* Read back value to make sure write has gone through */
926 RD_REG_DWORD((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 927 RD_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase);
927 off_value = (off & 0x0000FFFF); 928 off_value = (off & 0x0000FFFF);
928 929
929 if (flag) 930 if (flag)
930 WRT_REG_DWORD((void __iomem *) 931 WRT_REG_DWORD(off_value + CRB_INDIRECT_2M + ha->nx_pcibase,
931 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase), 932 data);
932 data);
933 else 933 else
934 rval = RD_REG_DWORD((void __iomem *) 934 rval = RD_REG_DWORD(off_value + CRB_INDIRECT_2M +
935 (off_value + CRB_INDIRECT_2M + ha->nx_pcibase)); 935 ha->nx_pcibase);
936 936
937 return rval; 937 return rval;
938} 938}
@@ -1660,8 +1660,7 @@ qla82xx_iospace_config(struct qla_hw_data *ha)
1660 } 1660 }
1661 1661
1662 len = pci_resource_len(ha->pdev, 0); 1662 len = pci_resource_len(ha->pdev, 0);
1663 ha->nx_pcibase = 1663 ha->nx_pcibase = ioremap(pci_resource_start(ha->pdev, 0), len);
1664 (unsigned long)ioremap(pci_resource_start(ha->pdev, 0), len);
1665 if (!ha->nx_pcibase) { 1664 if (!ha->nx_pcibase) {
1666 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e, 1665 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e,
1667 "Cannot remap pcibase MMIO, aborting.\n"); 1666 "Cannot remap pcibase MMIO, aborting.\n");
@@ -1670,17 +1669,13 @@ qla82xx_iospace_config(struct qla_hw_data *ha)
1670 1669
1671 /* Mapping of IO base pointer */ 1670 /* Mapping of IO base pointer */
1672 if (IS_QLA8044(ha)) { 1671 if (IS_QLA8044(ha)) {
1673 ha->iobase = 1672 ha->iobase = ha->nx_pcibase;
1674 (device_reg_t *)((uint8_t *)ha->nx_pcibase);
1675 } else if (IS_QLA82XX(ha)) { 1673 } else if (IS_QLA82XX(ha)) {
1676 ha->iobase = 1674 ha->iobase = ha->nx_pcibase + 0xbc000 + (ha->pdev->devfn << 11);
1677 (device_reg_t *)((uint8_t *)ha->nx_pcibase +
1678 0xbc000 + (ha->pdev->devfn << 11));
1679 } 1675 }
1680 1676
1681 if (!ql2xdbwr) { 1677 if (!ql2xdbwr) {
1682 ha->nxdb_wr_ptr = 1678 ha->nxdb_wr_ptr = ioremap((pci_resource_start(ha->pdev, 4) +
1683 (unsigned long)ioremap((pci_resource_start(ha->pdev, 4) +
1684 (ha->pdev->devfn << 12)), 4); 1679 (ha->pdev->devfn << 12)), 4);
1685 if (!ha->nxdb_wr_ptr) { 1680 if (!ha->nxdb_wr_ptr) {
1686 ql_log_pci(ql_log_fatal, ha->pdev, 0x000f, 1681 ql_log_pci(ql_log_fatal, ha->pdev, 0x000f,
@@ -1691,10 +1686,10 @@ qla82xx_iospace_config(struct qla_hw_data *ha)
1691 /* Mapping of IO base pointer, 1686 /* Mapping of IO base pointer,
1692 * door bell read and write pointer 1687 * door bell read and write pointer
1693 */ 1688 */
1694 ha->nxdb_rd_ptr = (uint8_t *) ha->nx_pcibase + (512 * 1024) + 1689 ha->nxdb_rd_ptr = ha->nx_pcibase + (512 * 1024) +
1695 (ha->pdev->devfn * 8); 1690 (ha->pdev->devfn * 8);
1696 } else { 1691 } else {
1697 ha->nxdb_wr_ptr = (ha->pdev->devfn == 6 ? 1692 ha->nxdb_wr_ptr = (void __iomem *)(ha->pdev->devfn == 6 ?
1698 QLA82XX_CAMRAM_DB1 : 1693 QLA82XX_CAMRAM_DB1 :
1699 QLA82XX_CAMRAM_DB2); 1694 QLA82XX_CAMRAM_DB2);
1700 } 1695 }
@@ -1704,12 +1699,12 @@ qla82xx_iospace_config(struct qla_hw_data *ha)
1704 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006, 1699 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006,
1705 "nx_pci_base=%p iobase=%p " 1700 "nx_pci_base=%p iobase=%p "
1706 "max_req_queues=%d msix_count=%d.\n", 1701 "max_req_queues=%d msix_count=%d.\n",
1707 (void *)ha->nx_pcibase, ha->iobase, 1702 ha->nx_pcibase, ha->iobase,
1708 ha->max_req_queues, ha->msix_count); 1703 ha->max_req_queues, ha->msix_count);
1709 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010, 1704 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010,
1710 "nx_pci_base=%p iobase=%p " 1705 "nx_pci_base=%p iobase=%p "
1711 "max_req_queues=%d msix_count=%d.\n", 1706 "max_req_queues=%d msix_count=%d.\n",
1712 (void *)ha->nx_pcibase, ha->iobase, 1707 ha->nx_pcibase, ha->iobase,
1713 ha->max_req_queues, ha->msix_count); 1708 ha->max_req_queues, ha->msix_count);
1714 return 0; 1709 return 0;
1715 1710
@@ -1774,9 +1769,9 @@ void qla82xx_config_rings(struct scsi_qla_host *vha)
1774 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); 1769 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1775 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); 1770 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
1776 1771
1777 WRT_REG_DWORD((unsigned long __iomem *)&reg->req_q_out[0], 0); 1772 WRT_REG_DWORD(&reg->req_q_out[0], 0);
1778 WRT_REG_DWORD((unsigned long __iomem *)&reg->rsp_q_in[0], 0); 1773 WRT_REG_DWORD(&reg->rsp_q_in[0], 0);
1779 WRT_REG_DWORD((unsigned long __iomem *)&reg->rsp_q_out[0], 0); 1774 WRT_REG_DWORD(&reg->rsp_q_out[0], 0);
1780} 1775}
1781 1776
1782static int 1777static int
@@ -2799,13 +2794,12 @@ qla82xx_start_iocbs(scsi_qla_host_t *vha)
2799 2794
2800 dbval = dbval | (req->id << 8) | (req->ring_index << 16); 2795 dbval = dbval | (req->id << 8) | (req->ring_index << 16);
2801 if (ql2xdbwr) 2796 if (ql2xdbwr)
2802 qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval); 2797 qla82xx_wr_32(ha, (unsigned long)ha->nxdb_wr_ptr, dbval);
2803 else { 2798 else {
2804 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval); 2799 WRT_REG_DWORD(ha->nxdb_wr_ptr, dbval);
2805 wmb(); 2800 wmb();
2806 while (RD_REG_DWORD((void __iomem *)ha->nxdb_rd_ptr) != dbval) { 2801 while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) {
2807 WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, 2802 WRT_REG_DWORD(ha->nxdb_wr_ptr, dbval);
2808 dbval);
2809 wmb(); 2803 wmb();
2810 } 2804 }
2811 } 2805 }
@@ -3836,8 +3830,7 @@ qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha,
3836 loop_cnt = ocm_hdr->op_count; 3830 loop_cnt = ocm_hdr->op_count;
3837 3831
3838 for (i = 0; i < loop_cnt; i++) { 3832 for (i = 0; i < loop_cnt; i++) {
3839 r_value = RD_REG_DWORD((void __iomem *) 3833 r_value = RD_REG_DWORD(r_addr + ha->nx_pcibase);
3840 (r_addr + ha->nx_pcibase));
3841 *data_ptr++ = cpu_to_le32(r_value); 3834 *data_ptr++ = cpu_to_le32(r_value);
3842 r_addr += r_stride; 3835 r_addr += r_stride;
3843 } 3836 }
diff --git a/drivers/scsi/qla2xxx/qla_tmpl.c b/drivers/scsi/qla2xxx/qla_tmpl.c
index 7e876d1e2f78..f4eb65524ae4 100644
--- a/drivers/scsi/qla2xxx/qla_tmpl.c
+++ b/drivers/scsi/qla2xxx/qla_tmpl.c
@@ -137,39 +137,39 @@ qla27xx_insertbuf(void *mem, ulong size, void *buf, ulong *len)
137} 137}
138 138
139static inline void 139static inline void
140qla27xx_read8(void *window, void *buf, ulong *len) 140qla27xx_read8(void __iomem *window, void *buf, ulong *len)
141{ 141{
142 uint8_t value = ~0; 142 uint8_t value = ~0;
143 143
144 if (buf) { 144 if (buf) {
145 value = RD_REG_BYTE((__iomem void *)window); 145 value = RD_REG_BYTE(window);
146 } 146 }
147 qla27xx_insert32(value, buf, len); 147 qla27xx_insert32(value, buf, len);
148} 148}
149 149
150static inline void 150static inline void
151qla27xx_read16(void *window, void *buf, ulong *len) 151qla27xx_read16(void __iomem *window, void *buf, ulong *len)
152{ 152{
153 uint16_t value = ~0; 153 uint16_t value = ~0;
154 154
155 if (buf) { 155 if (buf) {
156 value = RD_REG_WORD((__iomem void *)window); 156 value = RD_REG_WORD(window);
157 } 157 }
158 qla27xx_insert32(value, buf, len); 158 qla27xx_insert32(value, buf, len);
159} 159}
160 160
161static inline void 161static inline void
162qla27xx_read32(void *window, void *buf, ulong *len) 162qla27xx_read32(void __iomem *window, void *buf, ulong *len)
163{ 163{
164 uint32_t value = ~0; 164 uint32_t value = ~0;
165 165
166 if (buf) { 166 if (buf) {
167 value = RD_REG_DWORD((__iomem void *)window); 167 value = RD_REG_DWORD(window);
168 } 168 }
169 qla27xx_insert32(value, buf, len); 169 qla27xx_insert32(value, buf, len);
170} 170}
171 171
172static inline void (*qla27xx_read_vector(uint width))(void *, void *, ulong *) 172static inline void (*qla27xx_read_vector(uint width))(void __iomem*, void *, ulong *)
173{ 173{
174 return 174 return
175 (width == 1) ? qla27xx_read8 : 175 (width == 1) ? qla27xx_read8 :
@@ -181,7 +181,7 @@ static inline void
181qla27xx_read_reg(__iomem struct device_reg_24xx *reg, 181qla27xx_read_reg(__iomem struct device_reg_24xx *reg,
182 uint offset, void *buf, ulong *len) 182 uint offset, void *buf, ulong *len)
183{ 183{
184 void *window = (void *)reg + offset; 184 void __iomem *window = (void __iomem *)reg + offset;
185 185
186 qla27xx_read32(window, buf, len); 186 qla27xx_read32(window, buf, len);
187} 187}
@@ -202,8 +202,8 @@ qla27xx_read_window(__iomem struct device_reg_24xx *reg,
202 uint32_t addr, uint offset, uint count, uint width, void *buf, 202 uint32_t addr, uint offset, uint count, uint width, void *buf,
203 ulong *len) 203 ulong *len)
204{ 204{
205 void *window = (void *)reg + offset; 205 void __iomem *window = (void __iomem *)reg + offset;
206 void (*readn)(void *, void *, ulong *) = qla27xx_read_vector(width); 206 void (*readn)(void __iomem*, void *, ulong *) = qla27xx_read_vector(width);
207 207
208 qla27xx_write_reg(reg, IOBASE_ADDR, addr, buf); 208 qla27xx_write_reg(reg, IOBASE_ADDR, addr, buf);
209 while (count--) { 209 while (count--) {
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-22 09:41:30 -0400