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authorChristoph Hellwig <hch@lst.de>2015-11-11 07:00:17 -0500
committerMartin K. Petersen <martin.petersen@oracle.com>2015-11-11 18:11:23 -0500
commit3c5866565f37d45e3b812e3045caf2358f2f2377 (patch)
tree86c6c4a2e284b401bb56c30a9ce8659732810dd3 /drivers/scsi/mpt2sas/mpi
parent2a188cb42b43b7a579c2b6d0e9fa095182333540 (diff)
mpt2sas: Use mpi headers from mpt3sas
Use a single set of the hardware description headers instead of having them in the source tree twice. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Sreekanth Reddy <sreekanth.reddy@avagotech.com> Reviewed-by: Hannes Reinecke <hare@suse.de> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'drivers/scsi/mpt2sas/mpi')
-rw-r--r--drivers/scsi/mpt2sas/mpi/mpi2.h1170
-rw-r--r--drivers/scsi/mpt2sas/mpi/mpi2_cnfg.h3068
-rw-r--r--drivers/scsi/mpt2sas/mpi/mpi2_init.h461
-rw-r--r--drivers/scsi/mpt2sas/mpi/mpi2_ioc.h1708
-rw-r--r--drivers/scsi/mpt2sas/mpi/mpi2_raid.h366
-rw-r--r--drivers/scsi/mpt2sas/mpi/mpi2_sas.h288
-rw-r--r--drivers/scsi/mpt2sas/mpi/mpi2_tool.h481
-rw-r--r--drivers/scsi/mpt2sas/mpi/mpi2_type.h61
8 files changed, 0 insertions, 7603 deletions
diff --git a/drivers/scsi/mpt2sas/mpi/mpi2.h b/drivers/scsi/mpt2sas/mpi/mpi2.h
deleted file mode 100644
index 7fc6f23bd9dc..000000000000
--- a/drivers/scsi/mpt2sas/mpi/mpi2.h
+++ /dev/null
@@ -1,1170 +0,0 @@
1/*
2 * Copyright (c) 2000-2014 LSI Corporation.
3 *
4 *
5 * Name: mpi2.h
6 * Title: MPI Message independent structures and definitions
7 * including System Interface Register Set and
8 * scatter/gather formats.
9 * Creation Date: June 21, 2006
10 *
11 * mpi2.h Version: 02.00.35
12 *
13 * Version History
14 * ---------------
15 *
16 * Date Version Description
17 * -------- -------- ------------------------------------------------------
18 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
19 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT.
20 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT.
21 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT.
22 * Moved ReplyPostHostIndex register to offset 0x6C of the
23 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for
24 * MPI2_REPLY_POST_HOST_INDEX_OFFSET.
25 * Added union of request descriptors.
26 * Added union of reply descriptors.
27 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT.
28 * Added define for MPI2_VERSION_02_00.
29 * Fixed the size of the FunctionDependent5 field in the
30 * MPI2_DEFAULT_REPLY structure.
31 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT.
32 * Removed the MPI-defined Fault Codes and extended the
33 * product specific codes up to 0xEFFF.
34 * Added a sixth key value for the WriteSequence register
35 * and changed the flush value to 0x0.
36 * Added message function codes for Diagnostic Buffer Post
37 * and Diagnsotic Release.
38 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
39 * Moved MPI2_VERSION_UNION from mpi2_ioc.h.
40 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT.
41 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT.
42 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT.
43 * Added #defines for marking a reply descriptor as unused.
44 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT.
45 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT.
46 * Moved LUN field defines from mpi2_init.h.
47 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT.
48 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT.
49 * In all request and reply descriptors, replaced VF_ID
50 * field with MSIxIndex field.
51 * Removed DevHandle field from
52 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
53 * bytes reserved.
54 * Added RAID Accelerator functionality.
55 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT.
56 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT.
57 * Added MSI-x index mask and shift for Reply Post Host
58 * Index register.
59 * Added function code for Host Based Discovery Action.
60 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT.
61 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL.
62 * Added defines for product-specific range of message
63 * function codes, 0xF0 to 0xFF.
64 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT.
65 * Added alternative defines for the SGE Direction bit.
66 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT.
67 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT.
68 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define.
69 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT.
70 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE.
71 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT.
72 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT.
73 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT.
74 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT.
75 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT.
76 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT.
77 * Added Hard Reset delay timings.
78 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT.
79 * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT.
80 * 11-27-12 02.00.28 Bumped MPI2_HEADER_VERSION_UNIT.
81 * 12-20-12 02.00.29 Bumped MPI2_HEADER_VERSION_UNIT.
82 * Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET.
83 * 04-09-13 02.00.30 Bumped MPI2_HEADER_VERSION_UNIT.
84 * 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT.
85 * 08-19-13 02.00.32 Bumped MPI2_HEADER_VERSION_UNIT.
86 * 12-05-13 02.00.33 Bumped MPI2_HEADER_VERSION_UNIT.
87 * 01-08-14 02.00.34 Bumped MPI2_HEADER_VERSION_UNIT.
88 * 06-13-14 02.00.35 Bumped MPI2_HEADER_VERSION_UNIT.
89 * --------------------------------------------------------------------------
90 */
91
92#ifndef MPI2_H
93#define MPI2_H
94
95
96/*****************************************************************************
97*
98* MPI Version Definitions
99*
100*****************************************************************************/
101
102#define MPI2_VERSION_MAJOR (0x02)
103#define MPI2_VERSION_MINOR (0x00)
104#define MPI2_VERSION_MAJOR_MASK (0xFF00)
105#define MPI2_VERSION_MAJOR_SHIFT (8)
106#define MPI2_VERSION_MINOR_MASK (0x00FF)
107#define MPI2_VERSION_MINOR_SHIFT (0)
108#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
109 MPI2_VERSION_MINOR)
110
111#define MPI2_VERSION_02_00 (0x0200)
112
113/* versioning for this MPI header set */
114#define MPI2_HEADER_VERSION_UNIT (0x23)
115#define MPI2_HEADER_VERSION_DEV (0x00)
116#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
117#define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
118#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
119#define MPI2_HEADER_VERSION_DEV_SHIFT (0)
120#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV)
121
122
123/*****************************************************************************
124*
125* IOC State Definitions
126*
127*****************************************************************************/
128
129#define MPI2_IOC_STATE_RESET (0x00000000)
130#define MPI2_IOC_STATE_READY (0x10000000)
131#define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
132#define MPI2_IOC_STATE_FAULT (0x40000000)
133
134#define MPI2_IOC_STATE_MASK (0xF0000000)
135#define MPI2_IOC_STATE_SHIFT (28)
136
137/* Fault state range for prodcut specific codes */
138#define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000)
139#define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF)
140
141
142/*****************************************************************************
143*
144* System Interface Register Definitions
145*
146*****************************************************************************/
147
148typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS
149{
150 U32 Doorbell; /* 0x00 */
151 U32 WriteSequence; /* 0x04 */
152 U32 HostDiagnostic; /* 0x08 */
153 U32 Reserved1; /* 0x0C */
154 U32 DiagRWData; /* 0x10 */
155 U32 DiagRWAddressLow; /* 0x14 */
156 U32 DiagRWAddressHigh; /* 0x18 */
157 U32 Reserved2[5]; /* 0x1C */
158 U32 HostInterruptStatus; /* 0x30 */
159 U32 HostInterruptMask; /* 0x34 */
160 U32 DCRData; /* 0x38 */
161 U32 DCRAddress; /* 0x3C */
162 U32 Reserved3[2]; /* 0x40 */
163 U32 ReplyFreeHostIndex; /* 0x48 */
164 U32 Reserved4[8]; /* 0x4C */
165 U32 ReplyPostHostIndex; /* 0x6C */
166 U32 Reserved5; /* 0x70 */
167 U32 HCBSize; /* 0x74 */
168 U32 HCBAddressLow; /* 0x78 */
169 U32 HCBAddressHigh; /* 0x7C */
170 U32 Reserved6[16]; /* 0x80 */
171 U32 RequestDescriptorPostLow; /* 0xC0 */
172 U32 RequestDescriptorPostHigh; /* 0xC4 */
173 U32 Reserved7[14]; /* 0xC8 */
174} MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS,
175 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t;
176
177/*
178 * Defines for working with the Doorbell register.
179 */
180#define MPI2_DOORBELL_OFFSET (0x00000000)
181
182/* IOC --> System values */
183#define MPI2_DOORBELL_USED (0x08000000)
184#define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
185#define MPI2_DOORBELL_WHO_INIT_SHIFT (24)
186#define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
187#define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
188
189/* System --> IOC values */
190#define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
191#define MPI2_DOORBELL_FUNCTION_SHIFT (24)
192#define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
193#define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16)
194
195
196/*
197 * Defines for the WriteSequence register
198 */
199#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
200#define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
201#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
202#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
203#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
204#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
205#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
206#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
207#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
208
209/*
210 * Defines for the HostDiagnostic register
211 */
212#define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
213
214#define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
215#define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
216#define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
217
218#define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
219#define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
220#define MPI2_DIAG_HCB_MODE (0x00000100)
221#define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
222#define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
223#define MPI2_DIAG_RESET_HISTORY (0x00000020)
224#define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
225#define MPI2_DIAG_RESET_ADAPTER (0x00000004)
226#define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
227
228/*
229 * Offsets for DiagRWData and address
230 */
231#define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
232#define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
233#define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
234
235/*
236 * Defines for the HostInterruptStatus register
237 */
238#define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030)
239#define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000)
240#define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS
241#define MPI2_HIS_RESET_IRQ_STATUS (0x40000000)
242#define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008)
243#define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001)
244#define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS
245
246/*
247 * Defines for the HostInterruptMask register
248 */
249#define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034)
250#define MPI2_HIM_RESET_IRQ_MASK (0x40000000)
251#define MPI2_HIM_REPLY_INT_MASK (0x00000008)
252#define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK
253#define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001)
254#define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK
255
256/*
257 * Offsets for DCRData and address
258 */
259#define MPI2_DCR_DATA_OFFSET (0x00000038)
260#define MPI2_DCR_ADDRESS_OFFSET (0x0000003C)
261
262/*
263 * Offset for the Reply Free Queue
264 */
265#define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048)
266
267/*
268 * Defines for the Reply Descriptor Post Queue
269 */
270#define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
271#define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF)
272#define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000)
273#define MPI2_RPHI_MSIX_INDEX_SHIFT (24)
274#define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) /* MPI v2.5 only */
275
276/*
277 * Defines for the HCBSize and address
278 */
279#define MPI2_HCB_SIZE_OFFSET (0x00000074)
280#define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
281#define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
282
283#define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
284#define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
285
286/*
287 * Offsets for the Request Queue
288 */
289#define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
290#define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
291
292
293/* Hard Reset delay timings */
294#define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000)
295#define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000)
296#define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000)
297
298/*****************************************************************************
299*
300* Message Descriptors
301*
302*****************************************************************************/
303
304/* Request Descriptors */
305
306/* Default Request Descriptor */
307typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR
308{
309 U8 RequestFlags; /* 0x00 */
310 U8 MSIxIndex; /* 0x01 */
311 U16 SMID; /* 0x02 */
312 U16 LMID; /* 0x04 */
313 U16 DescriptorTypeDependent; /* 0x06 */
314} MPI2_DEFAULT_REQUEST_DESCRIPTOR,
315 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
316 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
317
318/* defines for the RequestFlags field */
319#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
320#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
321#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
322#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
323#define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
324#define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
325
326#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
327
328
329/* High Priority Request Descriptor */
330typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR
331{
332 U8 RequestFlags; /* 0x00 */
333 U8 MSIxIndex; /* 0x01 */
334 U16 SMID; /* 0x02 */
335 U16 LMID; /* 0x04 */
336 U16 Reserved1; /* 0x06 */
337} MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
338 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
339 Mpi2HighPriorityRequestDescriptor_t,
340 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
341
342
343/* SCSI IO Request Descriptor */
344typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR
345{
346 U8 RequestFlags; /* 0x00 */
347 U8 MSIxIndex; /* 0x01 */
348 U16 SMID; /* 0x02 */
349 U16 LMID; /* 0x04 */
350 U16 DevHandle; /* 0x06 */
351} MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
352 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
353 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t;
354
355
356/* SCSI Target Request Descriptor */
357typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR
358{
359 U8 RequestFlags; /* 0x00 */
360 U8 MSIxIndex; /* 0x01 */
361 U16 SMID; /* 0x02 */
362 U16 LMID; /* 0x04 */
363 U16 IoIndex; /* 0x06 */
364} MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
365 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
366 Mpi2SCSITargetRequestDescriptor_t,
367 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t;
368
369
370/* RAID Accelerator Request Descriptor */
371typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
372 U8 RequestFlags; /* 0x00 */
373 U8 MSIxIndex; /* 0x01 */
374 U16 SMID; /* 0x02 */
375 U16 LMID; /* 0x04 */
376 U16 Reserved; /* 0x06 */
377} MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
378 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
379 Mpi2RAIDAcceleratorRequestDescriptor_t,
380 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
381
382
383/* union of Request Descriptors */
384typedef union _MPI2_REQUEST_DESCRIPTOR_UNION
385{
386 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
387 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
388 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
389 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
390 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
391 U64 Words;
392} MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
393 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t;
394
395
396/* Reply Descriptors */
397
398/* Default Reply Descriptor */
399typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR
400{
401 U8 ReplyFlags; /* 0x00 */
402 U8 MSIxIndex; /* 0x01 */
403 U16 DescriptorTypeDependent1; /* 0x02 */
404 U32 DescriptorTypeDependent2; /* 0x04 */
405} MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
406 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
407
408/* defines for the ReplyFlags field */
409#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
410#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
411#define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
412#define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
413#define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
414#define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
415#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
416
417/* values for marking a reply descriptor as unused */
418#define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
419#define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
420
421/* Address Reply Descriptor */
422typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR
423{
424 U8 ReplyFlags; /* 0x00 */
425 U8 MSIxIndex; /* 0x01 */
426 U16 SMID; /* 0x02 */
427 U32 ReplyFrameAddress; /* 0x04 */
428} MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
429 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
430
431#define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
432
433
434/* SCSI IO Success Reply Descriptor */
435typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
436{
437 U8 ReplyFlags; /* 0x00 */
438 U8 MSIxIndex; /* 0x01 */
439 U16 SMID; /* 0x02 */
440 U16 TaskTag; /* 0x04 */
441 U16 Reserved1; /* 0x06 */
442} MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
443 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
444 Mpi2SCSIIOSuccessReplyDescriptor_t,
445 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t;
446
447
448/* TargetAssist Success Reply Descriptor */
449typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR
450{
451 U8 ReplyFlags; /* 0x00 */
452 U8 MSIxIndex; /* 0x01 */
453 U16 SMID; /* 0x02 */
454 U8 SequenceNumber; /* 0x04 */
455 U8 Reserved1; /* 0x05 */
456 U16 IoIndex; /* 0x06 */
457} MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
458 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
459 Mpi2TargetAssistSuccessReplyDescriptor_t,
460 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t;
461
462
463/* Target Command Buffer Reply Descriptor */
464typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR
465{
466 U8 ReplyFlags; /* 0x00 */
467 U8 MSIxIndex; /* 0x01 */
468 U8 VP_ID; /* 0x02 */
469 U8 Flags; /* 0x03 */
470 U16 InitiatorDevHandle; /* 0x04 */
471 U16 IoIndex; /* 0x06 */
472} MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
473 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
474 Mpi2TargetCommandBufferReplyDescriptor_t,
475 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t;
476
477/* defines for Flags field */
478#define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F)
479
480
481/* RAID Accelerator Success Reply Descriptor */
482typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
483 U8 ReplyFlags; /* 0x00 */
484 U8 MSIxIndex; /* 0x01 */
485 U16 SMID; /* 0x02 */
486 U32 Reserved; /* 0x04 */
487} MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
488 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
489 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
490 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
491
492
493/* union of Reply Descriptors */
494typedef union _MPI2_REPLY_DESCRIPTORS_UNION
495{
496 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
497 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
498 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
499 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
500 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
501 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
502 U64 Words;
503} MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
504Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
505
506
507
508/*****************************************************************************
509*
510* Message Functions
511*
512*****************************************************************************/
513
514#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
515#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */
516#define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
517#define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */
518#define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */
519#define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */
520#define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */
521#define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */
522#define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */
523#define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */
524#define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */
525#define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */
526#define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */
527#define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */
528#define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */
529#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */
530#define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */
531#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */
532#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */
533#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */
534#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */
535#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */
536#define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */
537#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */
538#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */
539#define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator*/
540/* Host Based Discovery Action */
541#define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F)
542/* Power Management Control */
543#define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30)
544/* Send Host Message */
545#define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31)
546/* beginning of product-specific range */
547#define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0)
548/* end of product-specific range */
549#define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF)
550
551
552
553
554/* Doorbell functions */
555#define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
556#define MPI2_FUNCTION_HANDSHAKE (0x42)
557
558
559/*****************************************************************************
560*
561* IOC Status Values
562*
563*****************************************************************************/
564
565/* mask for IOCStatus status value */
566#define MPI2_IOCSTATUS_MASK (0x7FFF)
567
568/****************************************************************************
569* Common IOCStatus values for all replies
570****************************************************************************/
571
572#define MPI2_IOCSTATUS_SUCCESS (0x0000)
573#define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
574#define MPI2_IOCSTATUS_BUSY (0x0002)
575#define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
576#define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
577#define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
578#define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
579#define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
580#define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
581#define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
582
583/****************************************************************************
584* Config IOCStatus values
585****************************************************************************/
586
587#define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
588#define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
589#define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
590#define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
591#define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
592#define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
593
594/****************************************************************************
595* SCSI IO Reply
596****************************************************************************/
597
598#define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
599#define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
600#define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
601#define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
602#define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
603#define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
604#define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
605#define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
606#define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
607#define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
608#define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
609#define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
610
611/****************************************************************************
612* For use by SCSI Initiator and SCSI Target end-to-end data protection
613****************************************************************************/
614
615#define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
616#define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
617#define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
618
619/****************************************************************************
620* SCSI Target values
621****************************************************************************/
622
623#define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
624#define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063)
625#define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
626#define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
627#define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
628#define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
629#define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
630#define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
631#define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
632#define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
633
634/****************************************************************************
635* Serial Attached SCSI values
636****************************************************************************/
637
638#define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
639#define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
640
641/****************************************************************************
642* Diagnostic Buffer Post / Diagnostic Release values
643****************************************************************************/
644
645#define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
646
647/****************************************************************************
648* RAID Accelerator values
649****************************************************************************/
650
651#define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0)
652
653/****************************************************************************
654* IOCStatus flag to indicate that log info is available
655****************************************************************************/
656
657#define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000)
658
659/****************************************************************************
660* IOCLogInfo Types
661****************************************************************************/
662
663#define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000)
664#define MPI2_IOCLOGINFO_TYPE_SHIFT (28)
665#define MPI2_IOCLOGINFO_TYPE_NONE (0x0)
666#define MPI2_IOCLOGINFO_TYPE_SCSI (0x1)
667#define MPI2_IOCLOGINFO_TYPE_FC (0x2)
668#define MPI2_IOCLOGINFO_TYPE_SAS (0x3)
669#define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4)
670#define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
671
672
673/*****************************************************************************
674*
675* Standard Message Structures
676*
677*****************************************************************************/
678
679/****************************************************************************
680* Request Message Header for all request messages
681****************************************************************************/
682
683typedef struct _MPI2_REQUEST_HEADER
684{
685 U16 FunctionDependent1; /* 0x00 */
686 U8 ChainOffset; /* 0x02 */
687 U8 Function; /* 0x03 */
688 U16 FunctionDependent2; /* 0x04 */
689 U8 FunctionDependent3; /* 0x06 */
690 U8 MsgFlags; /* 0x07 */
691 U8 VP_ID; /* 0x08 */
692 U8 VF_ID; /* 0x09 */
693 U16 Reserved1; /* 0x0A */
694} MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER,
695 MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t;
696
697
698/****************************************************************************
699* Default Reply
700****************************************************************************/
701
702typedef struct _MPI2_DEFAULT_REPLY
703{
704 U16 FunctionDependent1; /* 0x00 */
705 U8 MsgLength; /* 0x02 */
706 U8 Function; /* 0x03 */
707 U16 FunctionDependent2; /* 0x04 */
708 U8 FunctionDependent3; /* 0x06 */
709 U8 MsgFlags; /* 0x07 */
710 U8 VP_ID; /* 0x08 */
711 U8 VF_ID; /* 0x09 */
712 U16 Reserved1; /* 0x0A */
713 U16 FunctionDependent5; /* 0x0C */
714 U16 IOCStatus; /* 0x0E */
715 U32 IOCLogInfo; /* 0x10 */
716} MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY,
717 MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t;
718
719
720/* common version structure/union used in messages and configuration pages */
721
722typedef struct _MPI2_VERSION_STRUCT
723{
724 U8 Dev; /* 0x00 */
725 U8 Unit; /* 0x01 */
726 U8 Minor; /* 0x02 */
727 U8 Major; /* 0x03 */
728} MPI2_VERSION_STRUCT;
729
730typedef union _MPI2_VERSION_UNION
731{
732 MPI2_VERSION_STRUCT Struct;
733 U32 Word;
734} MPI2_VERSION_UNION;
735
736
737/* LUN field defines, common to many structures */
738#define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
739#define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
740#define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
741#define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
742#define MPI2_LUN_LEVEL_1_WORD (0xFF00)
743#define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00)
744
745
746/*****************************************************************************
747*
748* Fusion-MPT MPI Scatter Gather Elements
749*
750*****************************************************************************/
751
752/****************************************************************************
753* MPI Simple Element structures
754****************************************************************************/
755
756typedef struct _MPI2_SGE_SIMPLE32
757{
758 U32 FlagsLength;
759 U32 Address;
760} MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32,
761 Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t;
762
763typedef struct _MPI2_SGE_SIMPLE64
764{
765 U32 FlagsLength;
766 U64 Address;
767} MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64,
768 Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t;
769
770typedef struct _MPI2_SGE_SIMPLE_UNION
771{
772 U32 FlagsLength;
773 union
774 {
775 U32 Address32;
776 U64 Address64;
777 } u;
778} MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION,
779 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t;
780
781
782/****************************************************************************
783* MPI Chain Element structures
784****************************************************************************/
785
786typedef struct _MPI2_SGE_CHAIN32
787{
788 U16 Length;
789 U8 NextChainOffset;
790 U8 Flags;
791 U32 Address;
792} MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32,
793 Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t;
794
795typedef struct _MPI2_SGE_CHAIN64
796{
797 U16 Length;
798 U8 NextChainOffset;
799 U8 Flags;
800 U64 Address;
801} MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64,
802 Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t;
803
804typedef struct _MPI2_SGE_CHAIN_UNION
805{
806 U16 Length;
807 U8 NextChainOffset;
808 U8 Flags;
809 union
810 {
811 U32 Address32;
812 U64 Address64;
813 } u;
814} MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION,
815 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t;
816
817
818/****************************************************************************
819* MPI Transaction Context Element structures
820****************************************************************************/
821
822typedef struct _MPI2_SGE_TRANSACTION32
823{
824 U8 Reserved;
825 U8 ContextSize;
826 U8 DetailsLength;
827 U8 Flags;
828 U32 TransactionContext[1];
829 U32 TransactionDetails[1];
830} MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32,
831 Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t;
832
833typedef struct _MPI2_SGE_TRANSACTION64
834{
835 U8 Reserved;
836 U8 ContextSize;
837 U8 DetailsLength;
838 U8 Flags;
839 U32 TransactionContext[2];
840 U32 TransactionDetails[1];
841} MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64,
842 Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t;
843
844typedef struct _MPI2_SGE_TRANSACTION96
845{
846 U8 Reserved;
847 U8 ContextSize;
848 U8 DetailsLength;
849 U8 Flags;
850 U32 TransactionContext[3];
851 U32 TransactionDetails[1];
852} MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96,
853 Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t;
854
855typedef struct _MPI2_SGE_TRANSACTION128
856{
857 U8 Reserved;
858 U8 ContextSize;
859 U8 DetailsLength;
860 U8 Flags;
861 U32 TransactionContext[4];
862 U32 TransactionDetails[1];
863} MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128,
864 Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128;
865
866typedef struct _MPI2_SGE_TRANSACTION_UNION
867{
868 U8 Reserved;
869 U8 ContextSize;
870 U8 DetailsLength;
871 U8 Flags;
872 union
873 {
874 U32 TransactionContext32[1];
875 U32 TransactionContext64[2];
876 U32 TransactionContext96[3];
877 U32 TransactionContext128[4];
878 } u;
879 U32 TransactionDetails[1];
880} MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION,
881 Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t;
882
883
884/****************************************************************************
885* MPI SGE union for IO SGL's
886****************************************************************************/
887
888typedef struct _MPI2_MPI_SGE_IO_UNION
889{
890 union
891 {
892 MPI2_SGE_SIMPLE_UNION Simple;
893 MPI2_SGE_CHAIN_UNION Chain;
894 } u;
895} MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION,
896 Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t;
897
898
899/****************************************************************************
900* MPI SGE union for SGL's with Simple and Transaction elements
901****************************************************************************/
902
903typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION
904{
905 union
906 {
907 MPI2_SGE_SIMPLE_UNION Simple;
908 MPI2_SGE_TRANSACTION_UNION Transaction;
909 } u;
910} MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
911 Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t;
912
913
914/****************************************************************************
915* All MPI SGE types union
916****************************************************************************/
917
918typedef struct _MPI2_MPI_SGE_UNION
919{
920 union
921 {
922 MPI2_SGE_SIMPLE_UNION Simple;
923 MPI2_SGE_CHAIN_UNION Chain;
924 MPI2_SGE_TRANSACTION_UNION Transaction;
925 } u;
926} MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION,
927 Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t;
928
929
930/****************************************************************************
931* MPI SGE field definition and masks
932****************************************************************************/
933
934/* Flags field bit definitions */
935
936#define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80)
937#define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40)
938#define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30)
939#define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08)
940#define MPI2_SGE_FLAGS_DIRECTION (0x04)
941#define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02)
942#define MPI2_SGE_FLAGS_END_OF_LIST (0x01)
943
944#define MPI2_SGE_FLAGS_SHIFT (24)
945
946#define MPI2_SGE_LENGTH_MASK (0x00FFFFFF)
947#define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF)
948
949/* Element Type */
950
951#define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00)
952#define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10)
953#define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30)
954#define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30)
955
956/* Address location */
957
958#define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00)
959
960/* Direction */
961
962#define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00)
963#define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04)
964
965#define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST)
966#define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC)
967
968/* Address Size */
969
970#define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
971#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
972
973/* Context Size */
974
975#define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00)
976#define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02)
977#define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04)
978#define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06)
979
980#define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000)
981#define MPI2_SGE_CHAIN_OFFSET_SHIFT (16)
982
983/****************************************************************************
984* MPI SGE operation Macros
985****************************************************************************/
986
987/* SIMPLE FlagsLength manipulations... */
988#define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
989#define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT)
990#define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK)
991#define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
992
993#define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l))
994
995#define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
996#define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength)
997#define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l)
998
999/* CAUTION - The following are READ-MODIFY-WRITE! */
1000#define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f)
1001#define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l)
1002
1003#define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT)
1004
1005
1006/*****************************************************************************
1007*
1008* Fusion-MPT IEEE Scatter Gather Elements
1009*
1010*****************************************************************************/
1011
1012/****************************************************************************
1013* IEEE Simple Element structures
1014****************************************************************************/
1015
1016typedef struct _MPI2_IEEE_SGE_SIMPLE32
1017{
1018 U32 Address;
1019 U32 FlagsLength;
1020} MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32,
1021 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t;
1022
1023typedef struct _MPI2_IEEE_SGE_SIMPLE64
1024{
1025 U64 Address;
1026 U32 Length;
1027 U16 Reserved1;
1028 U8 Reserved2;
1029 U8 Flags;
1030} MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64,
1031 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t;
1032
1033typedef union _MPI2_IEEE_SGE_SIMPLE_UNION
1034{
1035 MPI2_IEEE_SGE_SIMPLE32 Simple32;
1036 MPI2_IEEE_SGE_SIMPLE64 Simple64;
1037} MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
1038 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
1039
1040
1041/****************************************************************************
1042* IEEE Chain Element structures
1043****************************************************************************/
1044
1045typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
1046
1047typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
1048
1049typedef union _MPI2_IEEE_SGE_CHAIN_UNION
1050{
1051 MPI2_IEEE_SGE_CHAIN32 Chain32;
1052 MPI2_IEEE_SGE_CHAIN64 Chain64;
1053} MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1054 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
1055
1056
1057/****************************************************************************
1058* All IEEE SGE types union
1059****************************************************************************/
1060
1061typedef struct _MPI2_IEEE_SGE_UNION
1062{
1063 union
1064 {
1065 MPI2_IEEE_SGE_SIMPLE_UNION Simple;
1066 MPI2_IEEE_SGE_CHAIN_UNION Chain;
1067 } u;
1068} MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION,
1069 Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t;
1070
1071
1072/****************************************************************************
1073* IEEE SGE field definitions and masks
1074****************************************************************************/
1075
1076/* Flags field bit definitions */
1077
1078#define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1079
1080#define MPI2_IEEE32_SGE_FLAGS_SHIFT (24)
1081
1082#define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1083
1084/* Element Type */
1085
1086#define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1087#define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1088
1089/* Data Location Address Space */
1090
1091#define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1092#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1093 /* IEEE Simple Element only */
1094#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1095 /* IEEE Simple Element only */
1096#define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1097#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1098 /* IEEE Simple Element only */
1099#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03)
1100 /* IEEE Chain Element only */
1101#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR \
1102 (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR) /* typo in name */
1103
1104/****************************************************************************
1105* IEEE SGE operation Macros
1106****************************************************************************/
1107
1108/* SIMPLE FlagsLength manipulations... */
1109#define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1110#define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1111#define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1112
1113#define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l))
1114
1115#define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1116#define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1117#define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l)
1118
1119/* CAUTION - The following are READ-MODIFY-WRITE! */
1120#define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f)
1121#define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l)
1122
1123
1124
1125
1126/*****************************************************************************
1127*
1128* Fusion-MPT MPI/IEEE Scatter Gather Unions
1129*
1130*****************************************************************************/
1131
1132typedef union _MPI2_SIMPLE_SGE_UNION
1133{
1134 MPI2_SGE_SIMPLE_UNION MpiSimple;
1135 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1136} MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION,
1137 Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t;
1138
1139
1140typedef union _MPI2_SGE_IO_UNION
1141{
1142 MPI2_SGE_SIMPLE_UNION MpiSimple;
1143 MPI2_SGE_CHAIN_UNION MpiChain;
1144 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1145 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1146} MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
1147 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
1148
1149
1150/****************************************************************************
1151*
1152* Values for SGLFlags field, used in many request messages with an SGL
1153*
1154****************************************************************************/
1155
1156/* values for MPI SGL Data Location Address Space subfield */
1157#define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1158#define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1159#define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1160#define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1161#define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C)
1162/* values for SGL Type subfield */
1163#define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1164#define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1165#define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01)
1166#define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)
1167
1168
1169#endif
1170
diff --git a/drivers/scsi/mpt2sas/mpi/mpi2_cnfg.h b/drivers/scsi/mpt2sas/mpi/mpi2_cnfg.h
deleted file mode 100644
index ee8d2d695d55..000000000000
--- a/drivers/scsi/mpt2sas/mpi/mpi2_cnfg.h
+++ /dev/null
@@ -1,3068 +0,0 @@
1/*
2 * Copyright (c) 2000-2014 LSI Corporation.
3 *
4 *
5 * Name: mpi2_cnfg.h
6 * Title: MPI Configuration messages and pages
7 * Creation Date: November 10, 2006
8 *
9 * mpi2_cnfg.h Version: 02.00.29
10 *
11 * Version History
12 * ---------------
13 *
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
17 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags.
18 * Added Manufacturing Page 11.
19 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
20 * define.
21 * 06-26-07 02.00.02 Adding generic structure for product-specific
22 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
23 * Rework of BIOS Page 2 configuration page.
24 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
25 * forms.
26 * Added configuration pages IOC Page 8 and Driver
27 * Persistent Mapping Page 0.
28 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated
29 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
30 * RAID Physical Disk Pages 0 and 1, RAID Configuration
31 * Page 0).
32 * Added new value for AccessStatus field of SAS Device
33 * Page 0 (_SATA_NEEDS_INITIALIZATION).
34 * 10-31-07 02.00.04 Added missing SEPDevHandle field to
35 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
36 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for
37 * NVDATA.
38 * Modified IOC Page 7 to use masks and added field for
39 * SASBroadcastPrimitiveMasks.
40 * Added MPI2_CONFIG_PAGE_BIOS_4.
41 * Added MPI2_CONFIG_PAGE_LOG_0.
42 * 02-29-08 02.00.06 Modified various names to make them 32-character unique.
43 * Added SAS Device IDs.
44 * Updated Integrated RAID configuration pages including
45 * Manufacturing Page 4, IOC Page 6, and RAID Configuration
46 * Page 0.
47 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
48 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
49 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
50 * Added missing MaxNumRoutedSasAddresses field to
51 * MPI2_CONFIG_PAGE_EXPANDER_0.
52 * Added SAS Port Page 0.
53 * Modified structure layout for
54 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
55 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
56 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
57 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
58 * to 0x000000FF.
59 * Added two new values for the Physical Disk Coercion Size
60 * bits in the Flags field of Manufacturing Page 4.
61 * Added product-specific Manufacturing pages 16 to 31.
62 * Modified Flags bits for controlling write cache on SATA
63 * drives in IO Unit Page 1.
64 * Added new bit to AdditionalControlFlags of SAS IO Unit
65 * Page 1 to control Invalid Topology Correction.
66 * Added additional defines for RAID Volume Page 0
67 * VolumeStatusFlags field.
68 * Modified meaning of RAID Volume Page 0 VolumeSettings
69 * define for auto-configure of hot-swap drives.
70 * Added SupportedPhysDisks field to RAID Volume Page 1 and
71 * added related defines.
72 * Added PhysDiskAttributes field (and related defines) to
73 * RAID Physical Disk Page 0.
74 * Added MPI2_SAS_PHYINFO_PHY_VACANT define.
75 * Added three new DiscoveryStatus bits for SAS IO Unit
76 * Page 0 and SAS Expander Page 0.
77 * Removed multiplexing information from SAS IO Unit pages.
78 * Added BootDeviceWaitTime field to SAS IO Unit Page 4.
79 * Removed Zone Address Resolved bit from PhyInfo and from
80 * Expander Page 0 Flags field.
81 * Added two new AccessStatus values to SAS Device Page 0
82 * for indicating routing problems. Added 3 reserved words
83 * to this page.
84 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3.
85 * Inserted missing reserved field into structure for IOC
86 * Page 6.
87 * Added more pending task bits to RAID Volume Page 0
88 * VolumeStatusFlags defines.
89 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
90 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0
91 * and SAS Expander Page 0 to flag a downstream initiator
92 * when in simplified routing mode.
93 * Removed SATA Init Failure defines for DiscoveryStatus
94 * fields of SAS IO Unit Page 0 and SAS Expander Page 0.
95 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
96 * Added PortGroups, DmaGroup, and ControlGroup fields to
97 * SAS Device Page 0.
98 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO
99 * Unit Page 6.
100 * Added expander reduced functionality data to SAS
101 * Expander Page 0.
102 * Added SAS PHY Page 2 and SAS PHY Page 3.
103 * 07-30-09 02.00.12 Added IO Unit Page 7.
104 * Added new device ids.
105 * Added SAS IO Unit Page 5.
106 * Added partial and slumber power management capable flags
107 * to SAS Device Page 0 Flags field.
108 * Added PhyInfo defines for power condition.
109 * Added Ethernet configuration pages.
110 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY.
111 * Added SAS PHY Page 4 structure and defines.
112 * 02-10-10 02.00.14 Modified the comments for the configuration page
113 * structures that contain an array of data. The host
114 * should use the "count" field in the page data (e.g. the
115 * NumPhys field) to determine the number of valid elements
116 * in the array.
117 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines.
118 * Added PowerManagementCapabilities to IO Unit Page 7.
119 * Added PortWidthModGroup field to
120 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS.
121 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines.
122 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines.
123 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines.
124 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT
125 * define.
126 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define.
127 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define.
128 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing)
129 * defines.
130 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to
131 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for
132 * the Pinout field.
133 * Added BoardTemperature and BoardTemperatureUnits fields
134 * to MPI2_CONFIG_PAGE_IO_UNIT_7.
135 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define
136 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure.
137 * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST.
138 * Added IO Unit Page 8, IO Unit Page 9,
139 * and IO Unit Page 10.
140 * Added SASNotifyPrimitiveMasks field to
141 * MPI2_CONFIG_PAGE_IOC_7.
142 * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec).
143 * 05-25-11 02.00.20 Cleaned up a few comments.
144 * 08-24-11 02.00.21 Marked the IO Unit Page 7 PowerManagementCapabilities
145 * for PCIe link as obsolete.
146 * Added SpinupFlags field containing a Disable Spin-up
147 * bit to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of
148 * SAS IO Unit Page 4.
149 * 11-18-11 02.00.22 Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT.
150 * Added UEFIVersion field to BIOS Page 1 and defined new
151 * BiosOptions bits.
152 * 11-27-12 02.00.23 Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER.
153 * Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID.
154 * 12-20-12 02.00.24 Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as
155 * obsolete for MPI v2.5 and later.
156 * Added some defines for 12G SAS speeds.
157 * 04-09-13 02.00.25 Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK.
158 * Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to
159 * match the specification.
160 * 12-05-13 02.00.27 Added MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL for
161 * MPI2_CONFIG_PAGE_MAN_7.
162 * Added EnclosureLevel and ConnectorName fields to
163 * MPI2_CONFIG_PAGE_SAS_DEV_0.
164 * Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for
165 * MPI2_CONFIG_PAGE_SAS_DEV_0.
166 * Added EnclosureLevel field to
167 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
168 * Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for
169 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
170 * 01-08-14 02.00.28 Added more defines for the BiosOptions field of
171 * MPI2_CONFIG_PAGE_BIOS_1.
172 * 06-13-14 02.00.29 Added SSUTimeout field to MPI2_CONFIG_PAGE_BIOS_1, and
173 * more defines for the BiosOptions field.
174 * --------------------------------------------------------------------------
175 */
176
177#ifndef MPI2_CNFG_H
178#define MPI2_CNFG_H
179
180/*****************************************************************************
181* Configuration Page Header and defines
182*****************************************************************************/
183
184/* Config Page Header */
185typedef struct _MPI2_CONFIG_PAGE_HEADER
186{
187 U8 PageVersion; /* 0x00 */
188 U8 PageLength; /* 0x01 */
189 U8 PageNumber; /* 0x02 */
190 U8 PageType; /* 0x03 */
191} MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER,
192 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t;
193
194typedef union _MPI2_CONFIG_PAGE_HEADER_UNION
195{
196 MPI2_CONFIG_PAGE_HEADER Struct;
197 U8 Bytes[4];
198 U16 Word16[2];
199 U32 Word32;
200} MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
201 Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion;
202
203/* Extended Config Page Header */
204typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER
205{
206 U8 PageVersion; /* 0x00 */
207 U8 Reserved1; /* 0x01 */
208 U8 PageNumber; /* 0x02 */
209 U8 PageType; /* 0x03 */
210 U16 ExtPageLength; /* 0x04 */
211 U8 ExtPageType; /* 0x06 */
212 U8 Reserved2; /* 0x07 */
213} MPI2_CONFIG_EXTENDED_PAGE_HEADER,
214 MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
215 Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t;
216
217typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION
218{
219 MPI2_CONFIG_PAGE_HEADER Struct;
220 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
221 U8 Bytes[8];
222 U16 Word16[4];
223 U32 Word32[2];
224} MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
225 Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion;
226
227
228/* PageType field values */
229#define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00)
230#define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10)
231#define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20)
232#define MPI2_CONFIG_PAGEATTR_MASK (0xF0)
233
234#define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00)
235#define MPI2_CONFIG_PAGETYPE_IOC (0x01)
236#define MPI2_CONFIG_PAGETYPE_BIOS (0x02)
237#define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
238#define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09)
239#define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
240#define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F)
241#define MPI2_CONFIG_PAGETYPE_MASK (0x0F)
242
243#define MPI2_CONFIG_TYPENUM_MASK (0x0FFF)
244
245
246/* ExtPageType field values */
247#define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
248#define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
249#define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
250#define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
251#define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14)
252#define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
253#define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16)
254#define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17)
255#define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18)
256#define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19)
257#define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A)
258
259
260/*****************************************************************************
261* PageAddress defines
262*****************************************************************************/
263
264/* RAID Volume PageAddress format */
265#define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000)
266#define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
267#define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000)
268
269#define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF)
270
271
272/* RAID Physical Disk PageAddress format */
273#define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000)
274#define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000)
275#define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000)
276#define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000)
277
278#define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
279#define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF)
280
281
282/* SAS Expander PageAddress format */
283#define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
284#define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000)
285#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000)
286#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000)
287
288#define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF)
289#define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000)
290#define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16)
291
292
293/* SAS Device PageAddress format */
294#define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
295#define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
296#define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000)
297
298#define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF)
299
300
301/* SAS PHY PageAddress format */
302#define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
303#define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000)
304#define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000)
305
306#define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
307#define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
308
309
310/* SAS Port PageAddress format */
311#define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000)
312#define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000)
313#define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000)
314
315#define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF)
316
317
318/* SAS Enclosure PageAddress format */
319#define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
320#define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
321#define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
322
323#define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF)
324
325
326/* RAID Configuration PageAddress format */
327#define MPI2_RAID_PGAD_FORM_MASK (0xF0000000)
328#define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000)
329#define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000)
330#define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000)
331
332#define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF)
333
334
335/* Driver Persistent Mapping PageAddress format */
336#define MPI2_DPM_PGAD_FORM_MASK (0xF0000000)
337#define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000)
338
339#define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000)
340#define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16)
341#define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF)
342
343
344/* Ethernet PageAddress format */
345#define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000)
346#define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000)
347
348#define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF)
349
350
351
352/****************************************************************************
353* Configuration messages
354****************************************************************************/
355
356/* Configuration Request Message */
357typedef struct _MPI2_CONFIG_REQUEST
358{
359 U8 Action; /* 0x00 */
360 U8 SGLFlags; /* 0x01 */
361 U8 ChainOffset; /* 0x02 */
362 U8 Function; /* 0x03 */
363 U16 ExtPageLength; /* 0x04 */
364 U8 ExtPageType; /* 0x06 */
365 U8 MsgFlags; /* 0x07 */
366 U8 VP_ID; /* 0x08 */
367 U8 VF_ID; /* 0x09 */
368 U16 Reserved1; /* 0x0A */
369 U8 Reserved2; /* 0x0C */
370 U8 ProxyVF_ID; /* 0x0D */
371 U16 Reserved4; /* 0x0E */
372 U32 Reserved3; /* 0x10 */
373 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
374 U32 PageAddress; /* 0x18 */
375 MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */
376} MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST,
377 Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t;
378
379/* values for the Action field */
380#define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00)
381#define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
382#define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
383#define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03)
384#define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
385#define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
386#define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
387#define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07)
388
389/* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
390
391
392/* Config Reply Message */
393typedef struct _MPI2_CONFIG_REPLY
394{
395 U8 Action; /* 0x00 */
396 U8 SGLFlags; /* 0x01 */
397 U8 MsgLength; /* 0x02 */
398 U8 Function; /* 0x03 */
399 U16 ExtPageLength; /* 0x04 */
400 U8 ExtPageType; /* 0x06 */
401 U8 MsgFlags; /* 0x07 */
402 U8 VP_ID; /* 0x08 */
403 U8 VF_ID; /* 0x09 */
404 U16 Reserved1; /* 0x0A */
405 U16 Reserved2; /* 0x0C */
406 U16 IOCStatus; /* 0x0E */
407 U32 IOCLogInfo; /* 0x10 */
408 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
409} MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY,
410 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t;
411
412
413
414/*****************************************************************************
415*
416* C o n f i g u r a t i o n P a g e s
417*
418*****************************************************************************/
419
420/****************************************************************************
421* Manufacturing Config pages
422****************************************************************************/
423
424#define MPI2_MFGPAGE_VENDORID_LSI (0x1000)
425
426/* SAS */
427#define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070)
428#define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072)
429#define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074)
430#define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076)
431#define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077)
432#define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064)
433#define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065)
434
435#define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E)
436
437#define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080)
438#define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081)
439#define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082)
440#define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083)
441#define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084)
442#define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085)
443#define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086)
444#define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087)
445#define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E)
446
447
448
449
450/* Manufacturing Page 0 */
451
452typedef struct _MPI2_CONFIG_PAGE_MAN_0
453{
454 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
455 U8 ChipName[16]; /* 0x04 */
456 U8 ChipRevision[8]; /* 0x14 */
457 U8 BoardName[16]; /* 0x1C */
458 U8 BoardAssembly[16]; /* 0x2C */
459 U8 BoardTracerNumber[16]; /* 0x3C */
460} MPI2_CONFIG_PAGE_MAN_0,
461 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0,
462 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t;
463
464#define MPI2_MANUFACTURING0_PAGEVERSION (0x00)
465
466
467/* Manufacturing Page 1 */
468
469typedef struct _MPI2_CONFIG_PAGE_MAN_1
470{
471 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
472 U8 VPD[256]; /* 0x04 */
473} MPI2_CONFIG_PAGE_MAN_1,
474 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1,
475 Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t;
476
477#define MPI2_MANUFACTURING1_PAGEVERSION (0x00)
478
479
480typedef struct _MPI2_CHIP_REVISION_ID
481{
482 U16 DeviceID; /* 0x00 */
483 U8 PCIRevisionID; /* 0x02 */
484 U8 Reserved; /* 0x03 */
485} MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID,
486 Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t;
487
488
489/* Manufacturing Page 2 */
490
491/*
492 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
493 * one and check Header.PageLength at runtime.
494 */
495#ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
496#define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
497#endif
498
499typedef struct _MPI2_CONFIG_PAGE_MAN_2
500{
501 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
502 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
503 U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */
504} MPI2_CONFIG_PAGE_MAN_2,
505 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2,
506 Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t;
507
508#define MPI2_MANUFACTURING2_PAGEVERSION (0x00)
509
510
511/* Manufacturing Page 3 */
512
513/*
514 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
515 * one and check Header.PageLength at runtime.
516 */
517#ifndef MPI2_MAN_PAGE_3_INFO_WORDS
518#define MPI2_MAN_PAGE_3_INFO_WORDS (1)
519#endif
520
521typedef struct _MPI2_CONFIG_PAGE_MAN_3
522{
523 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
524 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
525 U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */
526} MPI2_CONFIG_PAGE_MAN_3,
527 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3,
528 Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t;
529
530#define MPI2_MANUFACTURING3_PAGEVERSION (0x00)
531
532
533/* Manufacturing Page 4 */
534
535typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS
536{
537 U8 PowerSaveFlags; /* 0x00 */
538 U8 InternalOperationsSleepTime; /* 0x01 */
539 U8 InternalOperationsRunTime; /* 0x02 */
540 U8 HostIdleTime; /* 0x03 */
541} MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
542 MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
543 Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t;
544
545/* defines for the PowerSaveFlags field */
546#define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03)
547#define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00)
548#define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01)
549#define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02)
550
551typedef struct _MPI2_CONFIG_PAGE_MAN_4
552{
553 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
554 U32 Reserved1; /* 0x04 */
555 U32 Flags; /* 0x08 */
556 U8 InquirySize; /* 0x0C */
557 U8 Reserved2; /* 0x0D */
558 U16 Reserved3; /* 0x0E */
559 U8 InquiryData[56]; /* 0x10 */
560 U32 RAID0VolumeSettings; /* 0x48 */
561 U32 RAID1EVolumeSettings; /* 0x4C */
562 U32 RAID1VolumeSettings; /* 0x50 */
563 U32 RAID10VolumeSettings; /* 0x54 */
564 U32 Reserved4; /* 0x58 */
565 U32 Reserved5; /* 0x5C */
566 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */
567 U8 MaxOCEDisks; /* 0x64 */
568 U8 ResyncRate; /* 0x65 */
569 U16 DataScrubDuration; /* 0x66 */
570 U8 MaxHotSpares; /* 0x68 */
571 U8 MaxPhysDisksPerVol; /* 0x69 */
572 U8 MaxPhysDisks; /* 0x6A */
573 U8 MaxVolumes; /* 0x6B */
574} MPI2_CONFIG_PAGE_MAN_4,
575 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4,
576 Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t;
577
578#define MPI2_MANUFACTURING4_PAGEVERSION (0x0A)
579
580/* Manufacturing Page 4 Flags field */
581#define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000)
582#define MPI2_MANPAGE4_METADATA_512MB (0x00000000)
583
584#define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000)
585#define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000)
586#define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000)
587
588#define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00)
589#define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000)
590#define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400)
591#define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800)
592#define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00)
593
594#define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300)
595#define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000)
596#define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100)
597#define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200)
598
599#define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080)
600#define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040)
601#define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020)
602#define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010)
603#define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008)
604#define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004)
605#define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002)
606#define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001)
607
608
609/* Manufacturing Page 5 */
610
611/*
612 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
613 * one and check the value returned for NumPhys at runtime.
614 */
615#ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
616#define MPI2_MAN_PAGE_5_PHY_ENTRIES (1)
617#endif
618
619typedef struct _MPI2_MANUFACTURING5_ENTRY
620{
621 U64 WWID; /* 0x00 */
622 U64 DeviceName; /* 0x08 */
623} MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY,
624 Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t;
625
626typedef struct _MPI2_CONFIG_PAGE_MAN_5
627{
628 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
629 U8 NumPhys; /* 0x04 */
630 U8 Reserved1; /* 0x05 */
631 U16 Reserved2; /* 0x06 */
632 U32 Reserved3; /* 0x08 */
633 U32 Reserved4; /* 0x0C */
634 MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */
635} MPI2_CONFIG_PAGE_MAN_5,
636 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5,
637 Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t;
638
639#define MPI2_MANUFACTURING5_PAGEVERSION (0x03)
640
641
642/* Manufacturing Page 6 */
643
644typedef struct _MPI2_CONFIG_PAGE_MAN_6
645{
646 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
647 U32 ProductSpecificInfo;/* 0x04 */
648} MPI2_CONFIG_PAGE_MAN_6,
649 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6,
650 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t;
651
652#define MPI2_MANUFACTURING6_PAGEVERSION (0x00)
653
654
655/* Manufacturing Page 7 */
656
657typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO
658{
659 U32 Pinout; /* 0x00 */
660 U8 Connector[16]; /* 0x04 */
661 U8 Location; /* 0x14 */
662 U8 ReceptacleID; /* 0x15 */
663 U16 Slot; /* 0x16 */
664 U32 Reserved2; /* 0x18 */
665} MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
666 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t;
667
668/* defines for the Pinout field */
669#define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00)
670#define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8)
671
672#define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF)
673#define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00)
674#define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01)
675#define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02)
676#define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03)
677#define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04)
678#define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05)
679#define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06)
680#define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07)
681#define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08)
682#define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09)
683#define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A)
684#define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B)
685#define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C)
686#define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D)
687
688/* defines for the Location field */
689#define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01)
690#define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02)
691#define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04)
692#define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08)
693#define MPI2_MANPAGE7_LOCATION_AUTO (0x10)
694#define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20)
695#define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80)
696
697/*
698 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
699 * one and check the value returned for NumPhys at runtime.
700 */
701#ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
702#define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1)
703#endif
704
705typedef struct _MPI2_CONFIG_PAGE_MAN_7
706{
707 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
708 U32 Reserved1; /* 0x04 */
709 U32 Reserved2; /* 0x08 */
710 U32 Flags; /* 0x0C */
711 U8 EnclosureName[16]; /* 0x10 */
712 U8 NumPhys; /* 0x20 */
713 U8 Reserved3; /* 0x21 */
714 U16 Reserved4; /* 0x22 */
715 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */
716} MPI2_CONFIG_PAGE_MAN_7,
717 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7,
718 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t;
719
720#define MPI2_MANUFACTURING7_PAGEVERSION (0x01)
721
722/* defines for the Flags field */
723#define MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL (0x00000008)
724#define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER (0x00000002)
725#define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
726
727
728/*
729 * Generic structure to use for product-specific manufacturing pages
730 * (currently Manufacturing Page 8 through Manufacturing Page 31).
731 */
732
733typedef struct _MPI2_CONFIG_PAGE_MAN_PS
734{
735 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
736 U32 ProductSpecificInfo;/* 0x04 */
737} MPI2_CONFIG_PAGE_MAN_PS,
738 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS,
739 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t;
740
741#define MPI2_MANUFACTURING8_PAGEVERSION (0x00)
742#define MPI2_MANUFACTURING9_PAGEVERSION (0x00)
743#define MPI2_MANUFACTURING10_PAGEVERSION (0x00)
744#define MPI2_MANUFACTURING11_PAGEVERSION (0x00)
745#define MPI2_MANUFACTURING12_PAGEVERSION (0x00)
746#define MPI2_MANUFACTURING13_PAGEVERSION (0x00)
747#define MPI2_MANUFACTURING14_PAGEVERSION (0x00)
748#define MPI2_MANUFACTURING15_PAGEVERSION (0x00)
749#define MPI2_MANUFACTURING16_PAGEVERSION (0x00)
750#define MPI2_MANUFACTURING17_PAGEVERSION (0x00)
751#define MPI2_MANUFACTURING18_PAGEVERSION (0x00)
752#define MPI2_MANUFACTURING19_PAGEVERSION (0x00)
753#define MPI2_MANUFACTURING20_PAGEVERSION (0x00)
754#define MPI2_MANUFACTURING21_PAGEVERSION (0x00)
755#define MPI2_MANUFACTURING22_PAGEVERSION (0x00)
756#define MPI2_MANUFACTURING23_PAGEVERSION (0x00)
757#define MPI2_MANUFACTURING24_PAGEVERSION (0x00)
758#define MPI2_MANUFACTURING25_PAGEVERSION (0x00)
759#define MPI2_MANUFACTURING26_PAGEVERSION (0x00)
760#define MPI2_MANUFACTURING27_PAGEVERSION (0x00)
761#define MPI2_MANUFACTURING28_PAGEVERSION (0x00)
762#define MPI2_MANUFACTURING29_PAGEVERSION (0x00)
763#define MPI2_MANUFACTURING30_PAGEVERSION (0x00)
764#define MPI2_MANUFACTURING31_PAGEVERSION (0x00)
765
766
767/****************************************************************************
768* IO Unit Config Pages
769****************************************************************************/
770
771/* IO Unit Page 0 */
772
773typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0
774{
775 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
776 U64 UniqueValue; /* 0x04 */
777 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */
778 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */
779} MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
780 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t;
781
782#define MPI2_IOUNITPAGE0_PAGEVERSION (0x02)
783
784
785/* IO Unit Page 1 */
786
787typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1
788{
789 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
790 U32 Flags; /* 0x04 */
791} MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
792 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t;
793
794#define MPI2_IOUNITPAGE1_PAGEVERSION (0x04)
795
796/* IO Unit Page 1 Flags defines */
797#define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK (0x00004000)
798#define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800)
799#define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600)
800#define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9)
801#define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000)
802#define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200)
803#define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400)
804#define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
805#define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040)
806#define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
807#define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
808
809
810/* IO Unit Page 3 */
811
812/*
813 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
814 * one and check the value returned for GPIOCount at runtime.
815 */
816#ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
817#define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
818#endif
819
820typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3
821{
822 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
823 U8 GPIOCount; /* 0x04 */
824 U8 Reserved1; /* 0x05 */
825 U16 Reserved2; /* 0x06 */
826 U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */
827} MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
828 Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t;
829
830#define MPI2_IOUNITPAGE3_PAGEVERSION (0x01)
831
832/* defines for IO Unit Page 3 GPIOVal field */
833#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC)
834#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
835#define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000)
836#define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001)
837
838
839/* IO Unit Page 5 */
840
841/*
842 * Upper layer code (drivers, utilities, etc.) should leave this define set to
843 * one and check the value returned for NumDmaEngines at runtime.
844 */
845#ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES
846#define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1)
847#endif
848
849typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 {
850 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
851 U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */
852 U64 RaidAcceleratorBufferSize; /* 0x0C */
853 U64 RaidAcceleratorControlBaseAddress; /* 0x14 */
854 U8 RAControlSize; /* 0x1C */
855 U8 NumDmaEngines; /* 0x1D */
856 U8 RAMinControlSize; /* 0x1E */
857 U8 RAMaxControlSize; /* 0x1F */
858 U32 Reserved1; /* 0x20 */
859 U32 Reserved2; /* 0x24 */
860 U32 Reserved3; /* 0x28 */
861 U32 DmaEngineCapabilities
862 [MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */
863} MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
864 Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t;
865
866#define MPI2_IOUNITPAGE5_PAGEVERSION (0x00)
867
868/* defines for IO Unit Page 5 DmaEngineCapabilities field */
869#define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFFFF0000)
870#define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16)
871
872#define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008)
873#define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004)
874#define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002)
875#define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001)
876
877
878/* IO Unit Page 6 */
879
880typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 {
881 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
882 U16 Flags; /* 0x04 */
883 U8 RAHostControlSize; /* 0x06 */
884 U8 Reserved0; /* 0x07 */
885 U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */
886 U32 Reserved1; /* 0x10 */
887 U32 Reserved2; /* 0x14 */
888 U32 Reserved3; /* 0x18 */
889} MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
890 Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t;
891
892#define MPI2_IOUNITPAGE6_PAGEVERSION (0x00)
893
894/* defines for IO Unit Page 6 Flags field */
895#define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001)
896
897
898/* IO Unit Page 7 */
899
900typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 {
901 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
902 U16 Reserved1; /* 0x04 */
903 U8 PCIeWidth; /* 0x06 */
904 U8 PCIeSpeed; /* 0x07 */
905 U32 ProcessorState; /* 0x08 */
906 U32 PowerManagementCapabilities; /* 0x0C */
907 U16 IOCTemperature; /* 0x10 */
908 U8 IOCTemperatureUnits; /* 0x12 */
909 U8 IOCSpeed; /* 0x13 */
910 U16 BoardTemperature; /* 0x14 */
911 U8 BoardTemperatureUnits; /* 0x16 */
912 U8 Reserved3; /* 0x17 */
913 U32 Reserved4; /* 0x18 */
914 U32 Reserved5; /* 0x1C */
915 U32 Reserved6; /* 0x20 */
916 U32 Reserved7; /* 0x24 */
917} MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
918 Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t;
919
920#define MPI2_IOUNITPAGE7_PAGEVERSION (0x04)
921
922/* defines for IO Unit Page 7 PCIeWidth field */
923#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01)
924#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02)
925#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04)
926#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08)
927
928/* defines for IO Unit Page 7 PCIeSpeed field */
929#define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00)
930#define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01)
931#define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02)
932
933/* defines for IO Unit Page 7 ProcessorState field */
934#define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F)
935#define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0)
936
937#define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00)
938#define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01)
939#define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02)
940
941/* defines for IO Unit Page 7 PowerManagementCapabilities field */
942#define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400)
943#define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200)
944#define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100)
945#define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) /* obsolete */
946#define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) /* obsolete */
947
948/* defines for IO Unit Page 7 IOCTemperatureUnits field */
949#define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00)
950#define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01)
951#define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02)
952
953/* defines for IO Unit Page 7 IOCSpeed field */
954#define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01)
955#define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02)
956#define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04)
957#define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08)
958
959/* defines for IO Unit Page 7 BoardTemperatureUnits field */
960#define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00)
961#define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01)
962#define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02)
963
964/* IO Unit Page 8 */
965
966#define MPI2_IOUNIT8_NUM_THRESHOLDS (4)
967
968typedef struct _MPI2_IOUNIT8_SENSOR {
969 U16 Flags; /* 0x00 */
970 U16 Reserved1; /* 0x02 */
971 U16
972 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /* 0x04 */
973 U32 Reserved2; /* 0x0C */
974 U32 Reserved3; /* 0x10 */
975 U32 Reserved4; /* 0x14 */
976} MPI2_IOUNIT8_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT8_SENSOR,
977Mpi2IOUnit8Sensor_t, MPI2_POINTER pMpi2IOUnit8Sensor_t;
978
979/* defines for IO Unit Page 8 Sensor Flags field */
980#define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008)
981#define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004)
982#define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002)
983#define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001)
984
985/*
986 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
987 * one and check the value returned for NumSensors at runtime.
988 */
989#ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES
990#define MPI2_IOUNITPAGE8_SENSOR_ENTRIES (1)
991#endif
992
993typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 {
994 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
995 U32 Reserved1; /* 0x04 */
996 U32 Reserved2; /* 0x08 */
997 U8 NumSensors; /* 0x0C */
998 U8 PollingInterval; /* 0x0D */
999 U16 Reserved3; /* 0x0E */
1000 MPI2_IOUNIT8_SENSOR
1001 Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/* 0x10 */
1002} MPI2_CONFIG_PAGE_IO_UNIT_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_8,
1003Mpi2IOUnitPage8_t, MPI2_POINTER pMpi2IOUnitPage8_t;
1004
1005#define MPI2_IOUNITPAGE8_PAGEVERSION (0x00)
1006
1007
1008/* IO Unit Page 9 */
1009
1010typedef struct _MPI2_IOUNIT9_SENSOR {
1011 U16 CurrentTemperature; /* 0x00 */
1012 U16 Reserved1; /* 0x02 */
1013 U8 Flags; /* 0x04 */
1014 U8 Reserved2; /* 0x05 */
1015 U16 Reserved3; /* 0x06 */
1016 U32 Reserved4; /* 0x08 */
1017 U32 Reserved5; /* 0x0C */
1018} MPI2_IOUNIT9_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT9_SENSOR,
1019Mpi2IOUnit9Sensor_t, MPI2_POINTER pMpi2IOUnit9Sensor_t;
1020
1021/* defines for IO Unit Page 9 Sensor Flags field */
1022#define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01)
1023
1024/*
1025 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1026 * one and check the value returned for NumSensors at runtime.
1027 */
1028#ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES
1029#define MPI2_IOUNITPAGE9_SENSOR_ENTRIES (1)
1030#endif
1031
1032typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 {
1033 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1034 U32 Reserved1; /* 0x04 */
1035 U32 Reserved2; /* 0x08 */
1036 U8 NumSensors; /* 0x0C */
1037 U8 Reserved4; /* 0x0D */
1038 U16 Reserved3; /* 0x0E */
1039 MPI2_IOUNIT9_SENSOR
1040 Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/* 0x10 */
1041} MPI2_CONFIG_PAGE_IO_UNIT_9, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_9,
1042Mpi2IOUnitPage9_t, MPI2_POINTER pMpi2IOUnitPage9_t;
1043
1044#define MPI2_IOUNITPAGE9_PAGEVERSION (0x00)
1045
1046
1047/* IO Unit Page 10 */
1048
1049typedef struct _MPI2_IOUNIT10_FUNCTION {
1050 U8 CreditPercent; /* 0x00 */
1051 U8 Reserved1; /* 0x01 */
1052 U16 Reserved2; /* 0x02 */
1053} MPI2_IOUNIT10_FUNCTION, MPI2_POINTER PTR_MPI2_IOUNIT10_FUNCTION,
1054Mpi2IOUnit10Function_t, MPI2_POINTER pMpi2IOUnit10Function_t;
1055
1056/*
1057 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1058 * one and check the value returned for NumFunctions at runtime.
1059 */
1060#ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES
1061#define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES (1)
1062#endif
1063
1064typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 {
1065 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1066 U8 NumFunctions; /* 0x04 */
1067 U8 Reserved1; /* 0x05 */
1068 U16 Reserved2; /* 0x06 */
1069 U32 Reserved3; /* 0x08 */
1070 U32 Reserved4; /* 0x0C */
1071 MPI2_IOUNIT10_FUNCTION
1072 Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES];/* 0x10 */
1073} MPI2_CONFIG_PAGE_IO_UNIT_10, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_10,
1074Mpi2IOUnitPage10_t, MPI2_POINTER pMpi2IOUnitPage10_t;
1075
1076#define MPI2_IOUNITPAGE10_PAGEVERSION (0x01)
1077
1078
1079
1080/****************************************************************************
1081* IOC Config Pages
1082****************************************************************************/
1083
1084/* IOC Page 0 */
1085
1086typedef struct _MPI2_CONFIG_PAGE_IOC_0
1087{
1088 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1089 U32 Reserved1; /* 0x04 */
1090 U32 Reserved2; /* 0x08 */
1091 U16 VendorID; /* 0x0C */
1092 U16 DeviceID; /* 0x0E */
1093 U8 RevisionID; /* 0x10 */
1094 U8 Reserved3; /* 0x11 */
1095 U16 Reserved4; /* 0x12 */
1096 U32 ClassCode; /* 0x14 */
1097 U16 SubsystemVendorID; /* 0x18 */
1098 U16 SubsystemID; /* 0x1A */
1099} MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0,
1100 Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t;
1101
1102#define MPI2_IOCPAGE0_PAGEVERSION (0x02)
1103
1104
1105/* IOC Page 1 */
1106
1107typedef struct _MPI2_CONFIG_PAGE_IOC_1
1108{
1109 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1110 U32 Flags; /* 0x04 */
1111 U32 CoalescingTimeout; /* 0x08 */
1112 U8 CoalescingDepth; /* 0x0C */
1113 U8 PCISlotNum; /* 0x0D */
1114 U8 PCIBusNum; /* 0x0E */
1115 U8 PCIDomainSegment; /* 0x0F */
1116 U32 Reserved1; /* 0x10 */
1117 U32 Reserved2; /* 0x14 */
1118} MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1,
1119 Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t;
1120
1121#define MPI2_IOCPAGE1_PAGEVERSION (0x05)
1122
1123/* defines for IOC Page 1 Flags field */
1124#define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001)
1125
1126#define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
1127#define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF)
1128#define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF)
1129
1130/* IOC Page 6 */
1131
1132typedef struct _MPI2_CONFIG_PAGE_IOC_6
1133{
1134 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1135 U32 CapabilitiesFlags; /* 0x04 */
1136 U8 MaxDrivesRAID0; /* 0x08 */
1137 U8 MaxDrivesRAID1; /* 0x09 */
1138 U8 MaxDrivesRAID1E; /* 0x0A */
1139 U8 MaxDrivesRAID10; /* 0x0B */
1140 U8 MinDrivesRAID0; /* 0x0C */
1141 U8 MinDrivesRAID1; /* 0x0D */
1142 U8 MinDrivesRAID1E; /* 0x0E */
1143 U8 MinDrivesRAID10; /* 0x0F */
1144 U32 Reserved1; /* 0x10 */
1145 U8 MaxGlobalHotSpares; /* 0x14 */
1146 U8 MaxPhysDisks; /* 0x15 */
1147 U8 MaxVolumes; /* 0x16 */
1148 U8 MaxConfigs; /* 0x17 */
1149 U8 MaxOCEDisks; /* 0x18 */
1150 U8 Reserved2; /* 0x19 */
1151 U16 Reserved3; /* 0x1A */
1152 U32 SupportedStripeSizeMapRAID0; /* 0x1C */
1153 U32 SupportedStripeSizeMapRAID1E; /* 0x20 */
1154 U32 SupportedStripeSizeMapRAID10; /* 0x24 */
1155 U32 Reserved4; /* 0x28 */
1156 U32 Reserved5; /* 0x2C */
1157 U16 DefaultMetadataSize; /* 0x30 */
1158 U16 Reserved6; /* 0x32 */
1159 U16 MaxBadBlockTableEntries; /* 0x34 */
1160 U16 Reserved7; /* 0x36 */
1161 U32 IRNvsramVersion; /* 0x38 */
1162} MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6,
1163 Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t;
1164
1165#define MPI2_IOCPAGE6_PAGEVERSION (0x05)
1166
1167/* defines for IOC Page 6 CapabilitiesFlags */
1168#define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT (0x00000020)
1169#define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010)
1170#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008)
1171#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004)
1172#define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002)
1173#define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001)
1174
1175
1176/* IOC Page 7 */
1177
1178#define MPI2_IOCPAGE7_EVENTMASK_WORDS (4)
1179
1180typedef struct _MPI2_CONFIG_PAGE_IOC_7
1181{
1182 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1183 U32 Reserved1; /* 0x04 */
1184 U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */
1185 U16 SASBroadcastPrimitiveMasks; /* 0x18 */
1186 U16 SASNotifyPrimitiveMasks; /* 0x1A */
1187 U32 Reserved3; /* 0x1C */
1188} MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7,
1189 Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t;
1190
1191#define MPI2_IOCPAGE7_PAGEVERSION (0x02)
1192
1193
1194/* IOC Page 8 */
1195
1196typedef struct _MPI2_CONFIG_PAGE_IOC_8
1197{
1198 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1199 U8 NumDevsPerEnclosure; /* 0x04 */
1200 U8 Reserved1; /* 0x05 */
1201 U16 Reserved2; /* 0x06 */
1202 U16 MaxPersistentEntries; /* 0x08 */
1203 U16 MaxNumPhysicalMappedIDs; /* 0x0A */
1204 U16 Flags; /* 0x0C */
1205 U16 Reserved3; /* 0x0E */
1206 U16 IRVolumeMappingFlags; /* 0x10 */
1207 U16 Reserved4; /* 0x12 */
1208 U32 Reserved5; /* 0x14 */
1209} MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8,
1210 Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t;
1211
1212#define MPI2_IOCPAGE8_PAGEVERSION (0x00)
1213
1214/* defines for IOC Page 8 Flags field */
1215#define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020)
1216#define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010)
1217
1218#define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E)
1219#define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000)
1220#define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002)
1221
1222#define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001)
1223#define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000)
1224
1225/* defines for IOC Page 8 IRVolumeMappingFlags */
1226#define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003)
1227#define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000)
1228#define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001)
1229
1230
1231/****************************************************************************
1232* BIOS Config Pages
1233****************************************************************************/
1234
1235/* BIOS Page 1 */
1236
1237typedef struct _MPI2_CONFIG_PAGE_BIOS_1
1238{
1239 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1240 U32 BiosOptions; /* 0x04 */
1241 U32 IOCSettings; /* 0x08 */
1242 U8 SSUTimeout; /* 0x0C */
1243 U8 Reserved1; /* 0x0D */
1244 U16 Reserved2; /* 0x0E */
1245 U32 DeviceSettings; /* 0x10 */
1246 U16 NumberOfDevices; /* 0x14 */
1247 U16 UEFIVersion; /* 0x16 */
1248 U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */
1249 U16 IOTimeoutSequential; /* 0x1A */
1250 U16 IOTimeoutOther; /* 0x1C */
1251 U16 IOTimeoutBlockDevicesRM; /* 0x1E */
1252} MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1,
1253 Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t;
1254
1255#define MPI2_BIOSPAGE1_PAGEVERSION (0x07)
1256
1257/* values for BIOS Page 1 BiosOptions field */
1258#define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK (0x00003800)
1259#define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL (0x00000000)
1260#define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE (0x00000800)
1261#define MPI2_BIOSPAGE1_OPTIONS_PNS_LWWID (0x00001000)
1262#define MPI2_BIOSPAGE1_OPTIONS_PNS_PSENS (0x00001800)
1263#define MPI2_BIOSPAGE1_OPTIONS_PNS_ESPHY (0x00002000)
1264
1265#define MPI2_BIOSPAGE1_OPTIONS_X86_DISABLE_BIOS (0x00000400)
1266
1267#define MPI2_BIOSPAGE1_OPTIONS_MASK_REGISTRATION_UEFI_BSD (0x00000300)
1268#define MPI2_BIOSPAGE1_OPTIONS_USE_BIT0_REGISTRATION_UEFI_BSD (0x00000000)
1269#define MPI2_BIOSPAGE1_OPTIONS_FULL_REGISTRATION_UEFI_BSD (0x00000100)
1270#define MPI2_BIOSPAGE1_OPTIONS_ADAPTER_REGISTRATION_UEFI_BSD (0x00000200)
1271#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_REGISTRATION_UEFI_BSD (0x00000300)
1272
1273#define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID (0x000000F0)
1274#define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID (0x00000000)
1275
1276#define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006)
1277#define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000)
1278#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002)
1279#define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004)
1280
1281#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
1282
1283/* values for BIOS Page 1 IOCSettings field */
1284#define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
1285#define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
1286#define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
1287
1288#define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
1289#define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
1290#define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
1291#define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
1292
1293#define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
1294#define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
1295#define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
1296#define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
1297#define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
1298
1299#define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
1300
1301/* values for BIOS Page 1 DeviceSettings field */
1302#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010)
1303#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
1304#define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
1305#define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
1306#define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
1307
1308/* defines for BIOS Page 1 UEFIVersion field */
1309#define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK (0xFF00)
1310#define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT (8)
1311#define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK (0x00FF)
1312#define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT (0)
1313
1314
1315
1316/* BIOS Page 2 */
1317
1318typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER
1319{
1320 U32 Reserved1; /* 0x00 */
1321 U32 Reserved2; /* 0x04 */
1322 U32 Reserved3; /* 0x08 */
1323 U32 Reserved4; /* 0x0C */
1324 U32 Reserved5; /* 0x10 */
1325 U32 Reserved6; /* 0x14 */
1326} MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1327 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1328 Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t;
1329
1330typedef struct _MPI2_BOOT_DEVICE_SAS_WWID
1331{
1332 U64 SASAddress; /* 0x00 */
1333 U8 LUN[8]; /* 0x08 */
1334 U32 Reserved1; /* 0x10 */
1335 U32 Reserved2; /* 0x14 */
1336} MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID,
1337 Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t;
1338
1339typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT
1340{
1341 U64 EnclosureLogicalID; /* 0x00 */
1342 U32 Reserved1; /* 0x08 */
1343 U32 Reserved2; /* 0x0C */
1344 U16 SlotNumber; /* 0x10 */
1345 U16 Reserved3; /* 0x12 */
1346 U32 Reserved4; /* 0x14 */
1347} MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1348 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1349 Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t;
1350
1351typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME
1352{
1353 U64 DeviceName; /* 0x00 */
1354 U8 LUN[8]; /* 0x08 */
1355 U32 Reserved1; /* 0x10 */
1356 U32 Reserved2; /* 0x14 */
1357} MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
1358 Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t;
1359
1360typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE
1361{
1362 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
1363 MPI2_BOOT_DEVICE_SAS_WWID SasWwid;
1364 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1365 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName;
1366} MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
1367 Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t;
1368
1369typedef struct _MPI2_CONFIG_PAGE_BIOS_2
1370{
1371 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1372 U32 Reserved1; /* 0x04 */
1373 U32 Reserved2; /* 0x08 */
1374 U32 Reserved3; /* 0x0C */
1375 U32 Reserved4; /* 0x10 */
1376 U32 Reserved5; /* 0x14 */
1377 U32 Reserved6; /* 0x18 */
1378 U8 ReqBootDeviceForm; /* 0x1C */
1379 U8 Reserved7; /* 0x1D */
1380 U16 Reserved8; /* 0x1E */
1381 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */
1382 U8 ReqAltBootDeviceForm; /* 0x38 */
1383 U8 Reserved9; /* 0x39 */
1384 U16 Reserved10; /* 0x3A */
1385 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */
1386 U8 CurrentBootDeviceForm; /* 0x58 */
1387 U8 Reserved11; /* 0x59 */
1388 U16 Reserved12; /* 0x5A */
1389 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */
1390} MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2,
1391 Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t;
1392
1393#define MPI2_BIOSPAGE2_PAGEVERSION (0x04)
1394
1395/* values for BIOS Page 2 BootDeviceForm fields */
1396#define MPI2_BIOSPAGE2_FORM_MASK (0x0F)
1397#define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00)
1398#define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05)
1399#define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
1400#define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07)
1401
1402
1403/* BIOS Page 3 */
1404
1405typedef struct _MPI2_ADAPTER_INFO
1406{
1407 U8 PciBusNumber; /* 0x00 */
1408 U8 PciDeviceAndFunctionNumber; /* 0x01 */
1409 U16 AdapterFlags; /* 0x02 */
1410} MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO,
1411 Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t;
1412
1413#define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
1414#define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
1415
1416typedef struct _MPI2_CONFIG_PAGE_BIOS_3
1417{
1418 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1419 U32 GlobalFlags; /* 0x04 */
1420 U32 BiosVersion; /* 0x08 */
1421 MPI2_ADAPTER_INFO AdapterOrder[4]; /* 0x0C */
1422 U32 Reserved1; /* 0x1C */
1423} MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3,
1424 Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t;
1425
1426#define MPI2_BIOSPAGE3_PAGEVERSION (0x00)
1427
1428/* values for BIOS Page 3 GlobalFlags */
1429#define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002)
1430#define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004)
1431#define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010)
1432
1433#define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
1434#define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
1435#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020)
1436#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
1437
1438
1439/* BIOS Page 4 */
1440
1441/*
1442 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1443 * one and check the value returned for NumPhys at runtime.
1444 */
1445#ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
1446#define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1)
1447#endif
1448
1449typedef struct _MPI2_BIOS4_ENTRY
1450{
1451 U64 ReassignmentWWID; /* 0x00 */
1452 U64 ReassignmentDeviceName; /* 0x08 */
1453} MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY,
1454 Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t;
1455
1456typedef struct _MPI2_CONFIG_PAGE_BIOS_4
1457{
1458 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1459 U8 NumPhys; /* 0x04 */
1460 U8 Reserved1; /* 0x05 */
1461 U16 Reserved2; /* 0x06 */
1462 MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */
1463} MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4,
1464 Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t;
1465
1466#define MPI2_BIOSPAGE4_PAGEVERSION (0x01)
1467
1468
1469/****************************************************************************
1470* RAID Volume Config Pages
1471****************************************************************************/
1472
1473/* RAID Volume Page 0 */
1474
1475typedef struct _MPI2_RAIDVOL0_PHYS_DISK
1476{
1477 U8 RAIDSetNum; /* 0x00 */
1478 U8 PhysDiskMap; /* 0x01 */
1479 U8 PhysDiskNum; /* 0x02 */
1480 U8 Reserved; /* 0x03 */
1481} MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK,
1482 Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t;
1483
1484/* defines for the PhysDiskMap field */
1485#define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
1486#define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
1487
1488typedef struct _MPI2_RAIDVOL0_SETTINGS
1489{
1490 U16 Settings; /* 0x00 */
1491 U8 HotSparePool; /* 0x01 */
1492 U8 Reserved; /* 0x02 */
1493} MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS,
1494 Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t;
1495
1496/* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1497#define MPI2_RAID_HOT_SPARE_POOL_0 (0x01)
1498#define MPI2_RAID_HOT_SPARE_POOL_1 (0x02)
1499#define MPI2_RAID_HOT_SPARE_POOL_2 (0x04)
1500#define MPI2_RAID_HOT_SPARE_POOL_3 (0x08)
1501#define MPI2_RAID_HOT_SPARE_POOL_4 (0x10)
1502#define MPI2_RAID_HOT_SPARE_POOL_5 (0x20)
1503#define MPI2_RAID_HOT_SPARE_POOL_6 (0x40)
1504#define MPI2_RAID_HOT_SPARE_POOL_7 (0x80)
1505
1506/* RAID Volume Page 0 VolumeSettings defines */
1507#define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008)
1508#define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1509
1510#define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003)
1511#define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000)
1512#define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001)
1513#define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002)
1514
1515/*
1516 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1517 * one and check the value returned for NumPhysDisks at runtime.
1518 */
1519#ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
1520#define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
1521#endif
1522
1523typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0
1524{
1525 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1526 U16 DevHandle; /* 0x04 */
1527 U8 VolumeState; /* 0x06 */
1528 U8 VolumeType; /* 0x07 */
1529 U32 VolumeStatusFlags; /* 0x08 */
1530 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */
1531 U64 MaxLBA; /* 0x10 */
1532 U32 StripeSize; /* 0x18 */
1533 U16 BlockSize; /* 0x1C */
1534 U16 Reserved1; /* 0x1E */
1535 U8 SupportedPhysDisks; /* 0x20 */
1536 U8 ResyncRate; /* 0x21 */
1537 U16 DataScrubDuration; /* 0x22 */
1538 U8 NumPhysDisks; /* 0x24 */
1539 U8 Reserved2; /* 0x25 */
1540 U8 Reserved3; /* 0x26 */
1541 U8 InactiveStatus; /* 0x27 */
1542 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */
1543} MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
1544 Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t;
1545
1546#define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A)
1547
1548/* values for RAID VolumeState */
1549#define MPI2_RAID_VOL_STATE_MISSING (0x00)
1550#define MPI2_RAID_VOL_STATE_FAILED (0x01)
1551#define MPI2_RAID_VOL_STATE_INITIALIZING (0x02)
1552#define MPI2_RAID_VOL_STATE_ONLINE (0x03)
1553#define MPI2_RAID_VOL_STATE_DEGRADED (0x04)
1554#define MPI2_RAID_VOL_STATE_OPTIMAL (0x05)
1555
1556/* values for RAID VolumeType */
1557#define MPI2_RAID_VOL_TYPE_RAID0 (0x00)
1558#define MPI2_RAID_VOL_TYPE_RAID1E (0x01)
1559#define MPI2_RAID_VOL_TYPE_RAID1 (0x02)
1560#define MPI2_RAID_VOL_TYPE_RAID10 (0x05)
1561#define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF)
1562
1563/* values for RAID Volume Page 0 VolumeStatusFlags field */
1564#define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000)
1565#define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000)
1566#define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000)
1567#define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000)
1568#define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000)
1569#define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000)
1570#define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000)
1571#define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000)
1572#define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000)
1573#define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000)
1574#define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080)
1575#define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040)
1576#define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020)
1577#define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000)
1578#define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010)
1579#define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008)
1580#define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004)
1581#define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002)
1582#define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001)
1583
1584/* values for RAID Volume Page 0 SupportedPhysDisks field */
1585#define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08)
1586#define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04)
1587#define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02)
1588#define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01)
1589
1590/* values for RAID Volume Page 0 InactiveStatus field */
1591#define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
1592#define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
1593#define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
1594#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
1595#define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
1596#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
1597#define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
1598
1599
1600/* RAID Volume Page 1 */
1601
1602typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1
1603{
1604 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1605 U16 DevHandle; /* 0x04 */
1606 U16 Reserved0; /* 0x06 */
1607 U8 GUID[24]; /* 0x08 */
1608 U8 Name[16]; /* 0x20 */
1609 U64 WWID; /* 0x30 */
1610 U32 Reserved1; /* 0x38 */
1611 U32 Reserved2; /* 0x3C */
1612} MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
1613 Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t;
1614
1615#define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03)
1616
1617
1618/****************************************************************************
1619* RAID Physical Disk Config Pages
1620****************************************************************************/
1621
1622/* RAID Physical Disk Page 0 */
1623
1624typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS
1625{
1626 U16 Reserved1; /* 0x00 */
1627 U8 HotSparePool; /* 0x02 */
1628 U8 Reserved2; /* 0x03 */
1629} MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
1630 Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t;
1631
1632/* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
1633
1634typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA
1635{
1636 U8 VendorID[8]; /* 0x00 */
1637 U8 ProductID[16]; /* 0x08 */
1638 U8 ProductRevLevel[4]; /* 0x18 */
1639 U8 SerialNum[32]; /* 0x1C */
1640} MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1641 MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1642 Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t;
1643
1644typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0
1645{
1646 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1647 U16 DevHandle; /* 0x04 */
1648 U8 Reserved1; /* 0x06 */
1649 U8 PhysDiskNum; /* 0x07 */
1650 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */
1651 U32 Reserved2; /* 0x0C */
1652 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */
1653 U32 Reserved3; /* 0x4C */
1654 U8 PhysDiskState; /* 0x50 */
1655 U8 OfflineReason; /* 0x51 */
1656 U8 IncompatibleReason; /* 0x52 */
1657 U8 PhysDiskAttributes; /* 0x53 */
1658 U32 PhysDiskStatusFlags; /* 0x54 */
1659 U64 DeviceMaxLBA; /* 0x58 */
1660 U64 HostMaxLBA; /* 0x60 */
1661 U64 CoercedMaxLBA; /* 0x68 */
1662 U16 BlockSize; /* 0x70 */
1663 U16 Reserved5; /* 0x72 */
1664 U32 Reserved6; /* 0x74 */
1665} MPI2_CONFIG_PAGE_RD_PDISK_0,
1666 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
1667 Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t;
1668
1669#define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05)
1670
1671/* PhysDiskState defines */
1672#define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00)
1673#define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01)
1674#define MPI2_RAID_PD_STATE_OFFLINE (0x02)
1675#define MPI2_RAID_PD_STATE_ONLINE (0x03)
1676#define MPI2_RAID_PD_STATE_HOT_SPARE (0x04)
1677#define MPI2_RAID_PD_STATE_DEGRADED (0x05)
1678#define MPI2_RAID_PD_STATE_REBUILDING (0x06)
1679#define MPI2_RAID_PD_STATE_OPTIMAL (0x07)
1680
1681/* OfflineReason defines */
1682#define MPI2_PHYSDISK0_ONLINE (0x00)
1683#define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01)
1684#define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03)
1685#define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04)
1686#define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05)
1687#define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06)
1688#define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF)
1689
1690/* IncompatibleReason defines */
1691#define MPI2_PHYSDISK0_COMPATIBLE (0x00)
1692#define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01)
1693#define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02)
1694#define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03)
1695#define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04)
1696#define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05)
1697#define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06)
1698#define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF)
1699
1700/* PhysDiskAttributes defines */
1701#define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C)
1702#define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08)
1703#define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04)
1704
1705#define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03)
1706#define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02)
1707#define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01)
1708
1709/* PhysDiskStatusFlags defines */
1710#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040)
1711#define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020)
1712#define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010)
1713#define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000)
1714#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
1715#define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004)
1716#define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002)
1717#define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001)
1718
1719
1720/* RAID Physical Disk Page 1 */
1721
1722/*
1723 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1724 * one and check the value returned for NumPhysDiskPaths at runtime.
1725 */
1726#ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
1727#define MPI2_RAID_PHYS_DISK1_PATH_MAX (1)
1728#endif
1729
1730typedef struct _MPI2_RAIDPHYSDISK1_PATH
1731{
1732 U16 DevHandle; /* 0x00 */
1733 U16 Reserved1; /* 0x02 */
1734 U64 WWID; /* 0x04 */
1735 U64 OwnerWWID; /* 0x0C */
1736 U8 OwnerIdentifier; /* 0x14 */
1737 U8 Reserved2; /* 0x15 */
1738 U16 Flags; /* 0x16 */
1739} MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH,
1740 Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t;
1741
1742/* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
1743#define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004)
1744#define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
1745#define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
1746
1747typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1
1748{
1749 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1750 U8 NumPhysDiskPaths; /* 0x04 */
1751 U8 PhysDiskNum; /* 0x05 */
1752 U16 Reserved1; /* 0x06 */
1753 U32 Reserved2; /* 0x08 */
1754 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */
1755} MPI2_CONFIG_PAGE_RD_PDISK_1,
1756 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
1757 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t;
1758
1759#define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02)
1760
1761
1762/****************************************************************************
1763* values for fields used by several types of SAS Config Pages
1764****************************************************************************/
1765
1766/* values for NegotiatedLinkRates fields */
1767#define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0)
1768#define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4)
1769#define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F)
1770/* link rates used for Negotiated Physical and Logical Link Rate */
1771#define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00)
1772#define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01)
1773#define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02)
1774#define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03)
1775#define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04)
1776#define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05)
1777#define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06)
1778#define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08)
1779#define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09)
1780#define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A)
1781
1782
1783/* values for AttachedPhyInfo fields */
1784#define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040)
1785#define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020)
1786#define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010)
1787
1788#define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F)
1789#define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000)
1790#define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001)
1791#define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002)
1792#define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003)
1793#define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004)
1794#define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005)
1795#define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006)
1796#define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007)
1797#define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008)
1798
1799
1800/* values for PhyInfo fields */
1801#define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000)
1802
1803#define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000)
1804#define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27)
1805#define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000)
1806#define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000)
1807#define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000)
1808
1809#define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000)
1810#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000)
1811#define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000)
1812#define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000)
1813#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000)
1814#define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000)
1815
1816#define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000)
1817#define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000)
1818#define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000)
1819#define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000)
1820#define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000)
1821#define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000)
1822#define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000)
1823#define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000)
1824#define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000)
1825#define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000)
1826
1827#define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000)
1828#define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
1829#define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000)
1830#define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000)
1831
1832#define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
1833#define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
1834
1835#define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
1836#define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000)
1837#define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
1838#define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020)
1839
1840
1841/* values for SAS ProgrammedLinkRate fields */
1842#define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0)
1843#define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
1844#define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80)
1845#define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90)
1846#define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0)
1847#define MPI25_SAS_PRATE_MAX_RATE_12_0 (0xB0)
1848#define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F)
1849#define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
1850#define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08)
1851#define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09)
1852#define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A)
1853
1854
1855/* values for SAS HwLinkRate fields */
1856#define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0)
1857#define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80)
1858#define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90)
1859#define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0)
1860#define MPI25_SAS_HWRATE_MAX_RATE_12_0 (0xB0)
1861#define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F)
1862#define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08)
1863#define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09)
1864#define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A)
1865
1866
1867
1868/****************************************************************************
1869* SAS IO Unit Config Pages
1870****************************************************************************/
1871
1872/* SAS IO Unit Page 0 */
1873
1874typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA
1875{
1876 U8 Port; /* 0x00 */
1877 U8 PortFlags; /* 0x01 */
1878 U8 PhyFlags; /* 0x02 */
1879 U8 NegotiatedLinkRate; /* 0x03 */
1880 U32 ControllerPhyDeviceInfo;/* 0x04 */
1881 U16 AttachedDevHandle; /* 0x08 */
1882 U16 ControllerDevHandle; /* 0x0A */
1883 U32 DiscoveryStatus; /* 0x0C */
1884 U32 Reserved; /* 0x10 */
1885} MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
1886 Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t;
1887
1888/*
1889 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1890 * one and check the value returned for NumPhys at runtime.
1891 */
1892#ifndef MPI2_SAS_IOUNIT0_PHY_MAX
1893#define MPI2_SAS_IOUNIT0_PHY_MAX (1)
1894#endif
1895
1896typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0
1897{
1898 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1899 U32 Reserved1; /* 0x08 */
1900 U8 NumPhys; /* 0x0C */
1901 U8 Reserved2; /* 0x0D */
1902 U16 Reserved3; /* 0x0E */
1903 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */
1904} MPI2_CONFIG_PAGE_SASIOUNIT_0,
1905 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
1906 Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t;
1907
1908#define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05)
1909
1910/* values for SAS IO Unit Page 0 PortFlags */
1911#define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08)
1912#define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01)
1913
1914/* values for SAS IO Unit Page 0 PhyFlags */
1915#define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10)
1916#define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
1917
1918/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
1919
1920/* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
1921
1922/* values for SAS IO Unit Page 0 DiscoveryStatus */
1923#define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
1924#define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
1925#define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000)
1926#define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
1927#define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000)
1928#define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
1929#define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
1930#define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000)
1931#define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
1932#define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
1933#define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400)
1934#define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
1935#define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
1936#define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
1937#define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
1938#define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
1939#define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010)
1940#define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
1941#define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
1942#define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001)
1943
1944
1945/* SAS IO Unit Page 1 */
1946
1947typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA
1948{
1949 U8 Port; /* 0x00 */
1950 U8 PortFlags; /* 0x01 */
1951 U8 PhyFlags; /* 0x02 */
1952 U8 MaxMinLinkRate; /* 0x03 */
1953 U32 ControllerPhyDeviceInfo; /* 0x04 */
1954 U16 MaxTargetPortConnectTime; /* 0x08 */
1955 U16 Reserved1; /* 0x0A */
1956} MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
1957 Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t;
1958
1959/*
1960 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1961 * one and check the value returned for NumPhys at runtime.
1962 */
1963#ifndef MPI2_SAS_IOUNIT1_PHY_MAX
1964#define MPI2_SAS_IOUNIT1_PHY_MAX (1)
1965#endif
1966
1967typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1
1968{
1969 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1970 U16 ControlFlags; /* 0x08 */
1971 U16 SASNarrowMaxQueueDepth; /* 0x0A */
1972 U16 AdditionalControlFlags; /* 0x0C */
1973 U16 SASWideMaxQueueDepth; /* 0x0E */
1974 U8 NumPhys; /* 0x10 */
1975 U8 SATAMaxQDepth; /* 0x11 */
1976 U8 ReportDeviceMissingDelay; /* 0x12 */
1977 U8 IODeviceMissingDelay; /* 0x13 */
1978 MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */
1979} MPI2_CONFIG_PAGE_SASIOUNIT_1,
1980 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
1981 Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t;
1982
1983#define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09)
1984
1985/* values for SAS IO Unit Page 1 ControlFlags */
1986#define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
1987#define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
1988#define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)
1989#define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
1990
1991#define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
1992#define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
1993#define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0)
1994#define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1)
1995#define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2)
1996
1997#define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
1998#define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
1999#define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
2000#define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
2001#define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008)
2002#define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
2003#define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
2004#define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)
2005
2006/* values for SAS IO Unit Page 1 AdditionalControlFlags */
2007#define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080)
2008#define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040)
2009#define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020)
2010#define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010)
2011#define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008)
2012#define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
2013#define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
2014#define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
2015
2016/* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
2017#define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)
2018#define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80)
2019
2020/* values for SAS IO Unit Page 1 PortFlags */
2021#define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
2022
2023/* values for SAS IO Unit Page 1 PhyFlags */
2024#define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10)
2025#define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
2026
2027/* values for SAS IO Unit Page 1 MaxMinLinkRate */
2028#define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0)
2029#define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80)
2030#define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90)
2031#define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0)
2032#define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F)
2033#define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08)
2034#define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09)
2035#define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A)
2036
2037/* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
2038
2039
2040/* SAS IO Unit Page 4 */
2041
2042typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP
2043{
2044 U8 MaxTargetSpinup; /* 0x00 */
2045 U8 SpinupDelay; /* 0x01 */
2046 U8 SpinupFlags; /* 0x02 */
2047 U8 Reserved1; /* 0x03 */
2048} MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
2049 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t;
2050
2051/* defines for SAS IO Unit Page 4 SpinupFlags */
2052#define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG (0x01)
2053
2054/*
2055 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2056 * one and check the value returned for NumPhys at runtime.
2057 */
2058#ifndef MPI2_SAS_IOUNIT4_PHY_MAX
2059#define MPI2_SAS_IOUNIT4_PHY_MAX (4)
2060#endif
2061
2062typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4
2063{
2064 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2065 MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */
2066 U32 Reserved1; /* 0x18 */
2067 U32 Reserved2; /* 0x1C */
2068 U32 Reserved3; /* 0x20 */
2069 U8 BootDeviceWaitTime; /* 0x24 */
2070 U8 Reserved4; /* 0x25 */
2071 U16 Reserved5; /* 0x26 */
2072 U8 NumPhys; /* 0x28 */
2073 U8 PEInitialSpinupDelay; /* 0x29 */
2074 U8 PEReplyDelay; /* 0x2A */
2075 U8 Flags; /* 0x2B */
2076 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */
2077} MPI2_CONFIG_PAGE_SASIOUNIT_4,
2078 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
2079 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t;
2080
2081#define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02)
2082
2083/* defines for Flags field */
2084#define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01)
2085
2086/* defines for PHY field */
2087#define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03)
2088
2089
2090/* SAS IO Unit Page 5 */
2091
2092typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS {
2093 U8 ControlFlags; /* 0x00 */
2094 U8 PortWidthModGroup; /* 0x01 */
2095 U16 InactivityTimerExponent; /* 0x02 */
2096 U8 SATAPartialTimeout; /* 0x04 */
2097 U8 Reserved2; /* 0x05 */
2098 U8 SATASlumberTimeout; /* 0x06 */
2099 U8 Reserved3; /* 0x07 */
2100 U8 SASPartialTimeout; /* 0x08 */
2101 U8 Reserved4; /* 0x09 */
2102 U8 SASSlumberTimeout; /* 0x0A */
2103 U8 Reserved5; /* 0x0B */
2104} MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2105 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2106 Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t;
2107
2108/* defines for ControlFlags field */
2109#define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08)
2110#define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04)
2111#define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02)
2112#define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01)
2113
2114/* defines for PortWidthModeGroup field */
2115#define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF)
2116
2117/* defines for InactivityTimerExponent field */
2118#define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000)
2119#define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12)
2120#define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700)
2121#define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8)
2122#define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070)
2123#define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4)
2124#define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007)
2125#define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0)
2126
2127#define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7)
2128#define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6)
2129#define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5)
2130#define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4)
2131#define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3)
2132#define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2)
2133#define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1)
2134#define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0)
2135
2136/*
2137 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2138 * one and check the value returned for NumPhys at runtime.
2139 */
2140#ifndef MPI2_SAS_IOUNIT5_PHY_MAX
2141#define MPI2_SAS_IOUNIT5_PHY_MAX (1)
2142#endif
2143
2144typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 {
2145 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2146 U8 NumPhys; /* 0x08 */
2147 U8 Reserved1; /* 0x09 */
2148 U16 Reserved2; /* 0x0A */
2149 U32 Reserved3; /* 0x0C */
2150 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings
2151 [MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */
2152} MPI2_CONFIG_PAGE_SASIOUNIT_5,
2153 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
2154 Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t;
2155
2156#define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01)
2157
2158
2159/* SAS IO Unit Page 6 */
2160
2161typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS {
2162 U8 CurrentStatus; /* 0x00 */
2163 U8 CurrentModulation; /* 0x01 */
2164 U8 CurrentUtilization; /* 0x02 */
2165 U8 Reserved1; /* 0x03 */
2166 U32 Reserved2; /* 0x04 */
2167} MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2168 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2169 Mpi2SasIOUnit6PortWidthModGroupStatus_t,
2170 MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t;
2171
2172/* defines for CurrentStatus field */
2173#define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00)
2174#define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01)
2175#define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02)
2176#define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03)
2177#define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04)
2178#define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05)
2179#define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06)
2180#define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07)
2181
2182/* defines for CurrentModulation field */
2183#define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00)
2184#define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01)
2185#define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02)
2186#define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03)
2187
2188/*
2189 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2190 * one and check the value returned for NumGroups at runtime.
2191 */
2192#ifndef MPI2_SAS_IOUNIT6_GROUP_MAX
2193#define MPI2_SAS_IOUNIT6_GROUP_MAX (1)
2194#endif
2195
2196typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 {
2197 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2198 U32 Reserved1; /* 0x08 */
2199 U32 Reserved2; /* 0x0C */
2200 U8 NumGroups; /* 0x10 */
2201 U8 Reserved3; /* 0x11 */
2202 U16 Reserved4; /* 0x12 */
2203 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2204 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */
2205} MPI2_CONFIG_PAGE_SASIOUNIT_6,
2206 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6,
2207 Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t;
2208
2209#define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00)
2210
2211
2212/* SAS IO Unit Page 7 */
2213
2214typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS {
2215 U8 Flags; /* 0x00 */
2216 U8 Reserved1; /* 0x01 */
2217 U16 Reserved2; /* 0x02 */
2218 U8 Threshold75Pct; /* 0x04 */
2219 U8 Threshold50Pct; /* 0x05 */
2220 U8 Threshold25Pct; /* 0x06 */
2221 U8 Reserved3; /* 0x07 */
2222} MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2223 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2224 Mpi2SasIOUnit7PortWidthModGroupSettings_t,
2225 MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t;
2226
2227/* defines for Flags field */
2228#define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01)
2229
2230
2231/*
2232 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2233 * one and check the value returned for NumGroups at runtime.
2234 */
2235#ifndef MPI2_SAS_IOUNIT7_GROUP_MAX
2236#define MPI2_SAS_IOUNIT7_GROUP_MAX (1)
2237#endif
2238
2239typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 {
2240 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2241 U8 SamplingInterval; /* 0x08 */
2242 U8 WindowLength; /* 0x09 */
2243 U16 Reserved1; /* 0x0A */
2244 U32 Reserved2; /* 0x0C */
2245 U32 Reserved3; /* 0x10 */
2246 U8 NumGroups; /* 0x14 */
2247 U8 Reserved4; /* 0x15 */
2248 U16 Reserved5; /* 0x16 */
2249 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2250 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */
2251} MPI2_CONFIG_PAGE_SASIOUNIT_7,
2252 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7,
2253 Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t;
2254
2255#define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00)
2256
2257
2258/* SAS IO Unit Page 8 */
2259
2260typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 {
2261 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2262 U32 Reserved1; /* 0x08 */
2263 U32 PowerManagementCapabilities;/* 0x0C */
2264 U32 Reserved2; /* 0x10 */
2265} MPI2_CONFIG_PAGE_SASIOUNIT_8,
2266 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8,
2267 Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t;
2268
2269#define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00)
2270
2271/* defines for PowerManagementCapabilities field */
2272#define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000)
2273#define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800)
2274#define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400)
2275#define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200)
2276#define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100)
2277#define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010)
2278#define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008)
2279#define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004)
2280#define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002)
2281#define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001)
2282
2283
2284
2285/* SAS IO Unit Page 16 */
2286
2287typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16 {
2288 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2289 U64 TimeStamp; /* 0x08 */
2290 U32 Reserved1; /* 0x10 */
2291 U32 Reserved2; /* 0x14 */
2292 U32 FastPathPendedRequests; /* 0x18 */
2293 U32 FastPathUnPendedRequests; /* 0x1C */
2294 U32 FastPathHostRequestStarts; /* 0x20 */
2295 U32 FastPathFirmwareRequestStarts; /* 0x24 */
2296 U32 FastPathHostCompletions; /* 0x28 */
2297 U32 FastPathFirmwareCompletions; /* 0x2C */
2298 U32 NonFastPathRequestStarts; /* 0x30 */
2299 U32 NonFastPathHostCompletions; /* 0x30 */
2300} MPI2_CONFIG_PAGE_SASIOUNIT16,
2301MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT16,
2302Mpi2SasIOUnitPage16_t, MPI2_POINTER pMpi2SasIOUnitPage16_t;
2303
2304#define MPI2_SASIOUNITPAGE16_PAGEVERSION (0x00)
2305
2306
2307/****************************************************************************
2308* SAS Expander Config Pages
2309****************************************************************************/
2310
2311/* SAS Expander Page 0 */
2312
2313typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0
2314{
2315 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2316 U8 PhysicalPort; /* 0x08 */
2317 U8 ReportGenLength; /* 0x09 */
2318 U16 EnclosureHandle; /* 0x0A */
2319 U64 SASAddress; /* 0x0C */
2320 U32 DiscoveryStatus; /* 0x14 */
2321 U16 DevHandle; /* 0x18 */
2322 U16 ParentDevHandle; /* 0x1A */
2323 U16 ExpanderChangeCount; /* 0x1C */
2324 U16 ExpanderRouteIndexes; /* 0x1E */
2325 U8 NumPhys; /* 0x20 */
2326 U8 SASLevel; /* 0x21 */
2327 U16 Flags; /* 0x22 */
2328 U16 STPBusInactivityTimeLimit; /* 0x24 */
2329 U16 STPMaxConnectTimeLimit; /* 0x26 */
2330 U16 STP_SMP_NexusLossTime; /* 0x28 */
2331 U16 MaxNumRoutedSasAddresses; /* 0x2A */
2332 U64 ActiveZoneManagerSASAddress;/* 0x2C */
2333 U16 ZoneLockInactivityLimit; /* 0x34 */
2334 U16 Reserved1; /* 0x36 */
2335 U8 TimeToReducedFunc; /* 0x38 */
2336 U8 InitialTimeToReducedFunc; /* 0x39 */
2337 U8 MaxReducedFuncTime; /* 0x3A */
2338 U8 Reserved2; /* 0x3B */
2339} MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
2340 Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t;
2341
2342#define MPI2_SASEXPANDER0_PAGEVERSION (0x06)
2343
2344/* values for SAS Expander Page 0 DiscoveryStatus field */
2345#define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
2346#define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
2347#define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000)
2348#define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
2349#define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000)
2350#define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2351#define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
2352#define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000)
2353#define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
2354#define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
2355#define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
2356#define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
2357#define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
2358#define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
2359#define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
2360#define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2361#define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
2362#define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
2363#define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2364#define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
2365
2366/* values for SAS Expander Page 0 Flags field */
2367#define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000)
2368#define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000)
2369#define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800)
2370#define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400)
2371#define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200)
2372#define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100)
2373#define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080)
2374#define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010)
2375#define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004)
2376#define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002)
2377#define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001)
2378
2379
2380/* SAS Expander Page 1 */
2381
2382typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1
2383{
2384 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2385 U8 PhysicalPort; /* 0x08 */
2386 U8 Reserved1; /* 0x09 */
2387 U16 Reserved2; /* 0x0A */
2388 U8 NumPhys; /* 0x0C */
2389 U8 Phy; /* 0x0D */
2390 U16 NumTableEntriesProgrammed; /* 0x0E */
2391 U8 ProgrammedLinkRate; /* 0x10 */
2392 U8 HwLinkRate; /* 0x11 */
2393 U16 AttachedDevHandle; /* 0x12 */
2394 U32 PhyInfo; /* 0x14 */
2395 U32 AttachedDeviceInfo; /* 0x18 */
2396 U16 ExpanderDevHandle; /* 0x1C */
2397 U8 ChangeCount; /* 0x1E */
2398 U8 NegotiatedLinkRate; /* 0x1F */
2399 U8 PhyIdentifier; /* 0x20 */
2400 U8 AttachedPhyIdentifier; /* 0x21 */
2401 U8 Reserved3; /* 0x22 */
2402 U8 DiscoveryInfo; /* 0x23 */
2403 U32 AttachedPhyInfo; /* 0x24 */
2404 U8 ZoneGroup; /* 0x28 */
2405 U8 SelfConfigStatus; /* 0x29 */
2406 U16 Reserved4; /* 0x2A */
2407} MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
2408 Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t;
2409
2410#define MPI2_SASEXPANDER1_PAGEVERSION (0x02)
2411
2412/* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2413
2414/* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2415
2416/* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2417
2418/* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */
2419
2420/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2421
2422/* values for SAS Expander Page 1 DiscoveryInfo field */
2423#define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04)
2424#define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
2425#define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
2426
2427/* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2428
2429/****************************************************************************
2430* SAS Device Config Pages
2431****************************************************************************/
2432
2433/* SAS Device Page 0 */
2434
2435typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0
2436{
2437 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2438 U16 Slot; /* 0x08 */
2439 U16 EnclosureHandle; /* 0x0A */
2440 U64 SASAddress; /* 0x0C */
2441 U16 ParentDevHandle; /* 0x14 */
2442 U8 PhyNum; /* 0x16 */
2443 U8 AccessStatus; /* 0x17 */
2444 U16 DevHandle; /* 0x18 */
2445 U8 AttachedPhyIdentifier; /* 0x1A */
2446 U8 ZoneGroup; /* 0x1B */
2447 U32 DeviceInfo; /* 0x1C */
2448 U16 Flags; /* 0x20 */
2449 U8 PhysicalPort; /* 0x22 */
2450 U8 MaxPortConnections; /* 0x23 */
2451 U64 DeviceName; /* 0x24 */
2452 U8 PortGroups; /* 0x2C */
2453 U8 DmaGroup; /* 0x2D */
2454 U8 ControlGroup; /* 0x2E */
2455 U8 EnclosureLevel; /* 0x2F */
2456 U8 ConnectorName[4]; /* 0x30 */
2457 U32 Reserved3; /* 0x34 */
2458} MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
2459 Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t;
2460
2461#define MPI2_SASDEVICE0_PAGEVERSION (0x09)
2462
2463/* values for SAS Device Page 0 AccessStatus field */
2464#define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
2465#define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
2466#define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
2467#define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03)
2468#define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04)
2469#define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05)
2470#define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06)
2471#define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07)
2472/* specific values for SATA Init failures */
2473#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10)
2474#define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11)
2475#define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12)
2476#define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13)
2477#define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14)
2478#define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15)
2479#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16)
2480#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17)
2481#define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18)
2482#define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19)
2483#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F)
2484
2485/* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
2486
2487/* values for SAS Device Page 0 Flags field */
2488#define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000)
2489#define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000)
2490#define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800)
2491#define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)
2492#define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
2493#define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
2494#define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
2495#define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
2496#define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
2497#define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
2498#define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
2499#define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID (0x0002)
2500#define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
2501
2502
2503/* SAS Device Page 1 */
2504
2505typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1
2506{
2507 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2508 U32 Reserved1; /* 0x08 */
2509 U64 SASAddress; /* 0x0C */
2510 U32 Reserved2; /* 0x14 */
2511 U16 DevHandle; /* 0x18 */
2512 U16 Reserved3; /* 0x1A */
2513 U8 InitialRegDeviceFIS[20];/* 0x1C */
2514} MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
2515 Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t;
2516
2517#define MPI2_SASDEVICE1_PAGEVERSION (0x01)
2518
2519
2520/****************************************************************************
2521* SAS PHY Config Pages
2522****************************************************************************/
2523
2524/* SAS PHY Page 0 */
2525
2526typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0
2527{
2528 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2529 U16 OwnerDevHandle; /* 0x08 */
2530 U16 Reserved1; /* 0x0A */
2531 U16 AttachedDevHandle; /* 0x0C */
2532 U8 AttachedPhyIdentifier; /* 0x0E */
2533 U8 Reserved2; /* 0x0F */
2534 U32 AttachedPhyInfo; /* 0x10 */
2535 U8 ProgrammedLinkRate; /* 0x14 */
2536 U8 HwLinkRate; /* 0x15 */
2537 U8 ChangeCount; /* 0x16 */
2538 U8 Flags; /* 0x17 */
2539 U32 PhyInfo; /* 0x18 */
2540 U8 NegotiatedLinkRate; /* 0x1C */
2541 U8 Reserved3; /* 0x1D */
2542 U16 Reserved4; /* 0x1E */
2543} MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
2544 Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t;
2545
2546#define MPI2_SASPHY0_PAGEVERSION (0x03)
2547
2548/* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2549
2550/* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2551
2552/* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2553
2554/* values for SAS PHY Page 0 Flags field */
2555#define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
2556
2557/* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2558
2559/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2560
2561
2562/* SAS PHY Page 1 */
2563
2564typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1
2565{
2566 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2567 U32 Reserved1; /* 0x08 */
2568 U32 InvalidDwordCount; /* 0x0C */
2569 U32 RunningDisparityErrorCount; /* 0x10 */
2570 U32 LossDwordSynchCount; /* 0x14 */
2571 U32 PhyResetProblemCount; /* 0x18 */
2572} MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
2573 Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t;
2574
2575#define MPI2_SASPHY1_PAGEVERSION (0x01)
2576
2577
2578/* SAS PHY Page 2 */
2579
2580typedef struct _MPI2_SASPHY2_PHY_EVENT {
2581 U8 PhyEventCode; /* 0x00 */
2582 U8 Reserved1; /* 0x01 */
2583 U16 Reserved2; /* 0x02 */
2584 U32 PhyEventInfo; /* 0x04 */
2585} MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT,
2586 Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t;
2587
2588/* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
2589
2590
2591/*
2592 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2593 * one and check the value returned for NumPhyEvents at runtime.
2594 */
2595#ifndef MPI2_SASPHY2_PHY_EVENT_MAX
2596#define MPI2_SASPHY2_PHY_EVENT_MAX (1)
2597#endif
2598
2599typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 {
2600 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2601 U32 Reserved1; /* 0x08 */
2602 U8 NumPhyEvents; /* 0x0C */
2603 U8 Reserved2; /* 0x0D */
2604 U16 Reserved3; /* 0x0E */
2605 MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX];
2606 /* 0x10 */
2607} MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
2608 Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t;
2609
2610#define MPI2_SASPHY2_PAGEVERSION (0x00)
2611
2612
2613/* SAS PHY Page 3 */
2614
2615typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG {
2616 U8 PhyEventCode; /* 0x00 */
2617 U8 Reserved1; /* 0x01 */
2618 U16 Reserved2; /* 0x02 */
2619 U8 CounterType; /* 0x04 */
2620 U8 ThresholdWindow; /* 0x05 */
2621 U8 TimeUnits; /* 0x06 */
2622 U8 Reserved3; /* 0x07 */
2623 U32 EventThreshold; /* 0x08 */
2624 U16 ThresholdFlags; /* 0x0C */
2625 U16 Reserved4; /* 0x0E */
2626} MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
2627 Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t;
2628
2629/* values for PhyEventCode field */
2630#define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00)
2631#define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01)
2632#define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02)
2633#define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03)
2634#define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04)
2635#define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05)
2636#define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06)
2637#define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20)
2638#define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21)
2639#define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22)
2640#define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23)
2641#define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24)
2642#define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25)
2643#define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26)
2644#define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27)
2645#define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28)
2646#define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29)
2647#define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A)
2648#define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B)
2649#define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C)
2650#define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D)
2651#define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E)
2652#define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40)
2653#define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41)
2654#define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42)
2655#define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43)
2656#define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44)
2657#define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45)
2658#define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50)
2659#define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51)
2660#define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52)
2661#define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60)
2662#define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61)
2663#define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63)
2664#define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0)
2665#define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1)
2666#define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2)
2667
2668/* values for the CounterType field */
2669#define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00)
2670#define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01)
2671#define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02)
2672
2673/* values for the TimeUnits field */
2674#define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00)
2675#define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01)
2676#define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02)
2677#define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03)
2678
2679/* values for the ThresholdFlags field */
2680#define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002)
2681#define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001)
2682
2683/*
2684 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2685 * one and check the value returned for NumPhyEvents at runtime.
2686 */
2687#ifndef MPI2_SASPHY3_PHY_EVENT_MAX
2688#define MPI2_SASPHY3_PHY_EVENT_MAX (1)
2689#endif
2690
2691typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 {
2692 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2693 U32 Reserved1; /* 0x08 */
2694 U8 NumPhyEvents; /* 0x0C */
2695 U8 Reserved2; /* 0x0D */
2696 U16 Reserved3; /* 0x0E */
2697 MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig
2698 [MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */
2699} MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
2700 Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t;
2701
2702#define MPI2_SASPHY3_PAGEVERSION (0x00)
2703
2704
2705/* SAS PHY Page 4 */
2706
2707typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 {
2708 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2709 U16 Reserved1; /* 0x08 */
2710 U8 Reserved2; /* 0x0A */
2711 U8 Flags; /* 0x0B */
2712 U8 InitialFrame[28]; /* 0x0C */
2713} MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4,
2714 Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t;
2715
2716#define MPI2_SASPHY4_PAGEVERSION (0x00)
2717
2718/* values for the Flags field */
2719#define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02)
2720#define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01)
2721
2722
2723
2724
2725/****************************************************************************
2726* SAS Port Config Pages
2727****************************************************************************/
2728
2729/* SAS Port Page 0 */
2730
2731typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0
2732{
2733 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2734 U8 PortNumber; /* 0x08 */
2735 U8 PhysicalPort; /* 0x09 */
2736 U8 PortWidth; /* 0x0A */
2737 U8 PhysicalPortWidth; /* 0x0B */
2738 U8 ZoneGroup; /* 0x0C */
2739 U8 Reserved1; /* 0x0D */
2740 U16 Reserved2; /* 0x0E */
2741 U64 SASAddress; /* 0x10 */
2742 U32 DeviceInfo; /* 0x18 */
2743 U32 Reserved3; /* 0x1C */
2744 U32 Reserved4; /* 0x20 */
2745} MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
2746 Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t;
2747
2748#define MPI2_SASPORT0_PAGEVERSION (0x00)
2749
2750/* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
2751
2752
2753/****************************************************************************
2754* SAS Enclosure Config Pages
2755****************************************************************************/
2756
2757/* SAS Enclosure Page 0 */
2758
2759typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0
2760{
2761 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2762 U32 Reserved1; /* 0x08 */
2763 U64 EnclosureLogicalID; /* 0x0C */
2764 U16 Flags; /* 0x14 */
2765 U16 EnclosureHandle; /* 0x16 */
2766 U16 NumSlots; /* 0x18 */
2767 U16 StartSlot; /* 0x1A */
2768 U8 Reserved2; /* 0x1C */
2769 U8 EnclosureLevel; /* 0x1D */
2770 U16 SEPDevHandle; /* 0x1E */
2771 U32 Reserved3; /* 0x20 */
2772 U32 Reserved4; /* 0x24 */
2773} MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2774 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2775 Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t;
2776
2777#define MPI2_SASENCLOSURE0_PAGEVERSION (0x04)
2778
2779/* values for SAS Enclosure Page 0 Flags field */
2780#define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010)
2781#define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
2782#define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
2783#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
2784#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
2785#define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
2786#define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
2787#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
2788
2789
2790/****************************************************************************
2791* Log Config Page
2792****************************************************************************/
2793
2794/* Log Page 0 */
2795
2796/*
2797 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2798 * one and check the value returned for NumLogEntries at runtime.
2799 */
2800#ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
2801#define MPI2_LOG_0_NUM_LOG_ENTRIES (1)
2802#endif
2803
2804#define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C)
2805
2806typedef struct _MPI2_LOG_0_ENTRY
2807{
2808 U64 TimeStamp; /* 0x00 */
2809 U32 Reserved1; /* 0x08 */
2810 U16 LogSequence; /* 0x0C */
2811 U16 LogEntryQualifier; /* 0x0E */
2812 U8 VP_ID; /* 0x10 */
2813 U8 VF_ID; /* 0x11 */
2814 U16 Reserved2; /* 0x12 */
2815 U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */
2816} MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY,
2817 Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t;
2818
2819/* values for Log Page 0 LogEntry LogEntryQualifier field */
2820#define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
2821#define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
2822#define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002)
2823#define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000)
2824#define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF)
2825
2826typedef struct _MPI2_CONFIG_PAGE_LOG_0
2827{
2828 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2829 U32 Reserved1; /* 0x08 */
2830 U32 Reserved2; /* 0x0C */
2831 U16 NumLogEntries; /* 0x10 */
2832 U16 Reserved3; /* 0x12 */
2833 MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */
2834} MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0,
2835 Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t;
2836
2837#define MPI2_LOG_0_PAGEVERSION (0x02)
2838
2839
2840/****************************************************************************
2841* RAID Config Page
2842****************************************************************************/
2843
2844/* RAID Page 0 */
2845
2846/*
2847 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2848 * one and check the value returned for NumElements at runtime.
2849 */
2850#ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
2851#define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1)
2852#endif
2853
2854typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT
2855{
2856 U16 ElementFlags; /* 0x00 */
2857 U16 VolDevHandle; /* 0x02 */
2858 U8 HotSparePool; /* 0x04 */
2859 U8 PhysDiskNum; /* 0x05 */
2860 U16 PhysDiskDevHandle; /* 0x06 */
2861} MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2862 MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2863 Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t;
2864
2865/* values for the ElementFlags field */
2866#define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F)
2867#define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000)
2868#define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001)
2869#define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002)
2870#define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003)
2871
2872
2873typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0
2874{
2875 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2876 U8 NumHotSpares; /* 0x08 */
2877 U8 NumPhysDisks; /* 0x09 */
2878 U8 NumVolumes; /* 0x0A */
2879 U8 ConfigNum; /* 0x0B */
2880 U32 Flags; /* 0x0C */
2881 U8 ConfigGUID[24]; /* 0x10 */
2882 U32 Reserved1; /* 0x28 */
2883 U8 NumElements; /* 0x2C */
2884 U8 Reserved2; /* 0x2D */
2885 U16 Reserved3; /* 0x2E */
2886 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */
2887} MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2888 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2889 Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t;
2890
2891#define MPI2_RAIDCONFIG0_PAGEVERSION (0x00)
2892
2893/* values for RAID Configuration Page 0 Flags field */
2894#define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001)
2895
2896
2897/****************************************************************************
2898* Driver Persistent Mapping Config Pages
2899****************************************************************************/
2900
2901/* Driver Persistent Mapping Page 0 */
2902
2903typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY
2904{
2905 U64 PhysicalIdentifier; /* 0x00 */
2906 U16 MappingInformation; /* 0x08 */
2907 U16 DeviceIndex; /* 0x0A */
2908 U32 PhysicalBitsMapping; /* 0x0C */
2909 U32 Reserved1; /* 0x10 */
2910} MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2911 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2912 Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t;
2913
2914typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0
2915{
2916 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2917 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */
2918} MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2919 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2920 Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t;
2921
2922#define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00)
2923
2924/* values for Driver Persistent Mapping Page 0 MappingInformation field */
2925#define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0)
2926#define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4)
2927#define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F)
2928
2929
2930/****************************************************************************
2931* Ethernet Config Pages
2932****************************************************************************/
2933
2934/* Ethernet Page 0 */
2935
2936/* IP address (union of IPv4 and IPv6) */
2937typedef union _MPI2_ETHERNET_IP_ADDR {
2938 U32 IPv4Addr;
2939 U32 IPv6Addr[4];
2940} MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR,
2941 Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t;
2942
2943#define MPI2_ETHERNET_HOST_NAME_LENGTH (32)
2944
2945typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 {
2946 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2947 U8 NumInterfaces; /* 0x08 */
2948 U8 Reserved0; /* 0x09 */
2949 U16 Reserved1; /* 0x0A */
2950 U32 Status; /* 0x0C */
2951 U8 MediaState; /* 0x10 */
2952 U8 Reserved2; /* 0x11 */
2953 U16 Reserved3; /* 0x12 */
2954 U8 MacAddress[6]; /* 0x14 */
2955 U8 Reserved4; /* 0x1A */
2956 U8 Reserved5; /* 0x1B */
2957 MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */
2958 MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */
2959 MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */
2960 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */
2961 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */
2962 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */
2963 U8 HostName
2964 [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
2965} MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
2966 Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t;
2967
2968#define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00)
2969
2970/* values for Ethernet Page 0 Status field */
2971#define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000)
2972#define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000)
2973#define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000)
2974#define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100)
2975#define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080)
2976#define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040)
2977#define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020)
2978#define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010)
2979#define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008)
2980#define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004)
2981#define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002)
2982#define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001)
2983
2984/* values for Ethernet Page 0 MediaState field */
2985#define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80)
2986#define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00)
2987#define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80)
2988
2989#define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07)
2990#define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00)
2991#define MPI2_ETHPG0_MS_10MBIT (0x01)
2992#define MPI2_ETHPG0_MS_100MBIT (0x02)
2993#define MPI2_ETHPG0_MS_1GBIT (0x03)
2994
2995
2996/* Ethernet Page 1 */
2997
2998typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 {
2999 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
3000 U32 Reserved0; /* 0x08 */
3001 U32 Flags; /* 0x0C */
3002 U8 MediaState; /* 0x10 */
3003 U8 Reserved1; /* 0x11 */
3004 U16 Reserved2; /* 0x12 */
3005 U8 MacAddress[6]; /* 0x14 */
3006 U8 Reserved3; /* 0x1A */
3007 U8 Reserved4; /* 0x1B */
3008 MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */
3009 MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */
3010 MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */
3011 MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */
3012 MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */
3013 U32 Reserved5; /* 0x6C */
3014 U32 Reserved6; /* 0x70 */
3015 U32 Reserved7; /* 0x74 */
3016 U32 Reserved8; /* 0x78 */
3017 U8 HostName
3018 [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
3019} MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
3020 Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t;
3021
3022#define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00)
3023
3024/* values for Ethernet Page 1 Flags field */
3025#define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100)
3026#define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080)
3027#define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040)
3028#define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020)
3029#define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010)
3030#define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008)
3031#define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004)
3032#define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002)
3033#define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001)
3034
3035/* values for Ethernet Page 1 MediaState field */
3036#define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80)
3037#define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00)
3038#define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80)
3039
3040#define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07)
3041#define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00)
3042#define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01)
3043#define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02)
3044#define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03)
3045
3046
3047/****************************************************************************
3048* Extended Manufacturing Config Pages
3049****************************************************************************/
3050
3051/*
3052 * Generic structure to use for product-specific extended manufacturing pages
3053 * (currently Extended Manufacturing Page 40 through Extended Manufacturing
3054 * Page 60).
3055 */
3056
3057typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS {
3058 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
3059 U32 ProductSpecificInfo; /* 0x08 */
3060} MPI2_CONFIG_PAGE_EXT_MAN_PS,
3061 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS,
3062 Mpi2ExtManufacturingPagePS_t,
3063 MPI2_POINTER pMpi2ExtManufacturingPagePS_t;
3064
3065/* PageVersion should be provided by product-specific code */
3066
3067#endif
3068
diff --git a/drivers/scsi/mpt2sas/mpi/mpi2_init.h b/drivers/scsi/mpt2sas/mpi/mpi2_init.h
deleted file mode 100644
index eea1a16b13ec..000000000000
--- a/drivers/scsi/mpt2sas/mpi/mpi2_init.h
+++ /dev/null
@@ -1,461 +0,0 @@
1/*
2 * Copyright (c) 2000-2014 LSI Corporation.
3 *
4 *
5 * Name: mpi2_init.h
6 * Title: MPI SCSI initiator mode messages and structures
7 * Creation Date: June 23, 2006
8 *
9 * mpi2_init.h Version: 02.00.15
10 *
11 * Version History
12 * ---------------
13 *
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
17 * 10-31-07 02.00.01 Fixed name for pMpi2SCSITaskManagementRequest_t.
18 * 12-18-07 02.00.02 Modified Task Management Target Reset Method defines.
19 * 02-29-08 02.00.03 Added Query Task Set and Query Unit Attention.
20 * 03-03-08 02.00.04 Fixed name of struct _MPI2_SCSI_TASK_MANAGE_REPLY.
21 * 05-21-08 02.00.05 Fixed typo in name of Mpi2SepRequest_t.
22 * 10-02-08 02.00.06 Removed Untagged and No Disconnect values from SCSI IO
23 * Control field Task Attribute flags.
24 * Moved LUN field defines to mpi2.h because they are
25 * common to many structures.
26 * 05-06-09 02.00.07 Changed task management type of Query Unit Attention to
27 * Query Asynchronous Event.
28 * Defined two new bits in the SlotStatus field of the SCSI
29 * Enclosure Processor Request and Reply.
30 * 10-28-09 02.00.08 Added defines for decoding the ResponseInfo bytes for
31 * both SCSI IO Error Reply and SCSI Task Management Reply.
32 * Added ResponseInfo field to MPI2_SCSI_TASK_MANAGE_REPLY.
33 * Added MPI2_SCSITASKMGMT_RSP_TM_OVERLAPPED_TAG define.
34 * 02-10-10 02.00.09 Removed unused structure that had "#if 0" around it.
35 * 05-12-10 02.00.10 Added optional vendor-unique region to SCSI IO Request.
36 * 11-10-10 02.00.11 Added MPI2_SCSIIO_NUM_SGLOFFSETS define.
37 * 02-06-12 02.00.13 Added alternate defines for Task Priority / Command
38 * Priority to match SAM-4.
39 * 07-10-12 02.00.14 Added MPI2_SCSIIO_CONTROL_SHIFT_DATADIRECTION.
40 * 04-09-13 02.00.15 Added SCSIStatusQualifier field to MPI2_SCSI_IO_REPLY,
41 * replacing the Reserved4 field.
42 * --------------------------------------------------------------------------
43 */
44
45#ifndef MPI2_INIT_H
46#define MPI2_INIT_H
47
48/*****************************************************************************
49*
50* SCSI Initiator Messages
51*
52*****************************************************************************/
53
54/****************************************************************************
55* SCSI IO messages and associated structures
56****************************************************************************/
57
58typedef struct
59{
60 U8 CDB[20]; /* 0x00 */
61 U32 PrimaryReferenceTag; /* 0x14 */
62 U16 PrimaryApplicationTag; /* 0x18 */
63 U16 PrimaryApplicationTagMask; /* 0x1A */
64 U32 TransferLength; /* 0x1C */
65} MPI2_SCSI_IO_CDB_EEDP32, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_EEDP32,
66 Mpi2ScsiIoCdbEedp32_t, MPI2_POINTER pMpi2ScsiIoCdbEedp32_t;
67
68typedef union
69{
70 U8 CDB32[32];
71 MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
72 MPI2_SGE_SIMPLE_UNION SGE;
73} MPI2_SCSI_IO_CDB_UNION, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_UNION,
74 Mpi2ScsiIoCdb_t, MPI2_POINTER pMpi2ScsiIoCdb_t;
75
76/* SCSI IO Request Message */
77typedef struct _MPI2_SCSI_IO_REQUEST
78{
79 U16 DevHandle; /* 0x00 */
80 U8 ChainOffset; /* 0x02 */
81 U8 Function; /* 0x03 */
82 U16 Reserved1; /* 0x04 */
83 U8 Reserved2; /* 0x06 */
84 U8 MsgFlags; /* 0x07 */
85 U8 VP_ID; /* 0x08 */
86 U8 VF_ID; /* 0x09 */
87 U16 Reserved3; /* 0x0A */
88 U32 SenseBufferLowAddress; /* 0x0C */
89 U16 SGLFlags; /* 0x10 */
90 U8 SenseBufferLength; /* 0x12 */
91 U8 Reserved4; /* 0x13 */
92 U8 SGLOffset0; /* 0x14 */
93 U8 SGLOffset1; /* 0x15 */
94 U8 SGLOffset2; /* 0x16 */
95 U8 SGLOffset3; /* 0x17 */
96 U32 SkipCount; /* 0x18 */
97 U32 DataLength; /* 0x1C */
98 U32 BidirectionalDataLength; /* 0x20 */
99 U16 IoFlags; /* 0x24 */
100 U16 EEDPFlags; /* 0x26 */
101 U32 EEDPBlockSize; /* 0x28 */
102 U32 SecondaryReferenceTag; /* 0x2C */
103 U16 SecondaryApplicationTag; /* 0x30 */
104 U16 ApplicationTagTranslationMask; /* 0x32 */
105 U8 LUN[8]; /* 0x34 */
106 U32 Control; /* 0x3C */
107 MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */
108
109#ifdef MPI2_SCSI_IO_VENDOR_UNIQUE_REGION /* typically this is left undefined */
110 MPI2_SCSI_IO_VENDOR_UNIQUE VendorRegion;
111#endif
112
113 MPI2_SGE_IO_UNION SGL; /* 0x60 */
114
115} MPI2_SCSI_IO_REQUEST, MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST,
116 Mpi2SCSIIORequest_t, MPI2_POINTER pMpi2SCSIIORequest_t;
117
118/* SCSI IO MsgFlags bits */
119
120/* MsgFlags for SenseBufferAddressSpace */
121#define MPI2_SCSIIO_MSGFLAGS_MASK_SENSE_ADDR (0x0C)
122#define MPI2_SCSIIO_MSGFLAGS_SYSTEM_SENSE_ADDR (0x00)
123#define MPI2_SCSIIO_MSGFLAGS_IOCDDR_SENSE_ADDR (0x04)
124#define MPI2_SCSIIO_MSGFLAGS_IOCPLB_SENSE_ADDR (0x08)
125#define MPI2_SCSIIO_MSGFLAGS_IOCPLBNTA_SENSE_ADDR (0x0C)
126
127/* SCSI IO SGLFlags bits */
128
129/* base values for Data Location Address Space */
130#define MPI2_SCSIIO_SGLFLAGS_ADDR_MASK (0x0C)
131#define MPI2_SCSIIO_SGLFLAGS_SYSTEM_ADDR (0x00)
132#define MPI2_SCSIIO_SGLFLAGS_IOCDDR_ADDR (0x04)
133#define MPI2_SCSIIO_SGLFLAGS_IOCPLB_ADDR (0x08)
134#define MPI2_SCSIIO_SGLFLAGS_IOCPLBNTA_ADDR (0x0C)
135
136/* base values for Type */
137#define MPI2_SCSIIO_SGLFLAGS_TYPE_MASK (0x03)
138#define MPI2_SCSIIO_SGLFLAGS_TYPE_MPI (0x00)
139#define MPI2_SCSIIO_SGLFLAGS_TYPE_IEEE32 (0x01)
140#define MPI2_SCSIIO_SGLFLAGS_TYPE_IEEE64 (0x02)
141
142/* shift values for each sub-field */
143#define MPI2_SCSIIO_SGLFLAGS_SGL3_SHIFT (12)
144#define MPI2_SCSIIO_SGLFLAGS_SGL2_SHIFT (8)
145#define MPI2_SCSIIO_SGLFLAGS_SGL1_SHIFT (4)
146#define MPI2_SCSIIO_SGLFLAGS_SGL0_SHIFT (0)
147
148/* number of SGLOffset fields */
149#define MPI2_SCSIIO_NUM_SGLOFFSETS (4)
150
151/* SCSI IO IoFlags bits */
152
153/* Large CDB Address Space */
154#define MPI2_SCSIIO_CDB_ADDR_MASK (0x6000)
155#define MPI2_SCSIIO_CDB_ADDR_SYSTEM (0x0000)
156#define MPI2_SCSIIO_CDB_ADDR_IOCDDR (0x2000)
157#define MPI2_SCSIIO_CDB_ADDR_IOCPLB (0x4000)
158#define MPI2_SCSIIO_CDB_ADDR_IOCPLBNTA (0x6000)
159
160#define MPI2_SCSIIO_IOFLAGS_LARGE_CDB (0x1000)
161#define MPI2_SCSIIO_IOFLAGS_BIDIRECTIONAL (0x0800)
162#define MPI2_SCSIIO_IOFLAGS_MULTICAST (0x0400)
163#define MPI2_SCSIIO_IOFLAGS_CMD_DETERMINES_DATA_DIR (0x0200)
164#define MPI2_SCSIIO_IOFLAGS_CDBLENGTH_MASK (0x01FF)
165
166/* SCSI IO EEDPFlags bits */
167
168#define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000)
169#define MPI2_SCSIIO_EEDPFLAGS_INC_SEC_REFTAG (0x4000)
170#define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_APPTAG (0x2000)
171#define MPI2_SCSIIO_EEDPFLAGS_INC_SEC_APPTAG (0x1000)
172
173#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400)
174#define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200)
175#define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100)
176
177#define MPI2_SCSIIO_EEDPFLAGS_PASSTHRU_REFTAG (0x0008)
178
179#define MPI2_SCSIIO_EEDPFLAGS_MASK_OP (0x0007)
180#define MPI2_SCSIIO_EEDPFLAGS_NOOP_OP (0x0000)
181#define MPI2_SCSIIO_EEDPFLAGS_CHECK_OP (0x0001)
182#define MPI2_SCSIIO_EEDPFLAGS_STRIP_OP (0x0002)
183#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003)
184#define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004)
185#define MPI2_SCSIIO_EEDPFLAGS_REPLACE_OP (0x0006)
186#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REGEN_OP (0x0007)
187
188/* SCSI IO LUN fields: use MPI2_LUN_ from mpi2.h */
189
190/* SCSI IO Control bits */
191#define MPI2_SCSIIO_CONTROL_ADDCDBLEN_MASK (0xFC000000)
192#define MPI2_SCSIIO_CONTROL_ADDCDBLEN_SHIFT (26)
193
194#define MPI2_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000)
195#define MPI2_SCSIIO_CONTROL_SHIFT_DATADIRECTION (24)
196#define MPI2_SCSIIO_CONTROL_NODATATRANSFER (0x00000000)
197#define MPI2_SCSIIO_CONTROL_WRITE (0x01000000)
198#define MPI2_SCSIIO_CONTROL_READ (0x02000000)
199#define MPI2_SCSIIO_CONTROL_BIDIRECTIONAL (0x03000000)
200
201#define MPI2_SCSIIO_CONTROL_TASKPRI_MASK (0x00007800)
202#define MPI2_SCSIIO_CONTROL_TASKPRI_SHIFT (11)
203/* alternate name for the previous field; called Command Priority in SAM-4 */
204#define MPI2_SCSIIO_CONTROL_CMDPRI_MASK (0x00007800)
205#define MPI2_SCSIIO_CONTROL_CMDPRI_SHIFT (11)
206
207#define MPI2_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700)
208#define MPI2_SCSIIO_CONTROL_SIMPLEQ (0x00000000)
209#define MPI2_SCSIIO_CONTROL_HEADOFQ (0x00000100)
210#define MPI2_SCSIIO_CONTROL_ORDEREDQ (0x00000200)
211#define MPI2_SCSIIO_CONTROL_ACAQ (0x00000400)
212
213#define MPI2_SCSIIO_CONTROL_TLR_MASK (0x000000C0)
214#define MPI2_SCSIIO_CONTROL_NO_TLR (0x00000000)
215#define MPI2_SCSIIO_CONTROL_TLR_ON (0x00000040)
216#define MPI2_SCSIIO_CONTROL_TLR_OFF (0x00000080)
217
218
219/* SCSI IO Error Reply Message */
220typedef struct _MPI2_SCSI_IO_REPLY
221{
222 U16 DevHandle; /* 0x00 */
223 U8 MsgLength; /* 0x02 */
224 U8 Function; /* 0x03 */
225 U16 Reserved1; /* 0x04 */
226 U8 Reserved2; /* 0x06 */
227 U8 MsgFlags; /* 0x07 */
228 U8 VP_ID; /* 0x08 */
229 U8 VF_ID; /* 0x09 */
230 U16 Reserved3; /* 0x0A */
231 U8 SCSIStatus; /* 0x0C */
232 U8 SCSIState; /* 0x0D */
233 U16 IOCStatus; /* 0x0E */
234 U32 IOCLogInfo; /* 0x10 */
235 U32 TransferCount; /* 0x14 */
236 U32 SenseCount; /* 0x18 */
237 U32 ResponseInfo; /* 0x1C */
238 U16 TaskTag; /* 0x20 */
239 U16 SCSIStatusQualifier; /* 0x22 */
240 U32 BidirectionalTransferCount; /* 0x24 */
241 U32 Reserved5; /* 0x28 */
242 U32 Reserved6; /* 0x2C */
243} MPI2_SCSI_IO_REPLY, MPI2_POINTER PTR_MPI2_SCSI_IO_REPLY,
244 Mpi2SCSIIOReply_t, MPI2_POINTER pMpi2SCSIIOReply_t;
245
246/* SCSI IO Reply SCSIStatus values (SAM-4 status codes) */
247
248#define MPI2_SCSI_STATUS_GOOD (0x00)
249#define MPI2_SCSI_STATUS_CHECK_CONDITION (0x02)
250#define MPI2_SCSI_STATUS_CONDITION_MET (0x04)
251#define MPI2_SCSI_STATUS_BUSY (0x08)
252#define MPI2_SCSI_STATUS_INTERMEDIATE (0x10)
253#define MPI2_SCSI_STATUS_INTERMEDIATE_CONDMET (0x14)
254#define MPI2_SCSI_STATUS_RESERVATION_CONFLICT (0x18)
255#define MPI2_SCSI_STATUS_COMMAND_TERMINATED (0x22) /* obsolete */
256#define MPI2_SCSI_STATUS_TASK_SET_FULL (0x28)
257#define MPI2_SCSI_STATUS_ACA_ACTIVE (0x30)
258#define MPI2_SCSI_STATUS_TASK_ABORTED (0x40)
259
260/* SCSI IO Reply SCSIState flags */
261
262#define MPI2_SCSI_STATE_RESPONSE_INFO_VALID (0x10)
263#define MPI2_SCSI_STATE_TERMINATED (0x08)
264#define MPI2_SCSI_STATE_NO_SCSI_STATUS (0x04)
265#define MPI2_SCSI_STATE_AUTOSENSE_FAILED (0x02)
266#define MPI2_SCSI_STATE_AUTOSENSE_VALID (0x01)
267
268/* masks and shifts for the ResponseInfo field */
269
270#define MPI2_SCSI_RI_MASK_REASONCODE (0x000000FF)
271#define MPI2_SCSI_RI_SHIFT_REASONCODE (0)
272
273#define MPI2_SCSI_TASKTAG_UNKNOWN (0xFFFF)
274
275
276/****************************************************************************
277* SCSI Task Management messages
278****************************************************************************/
279
280/* SCSI Task Management Request Message */
281typedef struct _MPI2_SCSI_TASK_MANAGE_REQUEST
282{
283 U16 DevHandle; /* 0x00 */
284 U8 ChainOffset; /* 0x02 */
285 U8 Function; /* 0x03 */
286 U8 Reserved1; /* 0x04 */
287 U8 TaskType; /* 0x05 */
288 U8 Reserved2; /* 0x06 */
289 U8 MsgFlags; /* 0x07 */
290 U8 VP_ID; /* 0x08 */
291 U8 VF_ID; /* 0x09 */
292 U16 Reserved3; /* 0x0A */
293 U8 LUN[8]; /* 0x0C */
294 U32 Reserved4[7]; /* 0x14 */
295 U16 TaskMID; /* 0x30 */
296 U16 Reserved5; /* 0x32 */
297} MPI2_SCSI_TASK_MANAGE_REQUEST,
298 MPI2_POINTER PTR_MPI2_SCSI_TASK_MANAGE_REQUEST,
299 Mpi2SCSITaskManagementRequest_t,
300 MPI2_POINTER pMpi2SCSITaskManagementRequest_t;
301
302/* TaskType values */
303
304#define MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01)
305#define MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET (0x02)
306#define MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03)
307#define MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05)
308#define MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06)
309#define MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07)
310#define MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA (0x08)
311#define MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET (0x09)
312#define MPI2_SCSITASKMGMT_TASKTYPE_QRY_ASYNC_EVENT (0x0A)
313
314/* obsolete TaskType name */
315#define MPI2_SCSITASKMGMT_TASKTYPE_QRY_UNIT_ATTENTION \
316 (MPI2_SCSITASKMGMT_TASKTYPE_QRY_ASYNC_EVENT)
317
318/* MsgFlags bits */
319
320#define MPI2_SCSITASKMGMT_MSGFLAGS_MASK_TARGET_RESET (0x18)
321#define MPI2_SCSITASKMGMT_MSGFLAGS_LINK_RESET (0x00)
322#define MPI2_SCSITASKMGMT_MSGFLAGS_NEXUS_RESET_SRST (0x08)
323#define MPI2_SCSITASKMGMT_MSGFLAGS_SAS_HARD_LINK_RESET (0x10)
324
325#define MPI2_SCSITASKMGMT_MSGFLAGS_DO_NOT_SEND_TASK_IU (0x01)
326
327
328
329/* SCSI Task Management Reply Message */
330typedef struct _MPI2_SCSI_TASK_MANAGE_REPLY
331{
332 U16 DevHandle; /* 0x00 */
333 U8 MsgLength; /* 0x02 */
334 U8 Function; /* 0x03 */
335 U8 ResponseCode; /* 0x04 */
336 U8 TaskType; /* 0x05 */
337 U8 Reserved1; /* 0x06 */
338 U8 MsgFlags; /* 0x07 */
339 U8 VP_ID; /* 0x08 */
340 U8 VF_ID; /* 0x09 */
341 U16 Reserved2; /* 0x0A */
342 U16 Reserved3; /* 0x0C */
343 U16 IOCStatus; /* 0x0E */
344 U32 IOCLogInfo; /* 0x10 */
345 U32 TerminationCount; /* 0x14 */
346 U32 ResponseInfo; /* 0x18 */
347} MPI2_SCSI_TASK_MANAGE_REPLY,
348 MPI2_POINTER PTR_MPI2_SCSI_TASK_MANAGE_REPLY,
349 Mpi2SCSITaskManagementReply_t, MPI2_POINTER pMpi2SCSIManagementReply_t;
350
351/* ResponseCode values */
352
353#define MPI2_SCSITASKMGMT_RSP_TM_COMPLETE (0x00)
354#define MPI2_SCSITASKMGMT_RSP_INVALID_FRAME (0x02)
355#define MPI2_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED (0x04)
356#define MPI2_SCSITASKMGMT_RSP_TM_FAILED (0x05)
357#define MPI2_SCSITASKMGMT_RSP_TM_SUCCEEDED (0x08)
358#define MPI2_SCSITASKMGMT_RSP_TM_INVALID_LUN (0x09)
359#define MPI2_SCSITASKMGMT_RSP_TM_OVERLAPPED_TAG (0x0A)
360#define MPI2_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC (0x80)
361
362/* masks and shifts for the ResponseInfo field */
363
364#define MPI2_SCSITASKMGMT_RI_MASK_REASONCODE (0x000000FF)
365#define MPI2_SCSITASKMGMT_RI_SHIFT_REASONCODE (0)
366#define MPI2_SCSITASKMGMT_RI_MASK_ARI2 (0x0000FF00)
367#define MPI2_SCSITASKMGMT_RI_SHIFT_ARI2 (8)
368#define MPI2_SCSITASKMGMT_RI_MASK_ARI1 (0x00FF0000)
369#define MPI2_SCSITASKMGMT_RI_SHIFT_ARI1 (16)
370#define MPI2_SCSITASKMGMT_RI_MASK_ARI0 (0xFF000000)
371#define MPI2_SCSITASKMGMT_RI_SHIFT_ARI0 (24)
372
373
374/****************************************************************************
375* SCSI Enclosure Processor messages
376****************************************************************************/
377
378/* SCSI Enclosure Processor Request Message */
379typedef struct _MPI2_SEP_REQUEST
380{
381 U16 DevHandle; /* 0x00 */
382 U8 ChainOffset; /* 0x02 */
383 U8 Function; /* 0x03 */
384 U8 Action; /* 0x04 */
385 U8 Flags; /* 0x05 */
386 U8 Reserved1; /* 0x06 */
387 U8 MsgFlags; /* 0x07 */
388 U8 VP_ID; /* 0x08 */
389 U8 VF_ID; /* 0x09 */
390 U16 Reserved2; /* 0x0A */
391 U32 SlotStatus; /* 0x0C */
392 U32 Reserved3; /* 0x10 */
393 U32 Reserved4; /* 0x14 */
394 U32 Reserved5; /* 0x18 */
395 U16 Slot; /* 0x1C */
396 U16 EnclosureHandle; /* 0x1E */
397} MPI2_SEP_REQUEST, MPI2_POINTER PTR_MPI2_SEP_REQUEST,
398 Mpi2SepRequest_t, MPI2_POINTER pMpi2SepRequest_t;
399
400/* Action defines */
401#define MPI2_SEP_REQ_ACTION_WRITE_STATUS (0x00)
402#define MPI2_SEP_REQ_ACTION_READ_STATUS (0x01)
403
404/* Flags defines */
405#define MPI2_SEP_REQ_FLAGS_DEVHANDLE_ADDRESS (0x00)
406#define MPI2_SEP_REQ_FLAGS_ENCLOSURE_SLOT_ADDRESS (0x01)
407
408/* SlotStatus defines */
409#define MPI2_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE (0x00040000)
410#define MPI2_SEP_REQ_SLOTSTATUS_IDENTIFY_REQUEST (0x00020000)
411#define MPI2_SEP_REQ_SLOTSTATUS_REBUILD_STOPPED (0x00000200)
412#define MPI2_SEP_REQ_SLOTSTATUS_HOT_SPARE (0x00000100)
413#define MPI2_SEP_REQ_SLOTSTATUS_UNCONFIGURED (0x00000080)
414#define MPI2_SEP_REQ_SLOTSTATUS_PREDICTED_FAULT (0x00000040)
415#define MPI2_SEP_REQ_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000010)
416#define MPI2_SEP_REQ_SLOTSTATUS_IN_FAILED_ARRAY (0x00000008)
417#define MPI2_SEP_REQ_SLOTSTATUS_DEV_REBUILDING (0x00000004)
418#define MPI2_SEP_REQ_SLOTSTATUS_DEV_FAULTY (0x00000002)
419#define MPI2_SEP_REQ_SLOTSTATUS_NO_ERROR (0x00000001)
420
421
422/* SCSI Enclosure Processor Reply Message */
423typedef struct _MPI2_SEP_REPLY
424{
425 U16 DevHandle; /* 0x00 */
426 U8 MsgLength; /* 0x02 */
427 U8 Function; /* 0x03 */
428 U8 Action; /* 0x04 */
429 U8 Flags; /* 0x05 */
430 U8 Reserved1; /* 0x06 */
431 U8 MsgFlags; /* 0x07 */
432 U8 VP_ID; /* 0x08 */
433 U8 VF_ID; /* 0x09 */
434 U16 Reserved2; /* 0x0A */
435 U16 Reserved3; /* 0x0C */
436 U16 IOCStatus; /* 0x0E */
437 U32 IOCLogInfo; /* 0x10 */
438 U32 SlotStatus; /* 0x14 */
439 U32 Reserved4; /* 0x18 */
440 U16 Slot; /* 0x1C */
441 U16 EnclosureHandle; /* 0x1E */
442} MPI2_SEP_REPLY, MPI2_POINTER PTR_MPI2_SEP_REPLY,
443 Mpi2SepReply_t, MPI2_POINTER pMpi2SepReply_t;
444
445/* SlotStatus defines */
446#define MPI2_SEP_REPLY_SLOTSTATUS_REMOVE_READY (0x00040000)
447#define MPI2_SEP_REPLY_SLOTSTATUS_IDENTIFY_REQUEST (0x00020000)
448#define MPI2_SEP_REPLY_SLOTSTATUS_REBUILD_STOPPED (0x00000200)
449#define MPI2_SEP_REPLY_SLOTSTATUS_HOT_SPARE (0x00000100)
450#define MPI2_SEP_REPLY_SLOTSTATUS_UNCONFIGURED (0x00000080)
451#define MPI2_SEP_REPLY_SLOTSTATUS_PREDICTED_FAULT (0x00000040)
452#define MPI2_SEP_REPLY_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000010)
453#define MPI2_SEP_REPLY_SLOTSTATUS_IN_FAILED_ARRAY (0x00000008)
454#define MPI2_SEP_REPLY_SLOTSTATUS_DEV_REBUILDING (0x00000004)
455#define MPI2_SEP_REPLY_SLOTSTATUS_DEV_FAULTY (0x00000002)
456#define MPI2_SEP_REPLY_SLOTSTATUS_NO_ERROR (0x00000001)
457
458
459#endif
460
461
diff --git a/drivers/scsi/mpt2sas/mpi/mpi2_ioc.h b/drivers/scsi/mpt2sas/mpi/mpi2_ioc.h
deleted file mode 100644
index b02de48be204..000000000000
--- a/drivers/scsi/mpt2sas/mpi/mpi2_ioc.h
+++ /dev/null
@@ -1,1708 +0,0 @@
1/*
2 * Copyright (c) 2000-2014 LSI Corporation.
3 *
4 *
5 * Name: mpi2_ioc.h
6 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages
7 * Creation Date: October 11, 2006
8 *
9 * mpi2_ioc.h Version: 02.00.24
10 *
11 * Version History
12 * ---------------
13 *
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
17 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to
18 * MaxTargets.
19 * Added TotalImageSize field to FWDownload Request.
20 * Added reserved words to FWUpload Request.
21 * 06-26-07 02.00.02 Added IR Configuration Change List Event.
22 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit
23 * request and replaced it with
24 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
25 * Replaced the MinReplyQueueDepth field of the IOCFacts
26 * reply with MaxReplyDescriptorPostQueueDepth.
27 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
28 * depth for the Reply Descriptor Post Queue.
29 * Added SASAddress field to Initiator Device Table
30 * Overflow Event data.
31 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
32 * for SAS Initiator Device Status Change Event data.
33 * Modified Reason Code defines for SAS Topology Change
34 * List Event data, including adding a bit for PHY Vacant
35 * status, and adding a mask for the Reason Code.
36 * Added define for
37 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
38 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
39 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of
40 * the IOCFacts Reply.
41 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
42 * Moved MPI2_VERSION_UNION to mpi2.h.
43 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
44 * instead of enables, and added SASBroadcastPrimitiveMasks
45 * field.
46 * Added Log Entry Added Event and related structure.
47 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
48 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
49 * Added MaxVolumes and MaxPersistentEntries fields to
50 * IOCFacts reply.
51 * Added ProtocalFlags and IOCCapabilities fields to
52 * MPI2_FW_IMAGE_HEADER.
53 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
54 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
55 * a U16 (from a U32).
56 * Removed extra 's' from EventMasks name.
57 * 06-27-08 02.00.08 Fixed an offset in a comment.
58 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
59 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
60 * renamed MinReplyFrameSize to ReplyFrameSize.
61 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
62 * Added two new RAIDOperation values for Integrated RAID
63 * Operations Status Event data.
64 * Added four new IR Configuration Change List Event data
65 * ReasonCode values.
66 * Added two new ReasonCode defines for SAS Device Status
67 * Change Event data.
68 * Added three new DiscoveryStatus bits for the SAS
69 * Discovery event data.
70 * Added Multiplexing Status Change bit to the PhyStatus
71 * field of the SAS Topology Change List event data.
72 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
73 * BootFlags are now product-specific.
74 * Added defines for the indivdual signature bytes
75 * for MPI2_INIT_IMAGE_FOOTER.
76 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
77 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
78 * define.
79 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
80 * define.
81 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
82 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
83 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
84 * Added two new reason codes for SAS Device Status Change
85 * Event.
86 * Added new event: SAS PHY Counter.
87 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure.
88 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
89 * Added new product id family for 2208.
90 * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST.
91 * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY.
92 * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY.
93 * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY.
94 * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define.
95 * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define.
96 * Added Host Based Discovery Phy Event data.
97 * Added defines for ProductID Product field
98 * (MPI2_FW_HEADER_PID_).
99 * Modified values for SAS ProductID Family
100 * (MPI2_FW_HEADER_PID_FAMILY_).
101 * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines.
102 * Added PowerManagementControl Request structures and
103 * defines.
104 * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete.
105 * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define.
106 * 11-10-10 02.00.16 Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC.
107 * 02-23-11 02.00.17 Added SAS NOTIFY Primitive event, and added
108 * SASNotifyPrimitiveMasks field to
109 * MPI2_EVENT_NOTIFICATION_REQUEST.
110 * Added Temperature Threshold Event.
111 * Added Host Message Event.
112 * Added Send Host Message request and reply.
113 * 05-25-11 02.00.18 For Extended Image Header, added
114 * MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and
115 * MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines.
116 * Deprecated MPI2_EXT_IMAGE_TYPE_MAX define.
117 * 08-24-11 02.00.19 Added PhysicalPort field to
118 * MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure.
119 * Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete.
120 * 03-29-12 02.00.21 Added a product specific range to event values.
121 * 07-26-12 02.00.22 Added MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE.
122 * Added ElapsedSeconds field to
123 * MPI2_EVENT_DATA_IR_OPERATION_STATUS.
124 * 08-19-13 02.00.23 For IOCInit, added MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE
125 * and MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY.
126 * Added MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE.
127 * Added MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY.
128 * Added Encrypted Hash Extended Image.
129 * 12-05-13 02.00.24 Added MPI25_HASH_IMAGE_TYPE_BIOS.
130 * --------------------------------------------------------------------------
131 */
132
133#ifndef MPI2_IOC_H
134#define MPI2_IOC_H
135
136/*****************************************************************************
137*
138* IOC Messages
139*
140*****************************************************************************/
141
142/****************************************************************************
143* IOCInit message
144****************************************************************************/
145
146/* IOCInit Request message */
147typedef struct _MPI2_IOC_INIT_REQUEST
148{
149 U8 WhoInit; /* 0x00 */
150 U8 Reserved1; /* 0x01 */
151 U8 ChainOffset; /* 0x02 */
152 U8 Function; /* 0x03 */
153 U16 Reserved2; /* 0x04 */
154 U8 Reserved3; /* 0x06 */
155 U8 MsgFlags; /* 0x07 */
156 U8 VP_ID; /* 0x08 */
157 U8 VF_ID; /* 0x09 */
158 U16 Reserved4; /* 0x0A */
159 U16 MsgVersion; /* 0x0C */
160 U16 HeaderVersion; /* 0x0E */
161 U32 Reserved5; /* 0x10 */
162 U16 Reserved6; /* 0x14 */
163 U8 Reserved7; /* 0x16 */
164 U8 HostMSIxVectors; /* 0x17 */
165 U16 Reserved8; /* 0x18 */
166 U16 SystemRequestFrameSize; /* 0x1A */
167 U16 ReplyDescriptorPostQueueDepth; /* 0x1C */
168 U16 ReplyFreeQueueDepth; /* 0x1E */
169 U32 SenseBufferAddressHigh; /* 0x20 */
170 U32 SystemReplyAddressHigh; /* 0x24 */
171 U64 SystemRequestFrameBaseAddress; /* 0x28 */
172 U64 ReplyDescriptorPostQueueAddress;/* 0x30 */
173 U64 ReplyFreeQueueAddress; /* 0x38 */
174 U64 TimeStamp; /* 0x40 */
175} MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST,
176 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t;
177
178/* WhoInit values */
179#define MPI2_WHOINIT_NOT_INITIALIZED (0x00)
180#define MPI2_WHOINIT_SYSTEM_BIOS (0x01)
181#define MPI2_WHOINIT_ROM_BIOS (0x02)
182#define MPI2_WHOINIT_PCI_PEER (0x03)
183#define MPI2_WHOINIT_HOST_DRIVER (0x04)
184#define MPI2_WHOINIT_MANUFACTURER (0x05)
185
186/* MsgFlags */
187#define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01)
188
189/* MsgVersion */
190#define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00)
191#define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8)
192#define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF)
193#define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0)
194
195/* HeaderVersion */
196#define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00)
197#define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8)
198#define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF)
199#define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0)
200
201/* minimum depth for a Reply Descriptor Post Queue */
202#define MPI2_RDPQ_DEPTH_MIN (16)
203
204/* Reply Descriptor Post Queue Array Entry */
205typedef struct _MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY {
206 U64 RDPQBaseAddress; /* 0x00 */
207 U32 Reserved1; /* 0x08 */
208 U32 Reserved2; /* 0x0C */
209} MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
210MPI2_POINTER PTR_MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
211Mpi2IOCInitRDPQArrayEntry, MPI2_POINTER pMpi2IOCInitRDPQArrayEntry;
212
213/* IOCInit Reply message */
214typedef struct _MPI2_IOC_INIT_REPLY
215{
216 U8 WhoInit; /* 0x00 */
217 U8 Reserved1; /* 0x01 */
218 U8 MsgLength; /* 0x02 */
219 U8 Function; /* 0x03 */
220 U16 Reserved2; /* 0x04 */
221 U8 Reserved3; /* 0x06 */
222 U8 MsgFlags; /* 0x07 */
223 U8 VP_ID; /* 0x08 */
224 U8 VF_ID; /* 0x09 */
225 U16 Reserved4; /* 0x0A */
226 U16 Reserved5; /* 0x0C */
227 U16 IOCStatus; /* 0x0E */
228 U32 IOCLogInfo; /* 0x10 */
229} MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY,
230 Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t;
231
232
233/****************************************************************************
234* IOCFacts message
235****************************************************************************/
236
237/* IOCFacts Request message */
238typedef struct _MPI2_IOC_FACTS_REQUEST
239{
240 U16 Reserved1; /* 0x00 */
241 U8 ChainOffset; /* 0x02 */
242 U8 Function; /* 0x03 */
243 U16 Reserved2; /* 0x04 */
244 U8 Reserved3; /* 0x06 */
245 U8 MsgFlags; /* 0x07 */
246 U8 VP_ID; /* 0x08 */
247 U8 VF_ID; /* 0x09 */
248 U16 Reserved4; /* 0x0A */
249} MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST,
250 Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t;
251
252
253/* IOCFacts Reply message */
254typedef struct _MPI2_IOC_FACTS_REPLY
255{
256 U16 MsgVersion; /* 0x00 */
257 U8 MsgLength; /* 0x02 */
258 U8 Function; /* 0x03 */
259 U16 HeaderVersion; /* 0x04 */
260 U8 IOCNumber; /* 0x06 */
261 U8 MsgFlags; /* 0x07 */
262 U8 VP_ID; /* 0x08 */
263 U8 VF_ID; /* 0x09 */
264 U16 Reserved1; /* 0x0A */
265 U16 IOCExceptions; /* 0x0C */
266 U16 IOCStatus; /* 0x0E */
267 U32 IOCLogInfo; /* 0x10 */
268 U8 MaxChainDepth; /* 0x14 */
269 U8 WhoInit; /* 0x15 */
270 U8 NumberOfPorts; /* 0x16 */
271 U8 MaxMSIxVectors; /* 0x17 */
272 U16 RequestCredit; /* 0x18 */
273 U16 ProductID; /* 0x1A */
274 U32 IOCCapabilities; /* 0x1C */
275 MPI2_VERSION_UNION FWVersion; /* 0x20 */
276 U16 IOCRequestFrameSize; /* 0x24 */
277 U16 Reserved3; /* 0x26 */
278 U16 MaxInitiators; /* 0x28 */
279 U16 MaxTargets; /* 0x2A */
280 U16 MaxSasExpanders; /* 0x2C */
281 U16 MaxEnclosures; /* 0x2E */
282 U16 ProtocolFlags; /* 0x30 */
283 U16 HighPriorityCredit; /* 0x32 */
284 U16 MaxReplyDescriptorPostQueueDepth; /* 0x34 */
285 U8 ReplyFrameSize; /* 0x36 */
286 U8 MaxVolumes; /* 0x37 */
287 U16 MaxDevHandle; /* 0x38 */
288 U16 MaxPersistentEntries; /* 0x3A */
289 U16 MinDevHandle; /* 0x3C */
290 U16 Reserved4; /* 0x3E */
291} MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY,
292 Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t;
293
294/* MsgVersion */
295#define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00)
296#define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8)
297#define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF)
298#define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0)
299
300/* HeaderVersion */
301#define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00)
302#define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8)
303#define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF)
304#define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0)
305
306/* IOCExceptions */
307#define MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0200)
308#define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100)
309
310#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0)
311#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000)
312#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020)
313#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040)
314#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060)
315
316#define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010)
317#define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008)
318#define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004)
319#define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002)
320#define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001)
321
322/* defines for WhoInit field are after the IOCInit Request */
323
324/* ProductID field uses MPI2_FW_HEADER_PID_ */
325
326/* IOCCapabilities */
327#define MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE (0x00040000)
328#define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000)
329#define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000)
330#define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000)
331#define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000)
332#define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000)
333#define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800)
334#define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100)
335#define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080)
336#define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040)
337#define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020)
338#define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010)
339#define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008)
340#define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
341
342/* ProtocolFlags */
343#define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001)
344#define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002)
345
346
347/****************************************************************************
348* PortFacts message
349****************************************************************************/
350
351/* PortFacts Request message */
352typedef struct _MPI2_PORT_FACTS_REQUEST
353{
354 U16 Reserved1; /* 0x00 */
355 U8 ChainOffset; /* 0x02 */
356 U8 Function; /* 0x03 */
357 U16 Reserved2; /* 0x04 */
358 U8 PortNumber; /* 0x06 */
359 U8 MsgFlags; /* 0x07 */
360 U8 VP_ID; /* 0x08 */
361 U8 VF_ID; /* 0x09 */
362 U16 Reserved3; /* 0x0A */
363} MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST,
364 Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t;
365
366/* PortFacts Reply message */
367typedef struct _MPI2_PORT_FACTS_REPLY
368{
369 U16 Reserved1; /* 0x00 */
370 U8 MsgLength; /* 0x02 */
371 U8 Function; /* 0x03 */
372 U16 Reserved2; /* 0x04 */
373 U8 PortNumber; /* 0x06 */
374 U8 MsgFlags; /* 0x07 */
375 U8 VP_ID; /* 0x08 */
376 U8 VF_ID; /* 0x09 */
377 U16 Reserved3; /* 0x0A */
378 U16 Reserved4; /* 0x0C */
379 U16 IOCStatus; /* 0x0E */
380 U32 IOCLogInfo; /* 0x10 */
381 U8 Reserved5; /* 0x14 */
382 U8 PortType; /* 0x15 */
383 U16 Reserved6; /* 0x16 */
384 U16 MaxPostedCmdBuffers; /* 0x18 */
385 U16 Reserved7; /* 0x1A */
386} MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY,
387 Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t;
388
389/* PortType values */
390#define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00)
391#define MPI2_PORTFACTS_PORTTYPE_FC (0x10)
392#define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20)
393#define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30)
394#define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31)
395
396
397/****************************************************************************
398* PortEnable message
399****************************************************************************/
400
401/* PortEnable Request message */
402typedef struct _MPI2_PORT_ENABLE_REQUEST
403{
404 U16 Reserved1; /* 0x00 */
405 U8 ChainOffset; /* 0x02 */
406 U8 Function; /* 0x03 */
407 U8 Reserved2; /* 0x04 */
408 U8 PortFlags; /* 0x05 */
409 U8 Reserved3; /* 0x06 */
410 U8 MsgFlags; /* 0x07 */
411 U8 VP_ID; /* 0x08 */
412 U8 VF_ID; /* 0x09 */
413 U16 Reserved4; /* 0x0A */
414} MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST,
415 Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t;
416
417
418/* PortEnable Reply message */
419typedef struct _MPI2_PORT_ENABLE_REPLY
420{
421 U16 Reserved1; /* 0x00 */
422 U8 MsgLength; /* 0x02 */
423 U8 Function; /* 0x03 */
424 U8 Reserved2; /* 0x04 */
425 U8 PortFlags; /* 0x05 */
426 U8 Reserved3; /* 0x06 */
427 U8 MsgFlags; /* 0x07 */
428 U8 VP_ID; /* 0x08 */
429 U8 VF_ID; /* 0x09 */
430 U16 Reserved4; /* 0x0A */
431 U16 Reserved5; /* 0x0C */
432 U16 IOCStatus; /* 0x0E */
433 U32 IOCLogInfo; /* 0x10 */
434} MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY,
435 Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t;
436
437
438/****************************************************************************
439* EventNotification message
440****************************************************************************/
441
442/* EventNotification Request message */
443#define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4)
444
445typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST
446{
447 U16 Reserved1; /* 0x00 */
448 U8 ChainOffset; /* 0x02 */
449 U8 Function; /* 0x03 */
450 U16 Reserved2; /* 0x04 */
451 U8 Reserved3; /* 0x06 */
452 U8 MsgFlags; /* 0x07 */
453 U8 VP_ID; /* 0x08 */
454 U8 VF_ID; /* 0x09 */
455 U16 Reserved4; /* 0x0A */
456 U32 Reserved5; /* 0x0C */
457 U32 Reserved6; /* 0x10 */
458 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */
459 U16 SASBroadcastPrimitiveMasks; /* 0x24 */
460 U16 SASNotifyPrimitiveMasks; /* 0x26 */
461 U32 Reserved8; /* 0x28 */
462} MPI2_EVENT_NOTIFICATION_REQUEST,
463 MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
464 Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t;
465
466
467/* EventNotification Reply message */
468typedef struct _MPI2_EVENT_NOTIFICATION_REPLY
469{
470 U16 EventDataLength; /* 0x00 */
471 U8 MsgLength; /* 0x02 */
472 U8 Function; /* 0x03 */
473 U16 Reserved1; /* 0x04 */
474 U8 AckRequired; /* 0x06 */
475 U8 MsgFlags; /* 0x07 */
476 U8 VP_ID; /* 0x08 */
477 U8 VF_ID; /* 0x09 */
478 U16 Reserved2; /* 0x0A */
479 U16 Reserved3; /* 0x0C */
480 U16 IOCStatus; /* 0x0E */
481 U32 IOCLogInfo; /* 0x10 */
482 U16 Event; /* 0x14 */
483 U16 Reserved4; /* 0x16 */
484 U32 EventContext; /* 0x18 */
485 U32 EventData[1]; /* 0x1C */
486} MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY,
487 Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t;
488
489/* AckRequired */
490#define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00)
491#define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01)
492
493/* Event */
494#define MPI2_EVENT_LOG_DATA (0x0001)
495#define MPI2_EVENT_STATE_CHANGE (0x0002)
496#define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005)
497#define MPI2_EVENT_EVENT_CHANGE (0x000A)
498#define MPI2_EVENT_TASK_SET_FULL (0x000E) /* obsolete */
499#define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F)
500#define MPI2_EVENT_IR_OPERATION_STATUS (0x0014)
501#define MPI2_EVENT_SAS_DISCOVERY (0x0016)
502#define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017)
503#define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018)
504#define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019)
505#define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C)
506#define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D)
507#define MPI2_EVENT_IR_VOLUME (0x001E)
508#define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F)
509#define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020)
510#define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021)
511#define MPI2_EVENT_SAS_PHY_COUNTER (0x0022)
512#define MPI2_EVENT_GPIO_INTERRUPT (0x0023)
513#define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024)
514#define MPI2_EVENT_SAS_QUIESCE (0x0025)
515#define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE (0x0026)
516#define MPI2_EVENT_TEMP_THRESHOLD (0x0027)
517#define MPI2_EVENT_HOST_MESSAGE (0x0028)
518#define MPI2_EVENT_MIN_PRODUCT_SPECIFIC (0x006E)
519#define MPI2_EVENT_MAX_PRODUCT_SPECIFIC (0x007F)
520
521/* Log Entry Added Event data */
522
523/* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
524#define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C)
525
526typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED
527{
528 U64 TimeStamp; /* 0x00 */
529 U32 Reserved1; /* 0x08 */
530 U16 LogSequence; /* 0x0C */
531 U16 LogEntryQualifier; /* 0x0E */
532 U8 VP_ID; /* 0x10 */
533 U8 VF_ID; /* 0x11 */
534 U16 Reserved2; /* 0x12 */
535 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */
536} MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
537 MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
538 Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t;
539
540/* GPIO Interrupt Event data */
541
542typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT {
543 U8 GPIONum; /* 0x00 */
544 U8 Reserved1; /* 0x01 */
545 U16 Reserved2; /* 0x02 */
546} MPI2_EVENT_DATA_GPIO_INTERRUPT,
547 MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
548 Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t;
549
550/* Temperature Threshold Event data */
551
552typedef struct _MPI2_EVENT_DATA_TEMPERATURE {
553 U16 Status; /* 0x00 */
554 U8 SensorNum; /* 0x02 */
555 U8 Reserved1; /* 0x03 */
556 U16 CurrentTemperature; /* 0x04 */
557 U16 Reserved2; /* 0x06 */
558 U32 Reserved3; /* 0x08 */
559 U32 Reserved4; /* 0x0C */
560} MPI2_EVENT_DATA_TEMPERATURE,
561MPI2_POINTER PTR_MPI2_EVENT_DATA_TEMPERATURE,
562Mpi2EventDataTemperature_t, MPI2_POINTER pMpi2EventDataTemperature_t;
563
564/* Temperature Threshold Event data Status bits */
565#define MPI2_EVENT_TEMPERATURE3_EXCEEDED (0x0008)
566#define MPI2_EVENT_TEMPERATURE2_EXCEEDED (0x0004)
567#define MPI2_EVENT_TEMPERATURE1_EXCEEDED (0x0002)
568#define MPI2_EVENT_TEMPERATURE0_EXCEEDED (0x0001)
569
570
571/* Host Message Event data */
572
573typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE {
574 U8 SourceVF_ID; /* 0x00 */
575 U8 Reserved1; /* 0x01 */
576 U16 Reserved2; /* 0x02 */
577 U32 Reserved3; /* 0x04 */
578 U32 HostData[1]; /* 0x08 */
579} MPI2_EVENT_DATA_HOST_MESSAGE, MPI2_POINTER PTR_MPI2_EVENT_DATA_HOST_MESSAGE,
580Mpi2EventDataHostMessage_t, MPI2_POINTER pMpi2EventDataHostMessage_t;
581
582
583/* Hard Reset Received Event data */
584
585typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED
586{
587 U8 Reserved1; /* 0x00 */
588 U8 Port; /* 0x01 */
589 U16 Reserved2; /* 0x02 */
590} MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
591 MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
592 Mpi2EventDataHardResetReceived_t,
593 MPI2_POINTER pMpi2EventDataHardResetReceived_t;
594
595/* Task Set Full Event data */
596/* this event is obsolete */
597
598typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL
599{
600 U16 DevHandle; /* 0x00 */
601 U16 CurrentDepth; /* 0x02 */
602} MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
603 Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t;
604
605
606/* SAS Device Status Change Event data */
607
608typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE
609{
610 U16 TaskTag; /* 0x00 */
611 U8 ReasonCode; /* 0x02 */
612 U8 PhysicalPort; /* 0x03 */
613 U8 ASC; /* 0x04 */
614 U8 ASCQ; /* 0x05 */
615 U16 DevHandle; /* 0x06 */
616 U32 Reserved2; /* 0x08 */
617 U64 SASAddress; /* 0x0C */
618 U8 LUN[8]; /* 0x14 */
619} MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
620 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
621 Mpi2EventDataSasDeviceStatusChange_t,
622 MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t;
623
624/* SAS Device Status Change Event data ReasonCode values */
625#define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05)
626#define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07)
627#define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)
628#define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)
629#define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)
630#define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)
631#define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)
632#define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)
633#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E)
634#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F)
635#define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10)
636#define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11)
637#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12)
638
639
640/* Integrated RAID Operation Status Event data */
641
642typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS
643{
644 U16 VolDevHandle; /* 0x00 */
645 U16 Reserved1; /* 0x02 */
646 U8 RAIDOperation; /* 0x04 */
647 U8 PercentComplete; /* 0x05 */
648 U16 Reserved2; /* 0x06 */
649 U32 ElapsedSeconds; /* 0x08 */
650} MPI2_EVENT_DATA_IR_OPERATION_STATUS,
651 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
652 Mpi2EventDataIrOperationStatus_t,
653 MPI2_POINTER pMpi2EventDataIrOperationStatus_t;
654
655/* Integrated RAID Operation Status Event data RAIDOperation values */
656#define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00)
657#define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01)
658#define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02)
659#define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03)
660#define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04)
661
662
663/* Integrated RAID Volume Event data */
664
665typedef struct _MPI2_EVENT_DATA_IR_VOLUME
666{
667 U16 VolDevHandle; /* 0x00 */
668 U8 ReasonCode; /* 0x02 */
669 U8 Reserved1; /* 0x03 */
670 U32 NewValue; /* 0x04 */
671 U32 PreviousValue; /* 0x08 */
672} MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME,
673 Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t;
674
675/* Integrated RAID Volume Event data ReasonCode values */
676#define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01)
677#define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02)
678#define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03)
679
680
681/* Integrated RAID Physical Disk Event data */
682
683typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK
684{
685 U16 Reserved1; /* 0x00 */
686 U8 ReasonCode; /* 0x02 */
687 U8 PhysDiskNum; /* 0x03 */
688 U16 PhysDiskDevHandle; /* 0x04 */
689 U16 Reserved2; /* 0x06 */
690 U16 Slot; /* 0x08 */
691 U16 EnclosureHandle; /* 0x0A */
692 U32 NewValue; /* 0x0C */
693 U32 PreviousValue; /* 0x10 */
694} MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
695 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
696 Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t;
697
698/* Integrated RAID Physical Disk Event data ReasonCode values */
699#define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01)
700#define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02)
701#define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03)
702
703
704/* Integrated RAID Configuration Change List Event data */
705
706/*
707 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
708 * one and check NumElements at runtime.
709 */
710#ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
711#define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1)
712#endif
713
714typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT
715{
716 U16 ElementFlags; /* 0x00 */
717 U16 VolDevHandle; /* 0x02 */
718 U8 ReasonCode; /* 0x04 */
719 U8 PhysDiskNum; /* 0x05 */
720 U16 PhysDiskDevHandle; /* 0x06 */
721} MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
722 Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t;
723
724/* IR Configuration Change List Event data ElementFlags values */
725#define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F)
726#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000)
727#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
728#define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002)
729
730/* IR Configuration Change List Event data ReasonCode values */
731#define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01)
732#define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02)
733#define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03)
734#define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04)
735#define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05)
736#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06)
737#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07)
738#define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08)
739#define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09)
740
741typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST
742{
743 U8 NumElements; /* 0x00 */
744 U8 Reserved1; /* 0x01 */
745 U8 Reserved2; /* 0x02 */
746 U8 ConfigNum; /* 0x03 */
747 U32 Flags; /* 0x04 */
748 MPI2_EVENT_IR_CONFIG_ELEMENT ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT]; /* 0x08 */
749} MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
750 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
751 Mpi2EventDataIrConfigChangeList_t,
752 MPI2_POINTER pMpi2EventDataIrConfigChangeList_t;
753
754/* IR Configuration Change List Event data Flags values */
755#define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001)
756
757
758/* SAS Discovery Event data */
759
760typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY
761{
762 U8 Flags; /* 0x00 */
763 U8 ReasonCode; /* 0x01 */
764 U8 PhysicalPort; /* 0x02 */
765 U8 Reserved1; /* 0x03 */
766 U32 DiscoveryStatus; /* 0x04 */
767} MPI2_EVENT_DATA_SAS_DISCOVERY,
768 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
769 Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t;
770
771/* SAS Discovery Event data Flags values */
772#define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02)
773#define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01)
774
775/* SAS Discovery Event data ReasonCode values */
776#define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01)
777#define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02)
778
779/* SAS Discovery Event data DiscoveryStatus values */
780#define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
781#define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000)
782#define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000)
783#define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
784#define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000)
785#define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
786#define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
787#define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000)
788#define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
789#define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800)
790#define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400)
791#define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200)
792#define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100)
793#define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080)
794#define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040)
795#define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020)
796#define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010)
797#define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004)
798#define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002)
799#define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001)
800
801
802/* SAS Broadcast Primitive Event data */
803
804typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE
805{
806 U8 PhyNum; /* 0x00 */
807 U8 Port; /* 0x01 */
808 U8 PortWidth; /* 0x02 */
809 U8 Primitive; /* 0x03 */
810} MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
811 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
812 Mpi2EventDataSasBroadcastPrimitive_t,
813 MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t;
814
815/* defines for the Primitive field */
816#define MPI2_EVENT_PRIMITIVE_CHANGE (0x01)
817#define MPI2_EVENT_PRIMITIVE_SES (0x02)
818#define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03)
819#define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04)
820#define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05)
821#define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06)
822#define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07)
823#define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08)
824
825/* SAS Notify Primitive Event data */
826
827typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE {
828 U8 PhyNum; /* 0x00 */
829 U8 Port; /* 0x01 */
830 U8 Reserved1; /* 0x02 */
831 U8 Primitive; /* 0x03 */
832} MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
833MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
834Mpi2EventDataSasNotifyPrimitive_t,
835MPI2_POINTER pMpi2EventDataSasNotifyPrimitive_t;
836
837/* defines for the Primitive field */
838#define MPI2_EVENT_NOTIFY_ENABLE_SPINUP (0x01)
839#define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED (0x02)
840#define MPI2_EVENT_NOTIFY_RESERVED1 (0x03)
841#define MPI2_EVENT_NOTIFY_RESERVED2 (0x04)
842
843
844/* SAS Initiator Device Status Change Event data */
845
846typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE
847{
848 U8 ReasonCode; /* 0x00 */
849 U8 PhysicalPort; /* 0x01 */
850 U16 DevHandle; /* 0x02 */
851 U64 SASAddress; /* 0x04 */
852} MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
853 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
854 Mpi2EventDataSasInitDevStatusChange_t,
855 MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t;
856
857/* SAS Initiator Device Status Change event ReasonCode values */
858#define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01)
859#define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02)
860
861
862/* SAS Initiator Device Table Overflow Event data */
863
864typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW
865{
866 U16 MaxInit; /* 0x00 */
867 U16 CurrentInit; /* 0x02 */
868 U64 SASAddress; /* 0x04 */
869} MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
870 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
871 Mpi2EventDataSasInitTableOverflow_t,
872 MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t;
873
874
875/* SAS Topology Change List Event data */
876
877/*
878 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
879 * one and check NumEntries at runtime.
880 */
881#ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
882#define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1)
883#endif
884
885typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY
886{
887 U16 AttachedDevHandle; /* 0x00 */
888 U8 LinkRate; /* 0x02 */
889 U8 PhyStatus; /* 0x03 */
890} MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
891 Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t;
892
893typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST
894{
895 U16 EnclosureHandle; /* 0x00 */
896 U16 ExpanderDevHandle; /* 0x02 */
897 U8 NumPhys; /* 0x04 */
898 U8 Reserved1; /* 0x05 */
899 U16 Reserved2; /* 0x06 */
900 U8 NumEntries; /* 0x08 */
901 U8 StartPhyNum; /* 0x09 */
902 U8 ExpStatus; /* 0x0A */
903 U8 PhysicalPort; /* 0x0B */
904 MPI2_EVENT_SAS_TOPO_PHY_ENTRY PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/
905} MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
906 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
907 Mpi2EventDataSasTopologyChangeList_t,
908 MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t;
909
910/* values for the ExpStatus field */
911#define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00)
912#define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01)
913#define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02)
914#define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03)
915#define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04)
916
917/* defines for the LinkRate field */
918#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0)
919#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4)
920#define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F)
921#define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0)
922
923#define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00)
924#define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01)
925#define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02)
926#define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03)
927#define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04)
928#define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05)
929#define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06)
930#define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08)
931#define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09)
932#define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A)
933
934/* values for the PhyStatus field */
935#define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80)
936#define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10)
937/* values for the PhyStatus ReasonCode sub-field */
938#define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F)
939#define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01)
940#define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02)
941#define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03)
942#define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04)
943#define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05)
944
945
946/* SAS Enclosure Device Status Change Event data */
947
948typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE
949{
950 U16 EnclosureHandle; /* 0x00 */
951 U8 ReasonCode; /* 0x02 */
952 U8 PhysicalPort; /* 0x03 */
953 U64 EnclosureLogicalID; /* 0x04 */
954 U16 NumSlots; /* 0x0C */
955 U16 StartSlot; /* 0x0E */
956 U32 PhyBits; /* 0x10 */
957} MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
958 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
959 Mpi2EventDataSasEnclDevStatusChange_t,
960 MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t;
961
962/* SAS Enclosure Device Status Change event ReasonCode values */
963#define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01)
964#define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02)
965
966
967/* SAS PHY Counter Event data */
968
969typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER {
970 U64 TimeStamp; /* 0x00 */
971 U32 Reserved1; /* 0x08 */
972 U8 PhyEventCode; /* 0x0C */
973 U8 PhyNum; /* 0x0D */
974 U16 Reserved2; /* 0x0E */
975 U32 PhyEventInfo; /* 0x10 */
976 U8 CounterType; /* 0x14 */
977 U8 ThresholdWindow; /* 0x15 */
978 U8 TimeUnits; /* 0x16 */
979 U8 Reserved3; /* 0x17 */
980 U32 EventThreshold; /* 0x18 */
981 U16 ThresholdFlags; /* 0x1C */
982 U16 Reserved4; /* 0x1E */
983} MPI2_EVENT_DATA_SAS_PHY_COUNTER,
984 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
985 Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t;
986
987/* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the
988 * PhyEventCode field
989 * use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the
990 * CounterType field
991 * use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the
992 * TimeUnits field
993 * use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the
994 * ThresholdFlags field
995 * */
996
997
998/* SAS Quiesce Event data */
999
1000typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE {
1001 U8 ReasonCode; /* 0x00 */
1002 U8 Reserved1; /* 0x01 */
1003 U16 Reserved2; /* 0x02 */
1004 U32 Reserved3; /* 0x04 */
1005} MPI2_EVENT_DATA_SAS_QUIESCE,
1006 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_QUIESCE,
1007 Mpi2EventDataSasQuiesce_t, MPI2_POINTER pMpi2EventDataSasQuiesce_t;
1008
1009/* SAS Quiesce Event data ReasonCode values */
1010#define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01)
1011#define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02)
1012
1013
1014/* Host Based Discovery Phy Event data */
1015
1016typedef struct _MPI2_EVENT_HBD_PHY_SAS {
1017 U8 Flags; /* 0x00 */
1018 U8 NegotiatedLinkRate; /* 0x01 */
1019 U8 PhyNum; /* 0x02 */
1020 U8 PhysicalPort; /* 0x03 */
1021 U32 Reserved1; /* 0x04 */
1022 U8 InitialFrame[28]; /* 0x08 */
1023} MPI2_EVENT_HBD_PHY_SAS, MPI2_POINTER PTR_MPI2_EVENT_HBD_PHY_SAS,
1024 Mpi2EventHbdPhySas_t, MPI2_POINTER pMpi2EventHbdPhySas_t;
1025
1026/* values for the Flags field */
1027#define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02)
1028#define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01)
1029
1030/* use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h for
1031 * the NegotiatedLinkRate field */
1032
1033typedef union _MPI2_EVENT_HBD_DESCRIPTOR {
1034 MPI2_EVENT_HBD_PHY_SAS Sas;
1035} MPI2_EVENT_HBD_DESCRIPTOR, MPI2_POINTER PTR_MPI2_EVENT_HBD_DESCRIPTOR,
1036 Mpi2EventHbdDescriptor_t, MPI2_POINTER pMpi2EventHbdDescriptor_t;
1037
1038typedef struct _MPI2_EVENT_DATA_HBD_PHY {
1039 U8 DescriptorType; /* 0x00 */
1040 U8 Reserved1; /* 0x01 */
1041 U16 Reserved2; /* 0x02 */
1042 U32 Reserved3; /* 0x04 */
1043 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /* 0x08 */
1044} MPI2_EVENT_DATA_HBD_PHY, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY,
1045 Mpi2EventDataHbdPhy_t, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t;
1046
1047/* values for the DescriptorType field */
1048#define MPI2_EVENT_HBD_DT_SAS (0x01)
1049
1050
1051
1052/****************************************************************************
1053* EventAck message
1054****************************************************************************/
1055
1056/* EventAck Request message */
1057typedef struct _MPI2_EVENT_ACK_REQUEST
1058{
1059 U16 Reserved1; /* 0x00 */
1060 U8 ChainOffset; /* 0x02 */
1061 U8 Function; /* 0x03 */
1062 U16 Reserved2; /* 0x04 */
1063 U8 Reserved3; /* 0x06 */
1064 U8 MsgFlags; /* 0x07 */
1065 U8 VP_ID; /* 0x08 */
1066 U8 VF_ID; /* 0x09 */
1067 U16 Reserved4; /* 0x0A */
1068 U16 Event; /* 0x0C */
1069 U16 Reserved5; /* 0x0E */
1070 U32 EventContext; /* 0x10 */
1071} MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST,
1072 Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t;
1073
1074
1075/* EventAck Reply message */
1076typedef struct _MPI2_EVENT_ACK_REPLY
1077{
1078 U16 Reserved1; /* 0x00 */
1079 U8 MsgLength; /* 0x02 */
1080 U8 Function; /* 0x03 */
1081 U16 Reserved2; /* 0x04 */
1082 U8 Reserved3; /* 0x06 */
1083 U8 MsgFlags; /* 0x07 */
1084 U8 VP_ID; /* 0x08 */
1085 U8 VF_ID; /* 0x09 */
1086 U16 Reserved4; /* 0x0A */
1087 U16 Reserved5; /* 0x0C */
1088 U16 IOCStatus; /* 0x0E */
1089 U32 IOCLogInfo; /* 0x10 */
1090} MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY,
1091 Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t;
1092
1093
1094/****************************************************************************
1095* SendHostMessage message
1096****************************************************************************/
1097
1098/* SendHostMessage Request message */
1099typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST {
1100 U16 HostDataLength; /* 0x00 */
1101 U8 ChainOffset; /* 0x02 */
1102 U8 Function; /* 0x03 */
1103 U16 Reserved1; /* 0x04 */
1104 U8 Reserved2; /* 0x06 */
1105 U8 MsgFlags; /* 0x07 */
1106 U8 VP_ID; /* 0x08 */
1107 U8 VF_ID; /* 0x09 */
1108 U16 Reserved3; /* 0x0A */
1109 U8 Reserved4; /* 0x0C */
1110 U8 DestVF_ID; /* 0x0D */
1111 U16 Reserved5; /* 0x0E */
1112 U32 Reserved6; /* 0x10 */
1113 U32 Reserved7; /* 0x14 */
1114 U32 Reserved8; /* 0x18 */
1115 U32 Reserved9; /* 0x1C */
1116 U32 Reserved10; /* 0x20 */
1117 U32 HostData[1]; /* 0x24 */
1118} MPI2_SEND_HOST_MESSAGE_REQUEST,
1119MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REQUEST,
1120Mpi2SendHostMessageRequest_t, MPI2_POINTER pMpi2SendHostMessageRequest_t;
1121
1122
1123/* SendHostMessage Reply message */
1124typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY {
1125 U16 HostDataLength; /* 0x00 */
1126 U8 MsgLength; /* 0x02 */
1127 U8 Function; /* 0x03 */
1128 U16 Reserved1; /* 0x04 */
1129 U8 Reserved2; /* 0x06 */
1130 U8 MsgFlags; /* 0x07 */
1131 U8 VP_ID; /* 0x08 */
1132 U8 VF_ID; /* 0x09 */
1133 U16 Reserved3; /* 0x0A */
1134 U16 Reserved4; /* 0x0C */
1135 U16 IOCStatus; /* 0x0E */
1136 U32 IOCLogInfo; /* 0x10 */
1137} MPI2_SEND_HOST_MESSAGE_REPLY, MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REPLY,
1138Mpi2SendHostMessageReply_t, MPI2_POINTER pMpi2SendHostMessageReply_t;
1139
1140
1141/****************************************************************************
1142* FWDownload message
1143****************************************************************************/
1144
1145/* FWDownload Request message */
1146typedef struct _MPI2_FW_DOWNLOAD_REQUEST
1147{
1148 U8 ImageType; /* 0x00 */
1149 U8 Reserved1; /* 0x01 */
1150 U8 ChainOffset; /* 0x02 */
1151 U8 Function; /* 0x03 */
1152 U16 Reserved2; /* 0x04 */
1153 U8 Reserved3; /* 0x06 */
1154 U8 MsgFlags; /* 0x07 */
1155 U8 VP_ID; /* 0x08 */
1156 U8 VF_ID; /* 0x09 */
1157 U16 Reserved4; /* 0x0A */
1158 U32 TotalImageSize; /* 0x0C */
1159 U32 Reserved5; /* 0x10 */
1160 MPI2_MPI_SGE_UNION SGL; /* 0x14 */
1161} MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST,
1162 Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest;
1163
1164#define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01)
1165
1166#define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01)
1167#define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02)
1168#define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06)
1169#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07)
1170#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08)
1171#define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09)
1172#define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A)
1173#define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1174#define MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY (0x0C)
1175#define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)
1176
1177/* FWDownload TransactionContext Element */
1178typedef struct _MPI2_FW_DOWNLOAD_TCSGE
1179{
1180 U8 Reserved1; /* 0x00 */
1181 U8 ContextSize; /* 0x01 */
1182 U8 DetailsLength; /* 0x02 */
1183 U8 Flags; /* 0x03 */
1184 U32 Reserved2; /* 0x04 */
1185 U32 ImageOffset; /* 0x08 */
1186 U32 ImageSize; /* 0x0C */
1187} MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE,
1188 Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t;
1189
1190/* FWDownload Reply message */
1191typedef struct _MPI2_FW_DOWNLOAD_REPLY
1192{
1193 U8 ImageType; /* 0x00 */
1194 U8 Reserved1; /* 0x01 */
1195 U8 MsgLength; /* 0x02 */
1196 U8 Function; /* 0x03 */
1197 U16 Reserved2; /* 0x04 */
1198 U8 Reserved3; /* 0x06 */
1199 U8 MsgFlags; /* 0x07 */
1200 U8 VP_ID; /* 0x08 */
1201 U8 VF_ID; /* 0x09 */
1202 U16 Reserved4; /* 0x0A */
1203 U16 Reserved5; /* 0x0C */
1204 U16 IOCStatus; /* 0x0E */
1205 U32 IOCLogInfo; /* 0x10 */
1206} MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY,
1207 Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t;
1208
1209
1210/****************************************************************************
1211* FWUpload message
1212****************************************************************************/
1213
1214/* FWUpload Request message */
1215typedef struct _MPI2_FW_UPLOAD_REQUEST
1216{
1217 U8 ImageType; /* 0x00 */
1218 U8 Reserved1; /* 0x01 */
1219 U8 ChainOffset; /* 0x02 */
1220 U8 Function; /* 0x03 */
1221 U16 Reserved2; /* 0x04 */
1222 U8 Reserved3; /* 0x06 */
1223 U8 MsgFlags; /* 0x07 */
1224 U8 VP_ID; /* 0x08 */
1225 U8 VF_ID; /* 0x09 */
1226 U16 Reserved4; /* 0x0A */
1227 U32 Reserved5; /* 0x0C */
1228 U32 Reserved6; /* 0x10 */
1229 MPI2_MPI_SGE_UNION SGL; /* 0x14 */
1230} MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST,
1231 Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t;
1232
1233#define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00)
1234#define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01)
1235#define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02)
1236#define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05)
1237#define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06)
1238#define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07)
1239#define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08)
1240#define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09)
1241#define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A)
1242#define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1243
1244typedef struct _MPI2_FW_UPLOAD_TCSGE
1245{
1246 U8 Reserved1; /* 0x00 */
1247 U8 ContextSize; /* 0x01 */
1248 U8 DetailsLength; /* 0x02 */
1249 U8 Flags; /* 0x03 */
1250 U32 Reserved2; /* 0x04 */
1251 U32 ImageOffset; /* 0x08 */
1252 U32 ImageSize; /* 0x0C */
1253} MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE,
1254 Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t;
1255
1256/* FWUpload Reply message */
1257typedef struct _MPI2_FW_UPLOAD_REPLY
1258{
1259 U8 ImageType; /* 0x00 */
1260 U8 Reserved1; /* 0x01 */
1261 U8 MsgLength; /* 0x02 */
1262 U8 Function; /* 0x03 */
1263 U16 Reserved2; /* 0x04 */
1264 U8 Reserved3; /* 0x06 */
1265 U8 MsgFlags; /* 0x07 */
1266 U8 VP_ID; /* 0x08 */
1267 U8 VF_ID; /* 0x09 */
1268 U16 Reserved4; /* 0x0A */
1269 U16 Reserved5; /* 0x0C */
1270 U16 IOCStatus; /* 0x0E */
1271 U32 IOCLogInfo; /* 0x10 */
1272 U32 ActualImageSize; /* 0x14 */
1273} MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY,
1274 Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t;
1275
1276
1277/* FW Image Header */
1278typedef struct _MPI2_FW_IMAGE_HEADER
1279{
1280 U32 Signature; /* 0x00 */
1281 U32 Signature0; /* 0x04 */
1282 U32 Signature1; /* 0x08 */
1283 U32 Signature2; /* 0x0C */
1284 MPI2_VERSION_UNION MPIVersion; /* 0x10 */
1285 MPI2_VERSION_UNION FWVersion; /* 0x14 */
1286 MPI2_VERSION_UNION NVDATAVersion; /* 0x18 */
1287 MPI2_VERSION_UNION PackageVersion; /* 0x1C */
1288 U16 VendorID; /* 0x20 */
1289 U16 ProductID; /* 0x22 */
1290 U16 ProtocolFlags; /* 0x24 */
1291 U16 Reserved26; /* 0x26 */
1292 U32 IOCCapabilities; /* 0x28 */
1293 U32 ImageSize; /* 0x2C */
1294 U32 NextImageHeaderOffset; /* 0x30 */
1295 U32 Checksum; /* 0x34 */
1296 U32 Reserved38; /* 0x38 */
1297 U32 Reserved3C; /* 0x3C */
1298 U32 Reserved40; /* 0x40 */
1299 U32 Reserved44; /* 0x44 */
1300 U32 Reserved48; /* 0x48 */
1301 U32 Reserved4C; /* 0x4C */
1302 U32 Reserved50; /* 0x50 */
1303 U32 Reserved54; /* 0x54 */
1304 U32 Reserved58; /* 0x58 */
1305 U32 Reserved5C; /* 0x5C */
1306 U32 Reserved60; /* 0x60 */
1307 U32 FirmwareVersionNameWhat; /* 0x64 */
1308 U8 FirmwareVersionName[32]; /* 0x68 */
1309 U32 VendorNameWhat; /* 0x88 */
1310 U8 VendorName[32]; /* 0x8C */
1311 U32 PackageNameWhat; /* 0x88 */
1312 U8 PackageName[32]; /* 0x8C */
1313 U32 ReservedD0; /* 0xD0 */
1314 U32 ReservedD4; /* 0xD4 */
1315 U32 ReservedD8; /* 0xD8 */
1316 U32 ReservedDC; /* 0xDC */
1317 U32 ReservedE0; /* 0xE0 */
1318 U32 ReservedE4; /* 0xE4 */
1319 U32 ReservedE8; /* 0xE8 */
1320 U32 ReservedEC; /* 0xEC */
1321 U32 ReservedF0; /* 0xF0 */
1322 U32 ReservedF4; /* 0xF4 */
1323 U32 ReservedF8; /* 0xF8 */
1324 U32 ReservedFC; /* 0xFC */
1325} MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER,
1326 Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t;
1327
1328/* Signature field */
1329#define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00)
1330#define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000)
1331#define MPI2_FW_HEADER_SIGNATURE (0xEA000000)
1332
1333/* Signature0 field */
1334#define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04)
1335#define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A)
1336
1337/* Signature1 field */
1338#define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08)
1339#define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5)
1340
1341/* Signature2 field */
1342#define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C)
1343#define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA)
1344
1345
1346/* defines for using the ProductID field */
1347#define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000)
1348#define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000)
1349
1350#define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00)
1351#define MPI2_FW_HEADER_PID_PROD_A (0x0000)
1352#define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200)
1353#define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700)
1354
1355
1356#define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF)
1357/* SAS */
1358#define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013)
1359#define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014)
1360
1361/* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
1362
1363/* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
1364
1365
1366#define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C)
1367#define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30)
1368#define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64)
1369
1370#define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840)
1371
1372#define MPI2_FW_HEADER_SIZE (0x100)
1373
1374
1375/* Extended Image Header */
1376typedef struct _MPI2_EXT_IMAGE_HEADER
1377
1378{
1379 U8 ImageType; /* 0x00 */
1380 U8 Reserved1; /* 0x01 */
1381 U16 Reserved2; /* 0x02 */
1382 U32 Checksum; /* 0x04 */
1383 U32 ImageSize; /* 0x08 */
1384 U32 NextImageHeaderOffset; /* 0x0C */
1385 U32 PackageVersion; /* 0x10 */
1386 U32 Reserved3; /* 0x14 */
1387 U32 Reserved4; /* 0x18 */
1388 U32 Reserved5; /* 0x1C */
1389 U8 IdentifyString[32]; /* 0x20 */
1390} MPI2_EXT_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER,
1391 Mpi2ExtImageHeader_t, MPI2_POINTER pMpi2ExtImageHeader_t;
1392
1393/* useful offsets */
1394#define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00)
1395#define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08)
1396#define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C)
1397
1398#define MPI2_EXT_IMAGE_HEADER_SIZE (0x40)
1399
1400/* defines for the ImageType field */
1401#define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00)
1402#define MPI2_EXT_IMAGE_TYPE_FW (0x01)
1403#define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03)
1404#define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04)
1405#define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05)
1406#define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06)
1407#define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07)
1408#define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08)
1409#define MPI2_EXT_IMAGE_TYPE_ENCRYPTED_HASH (0x09)
1410#define MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC (0x80)
1411#define MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC (0xFF)
1412#define MPI2_EXT_IMAGE_TYPE_MAX \
1413 (MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC) /* deprecated */
1414
1415
1416
1417/* FLASH Layout Extended Image Data */
1418
1419/*
1420 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1421 * one and check RegionsPerLayout at runtime.
1422 */
1423#ifndef MPI2_FLASH_NUMBER_OF_REGIONS
1424#define MPI2_FLASH_NUMBER_OF_REGIONS (1)
1425#endif
1426
1427/*
1428 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1429 * one and check NumberOfLayouts at runtime.
1430 */
1431#ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS
1432#define MPI2_FLASH_NUMBER_OF_LAYOUTS (1)
1433#endif
1434
1435typedef struct _MPI2_FLASH_REGION
1436{
1437 U8 RegionType; /* 0x00 */
1438 U8 Reserved1; /* 0x01 */
1439 U16 Reserved2; /* 0x02 */
1440 U32 RegionOffset; /* 0x04 */
1441 U32 RegionSize; /* 0x08 */
1442 U32 Reserved3; /* 0x0C */
1443} MPI2_FLASH_REGION, MPI2_POINTER PTR_MPI2_FLASH_REGION,
1444 Mpi2FlashRegion_t, MPI2_POINTER pMpi2FlashRegion_t;
1445
1446typedef struct _MPI2_FLASH_LAYOUT
1447{
1448 U32 FlashSize; /* 0x00 */
1449 U32 Reserved1; /* 0x04 */
1450 U32 Reserved2; /* 0x08 */
1451 U32 Reserved3; /* 0x0C */
1452 MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */
1453} MPI2_FLASH_LAYOUT, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT,
1454 Mpi2FlashLayout_t, MPI2_POINTER pMpi2FlashLayout_t;
1455
1456typedef struct _MPI2_FLASH_LAYOUT_DATA
1457{
1458 U8 ImageRevision; /* 0x00 */
1459 U8 Reserved1; /* 0x01 */
1460 U8 SizeOfRegion; /* 0x02 */
1461 U8 Reserved2; /* 0x03 */
1462 U16 NumberOfLayouts; /* 0x04 */
1463 U16 RegionsPerLayout; /* 0x06 */
1464 U16 MinimumSectorAlignment; /* 0x08 */
1465 U16 Reserved3; /* 0x0A */
1466 U32 Reserved4; /* 0x0C */
1467 MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */
1468} MPI2_FLASH_LAYOUT_DATA, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA,
1469 Mpi2FlashLayoutData_t, MPI2_POINTER pMpi2FlashLayoutData_t;
1470
1471/* defines for the RegionType field */
1472#define MPI2_FLASH_REGION_UNUSED (0x00)
1473#define MPI2_FLASH_REGION_FIRMWARE (0x01)
1474#define MPI2_FLASH_REGION_BIOS (0x02)
1475#define MPI2_FLASH_REGION_NVDATA (0x03)
1476#define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05)
1477#define MPI2_FLASH_REGION_MFG_INFORMATION (0x06)
1478#define MPI2_FLASH_REGION_CONFIG_1 (0x07)
1479#define MPI2_FLASH_REGION_CONFIG_2 (0x08)
1480#define MPI2_FLASH_REGION_MEGARAID (0x09)
1481#define MPI2_FLASH_REGION_INIT (0x0A)
1482
1483/* ImageRevision */
1484#define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00)
1485
1486
1487
1488/* Supported Devices Extended Image Data */
1489
1490/*
1491 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1492 * one and check NumberOfDevices at runtime.
1493 */
1494#ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES
1495#define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1)
1496#endif
1497
1498typedef struct _MPI2_SUPPORTED_DEVICE
1499{
1500 U16 DeviceID; /* 0x00 */
1501 U16 VendorID; /* 0x02 */
1502 U16 DeviceIDMask; /* 0x04 */
1503 U16 Reserved1; /* 0x06 */
1504 U8 LowPCIRev; /* 0x08 */
1505 U8 HighPCIRev; /* 0x09 */
1506 U16 Reserved2; /* 0x0A */
1507 U32 Reserved3; /* 0x0C */
1508} MPI2_SUPPORTED_DEVICE, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE,
1509 Mpi2SupportedDevice_t, MPI2_POINTER pMpi2SupportedDevice_t;
1510
1511typedef struct _MPI2_SUPPORTED_DEVICES_DATA
1512{
1513 U8 ImageRevision; /* 0x00 */
1514 U8 Reserved1; /* 0x01 */
1515 U8 NumberOfDevices; /* 0x02 */
1516 U8 Reserved2; /* 0x03 */
1517 U32 Reserved3; /* 0x04 */
1518 MPI2_SUPPORTED_DEVICE SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */
1519} MPI2_SUPPORTED_DEVICES_DATA, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA,
1520 Mpi2SupportedDevicesData_t, MPI2_POINTER pMpi2SupportedDevicesData_t;
1521
1522/* ImageRevision */
1523#define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00)
1524
1525
1526/* Init Extended Image Data */
1527
1528typedef struct _MPI2_INIT_IMAGE_FOOTER
1529
1530{
1531 U32 BootFlags; /* 0x00 */
1532 U32 ImageSize; /* 0x04 */
1533 U32 Signature0; /* 0x08 */
1534 U32 Signature1; /* 0x0C */
1535 U32 Signature2; /* 0x10 */
1536 U32 ResetVector; /* 0x14 */
1537} MPI2_INIT_IMAGE_FOOTER, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER,
1538 Mpi2InitImageFooter_t, MPI2_POINTER pMpi2InitImageFooter_t;
1539
1540/* defines for the BootFlags field */
1541#define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00)
1542
1543/* defines for the ImageSize field */
1544#define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04)
1545
1546/* defines for the Signature0 field */
1547#define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08)
1548#define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA)
1549
1550/* defines for the Signature1 field */
1551#define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C)
1552#define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5)
1553
1554/* defines for the Signature2 field */
1555#define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10)
1556#define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A)
1557
1558/* Signature fields as individual bytes */
1559#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA)
1560#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A)
1561#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5)
1562#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A)
1563
1564#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5)
1565#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA)
1566#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A)
1567#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5)
1568
1569#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A)
1570#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5)
1571#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA)
1572#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A)
1573
1574/* defines for the ResetVector field */
1575#define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14)
1576
1577
1578/* Encrypted Hash Extended Image Data */
1579
1580typedef struct _MPI25_ENCRYPTED_HASH_ENTRY {
1581 U8 HashImageType; /* 0x00 */
1582 U8 HashAlgorithm; /* 0x01 */
1583 U8 EncryptionAlgorithm; /* 0x02 */
1584 U8 Reserved1; /* 0x03 */
1585 U32 Reserved2; /* 0x04 */
1586 U32 EncryptedHash[1]; /* 0x08 */
1587} MPI25_ENCRYPTED_HASH_ENTRY, MPI2_POINTER PTR_MPI25_ENCRYPTED_HASH_ENTRY,
1588Mpi25EncryptedHashEntry_t, MPI2_POINTER pMpi25EncryptedHashEntry_t;
1589
1590/* values for HashImageType */
1591#define MPI25_HASH_IMAGE_TYPE_UNUSED (0x00)
1592#define MPI25_HASH_IMAGE_TYPE_FIRMWARE (0x01)
1593#define MPI25_HASH_IMAGE_TYPE_BIOS (0x02)
1594
1595/* values for HashAlgorithm */
1596#define MPI25_HASH_ALGORITHM_UNUSED (0x00)
1597#define MPI25_HASH_ALGORITHM_SHA256 (0x01)
1598
1599/* values for EncryptionAlgorithm */
1600#define MPI25_ENCRYPTION_ALG_UNUSED (0x00)
1601#define MPI25_ENCRYPTION_ALG_RSA256 (0x01)
1602
1603typedef struct _MPI25_ENCRYPTED_HASH_DATA {
1604 U8 ImageVersion; /* 0x00 */
1605 U8 NumHash; /* 0x01 */
1606 U16 Reserved1; /* 0x02 */
1607 U32 Reserved2; /* 0x04 */
1608 MPI25_ENCRYPTED_HASH_ENTRY EncryptedHashEntry[1]; /* 0x08 */
1609} MPI25_ENCRYPTED_HASH_DATA, MPI2_POINTER PTR_MPI25_ENCRYPTED_HASH_DATA,
1610Mpi25EncryptedHashData_t, MPI2_POINTER pMpi25EncryptedHashData_t;
1611
1612/****************************************************************************
1613* PowerManagementControl message
1614****************************************************************************/
1615
1616/* PowerManagementControl Request message */
1617typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST {
1618 U8 Feature; /* 0x00 */
1619 U8 Reserved1; /* 0x01 */
1620 U8 ChainOffset; /* 0x02 */
1621 U8 Function; /* 0x03 */
1622 U16 Reserved2; /* 0x04 */
1623 U8 Reserved3; /* 0x06 */
1624 U8 MsgFlags; /* 0x07 */
1625 U8 VP_ID; /* 0x08 */
1626 U8 VF_ID; /* 0x09 */
1627 U16 Reserved4; /* 0x0A */
1628 U8 Parameter1; /* 0x0C */
1629 U8 Parameter2; /* 0x0D */
1630 U8 Parameter3; /* 0x0E */
1631 U8 Parameter4; /* 0x0F */
1632 U32 Reserved5; /* 0x10 */
1633 U32 Reserved6; /* 0x14 */
1634} MPI2_PWR_MGMT_CONTROL_REQUEST, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REQUEST,
1635 Mpi2PwrMgmtControlRequest_t, MPI2_POINTER pMpi2PwrMgmtControlRequest_t;
1636
1637/* defines for the Feature field */
1638#define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01)
1639#define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02)
1640#define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03) /* obsolete */
1641#define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04)
1642#define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80)
1643#define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF)
1644
1645/* parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */
1646/* Parameter1 contains a PHY number */
1647/* Parameter2 indicates power condition action using these defines */
1648#define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01)
1649#define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02)
1650#define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03)
1651/* Parameter3 and Parameter4 are reserved */
1652
1653/* parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION
1654 * Feature */
1655/* Parameter1 contains SAS port width modulation group number */
1656/* Parameter2 indicates IOC action using these defines */
1657#define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01)
1658#define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02)
1659#define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03)
1660/* Parameter3 indicates desired modulation level using these defines */
1661#define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00)
1662#define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01)
1663#define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02)
1664#define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03)
1665/* Parameter4 is reserved */
1666
1667/* parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */
1668/* Parameter1 indicates desired PCIe link speed using these defines */
1669#define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00) /* obsolete */
1670#define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01) /* obsolete */
1671#define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02) /* obsolete */
1672/* Parameter2 indicates desired PCIe link width using these defines */
1673#define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01) /* obsolete */
1674#define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02) /* obsolete */
1675#define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04) /* obsolete */
1676#define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08) /* obsolete */
1677/* Parameter3 and Parameter4 are reserved */
1678
1679/* parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */
1680/* Parameter1 indicates desired IOC hardware clock speed using these defines */
1681#define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01)
1682#define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02)
1683#define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04)
1684#define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08)
1685/* Parameter2, Parameter3, and Parameter4 are reserved */
1686
1687
1688/* PowerManagementControl Reply message */
1689typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY {
1690 U8 Feature; /* 0x00 */
1691 U8 Reserved1; /* 0x01 */
1692 U8 MsgLength; /* 0x02 */
1693 U8 Function; /* 0x03 */
1694 U16 Reserved2; /* 0x04 */
1695 U8 Reserved3; /* 0x06 */
1696 U8 MsgFlags; /* 0x07 */
1697 U8 VP_ID; /* 0x08 */
1698 U8 VF_ID; /* 0x09 */
1699 U16 Reserved4; /* 0x0A */
1700 U16 Reserved5; /* 0x0C */
1701 U16 IOCStatus; /* 0x0E */
1702 U32 IOCLogInfo; /* 0x10 */
1703} MPI2_PWR_MGMT_CONTROL_REPLY, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REPLY,
1704 Mpi2PwrMgmtControlReply_t, MPI2_POINTER pMpi2PwrMgmtControlReply_t;
1705
1706
1707#endif
1708
diff --git a/drivers/scsi/mpt2sas/mpi/mpi2_raid.h b/drivers/scsi/mpt2sas/mpi/mpi2_raid.h
deleted file mode 100644
index 7efa58ff0d34..000000000000
--- a/drivers/scsi/mpt2sas/mpi/mpi2_raid.h
+++ /dev/null
@@ -1,366 +0,0 @@
1/*
2 * Copyright (c) 2000-2014 LSI Corporation.
3 *
4 *
5 * Name: mpi2_raid.h
6 * Title: MPI Integrated RAID messages and structures
7 * Creation Date: April 26, 2007
8 *
9 * mpi2_raid.h Version: 02.00.10
10 *
11 * Version History
12 * ---------------
13 *
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
17 * 08-31-07 02.00.01 Modifications to RAID Action request and reply,
18 * including the Actions and ActionData.
19 * 02-29-08 02.00.02 Added MPI2_RAID_ACTION_ADATA_DISABL_FULL_REBUILD.
20 * 05-21-08 02.00.03 Added MPI2_RAID_VOL_CREATION_NUM_PHYSDISKS so that
21 * the PhysDisk array in MPI2_RAID_VOLUME_CREATION_STRUCT
22 * can be sized by the build environment.
23 * 07-30-09 02.00.04 Added proper define for the Use Default Settings bit of
24 * VolumeCreationFlags and marked the old one as obsolete.
25 * 05-12-10 02.00.05 Added MPI2_RAID_VOL_FLAGS_OP_MDC define.
26 * 08-24-10 02.00.06 Added MPI2_RAID_ACTION_COMPATIBILITY_CHECK along with
27 * related structures and defines.
28 * Added product-specific range to RAID Action values.
29 * 02-06-12 02.00.08 Added MPI2_RAID_ACTION_PHYSDISK_HIDDEN.
30 * 07-26-12 02.00.09 Added ElapsedSeconds field to MPI2_RAID_VOL_INDICATOR.
31 * Added MPI2_RAID_VOL_FLAGS_ELAPSED_SECONDS_VALID define.
32 * 04-17-13 02.00.10 Added MPI25_RAID_ACTION_ADATA_ALLOW_PI.
33 * --------------------------------------------------------------------------
34 */
35
36#ifndef MPI2_RAID_H
37#define MPI2_RAID_H
38
39/*****************************************************************************
40*
41* Integrated RAID Messages
42*
43*****************************************************************************/
44
45/****************************************************************************
46* RAID Action messages
47****************************************************************************/
48
49/* ActionDataWord defines for use with MPI2_RAID_ACTION_CREATE_VOLUME action */
50#define MPI25_RAID_ACTION_ADATA_ALLOW_PI (0x80000000)
51
52/* ActionDataWord defines for use with MPI2_RAID_ACTION_DELETE_VOLUME action */
53#define MPI2_RAID_ACTION_ADATA_KEEP_LBA0 (0x00000000)
54#define MPI2_RAID_ACTION_ADATA_ZERO_LBA0 (0x00000001)
55
56/* use MPI2_RAIDVOL0_SETTING_ defines from mpi2_cnfg.h for MPI2_RAID_ACTION_CHANGE_VOL_WRITE_CACHE action */
57
58/* ActionDataWord defines for use with MPI2_RAID_ACTION_DISABLE_ALL_VOLUMES action */
59#define MPI2_RAID_ACTION_ADATA_DISABL_FULL_REBUILD (0x00000001)
60
61/* ActionDataWord for MPI2_RAID_ACTION_SET_RAID_FUNCTION_RATE Action */
62typedef struct _MPI2_RAID_ACTION_RATE_DATA
63{
64 U8 RateToChange; /* 0x00 */
65 U8 RateOrMode; /* 0x01 */
66 U16 DataScrubDuration; /* 0x02 */
67} MPI2_RAID_ACTION_RATE_DATA, MPI2_POINTER PTR_MPI2_RAID_ACTION_RATE_DATA,
68 Mpi2RaidActionRateData_t, MPI2_POINTER pMpi2RaidActionRateData_t;
69
70#define MPI2_RAID_ACTION_SET_RATE_RESYNC (0x00)
71#define MPI2_RAID_ACTION_SET_RATE_DATA_SCRUB (0x01)
72#define MPI2_RAID_ACTION_SET_RATE_POWERSAVE_MODE (0x02)
73
74/* ActionDataWord for MPI2_RAID_ACTION_START_RAID_FUNCTION Action */
75typedef struct _MPI2_RAID_ACTION_START_RAID_FUNCTION
76{
77 U8 RAIDFunction; /* 0x00 */
78 U8 Flags; /* 0x01 */
79 U16 Reserved1; /* 0x02 */
80} MPI2_RAID_ACTION_START_RAID_FUNCTION,
81 MPI2_POINTER PTR_MPI2_RAID_ACTION_START_RAID_FUNCTION,
82 Mpi2RaidActionStartRaidFunction_t,
83 MPI2_POINTER pMpi2RaidActionStartRaidFunction_t;
84
85/* defines for the RAIDFunction field */
86#define MPI2_RAID_ACTION_START_BACKGROUND_INIT (0x00)
87#define MPI2_RAID_ACTION_START_ONLINE_CAP_EXPANSION (0x01)
88#define MPI2_RAID_ACTION_START_CONSISTENCY_CHECK (0x02)
89
90/* defines for the Flags field */
91#define MPI2_RAID_ACTION_START_NEW (0x00)
92#define MPI2_RAID_ACTION_START_RESUME (0x01)
93
94/* ActionDataWord for MPI2_RAID_ACTION_STOP_RAID_FUNCTION Action */
95typedef struct _MPI2_RAID_ACTION_STOP_RAID_FUNCTION
96{
97 U8 RAIDFunction; /* 0x00 */
98 U8 Flags; /* 0x01 */
99 U16 Reserved1; /* 0x02 */
100} MPI2_RAID_ACTION_STOP_RAID_FUNCTION,
101 MPI2_POINTER PTR_MPI2_RAID_ACTION_STOP_RAID_FUNCTION,
102 Mpi2RaidActionStopRaidFunction_t,
103 MPI2_POINTER pMpi2RaidActionStopRaidFunction_t;
104
105/* defines for the RAIDFunction field */
106#define MPI2_RAID_ACTION_STOP_BACKGROUND_INIT (0x00)
107#define MPI2_RAID_ACTION_STOP_ONLINE_CAP_EXPANSION (0x01)
108#define MPI2_RAID_ACTION_STOP_CONSISTENCY_CHECK (0x02)
109
110/* defines for the Flags field */
111#define MPI2_RAID_ACTION_STOP_ABORT (0x00)
112#define MPI2_RAID_ACTION_STOP_PAUSE (0x01)
113
114/* ActionDataWord for MPI2_RAID_ACTION_CREATE_HOT_SPARE Action */
115typedef struct _MPI2_RAID_ACTION_HOT_SPARE
116{
117 U8 HotSparePool; /* 0x00 */
118 U8 Reserved1; /* 0x01 */
119 U16 DevHandle; /* 0x02 */
120} MPI2_RAID_ACTION_HOT_SPARE, MPI2_POINTER PTR_MPI2_RAID_ACTION_HOT_SPARE,
121 Mpi2RaidActionHotSpare_t, MPI2_POINTER pMpi2RaidActionHotSpare_t;
122
123/* ActionDataWord for MPI2_RAID_ACTION_DEVICE_FW_UPDATE_MODE Action */
124typedef struct _MPI2_RAID_ACTION_FW_UPDATE_MODE
125{
126 U8 Flags; /* 0x00 */
127 U8 DeviceFirmwareUpdateModeTimeout; /* 0x01 */
128 U16 Reserved1; /* 0x02 */
129} MPI2_RAID_ACTION_FW_UPDATE_MODE,
130 MPI2_POINTER PTR_MPI2_RAID_ACTION_FW_UPDATE_MODE,
131 Mpi2RaidActionFwUpdateMode_t, MPI2_POINTER pMpi2RaidActionFwUpdateMode_t;
132
133/* ActionDataWord defines for use with MPI2_RAID_ACTION_DEVICE_FW_UPDATE_MODE action */
134#define MPI2_RAID_ACTION_ADATA_DISABLE_FW_UPDATE (0x00)
135#define MPI2_RAID_ACTION_ADATA_ENABLE_FW_UPDATE (0x01)
136
137typedef union _MPI2_RAID_ACTION_DATA
138{
139 U32 Word;
140 MPI2_RAID_ACTION_RATE_DATA Rates;
141 MPI2_RAID_ACTION_START_RAID_FUNCTION StartRaidFunction;
142 MPI2_RAID_ACTION_STOP_RAID_FUNCTION StopRaidFunction;
143 MPI2_RAID_ACTION_HOT_SPARE HotSpare;
144 MPI2_RAID_ACTION_FW_UPDATE_MODE FwUpdateMode;
145} MPI2_RAID_ACTION_DATA, MPI2_POINTER PTR_MPI2_RAID_ACTION_DATA,
146 Mpi2RaidActionData_t, MPI2_POINTER pMpi2RaidActionData_t;
147
148
149/* RAID Action Request Message */
150typedef struct _MPI2_RAID_ACTION_REQUEST
151{
152 U8 Action; /* 0x00 */
153 U8 Reserved1; /* 0x01 */
154 U8 ChainOffset; /* 0x02 */
155 U8 Function; /* 0x03 */
156 U16 VolDevHandle; /* 0x04 */
157 U8 PhysDiskNum; /* 0x06 */
158 U8 MsgFlags; /* 0x07 */
159 U8 VP_ID; /* 0x08 */
160 U8 VF_ID; /* 0x09 */
161 U16 Reserved2; /* 0x0A */
162 U32 Reserved3; /* 0x0C */
163 MPI2_RAID_ACTION_DATA ActionDataWord; /* 0x10 */
164 MPI2_SGE_SIMPLE_UNION ActionDataSGE; /* 0x14 */
165} MPI2_RAID_ACTION_REQUEST, MPI2_POINTER PTR_MPI2_RAID_ACTION_REQUEST,
166 Mpi2RaidActionRequest_t, MPI2_POINTER pMpi2RaidActionRequest_t;
167
168/* RAID Action request Action values */
169
170#define MPI2_RAID_ACTION_INDICATOR_STRUCT (0x01)
171#define MPI2_RAID_ACTION_CREATE_VOLUME (0x02)
172#define MPI2_RAID_ACTION_DELETE_VOLUME (0x03)
173#define MPI2_RAID_ACTION_DISABLE_ALL_VOLUMES (0x04)
174#define MPI2_RAID_ACTION_ENABLE_ALL_VOLUMES (0x05)
175#define MPI2_RAID_ACTION_PHYSDISK_OFFLINE (0x0A)
176#define MPI2_RAID_ACTION_PHYSDISK_ONLINE (0x0B)
177#define MPI2_RAID_ACTION_FAIL_PHYSDISK (0x0F)
178#define MPI2_RAID_ACTION_ACTIVATE_VOLUME (0x11)
179#define MPI2_RAID_ACTION_DEVICE_FW_UPDATE_MODE (0x15)
180#define MPI2_RAID_ACTION_CHANGE_VOL_WRITE_CACHE (0x17)
181#define MPI2_RAID_ACTION_SET_VOLUME_NAME (0x18)
182#define MPI2_RAID_ACTION_SET_RAID_FUNCTION_RATE (0x19)
183#define MPI2_RAID_ACTION_ENABLE_FAILED_VOLUME (0x1C)
184#define MPI2_RAID_ACTION_CREATE_HOT_SPARE (0x1D)
185#define MPI2_RAID_ACTION_DELETE_HOT_SPARE (0x1E)
186#define MPI2_RAID_ACTION_SYSTEM_SHUTDOWN_INITIATED (0x20)
187#define MPI2_RAID_ACTION_START_RAID_FUNCTION (0x21)
188#define MPI2_RAID_ACTION_STOP_RAID_FUNCTION (0x22)
189#define MPI2_RAID_ACTION_COMPATIBILITY_CHECK (0x23)
190#define MPI2_RAID_ACTION_PHYSDISK_HIDDEN (0x24)
191#define MPI2_RAID_ACTION_MIN_PRODUCT_SPECIFIC (0x80)
192#define MPI2_RAID_ACTION_MAX_PRODUCT_SPECIFIC (0xFF)
193
194/* RAID Volume Creation Structure */
195
196/*
197 * The following define can be customized for the targeted product.
198 */
199#ifndef MPI2_RAID_VOL_CREATION_NUM_PHYSDISKS
200#define MPI2_RAID_VOL_CREATION_NUM_PHYSDISKS (1)
201#endif
202
203typedef struct _MPI2_RAID_VOLUME_PHYSDISK
204{
205 U8 RAIDSetNum; /* 0x00 */
206 U8 PhysDiskMap; /* 0x01 */
207 U16 PhysDiskDevHandle; /* 0x02 */
208} MPI2_RAID_VOLUME_PHYSDISK, MPI2_POINTER PTR_MPI2_RAID_VOLUME_PHYSDISK,
209 Mpi2RaidVolumePhysDisk_t, MPI2_POINTER pMpi2RaidVolumePhysDisk_t;
210
211/* defines for the PhysDiskMap field */
212#define MPI2_RAIDACTION_PHYSDISK_PRIMARY (0x01)
213#define MPI2_RAIDACTION_PHYSDISK_SECONDARY (0x02)
214
215typedef struct _MPI2_RAID_VOLUME_CREATION_STRUCT
216{
217 U8 NumPhysDisks; /* 0x00 */
218 U8 VolumeType; /* 0x01 */
219 U16 Reserved1; /* 0x02 */
220 U32 VolumeCreationFlags; /* 0x04 */
221 U32 VolumeSettings; /* 0x08 */
222 U8 Reserved2; /* 0x0C */
223 U8 ResyncRate; /* 0x0D */
224 U16 DataScrubDuration; /* 0x0E */
225 U64 VolumeMaxLBA; /* 0x10 */
226 U32 StripeSize; /* 0x18 */
227 U8 Name[16]; /* 0x1C */
228 MPI2_RAID_VOLUME_PHYSDISK PhysDisk[MPI2_RAID_VOL_CREATION_NUM_PHYSDISKS];/* 0x2C */
229} MPI2_RAID_VOLUME_CREATION_STRUCT,
230 MPI2_POINTER PTR_MPI2_RAID_VOLUME_CREATION_STRUCT,
231 Mpi2RaidVolumeCreationStruct_t, MPI2_POINTER pMpi2RaidVolumeCreationStruct_t;
232
233/* use MPI2_RAID_VOL_TYPE_ defines from mpi2_cnfg.h for VolumeType */
234
235/* defines for the VolumeCreationFlags field */
236#define MPI2_RAID_VOL_CREATION_DEFAULT_SETTINGS (0x80000000)
237#define MPI2_RAID_VOL_CREATION_BACKGROUND_INIT (0x00000004)
238#define MPI2_RAID_VOL_CREATION_LOW_LEVEL_INIT (0x00000002)
239#define MPI2_RAID_VOL_CREATION_MIGRATE_DATA (0x00000001)
240/* The following is an obsolete define.
241 * It must be shifted left 24 bits in order to set the proper bit.
242 */
243#define MPI2_RAID_VOL_CREATION_USE_DEFAULT_SETTINGS (0x80)
244
245
246/* RAID Online Capacity Expansion Structure */
247
248typedef struct _MPI2_RAID_ONLINE_CAPACITY_EXPANSION
249{
250 U32 Flags; /* 0x00 */
251 U16 DevHandle0; /* 0x04 */
252 U16 Reserved1; /* 0x06 */
253 U16 DevHandle1; /* 0x08 */
254 U16 Reserved2; /* 0x0A */
255} MPI2_RAID_ONLINE_CAPACITY_EXPANSION,
256 MPI2_POINTER PTR_MPI2_RAID_ONLINE_CAPACITY_EXPANSION,
257 Mpi2RaidOnlineCapacityExpansion_t,
258 MPI2_POINTER pMpi2RaidOnlineCapacityExpansion_t;
259
260/* RAID Compatibility Input Structure */
261
262typedef struct _MPI2_RAID_COMPATIBILITY_INPUT_STRUCT {
263 U16 SourceDevHandle; /* 0x00 */
264 U16 CandidateDevHandle; /* 0x02 */
265 U32 Flags; /* 0x04 */
266 U32 Reserved1; /* 0x08 */
267 U32 Reserved2; /* 0x0C */
268} MPI2_RAID_COMPATIBILITY_INPUT_STRUCT,
269MPI2_POINTER PTR_MPI2_RAID_COMPATIBILITY_INPUT_STRUCT,
270Mpi2RaidCompatibilityInputStruct_t,
271MPI2_POINTER pMpi2RaidCompatibilityInputStruct_t;
272
273/* defines for RAID Compatibility Structure Flags field */
274#define MPI2_RAID_COMPAT_SOURCE_IS_VOLUME_FLAG (0x00000002)
275#define MPI2_RAID_COMPAT_REPORT_SOURCE_INFO_FLAG (0x00000001)
276
277
278/* RAID Volume Indicator Structure */
279
280typedef struct _MPI2_RAID_VOL_INDICATOR
281{
282 U64 TotalBlocks; /* 0x00 */
283 U64 BlocksRemaining; /* 0x08 */
284 U32 Flags; /* 0x10 */
285 U32 ElapsedSeconds; /* 0x14 */
286} MPI2_RAID_VOL_INDICATOR, MPI2_POINTER PTR_MPI2_RAID_VOL_INDICATOR,
287 Mpi2RaidVolIndicator_t, MPI2_POINTER pMpi2RaidVolIndicator_t;
288
289/* defines for RAID Volume Indicator Flags field */
290#define MPI2_RAID_VOL_FLAGS_ELAPSED_SECONDS_VALID (0x80000000)
291
292#define MPI2_RAID_VOL_FLAGS_OP_MASK (0x0000000F)
293#define MPI2_RAID_VOL_FLAGS_OP_BACKGROUND_INIT (0x00000000)
294#define MPI2_RAID_VOL_FLAGS_OP_ONLINE_CAP_EXPANSION (0x00000001)
295#define MPI2_RAID_VOL_FLAGS_OP_CONSISTENCY_CHECK (0x00000002)
296#define MPI2_RAID_VOL_FLAGS_OP_RESYNC (0x00000003)
297#define MPI2_RAID_VOL_FLAGS_OP_MDC (0x00000004)
298
299/* RAID Compatibility Result Structure */
300
301typedef struct _MPI2_RAID_COMPATIBILITY_RESULT_STRUCT {
302 U8 State; /* 0x00 */
303 U8 Reserved1; /* 0x01 */
304 U16 Reserved2; /* 0x02 */
305 U32 GenericAttributes; /* 0x04 */
306 U32 OEMSpecificAttributes; /* 0x08 */
307 U32 Reserved3; /* 0x0C */
308 U32 Reserved4; /* 0x10 */
309} MPI2_RAID_COMPATIBILITY_RESULT_STRUCT,
310MPI2_POINTER PTR_MPI2_RAID_COMPATIBILITY_RESULT_STRUCT,
311Mpi2RaidCompatibilityResultStruct_t,
312MPI2_POINTER pMpi2RaidCompatibilityResultStruct_t;
313
314/* defines for RAID Compatibility Result Structure State field */
315#define MPI2_RAID_COMPAT_STATE_COMPATIBLE (0x00)
316#define MPI2_RAID_COMPAT_STATE_NOT_COMPATIBLE (0x01)
317
318/* defines for RAID Compatibility Result Structure GenericAttributes field */
319#define MPI2_RAID_COMPAT_GENATTRIB_4K_SECTOR (0x00000010)
320
321#define MPI2_RAID_COMPAT_GENATTRIB_MEDIA_MASK (0x0000000C)
322#define MPI2_RAID_COMPAT_GENATTRIB_SOLID_STATE_DRIVE (0x00000008)
323#define MPI2_RAID_COMPAT_GENATTRIB_HARD_DISK_DRIVE (0x00000004)
324
325#define MPI2_RAID_COMPAT_GENATTRIB_PROTOCOL_MASK (0x00000003)
326#define MPI2_RAID_COMPAT_GENATTRIB_SAS_PROTOCOL (0x00000002)
327#define MPI2_RAID_COMPAT_GENATTRIB_SATA_PROTOCOL (0x00000001)
328
329/* RAID Action Reply ActionData union */
330typedef union _MPI2_RAID_ACTION_REPLY_DATA
331{
332 U32 Word[6];
333 MPI2_RAID_VOL_INDICATOR RaidVolumeIndicator;
334 U16 VolDevHandle;
335 U8 VolumeState;
336 U8 PhysDiskNum;
337 MPI2_RAID_COMPATIBILITY_RESULT_STRUCT RaidCompatibilityResult;
338} MPI2_RAID_ACTION_REPLY_DATA, MPI2_POINTER PTR_MPI2_RAID_ACTION_REPLY_DATA,
339 Mpi2RaidActionReplyData_t, MPI2_POINTER pMpi2RaidActionReplyData_t;
340
341/* use MPI2_RAIDVOL0_SETTING_ defines from mpi2_cnfg.h for MPI2_RAID_ACTION_CHANGE_VOL_WRITE_CACHE action */
342
343
344/* RAID Action Reply Message */
345typedef struct _MPI2_RAID_ACTION_REPLY
346{
347 U8 Action; /* 0x00 */
348 U8 Reserved1; /* 0x01 */
349 U8 MsgLength; /* 0x02 */
350 U8 Function; /* 0x03 */
351 U16 VolDevHandle; /* 0x04 */
352 U8 PhysDiskNum; /* 0x06 */
353 U8 MsgFlags; /* 0x07 */
354 U8 VP_ID; /* 0x08 */
355 U8 VF_ID; /* 0x09 */
356 U16 Reserved2; /* 0x0A */
357 U16 Reserved3; /* 0x0C */
358 U16 IOCStatus; /* 0x0E */
359 U32 IOCLogInfo; /* 0x10 */
360 MPI2_RAID_ACTION_REPLY_DATA ActionData; /* 0x14 */
361} MPI2_RAID_ACTION_REPLY, MPI2_POINTER PTR_MPI2_RAID_ACTION_REPLY,
362 Mpi2RaidActionReply_t, MPI2_POINTER pMpi2RaidActionReply_t;
363
364
365#endif
366
diff --git a/drivers/scsi/mpt2sas/mpi/mpi2_sas.h b/drivers/scsi/mpt2sas/mpi/mpi2_sas.h
deleted file mode 100644
index 45b6fa10b803..000000000000
--- a/drivers/scsi/mpt2sas/mpi/mpi2_sas.h
+++ /dev/null
@@ -1,288 +0,0 @@
1/*
2 * Copyright (c) 2000-2014 LSI Corporation.
3 *
4 *
5 * Name: mpi2_sas.h
6 * Title: MPI Serial Attached SCSI structures and definitions
7 * Creation Date: February 9, 2007
8 *
9 * mpi2_sas.h Version: 02.00.05
10 *
11 * Version History
12 * ---------------
13 *
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
17 * 06-26-07 02.00.01 Added Clear All Persistent Operation to SAS IO Unit
18 * Control Request.
19 * 10-02-08 02.00.02 Added Set IOC Parameter Operation to SAS IO Unit Control
20 * Request.
21 * 10-28-09 02.00.03 Changed the type of SGL in MPI2_SATA_PASSTHROUGH_REQUEST
22 * to MPI2_SGE_IO_UNION since it supports chained SGLs.
23 * 05-12-10 02.00.04 Modified some comments.
24 * 08-11-10 02.00.05 Added NCQ operations to SAS IO Unit Control.
25 * --------------------------------------------------------------------------
26 */
27
28#ifndef MPI2_SAS_H
29#define MPI2_SAS_H
30
31/*
32 * Values for SASStatus.
33 */
34#define MPI2_SASSTATUS_SUCCESS (0x00)
35#define MPI2_SASSTATUS_UNKNOWN_ERROR (0x01)
36#define MPI2_SASSTATUS_INVALID_FRAME (0x02)
37#define MPI2_SASSTATUS_UTC_BAD_DEST (0x03)
38#define MPI2_SASSTATUS_UTC_BREAK_RECEIVED (0x04)
39#define MPI2_SASSTATUS_UTC_CONNECT_RATE_NOT_SUPPORTED (0x05)
40#define MPI2_SASSTATUS_UTC_PORT_LAYER_REQUEST (0x06)
41#define MPI2_SASSTATUS_UTC_PROTOCOL_NOT_SUPPORTED (0x07)
42#define MPI2_SASSTATUS_UTC_STP_RESOURCES_BUSY (0x08)
43#define MPI2_SASSTATUS_UTC_WRONG_DESTINATION (0x09)
44#define MPI2_SASSTATUS_SHORT_INFORMATION_UNIT (0x0A)
45#define MPI2_SASSTATUS_LONG_INFORMATION_UNIT (0x0B)
46#define MPI2_SASSTATUS_XFER_RDY_INCORRECT_WRITE_DATA (0x0C)
47#define MPI2_SASSTATUS_XFER_RDY_REQUEST_OFFSET_ERROR (0x0D)
48#define MPI2_SASSTATUS_XFER_RDY_NOT_EXPECTED (0x0E)
49#define MPI2_SASSTATUS_DATA_INCORRECT_DATA_LENGTH (0x0F)
50#define MPI2_SASSTATUS_DATA_TOO_MUCH_READ_DATA (0x10)
51#define MPI2_SASSTATUS_DATA_OFFSET_ERROR (0x11)
52#define MPI2_SASSTATUS_SDSF_NAK_RECEIVED (0x12)
53#define MPI2_SASSTATUS_SDSF_CONNECTION_FAILED (0x13)
54#define MPI2_SASSTATUS_INITIATOR_RESPONSE_TIMEOUT (0x14)
55
56
57/*
58 * Values for the SAS DeviceInfo field used in SAS Device Status Change Event
59 * data and SAS Configuration pages.
60 */
61#define MPI2_SAS_DEVICE_INFO_SEP (0x00004000)
62#define MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE (0x00002000)
63#define MPI2_SAS_DEVICE_INFO_LSI_DEVICE (0x00001000)
64#define MPI2_SAS_DEVICE_INFO_DIRECT_ATTACH (0x00000800)
65#define MPI2_SAS_DEVICE_INFO_SSP_TARGET (0x00000400)
66#define MPI2_SAS_DEVICE_INFO_STP_TARGET (0x00000200)
67#define MPI2_SAS_DEVICE_INFO_SMP_TARGET (0x00000100)
68#define MPI2_SAS_DEVICE_INFO_SATA_DEVICE (0x00000080)
69#define MPI2_SAS_DEVICE_INFO_SSP_INITIATOR (0x00000040)
70#define MPI2_SAS_DEVICE_INFO_STP_INITIATOR (0x00000020)
71#define MPI2_SAS_DEVICE_INFO_SMP_INITIATOR (0x00000010)
72#define MPI2_SAS_DEVICE_INFO_SATA_HOST (0x00000008)
73
74#define MPI2_SAS_DEVICE_INFO_MASK_DEVICE_TYPE (0x00000007)
75#define MPI2_SAS_DEVICE_INFO_NO_DEVICE (0x00000000)
76#define MPI2_SAS_DEVICE_INFO_END_DEVICE (0x00000001)
77#define MPI2_SAS_DEVICE_INFO_EDGE_EXPANDER (0x00000002)
78#define MPI2_SAS_DEVICE_INFO_FANOUT_EXPANDER (0x00000003)
79
80
81/*****************************************************************************
82*
83* SAS Messages
84*
85*****************************************************************************/
86
87/****************************************************************************
88* SMP Passthrough messages
89****************************************************************************/
90
91/* SMP Passthrough Request Message */
92typedef struct _MPI2_SMP_PASSTHROUGH_REQUEST
93{
94 U8 PassthroughFlags; /* 0x00 */
95 U8 PhysicalPort; /* 0x01 */
96 U8 ChainOffset; /* 0x02 */
97 U8 Function; /* 0x03 */
98 U16 RequestDataLength; /* 0x04 */
99 U8 SGLFlags; /* 0x06 */
100 U8 MsgFlags; /* 0x07 */
101 U8 VP_ID; /* 0x08 */
102 U8 VF_ID; /* 0x09 */
103 U16 Reserved1; /* 0x0A */
104 U32 Reserved2; /* 0x0C */
105 U64 SASAddress; /* 0x10 */
106 U32 Reserved3; /* 0x18 */
107 U32 Reserved4; /* 0x1C */
108 MPI2_SIMPLE_SGE_UNION SGL; /* 0x20 */
109} MPI2_SMP_PASSTHROUGH_REQUEST, MPI2_POINTER PTR_MPI2_SMP_PASSTHROUGH_REQUEST,
110 Mpi2SmpPassthroughRequest_t, MPI2_POINTER pMpi2SmpPassthroughRequest_t;
111
112/* values for PassthroughFlags field */
113#define MPI2_SMP_PT_REQ_PT_FLAGS_IMMEDIATE (0x80)
114
115/* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
116
117
118/* SMP Passthrough Reply Message */
119typedef struct _MPI2_SMP_PASSTHROUGH_REPLY
120{
121 U8 PassthroughFlags; /* 0x00 */
122 U8 PhysicalPort; /* 0x01 */
123 U8 MsgLength; /* 0x02 */
124 U8 Function; /* 0x03 */
125 U16 ResponseDataLength; /* 0x04 */
126 U8 SGLFlags; /* 0x06 */
127 U8 MsgFlags; /* 0x07 */
128 U8 VP_ID; /* 0x08 */
129 U8 VF_ID; /* 0x09 */
130 U16 Reserved1; /* 0x0A */
131 U8 Reserved2; /* 0x0C */
132 U8 SASStatus; /* 0x0D */
133 U16 IOCStatus; /* 0x0E */
134 U32 IOCLogInfo; /* 0x10 */
135 U32 Reserved3; /* 0x14 */
136 U8 ResponseData[4]; /* 0x18 */
137} MPI2_SMP_PASSTHROUGH_REPLY, MPI2_POINTER PTR_MPI2_SMP_PASSTHROUGH_REPLY,
138 Mpi2SmpPassthroughReply_t, MPI2_POINTER pMpi2SmpPassthroughReply_t;
139
140/* values for PassthroughFlags field */
141#define MPI2_SMP_PT_REPLY_PT_FLAGS_IMMEDIATE (0x80)
142
143/* values for SASStatus field are at the top of this file */
144
145
146/****************************************************************************
147* SATA Passthrough messages
148****************************************************************************/
149
150/* SATA Passthrough Request Message */
151typedef struct _MPI2_SATA_PASSTHROUGH_REQUEST
152{
153 U16 DevHandle; /* 0x00 */
154 U8 ChainOffset; /* 0x02 */
155 U8 Function; /* 0x03 */
156 U16 PassthroughFlags; /* 0x04 */
157 U8 SGLFlags; /* 0x06 */
158 U8 MsgFlags; /* 0x07 */
159 U8 VP_ID; /* 0x08 */
160 U8 VF_ID; /* 0x09 */
161 U16 Reserved1; /* 0x0A */
162 U32 Reserved2; /* 0x0C */
163 U32 Reserved3; /* 0x10 */
164 U32 Reserved4; /* 0x14 */
165 U32 DataLength; /* 0x18 */
166 U8 CommandFIS[20]; /* 0x1C */
167 MPI2_SGE_IO_UNION SGL; /* 0x30 */
168} MPI2_SATA_PASSTHROUGH_REQUEST, MPI2_POINTER PTR_MPI2_SATA_PASSTHROUGH_REQUEST,
169 Mpi2SataPassthroughRequest_t, MPI2_POINTER pMpi2SataPassthroughRequest_t;
170
171/* values for PassthroughFlags field */
172#define MPI2_SATA_PT_REQ_PT_FLAGS_EXECUTE_DIAG (0x0100)
173#define MPI2_SATA_PT_REQ_PT_FLAGS_DMA (0x0020)
174#define MPI2_SATA_PT_REQ_PT_FLAGS_PIO (0x0010)
175#define MPI2_SATA_PT_REQ_PT_FLAGS_UNSPECIFIED_VU (0x0004)
176#define MPI2_SATA_PT_REQ_PT_FLAGS_WRITE (0x0002)
177#define MPI2_SATA_PT_REQ_PT_FLAGS_READ (0x0001)
178
179/* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
180
181
182/* SATA Passthrough Reply Message */
183typedef struct _MPI2_SATA_PASSTHROUGH_REPLY
184{
185 U16 DevHandle; /* 0x00 */
186 U8 MsgLength; /* 0x02 */
187 U8 Function; /* 0x03 */
188 U16 PassthroughFlags; /* 0x04 */
189 U8 SGLFlags; /* 0x06 */
190 U8 MsgFlags; /* 0x07 */
191 U8 VP_ID; /* 0x08 */
192 U8 VF_ID; /* 0x09 */
193 U16 Reserved1; /* 0x0A */
194 U8 Reserved2; /* 0x0C */
195 U8 SASStatus; /* 0x0D */
196 U16 IOCStatus; /* 0x0E */
197 U32 IOCLogInfo; /* 0x10 */
198 U8 StatusFIS[20]; /* 0x14 */
199 U32 StatusControlRegisters; /* 0x28 */
200 U32 TransferCount; /* 0x2C */
201} MPI2_SATA_PASSTHROUGH_REPLY, MPI2_POINTER PTR_MPI2_SATA_PASSTHROUGH_REPLY,
202 Mpi2SataPassthroughReply_t, MPI2_POINTER pMpi2SataPassthroughReply_t;
203
204/* values for SASStatus field are at the top of this file */
205
206
207/****************************************************************************
208* SAS IO Unit Control messages
209****************************************************************************/
210
211/* SAS IO Unit Control Request Message */
212typedef struct _MPI2_SAS_IOUNIT_CONTROL_REQUEST
213{
214 U8 Operation; /* 0x00 */
215 U8 Reserved1; /* 0x01 */
216 U8 ChainOffset; /* 0x02 */
217 U8 Function; /* 0x03 */
218 U16 DevHandle; /* 0x04 */
219 U8 IOCParameter; /* 0x06 */
220 U8 MsgFlags; /* 0x07 */
221 U8 VP_ID; /* 0x08 */
222 U8 VF_ID; /* 0x09 */
223 U16 Reserved3; /* 0x0A */
224 U16 Reserved4; /* 0x0C */
225 U8 PhyNum; /* 0x0E */
226 U8 PrimFlags; /* 0x0F */
227 U32 Primitive; /* 0x10 */
228 U8 LookupMethod; /* 0x14 */
229 U8 Reserved5; /* 0x15 */
230 U16 SlotNumber; /* 0x16 */
231 U64 LookupAddress; /* 0x18 */
232 U32 IOCParameterValue; /* 0x20 */
233 U32 Reserved7; /* 0x24 */
234 U32 Reserved8; /* 0x28 */
235} MPI2_SAS_IOUNIT_CONTROL_REQUEST,
236 MPI2_POINTER PTR_MPI2_SAS_IOUNIT_CONTROL_REQUEST,
237 Mpi2SasIoUnitControlRequest_t, MPI2_POINTER pMpi2SasIoUnitControlRequest_t;
238
239/* values for the Operation field */
240#define MPI2_SAS_OP_CLEAR_ALL_PERSISTENT (0x02)
241#define MPI2_SAS_OP_PHY_LINK_RESET (0x06)
242#define MPI2_SAS_OP_PHY_HARD_RESET (0x07)
243#define MPI2_SAS_OP_PHY_CLEAR_ERROR_LOG (0x08)
244#define MPI2_SAS_OP_SEND_PRIMITIVE (0x0A)
245#define MPI2_SAS_OP_FORCE_FULL_DISCOVERY (0x0B)
246#define MPI2_SAS_OP_TRANSMIT_PORT_SELECT_SIGNAL (0x0C)
247#define MPI2_SAS_OP_REMOVE_DEVICE (0x0D)
248#define MPI2_SAS_OP_LOOKUP_MAPPING (0x0E)
249#define MPI2_SAS_OP_SET_IOC_PARAMETER (0x0F)
250#define MPI2_SAS_OP_DEV_ENABLE_NCQ (0x14)
251#define MPI2_SAS_OP_DEV_DISABLE_NCQ (0x15)
252#define MPI2_SAS_OP_PRODUCT_SPECIFIC_MIN (0x80)
253
254/* values for the PrimFlags field */
255#define MPI2_SAS_PRIMFLAGS_SINGLE (0x08)
256#define MPI2_SAS_PRIMFLAGS_TRIPLE (0x02)
257#define MPI2_SAS_PRIMFLAGS_REDUNDANT (0x01)
258
259/* values for the LookupMethod field */
260#define MPI2_SAS_LOOKUP_METHOD_SAS_ADDRESS (0x01)
261#define MPI2_SAS_LOOKUP_METHOD_SAS_ENCLOSURE_SLOT (0x02)
262#define MPI2_SAS_LOOKUP_METHOD_SAS_DEVICE_NAME (0x03)
263
264
265/* SAS IO Unit Control Reply Message */
266typedef struct _MPI2_SAS_IOUNIT_CONTROL_REPLY
267{
268 U8 Operation; /* 0x00 */
269 U8 Reserved1; /* 0x01 */
270 U8 MsgLength; /* 0x02 */
271 U8 Function; /* 0x03 */
272 U16 DevHandle; /* 0x04 */
273 U8 IOCParameter; /* 0x06 */
274 U8 MsgFlags; /* 0x07 */
275 U8 VP_ID; /* 0x08 */
276 U8 VF_ID; /* 0x09 */
277 U16 Reserved3; /* 0x0A */
278 U16 Reserved4; /* 0x0C */
279 U16 IOCStatus; /* 0x0E */
280 U32 IOCLogInfo; /* 0x10 */
281} MPI2_SAS_IOUNIT_CONTROL_REPLY,
282 MPI2_POINTER PTR_MPI2_SAS_IOUNIT_CONTROL_REPLY,
283 Mpi2SasIoUnitControlReply_t, MPI2_POINTER pMpi2SasIoUnitControlReply_t;
284
285
286#endif
287
288
diff --git a/drivers/scsi/mpt2sas/mpi/mpi2_tool.h b/drivers/scsi/mpt2sas/mpi/mpi2_tool.h
deleted file mode 100644
index 659b8ac83ceb..000000000000
--- a/drivers/scsi/mpt2sas/mpi/mpi2_tool.h
+++ /dev/null
@@ -1,481 +0,0 @@
1/*
2 * Copyright (c) 2000-2014 LSI Corporation.
3 *
4 *
5 * Name: mpi2_tool.h
6 * Title: MPI diagnostic tool structures and definitions
7 * Creation Date: March 26, 2007
8 *
9 * mpi2_tool.h Version: 02.00.12
10 *
11 * Version History
12 * ---------------
13 *
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
17 * 12-18-07 02.00.01 Added Diagnostic Buffer Post and Diagnostic Release
18 * structures and defines.
19 * 02-29-08 02.00.02 Modified various names to make them 32-character unique.
20 * 05-06-09 02.00.03 Added ISTWI Read Write Tool and Diagnostic CLI Tool.
21 * 07-30-09 02.00.04 Added ExtendedType field to DiagnosticBufferPost request
22 * and reply messages.
23 * Added MPI2_DIAG_BUF_TYPE_EXTENDED.
24 * Incremented MPI2_DIAG_BUF_TYPE_COUNT.
25 * 05-12-10 02.00.05 Added Diagnostic Data Upload tool.
26 * 08-11-10 02.00.06 Added defines that were missing for Diagnostic Buffer
27 * Post Request.
28 * 05-25-11 02.00.07 Added Flags field and related defines to
29 * MPI2_TOOLBOX_ISTWI_READ_WRITE_REQUEST.
30 * 07-26-12 02.00.10 Modified MPI2_TOOLBOX_DIAGNOSTIC_CLI_REQUEST so that
31 * it uses MPI Chain SGE as well as MPI Simple SGE.
32 * 08-19-13 02.00.11 Added MPI2_TOOLBOX_TEXT_DISPLAY_TOOL and related info.
33 * 01-08-14 02.00.12 Added MPI2_TOOLBOX_CLEAN_BIT26_PRODUCT_SPECIFIC.
34 * --------------------------------------------------------------------------
35 */
36
37#ifndef MPI2_TOOL_H
38#define MPI2_TOOL_H
39
40/*****************************************************************************
41*
42* Toolbox Messages
43*
44*****************************************************************************/
45
46/* defines for the Tools */
47#define MPI2_TOOLBOX_CLEAN_TOOL (0x00)
48#define MPI2_TOOLBOX_MEMORY_MOVE_TOOL (0x01)
49#define MPI2_TOOLBOX_DIAG_DATA_UPLOAD_TOOL (0x02)
50#define MPI2_TOOLBOX_ISTWI_READ_WRITE_TOOL (0x03)
51#define MPI2_TOOLBOX_BEACON_TOOL (0x05)
52#define MPI2_TOOLBOX_DIAGNOSTIC_CLI_TOOL (0x06)
53#define MPI2_TOOLBOX_TEXT_DISPLAY_TOOL (0x07)
54
55
56/****************************************************************************
57* Toolbox reply
58****************************************************************************/
59
60typedef struct _MPI2_TOOLBOX_REPLY
61{
62 U8 Tool; /* 0x00 */
63 U8 Reserved1; /* 0x01 */
64 U8 MsgLength; /* 0x02 */
65 U8 Function; /* 0x03 */
66 U16 Reserved2; /* 0x04 */
67 U8 Reserved3; /* 0x06 */
68 U8 MsgFlags; /* 0x07 */
69 U8 VP_ID; /* 0x08 */
70 U8 VF_ID; /* 0x09 */
71 U16 Reserved4; /* 0x0A */
72 U16 Reserved5; /* 0x0C */
73 U16 IOCStatus; /* 0x0E */
74 U32 IOCLogInfo; /* 0x10 */
75} MPI2_TOOLBOX_REPLY, MPI2_POINTER PTR_MPI2_TOOLBOX_REPLY,
76 Mpi2ToolboxReply_t, MPI2_POINTER pMpi2ToolboxReply_t;
77
78
79/****************************************************************************
80* Toolbox Clean Tool request
81****************************************************************************/
82
83typedef struct _MPI2_TOOLBOX_CLEAN_REQUEST
84{
85 U8 Tool; /* 0x00 */
86 U8 Reserved1; /* 0x01 */
87 U8 ChainOffset; /* 0x02 */
88 U8 Function; /* 0x03 */
89 U16 Reserved2; /* 0x04 */
90 U8 Reserved3; /* 0x06 */
91 U8 MsgFlags; /* 0x07 */
92 U8 VP_ID; /* 0x08 */
93 U8 VF_ID; /* 0x09 */
94 U16 Reserved4; /* 0x0A */
95 U32 Flags; /* 0x0C */
96 } MPI2_TOOLBOX_CLEAN_REQUEST, MPI2_POINTER PTR_MPI2_TOOLBOX_CLEAN_REQUEST,
97 Mpi2ToolboxCleanRequest_t, MPI2_POINTER pMpi2ToolboxCleanRequest_t;
98
99/* values for the Flags field */
100#define MPI2_TOOLBOX_CLEAN_BOOT_SERVICES (0x80000000)
101#define MPI2_TOOLBOX_CLEAN_PERSIST_MANUFACT_PAGES (0x40000000)
102#define MPI2_TOOLBOX_CLEAN_OTHER_PERSIST_PAGES (0x20000000)
103#define MPI2_TOOLBOX_CLEAN_FW_CURRENT (0x10000000)
104#define MPI2_TOOLBOX_CLEAN_FW_BACKUP (0x08000000)
105#define MPI2_TOOLBOX_CLEAN_BIT26_PRODUCT_SPECIFIC (0x04000000)
106#define MPI2_TOOLBOX_CLEAN_MEGARAID (0x02000000)
107#define MPI2_TOOLBOX_CLEAN_INITIALIZATION (0x01000000)
108#define MPI2_TOOLBOX_CLEAN_FLASH (0x00000004)
109#define MPI2_TOOLBOX_CLEAN_SEEPROM (0x00000002)
110#define MPI2_TOOLBOX_CLEAN_NVSRAM (0x00000001)
111
112
113/****************************************************************************
114* Toolbox Memory Move request
115****************************************************************************/
116
117typedef struct _MPI2_TOOLBOX_MEM_MOVE_REQUEST {
118 U8 Tool; /* 0x00 */
119 U8 Reserved1; /* 0x01 */
120 U8 ChainOffset; /* 0x02 */
121 U8 Function; /* 0x03 */
122 U16 Reserved2; /* 0x04 */
123 U8 Reserved3; /* 0x06 */
124 U8 MsgFlags; /* 0x07 */
125 U8 VP_ID; /* 0x08 */
126 U8 VF_ID; /* 0x09 */
127 U16 Reserved4; /* 0x0A */
128 MPI2_SGE_SIMPLE_UNION SGL; /* 0x0C */
129} MPI2_TOOLBOX_MEM_MOVE_REQUEST, MPI2_POINTER PTR_MPI2_TOOLBOX_MEM_MOVE_REQUEST,
130 Mpi2ToolboxMemMoveRequest_t, MPI2_POINTER pMpi2ToolboxMemMoveRequest_t;
131
132
133/****************************************************************************
134* Toolbox Diagnostic Data Upload request
135****************************************************************************/
136
137typedef struct _MPI2_TOOLBOX_DIAG_DATA_UPLOAD_REQUEST {
138 U8 Tool; /* 0x00 */
139 U8 Reserved1; /* 0x01 */
140 U8 ChainOffset; /* 0x02 */
141 U8 Function; /* 0x03 */
142 U16 Reserved2; /* 0x04 */
143 U8 Reserved3; /* 0x06 */
144 U8 MsgFlags; /* 0x07 */
145 U8 VP_ID; /* 0x08 */
146 U8 VF_ID; /* 0x09 */
147 U16 Reserved4; /* 0x0A */
148 U8 SGLFlags; /* 0x0C */
149 U8 Reserved5; /* 0x0D */
150 U16 Reserved6; /* 0x0E */
151 U32 Flags; /* 0x10 */
152 U32 DataLength; /* 0x14 */
153 MPI2_SGE_SIMPLE_UNION SGL; /* 0x18 */
154} MPI2_TOOLBOX_DIAG_DATA_UPLOAD_REQUEST,
155MPI2_POINTER PTR_MPI2_TOOLBOX_DIAG_DATA_UPLOAD_REQUEST,
156Mpi2ToolboxDiagDataUploadRequest_t,
157MPI2_POINTER pMpi2ToolboxDiagDataUploadRequest_t;
158
159/* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
160
161
162typedef struct _MPI2_DIAG_DATA_UPLOAD_HEADER {
163 U32 DiagDataLength; /* 00h */
164 U8 FormatCode; /* 04h */
165 U8 Reserved1; /* 05h */
166 U16 Reserved2; /* 06h */
167} MPI2_DIAG_DATA_UPLOAD_HEADER, MPI2_POINTER PTR_MPI2_DIAG_DATA_UPLOAD_HEADER,
168Mpi2DiagDataUploadHeader_t, MPI2_POINTER pMpi2DiagDataUploadHeader_t;
169
170
171/****************************************************************************
172* Toolbox ISTWI Read Write Tool
173****************************************************************************/
174
175/* Toolbox ISTWI Read Write Tool request message */
176typedef struct _MPI2_TOOLBOX_ISTWI_READ_WRITE_REQUEST {
177 U8 Tool; /* 0x00 */
178 U8 Reserved1; /* 0x01 */
179 U8 ChainOffset; /* 0x02 */
180 U8 Function; /* 0x03 */
181 U16 Reserved2; /* 0x04 */
182 U8 Reserved3; /* 0x06 */
183 U8 MsgFlags; /* 0x07 */
184 U8 VP_ID; /* 0x08 */
185 U8 VF_ID; /* 0x09 */
186 U16 Reserved4; /* 0x0A */
187 U32 Reserved5; /* 0x0C */
188 U32 Reserved6; /* 0x10 */
189 U8 DevIndex; /* 0x14 */
190 U8 Action; /* 0x15 */
191 U8 SGLFlags; /* 0x16 */
192 U8 Flags; /* 0x17 */
193 U16 TxDataLength; /* 0x18 */
194 U16 RxDataLength; /* 0x1A */
195 U32 Reserved8; /* 0x1C */
196 U32 Reserved9; /* 0x20 */
197 U32 Reserved10; /* 0x24 */
198 U32 Reserved11; /* 0x28 */
199 U32 Reserved12; /* 0x2C */
200 MPI2_SGE_SIMPLE_UNION SGL; /* 0x30 */
201} MPI2_TOOLBOX_ISTWI_READ_WRITE_REQUEST,
202 MPI2_POINTER PTR_MPI2_TOOLBOX_ISTWI_READ_WRITE_REQUEST,
203 Mpi2ToolboxIstwiReadWriteRequest_t,
204 MPI2_POINTER pMpi2ToolboxIstwiReadWriteRequest_t;
205
206/* values for the Action field */
207#define MPI2_TOOL_ISTWI_ACTION_READ_DATA (0x01)
208#define MPI2_TOOL_ISTWI_ACTION_WRITE_DATA (0x02)
209#define MPI2_TOOL_ISTWI_ACTION_SEQUENCE (0x03)
210#define MPI2_TOOL_ISTWI_ACTION_RESERVE_BUS (0x10)
211#define MPI2_TOOL_ISTWI_ACTION_RELEASE_BUS (0x11)
212#define MPI2_TOOL_ISTWI_ACTION_RESET (0x12)
213
214/* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
215
216/* values for the Flags field */
217#define MPI2_TOOL_ISTWI_FLAG_AUTO_RESERVE_RELEASE (0x80)
218#define MPI2_TOOL_ISTWI_FLAG_PAGE_ADDR_MASK (0x07)
219
220/* Toolbox ISTWI Read Write Tool reply message */
221typedef struct _MPI2_TOOLBOX_ISTWI_REPLY {
222 U8 Tool; /* 0x00 */
223 U8 Reserved1; /* 0x01 */
224 U8 MsgLength; /* 0x02 */
225 U8 Function; /* 0x03 */
226 U16 Reserved2; /* 0x04 */
227 U8 Reserved3; /* 0x06 */
228 U8 MsgFlags; /* 0x07 */
229 U8 VP_ID; /* 0x08 */
230 U8 VF_ID; /* 0x09 */
231 U16 Reserved4; /* 0x0A */
232 U16 Reserved5; /* 0x0C */
233 U16 IOCStatus; /* 0x0E */
234 U32 IOCLogInfo; /* 0x10 */
235 U8 DevIndex; /* 0x14 */
236 U8 Action; /* 0x15 */
237 U8 IstwiStatus; /* 0x16 */
238 U8 Reserved6; /* 0x17 */
239 U16 TxDataCount; /* 0x18 */
240 U16 RxDataCount; /* 0x1A */
241} MPI2_TOOLBOX_ISTWI_REPLY, MPI2_POINTER PTR_MPI2_TOOLBOX_ISTWI_REPLY,
242 Mpi2ToolboxIstwiReply_t, MPI2_POINTER pMpi2ToolboxIstwiReply_t;
243
244
245/****************************************************************************
246* Toolbox Beacon Tool request
247****************************************************************************/
248
249typedef struct _MPI2_TOOLBOX_BEACON_REQUEST
250{
251 U8 Tool; /* 0x00 */
252 U8 Reserved1; /* 0x01 */
253 U8 ChainOffset; /* 0x02 */
254 U8 Function; /* 0x03 */
255 U16 Reserved2; /* 0x04 */
256 U8 Reserved3; /* 0x06 */
257 U8 MsgFlags; /* 0x07 */
258 U8 VP_ID; /* 0x08 */
259 U8 VF_ID; /* 0x09 */
260 U16 Reserved4; /* 0x0A */
261 U8 Reserved5; /* 0x0C */
262 U8 PhysicalPort; /* 0x0D */
263 U8 Reserved6; /* 0x0E */
264 U8 Flags; /* 0x0F */
265} MPI2_TOOLBOX_BEACON_REQUEST, MPI2_POINTER PTR_MPI2_TOOLBOX_BEACON_REQUEST,
266 Mpi2ToolboxBeaconRequest_t, MPI2_POINTER pMpi2ToolboxBeaconRequest_t;
267
268/* values for the Flags field */
269#define MPI2_TOOLBOX_FLAGS_BEACONMODE_OFF (0x00)
270#define MPI2_TOOLBOX_FLAGS_BEACONMODE_ON (0x01)
271
272
273/****************************************************************************
274* Toolbox Diagnostic CLI Tool
275****************************************************************************/
276
277#define MPI2_TOOLBOX_DIAG_CLI_CMD_LENGTH (0x5C)
278
279/* MPI v2.0 Toolbox Diagnostic CLI Tool request message */
280typedef struct _MPI2_TOOLBOX_DIAGNOSTIC_CLI_REQUEST {
281 U8 Tool; /* 0x00 */
282 U8 Reserved1; /* 0x01 */
283 U8 ChainOffset; /* 0x02 */
284 U8 Function; /* 0x03 */
285 U16 Reserved2; /* 0x04 */
286 U8 Reserved3; /* 0x06 */
287 U8 MsgFlags; /* 0x07 */
288 U8 VP_ID; /* 0x08 */
289 U8 VF_ID; /* 0x09 */
290 U16 Reserved4; /* 0x0A */
291 U8 SGLFlags; /* 0x0C */
292 U8 Reserved5; /* 0x0D */
293 U16 Reserved6; /* 0x0E */
294 U32 DataLength; /* 0x10 */
295 U8 DiagnosticCliCommand
296 [MPI2_TOOLBOX_DIAG_CLI_CMD_LENGTH]; /* 0x14 */
297 MPI2_MPI_SGE_IO_UNION SGL; /* 0x70 */
298} MPI2_TOOLBOX_DIAGNOSTIC_CLI_REQUEST,
299 MPI2_POINTER PTR_MPI2_TOOLBOX_DIAGNOSTIC_CLI_REQUEST,
300 Mpi2ToolboxDiagnosticCliRequest_t,
301 MPI2_POINTER pMpi2ToolboxDiagnosticCliRequest_t;
302
303/* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
304
305
306/* Toolbox Diagnostic CLI Tool reply message */
307typedef struct _MPI2_TOOLBOX_DIAGNOSTIC_CLI_REPLY {
308 U8 Tool; /* 0x00 */
309 U8 Reserved1; /* 0x01 */
310 U8 MsgLength; /* 0x02 */
311 U8 Function; /* 0x03 */
312 U16 Reserved2; /* 0x04 */
313 U8 Reserved3; /* 0x06 */
314 U8 MsgFlags; /* 0x07 */
315 U8 VP_ID; /* 0x08 */
316 U8 VF_ID; /* 0x09 */
317 U16 Reserved4; /* 0x0A */
318 U16 Reserved5; /* 0x0C */
319 U16 IOCStatus; /* 0x0E */
320 U32 IOCLogInfo; /* 0x10 */
321 U32 ReturnedDataLength; /* 0x14 */
322} MPI2_TOOLBOX_DIAGNOSTIC_CLI_REPLY,
323 MPI2_POINTER PTR_MPI2_TOOLBOX_DIAG_CLI_REPLY,
324 Mpi2ToolboxDiagnosticCliReply_t,
325 MPI2_POINTER pMpi2ToolboxDiagnosticCliReply_t;
326
327
328/****************************************************************************
329* Toolbox Console Text Display Tool
330****************************************************************************/
331
332/* Toolbox Console Text Display Tool request message */
333typedef struct _MPI2_TOOLBOX_TEXT_DISPLAY_REQUEST {
334 U8 Tool; /* 0x00 */
335 U8 Reserved1; /* 0x01 */
336 U8 ChainOffset; /* 0x02 */
337 U8 Function; /* 0x03 */
338 U16 Reserved2; /* 0x04 */
339 U8 Reserved3; /* 0x06 */
340 U8 MsgFlags; /* 0x07 */
341 U8 VP_ID; /* 0x08 */
342 U8 VF_ID; /* 0x09 */
343 U16 Reserved4; /* 0x0A */
344 U8 Console; /* 0x0C */
345 U8 Flags; /* 0x0D */
346 U16 Reserved6; /* 0x0E */
347 U8 TextToDisplay[4]; /* 0x10 */
348} MPI2_TOOLBOX_TEXT_DISPLAY_REQUEST,
349MPI2_POINTER PTR_MPI2_TOOLBOX_TEXT_DISPLAY_REQUEST,
350Mpi2ToolboxTextDisplayRequest_t,
351MPI2_POINTER pMpi2ToolboxTextDisplayRequest_t;
352
353/* defines for the Console field */
354#define MPI2_TOOLBOX_CONSOLE_TYPE_MASK (0xF0)
355#define MPI2_TOOLBOX_CONSOLE_TYPE_DEFAULT (0x00)
356#define MPI2_TOOLBOX_CONSOLE_TYPE_UART (0x10)
357#define MPI2_TOOLBOX_CONSOLE_TYPE_ETHERNET (0x20)
358
359#define MPI2_TOOLBOX_CONSOLE_NUMBER_MASK (0x0F)
360
361/* defines for the Flags field */
362#define MPI2_TOOLBOX_CONSOLE_FLAG_TIMESTAMP (0x01)
363
364
365
366/*****************************************************************************
367*
368* Diagnostic Buffer Messages
369*
370*****************************************************************************/
371
372
373/****************************************************************************
374* Diagnostic Buffer Post request
375****************************************************************************/
376
377typedef struct _MPI2_DIAG_BUFFER_POST_REQUEST
378{
379 U8 ExtendedType; /* 0x00 */
380 U8 BufferType; /* 0x01 */
381 U8 ChainOffset; /* 0x02 */
382 U8 Function; /* 0x03 */
383 U16 Reserved2; /* 0x04 */
384 U8 Reserved3; /* 0x06 */
385 U8 MsgFlags; /* 0x07 */
386 U8 VP_ID; /* 0x08 */
387 U8 VF_ID; /* 0x09 */
388 U16 Reserved4; /* 0x0A */
389 U64 BufferAddress; /* 0x0C */
390 U32 BufferLength; /* 0x14 */
391 U32 Reserved5; /* 0x18 */
392 U32 Reserved6; /* 0x1C */
393 U32 Flags; /* 0x20 */
394 U32 ProductSpecific[23]; /* 0x24 */
395} MPI2_DIAG_BUFFER_POST_REQUEST, MPI2_POINTER PTR_MPI2_DIAG_BUFFER_POST_REQUEST,
396 Mpi2DiagBufferPostRequest_t, MPI2_POINTER pMpi2DiagBufferPostRequest_t;
397
398/* values for the ExtendedType field */
399#define MPI2_DIAG_EXTENDED_TYPE_UTILIZATION (0x02)
400
401/* values for the BufferType field */
402#define MPI2_DIAG_BUF_TYPE_TRACE (0x00)
403#define MPI2_DIAG_BUF_TYPE_SNAPSHOT (0x01)
404#define MPI2_DIAG_BUF_TYPE_EXTENDED (0x02)
405/* count of the number of buffer types */
406#define MPI2_DIAG_BUF_TYPE_COUNT (0x03)
407
408/* values for the Flags field */
409#define MPI2_DIAG_BUF_FLAG_RELEASE_ON_FULL (0x00000002)
410#define MPI2_DIAG_BUF_FLAG_IMMEDIATE_RELEASE (0x00000001)
411
412
413/****************************************************************************
414* Diagnostic Buffer Post reply
415****************************************************************************/
416
417typedef struct _MPI2_DIAG_BUFFER_POST_REPLY
418{
419 U8 ExtendedType; /* 0x00 */
420 U8 BufferType; /* 0x01 */
421 U8 MsgLength; /* 0x02 */
422 U8 Function; /* 0x03 */
423 U16 Reserved2; /* 0x04 */
424 U8 Reserved3; /* 0x06 */
425 U8 MsgFlags; /* 0x07 */
426 U8 VP_ID; /* 0x08 */
427 U8 VF_ID; /* 0x09 */
428 U16 Reserved4; /* 0x0A */
429 U16 Reserved5; /* 0x0C */
430 U16 IOCStatus; /* 0x0E */
431 U32 IOCLogInfo; /* 0x10 */
432 U32 TransferLength; /* 0x14 */
433} MPI2_DIAG_BUFFER_POST_REPLY, MPI2_POINTER PTR_MPI2_DIAG_BUFFER_POST_REPLY,
434 Mpi2DiagBufferPostReply_t, MPI2_POINTER pMpi2DiagBufferPostReply_t;
435
436
437/****************************************************************************
438* Diagnostic Release request
439****************************************************************************/
440
441typedef struct _MPI2_DIAG_RELEASE_REQUEST
442{
443 U8 Reserved1; /* 0x00 */
444 U8 BufferType; /* 0x01 */
445 U8 ChainOffset; /* 0x02 */
446 U8 Function; /* 0x03 */
447 U16 Reserved2; /* 0x04 */
448 U8 Reserved3; /* 0x06 */
449 U8 MsgFlags; /* 0x07 */
450 U8 VP_ID; /* 0x08 */
451 U8 VF_ID; /* 0x09 */
452 U16 Reserved4; /* 0x0A */
453} MPI2_DIAG_RELEASE_REQUEST, MPI2_POINTER PTR_MPI2_DIAG_RELEASE_REQUEST,
454 Mpi2DiagReleaseRequest_t, MPI2_POINTER pMpi2DiagReleaseRequest_t;
455
456
457/****************************************************************************
458* Diagnostic Buffer Post reply
459****************************************************************************/
460
461typedef struct _MPI2_DIAG_RELEASE_REPLY
462{
463 U8 Reserved1; /* 0x00 */
464 U8 BufferType; /* 0x01 */
465 U8 MsgLength; /* 0x02 */
466 U8 Function; /* 0x03 */
467 U16 Reserved2; /* 0x04 */
468 U8 Reserved3; /* 0x06 */
469 U8 MsgFlags; /* 0x07 */
470 U8 VP_ID; /* 0x08 */
471 U8 VF_ID; /* 0x09 */
472 U16 Reserved4; /* 0x0A */
473 U16 Reserved5; /* 0x0C */
474 U16 IOCStatus; /* 0x0E */
475 U32 IOCLogInfo; /* 0x10 */
476} MPI2_DIAG_RELEASE_REPLY, MPI2_POINTER PTR_MPI2_DIAG_RELEASE_REPLY,
477 Mpi2DiagReleaseReply_t, MPI2_POINTER pMpi2DiagReleaseReply_t;
478
479
480#endif
481
diff --git a/drivers/scsi/mpt2sas/mpi/mpi2_type.h b/drivers/scsi/mpt2sas/mpi/mpi2_type.h
deleted file mode 100644
index 6b0dcdd02f68..000000000000
--- a/drivers/scsi/mpt2sas/mpi/mpi2_type.h
+++ /dev/null
@@ -1,61 +0,0 @@
1/*
2 * Copyright (c) 2000-2014 LSI Corporation.
3 *
4 *
5 * Name: mpi2_type.h
6 * Title: MPI basic type definitions
7 * Creation Date: August 16, 2006
8 *
9 * mpi2_type.h Version: 02.00.00
10 *
11 * Version History
12 * ---------------
13 *
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
17 * --------------------------------------------------------------------------
18 */
19
20#ifndef MPI2_TYPE_H
21#define MPI2_TYPE_H
22
23
24/*******************************************************************************
25 * Define MPI2_POINTER if it hasn't already been defined. By default
26 * MPI2_POINTER is defined to be a near pointer. MPI2_POINTER can be defined as
27 * a far pointer by defining MPI2_POINTER as "far *" before this header file is
28 * included.
29 */
30#ifndef MPI2_POINTER
31#define MPI2_POINTER *
32#endif
33
34/* the basic types may have already been included by mpi_type.h */
35#ifndef MPI_TYPE_H
36/*****************************************************************************
37*
38* Basic Types
39*
40*****************************************************************************/
41
42typedef u8 U8;
43typedef __le16 U16;
44typedef __le32 U32;
45typedef __le64 U64 __attribute__((aligned(4)));
46
47/*****************************************************************************
48*
49* Pointer Types
50*
51*****************************************************************************/
52
53typedef U8 *PU8;
54typedef U16 *PU16;
55typedef U32 *PU32;
56typedef U64 *PU64;
57
58#endif
59
60#endif
61
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-17 14:23:43 -0400