diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2017-05-09 13:01:15 -0400 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2017-05-09 13:01:15 -0400 |
commit | 0160e00ae8e987be8822745fb166aa76451c9bcc (patch) | |
tree | deca2d09a729155ed0cb631f2bc8f557e634ab06 /drivers/reset/reset-uniphier.c | |
parent | c81ee18e97e4e3162169a749eb7f2b79b3510c7a (diff) | |
parent | b6942b68f85ed3161c91741791ec6f1779574919 (diff) |
Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Olof Johansson:
"Driver updates for ARM SoCs:
Reset subsystem, merged through arm-soc by tradition:
- Make bool drivers explicitly non-modular
- New support for i.MX7 and Arria10 reset controllers
PATA driver for Palmchip BK371 (acked by Tejun)
Power domain drivers for i.MX (GPC, GPCv2)
- Moved out of mach-imx for GPC
- Bunch of tweaks, fixes, etc
PMC support for Tegra186
SoC detection support for Renesas RZ/G1H and RZ/G1N
Move Tegra flow controller driver from mach directory to drivers/soc
- (Power management / CPU power driver)
Misc smaller tweaks for other platforms"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (60 commits)
soc: pm-domain: Fix the mangled urls
soc: renesas: rcar-sysc: Add support for R-Car H3 ES2.0
soc: renesas: rcar-sysc: Add support for fixing up power area tables
soc: renesas: Register SoC device early
soc: imx: gpc: add workaround for i.MX6QP to the GPC PD driver
dt-bindings: imx-gpc: add i.MX6 QuadPlus compatible
soc: imx: gpc: add defines for domain index
soc: imx: Add GPCv2 power gating driver
dt-bindings: Add GPCv2 power gating driver
ARM/clk: move the ICST library to drivers/clk
ARM: plat-versatile: remove stale clock header
ARM: keystone: Drop PM domain support for k2g
soc: ti: Add ti_sci_pm_domains driver
dt-bindings: Add TI SCI PM Domains
PM / Domains: Do not check if simple providers have phandle cells
PM / Domains: Add generic data pointer to genpd data struct
soc/tegra: Add initial flowctrl support for Tegra132/210
soc/tegra: flowctrl: Add basic platform driver
soc/tegra: Move Tegra flowctrl driver
ARM: tegra: Remove unnecessary inclusion of flowctrl header
...
Diffstat (limited to 'drivers/reset/reset-uniphier.c')
-rw-r--r-- | drivers/reset/reset-uniphier.c | 37 |
1 files changed, 27 insertions, 10 deletions
diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c index 9c11be3d3450..c4ba89832796 100644 --- a/drivers/reset/reset-uniphier.c +++ b/drivers/reset/reset-uniphier.c | |||
@@ -50,6 +50,15 @@ struct uniphier_reset_data { | |||
50 | } | 50 | } |
51 | 51 | ||
52 | /* System reset data */ | 52 | /* System reset data */ |
53 | #define UNIPHIER_SLD3_SYS_RESET_NAND(id) \ | ||
54 | UNIPHIER_RESETX((id), 0x2004, 2) | ||
55 | |||
56 | #define UNIPHIER_LD11_SYS_RESET_NAND(id) \ | ||
57 | UNIPHIER_RESETX((id), 0x200c, 0) | ||
58 | |||
59 | #define UNIPHIER_LD11_SYS_RESET_EMMC(id) \ | ||
60 | UNIPHIER_RESETX((id), 0x200c, 2) | ||
61 | |||
53 | #define UNIPHIER_SLD3_SYS_RESET_STDMAC(id) \ | 62 | #define UNIPHIER_SLD3_SYS_RESET_STDMAC(id) \ |
54 | UNIPHIER_RESETX((id), 0x2000, 10) | 63 | UNIPHIER_RESETX((id), 0x2000, 10) |
55 | 64 | ||
@@ -65,12 +74,14 @@ struct uniphier_reset_data { | |||
65 | #define UNIPHIER_PRO4_SYS_RESET_USB3(id, ch) \ | 74 | #define UNIPHIER_PRO4_SYS_RESET_USB3(id, ch) \ |
66 | UNIPHIER_RESETX((id), 0x2000 + 0x4 * (ch), 17) | 75 | UNIPHIER_RESETX((id), 0x2000 + 0x4 * (ch), 17) |
67 | 76 | ||
68 | const struct uniphier_reset_data uniphier_sld3_sys_reset_data[] = { | 77 | static const struct uniphier_reset_data uniphier_sld3_sys_reset_data[] = { |
78 | UNIPHIER_SLD3_SYS_RESET_NAND(2), | ||
69 | UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* Ether, HSC, MIO */ | 79 | UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* Ether, HSC, MIO */ |
70 | UNIPHIER_RESET_END, | 80 | UNIPHIER_RESET_END, |
71 | }; | 81 | }; |
72 | 82 | ||
73 | const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = { | 83 | static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = { |
84 | UNIPHIER_SLD3_SYS_RESET_NAND(2), | ||
74 | UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, MIO, RLE */ | 85 | UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, MIO, RLE */ |
75 | UNIPHIER_PRO4_SYS_RESET_GIO(12), /* Ether, SATA, USB3 */ | 86 | UNIPHIER_PRO4_SYS_RESET_GIO(12), /* Ether, SATA, USB3 */ |
76 | UNIPHIER_PRO4_SYS_RESET_USB3(14, 0), | 87 | UNIPHIER_PRO4_SYS_RESET_USB3(14, 0), |
@@ -78,7 +89,8 @@ const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = { | |||
78 | UNIPHIER_RESET_END, | 89 | UNIPHIER_RESET_END, |
79 | }; | 90 | }; |
80 | 91 | ||
81 | const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = { | 92 | static const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = { |
93 | UNIPHIER_SLD3_SYS_RESET_NAND(2), | ||
82 | UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC */ | 94 | UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC */ |
83 | UNIPHIER_PRO4_SYS_RESET_GIO(12), /* PCIe, USB3 */ | 95 | UNIPHIER_PRO4_SYS_RESET_GIO(12), /* PCIe, USB3 */ |
84 | UNIPHIER_PRO4_SYS_RESET_USB3(14, 0), | 96 | UNIPHIER_PRO4_SYS_RESET_USB3(14, 0), |
@@ -86,7 +98,8 @@ const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = { | |||
86 | UNIPHIER_RESET_END, | 98 | UNIPHIER_RESET_END, |
87 | }; | 99 | }; |
88 | 100 | ||
89 | const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = { | 101 | static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = { |
102 | UNIPHIER_SLD3_SYS_RESET_NAND(2), | ||
90 | UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, RLE */ | 103 | UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, RLE */ |
91 | UNIPHIER_PRO4_SYS_RESET_USB3(14, 0), | 104 | UNIPHIER_PRO4_SYS_RESET_USB3(14, 0), |
92 | UNIPHIER_PRO4_SYS_RESET_USB3(15, 1), | 105 | UNIPHIER_PRO4_SYS_RESET_USB3(15, 1), |
@@ -100,12 +113,16 @@ const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = { | |||
100 | UNIPHIER_RESET_END, | 113 | UNIPHIER_RESET_END, |
101 | }; | 114 | }; |
102 | 115 | ||
103 | const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = { | 116 | static const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = { |
117 | UNIPHIER_LD11_SYS_RESET_NAND(2), | ||
118 | UNIPHIER_LD11_SYS_RESET_EMMC(4), | ||
104 | UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC, MIO */ | 119 | UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC, MIO */ |
105 | UNIPHIER_RESET_END, | 120 | UNIPHIER_RESET_END, |
106 | }; | 121 | }; |
107 | 122 | ||
108 | const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = { | 123 | static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = { |
124 | UNIPHIER_LD11_SYS_RESET_NAND(2), | ||
125 | UNIPHIER_LD11_SYS_RESET_EMMC(4), | ||
109 | UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC */ | 126 | UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC */ |
110 | UNIPHIER_LD20_SYS_RESET_GIO(12), /* PCIe, USB3 */ | 127 | UNIPHIER_LD20_SYS_RESET_GIO(12), /* PCIe, USB3 */ |
111 | UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */ | 128 | UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */ |
@@ -134,7 +151,7 @@ const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = { | |||
134 | #define UNIPHIER_MIO_RESET_DMAC(id) \ | 151 | #define UNIPHIER_MIO_RESET_DMAC(id) \ |
135 | UNIPHIER_RESETX((id), 0x110, 17) | 152 | UNIPHIER_RESETX((id), 0x110, 17) |
136 | 153 | ||
137 | const struct uniphier_reset_data uniphier_sld3_mio_reset_data[] = { | 154 | static const struct uniphier_reset_data uniphier_sld3_mio_reset_data[] = { |
138 | UNIPHIER_MIO_RESET_SD(0, 0), | 155 | UNIPHIER_MIO_RESET_SD(0, 0), |
139 | UNIPHIER_MIO_RESET_SD(1, 1), | 156 | UNIPHIER_MIO_RESET_SD(1, 1), |
140 | UNIPHIER_MIO_RESET_SD(2, 2), | 157 | UNIPHIER_MIO_RESET_SD(2, 2), |
@@ -154,7 +171,7 @@ const struct uniphier_reset_data uniphier_sld3_mio_reset_data[] = { | |||
154 | UNIPHIER_RESET_END, | 171 | UNIPHIER_RESET_END, |
155 | }; | 172 | }; |
156 | 173 | ||
157 | const struct uniphier_reset_data uniphier_pro5_sd_reset_data[] = { | 174 | static const struct uniphier_reset_data uniphier_pro5_sd_reset_data[] = { |
158 | UNIPHIER_MIO_RESET_SD(0, 0), | 175 | UNIPHIER_MIO_RESET_SD(0, 0), |
159 | UNIPHIER_MIO_RESET_SD(1, 1), | 176 | UNIPHIER_MIO_RESET_SD(1, 1), |
160 | UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1), | 177 | UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1), |
@@ -171,7 +188,7 @@ const struct uniphier_reset_data uniphier_pro5_sd_reset_data[] = { | |||
171 | #define UNIPHIER_PERI_RESET_FI2C(id, ch) \ | 188 | #define UNIPHIER_PERI_RESET_FI2C(id, ch) \ |
172 | UNIPHIER_RESETX((id), 0x114, 24 + (ch)) | 189 | UNIPHIER_RESETX((id), 0x114, 24 + (ch)) |
173 | 190 | ||
174 | const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = { | 191 | static const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = { |
175 | UNIPHIER_PERI_RESET_UART(0, 0), | 192 | UNIPHIER_PERI_RESET_UART(0, 0), |
176 | UNIPHIER_PERI_RESET_UART(1, 1), | 193 | UNIPHIER_PERI_RESET_UART(1, 1), |
177 | UNIPHIER_PERI_RESET_UART(2, 2), | 194 | UNIPHIER_PERI_RESET_UART(2, 2), |
@@ -184,7 +201,7 @@ const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = { | |||
184 | UNIPHIER_RESET_END, | 201 | UNIPHIER_RESET_END, |
185 | }; | 202 | }; |
186 | 203 | ||
187 | const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = { | 204 | static const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = { |
188 | UNIPHIER_PERI_RESET_UART(0, 0), | 205 | UNIPHIER_PERI_RESET_UART(0, 0), |
189 | UNIPHIER_PERI_RESET_UART(1, 1), | 206 | UNIPHIER_PERI_RESET_UART(1, 1), |
190 | UNIPHIER_PERI_RESET_UART(2, 2), | 207 | UNIPHIER_PERI_RESET_UART(2, 2), |