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authorZhi Mao <zhi.mao@mediatek.com>2017-10-25 06:11:01 -0400
committerThierry Reding <thierry.reding@gmail.com>2017-11-15 04:57:53 -0500
commit424268c7494c2ae24c95565b9047bbf30309e88a (patch)
tree674b24ebe4322706685730388b65f1fd9efad5fb /drivers/pwm/pwm-mediatek.c
parentdf4f6e8c9f089d8c8406f87df819b4d91277979c (diff)
pwm: mediatek: Add MT2712/MT7622 support
Add support for MT2712 and MT7622. Due to register offset address of pwm7 for MT2712 is not fixed 0x40, add mtk_pwm_reg_offset array for PWM register offset. Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Zhi Mao <zhi.mao@mediatek.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Diffstat (limited to 'drivers/pwm/pwm-mediatek.c')
-rw-r--r--drivers/pwm/pwm-mediatek.c53
1 files changed, 44 insertions, 9 deletions
diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
index b52f3afb2ba1..f5d97e0ad52b 100644
--- a/drivers/pwm/pwm-mediatek.c
+++ b/drivers/pwm/pwm-mediatek.c
@@ -16,6 +16,7 @@
16#include <linux/module.h> 16#include <linux/module.h>
17#include <linux/clk.h> 17#include <linux/clk.h>
18#include <linux/of.h> 18#include <linux/of.h>
19#include <linux/of_device.h>
19#include <linux/platform_device.h> 20#include <linux/platform_device.h>
20#include <linux/pwm.h> 21#include <linux/pwm.h>
21#include <linux/slab.h> 22#include <linux/slab.h>
@@ -40,11 +41,19 @@ enum {
40 MTK_CLK_PWM3, 41 MTK_CLK_PWM3,
41 MTK_CLK_PWM4, 42 MTK_CLK_PWM4,
42 MTK_CLK_PWM5, 43 MTK_CLK_PWM5,
44 MTK_CLK_PWM6,
45 MTK_CLK_PWM7,
46 MTK_CLK_PWM8,
43 MTK_CLK_MAX, 47 MTK_CLK_MAX,
44}; 48};
45 49
46static const char * const mtk_pwm_clk_name[] = { 50static const char * const mtk_pwm_clk_name[MTK_CLK_MAX] = {
47 "main", "top", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5" 51 "main", "top", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6", "pwm7",
52 "pwm8"
53};
54
55struct mtk_pwm_platform_data {
56 unsigned int num_pwms;
48}; 57};
49 58
50/** 59/**
@@ -59,6 +68,10 @@ struct mtk_pwm_chip {
59 struct clk *clks[MTK_CLK_MAX]; 68 struct clk *clks[MTK_CLK_MAX];
60}; 69};
61 70
71static const unsigned int mtk_pwm_reg_offset[] = {
72 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
73};
74
62static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip) 75static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip)
63{ 76{
64 return container_of(chip, struct mtk_pwm_chip, chip); 77 return container_of(chip, struct mtk_pwm_chip, chip);
@@ -103,14 +116,14 @@ static void mtk_pwm_clk_disable(struct pwm_chip *chip, struct pwm_device *pwm)
103static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num, 116static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num,
104 unsigned int offset) 117 unsigned int offset)
105{ 118{
106 return readl(chip->regs + 0x10 + (num * 0x40) + offset); 119 return readl(chip->regs + mtk_pwm_reg_offset[num] + offset);
107} 120}
108 121
109static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip, 122static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip,
110 unsigned int num, unsigned int offset, 123 unsigned int num, unsigned int offset,
111 u32 value) 124 u32 value)
112{ 125{
113 writel(value, chip->regs + 0x10 + (num * 0x40) + offset); 126 writel(value, chip->regs + mtk_pwm_reg_offset[num] + offset);
114} 127}
115 128
116static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 129static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
@@ -185,6 +198,7 @@ static const struct pwm_ops mtk_pwm_ops = {
185 198
186static int mtk_pwm_probe(struct platform_device *pdev) 199static int mtk_pwm_probe(struct platform_device *pdev)
187{ 200{
201 const struct mtk_pwm_platform_data *data;
188 struct mtk_pwm_chip *pc; 202 struct mtk_pwm_chip *pc;
189 struct resource *res; 203 struct resource *res;
190 unsigned int i; 204 unsigned int i;
@@ -194,15 +208,22 @@ static int mtk_pwm_probe(struct platform_device *pdev)
194 if (!pc) 208 if (!pc)
195 return -ENOMEM; 209 return -ENOMEM;
196 210
211 data = of_device_get_match_data(&pdev->dev);
212 if (data == NULL)
213 return -EINVAL;
214
197 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 215 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
198 pc->regs = devm_ioremap_resource(&pdev->dev, res); 216 pc->regs = devm_ioremap_resource(&pdev->dev, res);
199 if (IS_ERR(pc->regs)) 217 if (IS_ERR(pc->regs))
200 return PTR_ERR(pc->regs); 218 return PTR_ERR(pc->regs);
201 219
202 for (i = 0; i < MTK_CLK_MAX; i++) { 220 for (i = 0; i < data->num_pwms + 2; i++) {
203 pc->clks[i] = devm_clk_get(&pdev->dev, mtk_pwm_clk_name[i]); 221 pc->clks[i] = devm_clk_get(&pdev->dev, mtk_pwm_clk_name[i]);
204 if (IS_ERR(pc->clks[i])) 222 if (IS_ERR(pc->clks[i])) {
223 dev_err(&pdev->dev, "clock: %s fail: %ld\n",
224 mtk_pwm_clk_name[i], PTR_ERR(pc->clks[i]));
205 return PTR_ERR(pc->clks[i]); 225 return PTR_ERR(pc->clks[i]);
226 }
206 } 227 }
207 228
208 platform_set_drvdata(pdev, pc); 229 platform_set_drvdata(pdev, pc);
@@ -210,7 +231,7 @@ static int mtk_pwm_probe(struct platform_device *pdev)
210 pc->chip.dev = &pdev->dev; 231 pc->chip.dev = &pdev->dev;
211 pc->chip.ops = &mtk_pwm_ops; 232 pc->chip.ops = &mtk_pwm_ops;
212 pc->chip.base = -1; 233 pc->chip.base = -1;
213 pc->chip.npwm = 5; 234 pc->chip.npwm = data->num_pwms;
214 235
215 ret = pwmchip_add(&pc->chip); 236 ret = pwmchip_add(&pc->chip);
216 if (ret < 0) { 237 if (ret < 0) {
@@ -228,9 +249,23 @@ static int mtk_pwm_remove(struct platform_device *pdev)
228 return pwmchip_remove(&pc->chip); 249 return pwmchip_remove(&pc->chip);
229} 250}
230 251
252static const struct mtk_pwm_platform_data mt2712_pwm_data = {
253 .num_pwms = 8,
254};
255
256static const struct mtk_pwm_platform_data mt7622_pwm_data = {
257 .num_pwms = 6,
258};
259
260static const struct mtk_pwm_platform_data mt7623_pwm_data = {
261 .num_pwms = 5,
262};
263
231static const struct of_device_id mtk_pwm_of_match[] = { 264static const struct of_device_id mtk_pwm_of_match[] = {
232 { .compatible = "mediatek,mt7623-pwm" }, 265 { .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data },
233 { } 266 { .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data },
267 { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
268 { },
234}; 269};
235MODULE_DEVICE_TABLE(of, mtk_pwm_of_match); 270MODULE_DEVICE_TABLE(of, mtk_pwm_of_match);
236 271