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authorMaxime Ripard <maxime.ripard@free-electrons.com>2014-04-24 10:06:52 -0400
committerMaxime Ripard <maxime.ripard@free-electrons.com>2014-05-04 02:59:44 -0400
commitd10acc635330d6089601fd01d482ecda32e02c45 (patch)
tree5d48acde26c134d982d3fa4da83f1e3f8684301e /drivers/pinctrl
parent5f9107774fc81eb7a33ac7a2c296523ce5fbb14a (diff)
pinctrl: sunxi: Replace hardcoded pin defines by a macro
We previously had an evergrowing (and exhaustive) list of the pins that could be used on any Allwinner SoCs. These defines were then used by each pinctrl driver to declare the list of functions for this pin. Since it's pretty much all boilerplate, we can remove it just by a single macro. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sunxi-pins.h1454
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sunxi.h364
2 files changed, 729 insertions, 1089 deletions
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi-pins.h b/drivers/pinctrl/sunxi/pinctrl-sunxi-pins.h
index 51100caf05f9..e1ea6d8345b0 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi-pins.h
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi-pins.h
@@ -16,637 +16,637 @@
16#include "pinctrl-sunxi.h" 16#include "pinctrl-sunxi.h"
17 17
18static const struct sunxi_desc_pin sun4i_a10_pins[] = { 18static const struct sunxi_desc_pin sun4i_a10_pins[] = {
19 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0, 19 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
20 SUNXI_FUNCTION(0x0, "gpio_in"), 20 SUNXI_FUNCTION(0x0, "gpio_in"),
21 SUNXI_FUNCTION(0x1, "gpio_out"), 21 SUNXI_FUNCTION(0x1, "gpio_out"),
22 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */ 22 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
23 SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */ 23 SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
24 SUNXI_FUNCTION(0x4, "uart2")), /* RTS */ 24 SUNXI_FUNCTION(0x4, "uart2")), /* RTS */
25 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1, 25 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
26 SUNXI_FUNCTION(0x0, "gpio_in"), 26 SUNXI_FUNCTION(0x0, "gpio_in"),
27 SUNXI_FUNCTION(0x1, "gpio_out"), 27 SUNXI_FUNCTION(0x1, "gpio_out"),
28 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */ 28 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
29 SUNXI_FUNCTION(0x3, "spi1"), /* CLK */ 29 SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
30 SUNXI_FUNCTION(0x4, "uart2")), /* CTS */ 30 SUNXI_FUNCTION(0x4, "uart2")), /* CTS */
31 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2, 31 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
32 SUNXI_FUNCTION(0x0, "gpio_in"), 32 SUNXI_FUNCTION(0x0, "gpio_in"),
33 SUNXI_FUNCTION(0x1, "gpio_out"), 33 SUNXI_FUNCTION(0x1, "gpio_out"),
34 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */ 34 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
35 SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */ 35 SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
36 SUNXI_FUNCTION(0x4, "uart2")), /* TX */ 36 SUNXI_FUNCTION(0x4, "uart2")), /* TX */
37 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3, 37 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
38 SUNXI_FUNCTION(0x0, "gpio_in"), 38 SUNXI_FUNCTION(0x0, "gpio_in"),
39 SUNXI_FUNCTION(0x1, "gpio_out"), 39 SUNXI_FUNCTION(0x1, "gpio_out"),
40 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */ 40 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
41 SUNXI_FUNCTION(0x3, "spi1"), /* MISO */ 41 SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
42 SUNXI_FUNCTION(0x4, "uart2")), /* RX */ 42 SUNXI_FUNCTION(0x4, "uart2")), /* RX */
43 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4, 43 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
44 SUNXI_FUNCTION(0x0, "gpio_in"), 44 SUNXI_FUNCTION(0x0, "gpio_in"),
45 SUNXI_FUNCTION(0x1, "gpio_out"), 45 SUNXI_FUNCTION(0x1, "gpio_out"),
46 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */ 46 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
47 SUNXI_FUNCTION(0x3, "spi1")), /* CS1 */ 47 SUNXI_FUNCTION(0x3, "spi1")), /* CS1 */
48 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5, 48 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
49 SUNXI_FUNCTION(0x0, "gpio_in"), 49 SUNXI_FUNCTION(0x0, "gpio_in"),
50 SUNXI_FUNCTION(0x1, "gpio_out"), 50 SUNXI_FUNCTION(0x1, "gpio_out"),
51 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */ 51 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
52 SUNXI_FUNCTION(0x3, "spi3")), /* CS0 */ 52 SUNXI_FUNCTION(0x3, "spi3")), /* CS0 */
53 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6, 53 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
54 SUNXI_FUNCTION(0x0, "gpio_in"), 54 SUNXI_FUNCTION(0x0, "gpio_in"),
55 SUNXI_FUNCTION(0x1, "gpio_out"), 55 SUNXI_FUNCTION(0x1, "gpio_out"),
56 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */ 56 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
57 SUNXI_FUNCTION(0x3, "spi3")), /* CLK */ 57 SUNXI_FUNCTION(0x3, "spi3")), /* CLK */
58 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7, 58 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
59 SUNXI_FUNCTION(0x0, "gpio_in"), 59 SUNXI_FUNCTION(0x0, "gpio_in"),
60 SUNXI_FUNCTION(0x1, "gpio_out"), 60 SUNXI_FUNCTION(0x1, "gpio_out"),
61 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */ 61 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
62 SUNXI_FUNCTION(0x3, "spi3")), /* MOSI */ 62 SUNXI_FUNCTION(0x3, "spi3")), /* MOSI */
63 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8, 63 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
64 SUNXI_FUNCTION(0x0, "gpio_in"), 64 SUNXI_FUNCTION(0x0, "gpio_in"),
65 SUNXI_FUNCTION(0x1, "gpio_out"), 65 SUNXI_FUNCTION(0x1, "gpio_out"),
66 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */ 66 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
67 SUNXI_FUNCTION(0x3, "spi3")), /* MISO */ 67 SUNXI_FUNCTION(0x3, "spi3")), /* MISO */
68 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9, 68 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
69 SUNXI_FUNCTION(0x0, "gpio_in"), 69 SUNXI_FUNCTION(0x0, "gpio_in"),
70 SUNXI_FUNCTION(0x1, "gpio_out"), 70 SUNXI_FUNCTION(0x1, "gpio_out"),
71 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */ 71 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
72 SUNXI_FUNCTION(0x3, "spi3")), /* CS1 */ 72 SUNXI_FUNCTION(0x3, "spi3")), /* CS1 */
73 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10, 73 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
74 SUNXI_FUNCTION(0x0, "gpio_in"), 74 SUNXI_FUNCTION(0x0, "gpio_in"),
75 SUNXI_FUNCTION(0x1, "gpio_out"), 75 SUNXI_FUNCTION(0x1, "gpio_out"),
76 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */ 76 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
77 SUNXI_FUNCTION(0x4, "uart1")), /* TX */ 77 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
78 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11, 78 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
79 SUNXI_FUNCTION(0x0, "gpio_in"), 79 SUNXI_FUNCTION(0x0, "gpio_in"),
80 SUNXI_FUNCTION(0x1, "gpio_out"), 80 SUNXI_FUNCTION(0x1, "gpio_out"),
81 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */ 81 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
82 SUNXI_FUNCTION(0x4, "uart1")), /* RX */ 82 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
83 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12, 83 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
84 SUNXI_FUNCTION(0x0, "gpio_in"), 84 SUNXI_FUNCTION(0x0, "gpio_in"),
85 SUNXI_FUNCTION(0x1, "gpio_out"), 85 SUNXI_FUNCTION(0x1, "gpio_out"),
86 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */ 86 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
87 SUNXI_FUNCTION(0x3, "uart6"), /* TX */ 87 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
88 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */ 88 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */
89 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13, 89 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
90 SUNXI_FUNCTION(0x0, "gpio_in"), 90 SUNXI_FUNCTION(0x0, "gpio_in"),
91 SUNXI_FUNCTION(0x1, "gpio_out"), 91 SUNXI_FUNCTION(0x1, "gpio_out"),
92 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */ 92 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
93 SUNXI_FUNCTION(0x3, "uart6"), /* RX */ 93 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
94 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */ 94 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */
95 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14, 95 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
96 SUNXI_FUNCTION(0x0, "gpio_in"), 96 SUNXI_FUNCTION(0x0, "gpio_in"),
97 SUNXI_FUNCTION(0x1, "gpio_out"), 97 SUNXI_FUNCTION(0x1, "gpio_out"),
98 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */ 98 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
99 SUNXI_FUNCTION(0x3, "uart7"), /* TX */ 99 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
100 SUNXI_FUNCTION(0x4, "uart1")), /* DTR */ 100 SUNXI_FUNCTION(0x4, "uart1")), /* DTR */
101 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15, 101 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
102 SUNXI_FUNCTION(0x0, "gpio_in"), 102 SUNXI_FUNCTION(0x0, "gpio_in"),
103 SUNXI_FUNCTION(0x1, "gpio_out"), 103 SUNXI_FUNCTION(0x1, "gpio_out"),
104 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */ 104 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
105 SUNXI_FUNCTION(0x3, "uart7"), /* RX */ 105 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
106 SUNXI_FUNCTION(0x4, "uart1")), /* DSR */ 106 SUNXI_FUNCTION(0x4, "uart1")), /* DSR */
107 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16, 107 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
108 SUNXI_FUNCTION(0x0, "gpio_in"), 108 SUNXI_FUNCTION(0x0, "gpio_in"),
109 SUNXI_FUNCTION(0x1, "gpio_out"), 109 SUNXI_FUNCTION(0x1, "gpio_out"),
110 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */ 110 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
111 SUNXI_FUNCTION(0x3, "can"), /* TX */ 111 SUNXI_FUNCTION(0x3, "can"), /* TX */
112 SUNXI_FUNCTION(0x4, "uart1")), /* DCD */ 112 SUNXI_FUNCTION(0x4, "uart1")), /* DCD */
113 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17, 113 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
114 SUNXI_FUNCTION(0x0, "gpio_in"), 114 SUNXI_FUNCTION(0x0, "gpio_in"),
115 SUNXI_FUNCTION(0x1, "gpio_out"), 115 SUNXI_FUNCTION(0x1, "gpio_out"),
116 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */ 116 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
117 SUNXI_FUNCTION(0x3, "can"), /* RX */ 117 SUNXI_FUNCTION(0x3, "can"), /* RX */
118 SUNXI_FUNCTION(0x4, "uart1")), /* RING */ 118 SUNXI_FUNCTION(0x4, "uart1")), /* RING */
119 /* Hole */ 119 /* Hole */
120 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0, 120 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
121 SUNXI_FUNCTION(0x0, "gpio_in"), 121 SUNXI_FUNCTION(0x0, "gpio_in"),
122 SUNXI_FUNCTION(0x1, "gpio_out"), 122 SUNXI_FUNCTION(0x1, "gpio_out"),
123 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ 123 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
124 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1, 124 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
125 SUNXI_FUNCTION(0x0, "gpio_in"), 125 SUNXI_FUNCTION(0x0, "gpio_in"),
126 SUNXI_FUNCTION(0x1, "gpio_out"), 126 SUNXI_FUNCTION(0x1, "gpio_out"),
127 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ 127 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
128 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2, 128 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
129 SUNXI_FUNCTION(0x0, "gpio_in"), 129 SUNXI_FUNCTION(0x0, "gpio_in"),
130 SUNXI_FUNCTION(0x1, "gpio_out"), 130 SUNXI_FUNCTION(0x1, "gpio_out"),
131 SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */ 131 SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */
132 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3, 132 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
133 SUNXI_FUNCTION(0x0, "gpio_in"), 133 SUNXI_FUNCTION(0x0, "gpio_in"),
134 SUNXI_FUNCTION(0x1, "gpio_out"), 134 SUNXI_FUNCTION(0x1, "gpio_out"),
135 SUNXI_FUNCTION(0x2, "ir0")), /* TX */ 135 SUNXI_FUNCTION(0x2, "ir0")), /* TX */
136 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4, 136 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
137 SUNXI_FUNCTION(0x0, "gpio_in"), 137 SUNXI_FUNCTION(0x0, "gpio_in"),
138 SUNXI_FUNCTION(0x1, "gpio_out"), 138 SUNXI_FUNCTION(0x1, "gpio_out"),
139 SUNXI_FUNCTION(0x2, "ir0")), /* RX */ 139 SUNXI_FUNCTION(0x2, "ir0")), /* RX */
140 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5, 140 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
141 SUNXI_FUNCTION(0x0, "gpio_in"), 141 SUNXI_FUNCTION(0x0, "gpio_in"),
142 SUNXI_FUNCTION(0x1, "gpio_out"), 142 SUNXI_FUNCTION(0x1, "gpio_out"),
143 SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */ 143 SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
144 SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */ 144 SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */
145 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6, 145 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
146 SUNXI_FUNCTION(0x0, "gpio_in"), 146 SUNXI_FUNCTION(0x0, "gpio_in"),
147 SUNXI_FUNCTION(0x1, "gpio_out"), 147 SUNXI_FUNCTION(0x1, "gpio_out"),
148 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */ 148 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
149 SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */ 149 SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */
150 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7, 150 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
151 SUNXI_FUNCTION(0x0, "gpio_in"), 151 SUNXI_FUNCTION(0x0, "gpio_in"),
152 SUNXI_FUNCTION(0x1, "gpio_out"), 152 SUNXI_FUNCTION(0x1, "gpio_out"),
153 SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */ 153 SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */
154 SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */ 154 SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */
155 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8, 155 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
156 SUNXI_FUNCTION(0x0, "gpio_in"), 156 SUNXI_FUNCTION(0x0, "gpio_in"),
157 SUNXI_FUNCTION(0x1, "gpio_out"), 157 SUNXI_FUNCTION(0x1, "gpio_out"),
158 SUNXI_FUNCTION(0x2, "i2s"), /* DO0 */ 158 SUNXI_FUNCTION(0x2, "i2s"), /* DO0 */
159 SUNXI_FUNCTION(0x3, "ac97")), /* DO */ 159 SUNXI_FUNCTION(0x3, "ac97")), /* DO */
160 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9, 160 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
161 SUNXI_FUNCTION(0x0, "gpio_in"), 161 SUNXI_FUNCTION(0x0, "gpio_in"),
162 SUNXI_FUNCTION(0x1, "gpio_out"), 162 SUNXI_FUNCTION(0x1, "gpio_out"),
163 SUNXI_FUNCTION(0x2, "i2s")), /* DO1 */ 163 SUNXI_FUNCTION(0x2, "i2s")), /* DO1 */
164 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10, 164 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
165 SUNXI_FUNCTION(0x0, "gpio_in"), 165 SUNXI_FUNCTION(0x0, "gpio_in"),
166 SUNXI_FUNCTION(0x1, "gpio_out"), 166 SUNXI_FUNCTION(0x1, "gpio_out"),
167 SUNXI_FUNCTION(0x2, "i2s")), /* DO2 */ 167 SUNXI_FUNCTION(0x2, "i2s")), /* DO2 */
168 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11, 168 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
169 SUNXI_FUNCTION(0x0, "gpio_in"), 169 SUNXI_FUNCTION(0x0, "gpio_in"),
170 SUNXI_FUNCTION(0x1, "gpio_out"), 170 SUNXI_FUNCTION(0x1, "gpio_out"),
171 SUNXI_FUNCTION(0x2, "i2s")), /* DO3 */ 171 SUNXI_FUNCTION(0x2, "i2s")), /* DO3 */
172 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12, 172 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
173 SUNXI_FUNCTION(0x0, "gpio_in"), 173 SUNXI_FUNCTION(0x0, "gpio_in"),
174 SUNXI_FUNCTION(0x1, "gpio_out"), 174 SUNXI_FUNCTION(0x1, "gpio_out"),
175 SUNXI_FUNCTION(0x2, "i2s"), /* DI */ 175 SUNXI_FUNCTION(0x2, "i2s"), /* DI */
176 SUNXI_FUNCTION(0x3, "ac97")), /* DI */ 176 SUNXI_FUNCTION(0x3, "ac97")), /* DI */
177 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13, 177 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
178 SUNXI_FUNCTION(0x0, "gpio_in"), 178 SUNXI_FUNCTION(0x0, "gpio_in"),
179 SUNXI_FUNCTION(0x1, "gpio_out"), 179 SUNXI_FUNCTION(0x1, "gpio_out"),
180 SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */ 180 SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */
181 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14, 181 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
182 SUNXI_FUNCTION(0x0, "gpio_in"), 182 SUNXI_FUNCTION(0x0, "gpio_in"),
183 SUNXI_FUNCTION(0x1, "gpio_out"), 183 SUNXI_FUNCTION(0x1, "gpio_out"),
184 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */ 184 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
185 SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */ 185 SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */
186 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15, 186 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
187 SUNXI_FUNCTION(0x0, "gpio_in"), 187 SUNXI_FUNCTION(0x0, "gpio_in"),
188 SUNXI_FUNCTION(0x1, "gpio_out"), 188 SUNXI_FUNCTION(0x1, "gpio_out"),
189 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */ 189 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
190 SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */ 190 SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */
191 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16, 191 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
192 SUNXI_FUNCTION(0x0, "gpio_in"), 192 SUNXI_FUNCTION(0x0, "gpio_in"),
193 SUNXI_FUNCTION(0x1, "gpio_out"), 193 SUNXI_FUNCTION(0x1, "gpio_out"),
194 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */ 194 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
195 SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */ 195 SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */
196 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17, 196 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
197 SUNXI_FUNCTION(0x0, "gpio_in"), 197 SUNXI_FUNCTION(0x0, "gpio_in"),
198 SUNXI_FUNCTION(0x1, "gpio_out"), 198 SUNXI_FUNCTION(0x1, "gpio_out"),
199 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */ 199 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
200 SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */ 200 SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */
201 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18, 201 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
202 SUNXI_FUNCTION(0x0, "gpio_in"), 202 SUNXI_FUNCTION(0x0, "gpio_in"),
203 SUNXI_FUNCTION(0x1, "gpio_out"), 203 SUNXI_FUNCTION(0x1, "gpio_out"),
204 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ 204 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
205 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19, 205 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 19),
206 SUNXI_FUNCTION(0x0, "gpio_in"), 206 SUNXI_FUNCTION(0x0, "gpio_in"),
207 SUNXI_FUNCTION(0x1, "gpio_out"), 207 SUNXI_FUNCTION(0x1, "gpio_out"),
208 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ 208 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
209 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20, 209 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20),
210 SUNXI_FUNCTION(0x0, "gpio_in"), 210 SUNXI_FUNCTION(0x0, "gpio_in"),
211 SUNXI_FUNCTION(0x1, "gpio_out"), 211 SUNXI_FUNCTION(0x1, "gpio_out"),
212 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ 212 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
213 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21, 213 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 21),
214 SUNXI_FUNCTION(0x0, "gpio_in"), 214 SUNXI_FUNCTION(0x0, "gpio_in"),
215 SUNXI_FUNCTION(0x1, "gpio_out"), 215 SUNXI_FUNCTION(0x1, "gpio_out"),
216 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ 216 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
217 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22, 217 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 22),
218 SUNXI_FUNCTION(0x0, "gpio_in"), 218 SUNXI_FUNCTION(0x0, "gpio_in"),
219 SUNXI_FUNCTION(0x1, "gpio_out"), 219 SUNXI_FUNCTION(0x1, "gpio_out"),
220 SUNXI_FUNCTION(0x2, "uart0"), /* TX */ 220 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
221 SUNXI_FUNCTION(0x3, "ir1")), /* TX */ 221 SUNXI_FUNCTION(0x3, "ir1")), /* TX */
222 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23, 222 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 23),
223 SUNXI_FUNCTION(0x0, "gpio_in"), 223 SUNXI_FUNCTION(0x0, "gpio_in"),
224 SUNXI_FUNCTION(0x1, "gpio_out"), 224 SUNXI_FUNCTION(0x1, "gpio_out"),
225 SUNXI_FUNCTION(0x2, "uart0"), /* RX */ 225 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
226 SUNXI_FUNCTION(0x3, "ir1")), /* RX */ 226 SUNXI_FUNCTION(0x3, "ir1")), /* RX */
227 /* Hole */ 227 /* Hole */
228 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0, 228 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
229 SUNXI_FUNCTION(0x0, "gpio_in"), 229 SUNXI_FUNCTION(0x0, "gpio_in"),
230 SUNXI_FUNCTION(0x1, "gpio_out"), 230 SUNXI_FUNCTION(0x1, "gpio_out"),
231 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ 231 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
232 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ 232 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
233 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1, 233 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
234 SUNXI_FUNCTION(0x0, "gpio_in"), 234 SUNXI_FUNCTION(0x0, "gpio_in"),
235 SUNXI_FUNCTION(0x1, "gpio_out"), 235 SUNXI_FUNCTION(0x1, "gpio_out"),
236 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ 236 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
237 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ 237 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
238 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2, 238 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
239 SUNXI_FUNCTION(0x0, "gpio_in"), 239 SUNXI_FUNCTION(0x0, "gpio_in"),
240 SUNXI_FUNCTION(0x1, "gpio_out"), 240 SUNXI_FUNCTION(0x1, "gpio_out"),
241 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ 241 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
242 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */ 242 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
243 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3, 243 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
244 SUNXI_FUNCTION(0x0, "gpio_in"), 244 SUNXI_FUNCTION(0x0, "gpio_in"),
245 SUNXI_FUNCTION(0x1, "gpio_out"), 245 SUNXI_FUNCTION(0x1, "gpio_out"),
246 SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */ 246 SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */
247 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4, 247 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
248 SUNXI_FUNCTION(0x0, "gpio_in"), 248 SUNXI_FUNCTION(0x0, "gpio_in"),
249 SUNXI_FUNCTION(0x1, "gpio_out"), 249 SUNXI_FUNCTION(0x1, "gpio_out"),
250 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ 250 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
251 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5, 251 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
252 SUNXI_FUNCTION(0x0, "gpio_in"), 252 SUNXI_FUNCTION(0x0, "gpio_in"),
253 SUNXI_FUNCTION(0x1, "gpio_out"), 253 SUNXI_FUNCTION(0x1, "gpio_out"),
254 SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */ 254 SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */
255 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6, 255 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
256 SUNXI_FUNCTION(0x0, "gpio_in"), 256 SUNXI_FUNCTION(0x0, "gpio_in"),
257 SUNXI_FUNCTION(0x1, "gpio_out"), 257 SUNXI_FUNCTION(0x1, "gpio_out"),
258 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ 258 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
259 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ 259 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
260 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7, 260 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
261 SUNXI_FUNCTION(0x0, "gpio_in"), 261 SUNXI_FUNCTION(0x0, "gpio_in"),
262 SUNXI_FUNCTION(0x1, "gpio_out"), 262 SUNXI_FUNCTION(0x1, "gpio_out"),
263 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */ 263 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
264 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ 264 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
265 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8, 265 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
266 SUNXI_FUNCTION(0x0, "gpio_in"), 266 SUNXI_FUNCTION(0x0, "gpio_in"),
267 SUNXI_FUNCTION(0x1, "gpio_out"), 267 SUNXI_FUNCTION(0x1, "gpio_out"),
268 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ 268 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
269 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ 269 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
270 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9, 270 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
271 SUNXI_FUNCTION(0x0, "gpio_in"), 271 SUNXI_FUNCTION(0x0, "gpio_in"),
272 SUNXI_FUNCTION(0x1, "gpio_out"), 272 SUNXI_FUNCTION(0x1, "gpio_out"),
273 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ 273 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
274 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ 274 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
275 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10, 275 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
276 SUNXI_FUNCTION(0x0, "gpio_in"), 276 SUNXI_FUNCTION(0x0, "gpio_in"),
277 SUNXI_FUNCTION(0x1, "gpio_out"), 277 SUNXI_FUNCTION(0x1, "gpio_out"),
278 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ 278 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
279 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ 279 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
280 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11, 280 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
281 SUNXI_FUNCTION(0x0, "gpio_in"), 281 SUNXI_FUNCTION(0x0, "gpio_in"),
282 SUNXI_FUNCTION(0x1, "gpio_out"), 282 SUNXI_FUNCTION(0x1, "gpio_out"),
283 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ 283 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
284 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ 284 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
285 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12, 285 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
286 SUNXI_FUNCTION(0x0, "gpio_in"), 286 SUNXI_FUNCTION(0x0, "gpio_in"),
287 SUNXI_FUNCTION(0x1, "gpio_out"), 287 SUNXI_FUNCTION(0x1, "gpio_out"),
288 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */ 288 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */
289 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13, 289 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
290 SUNXI_FUNCTION(0x0, "gpio_in"), 290 SUNXI_FUNCTION(0x0, "gpio_in"),
291 SUNXI_FUNCTION(0x1, "gpio_out"), 291 SUNXI_FUNCTION(0x1, "gpio_out"),
292 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */ 292 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */
293 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14, 293 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
294 SUNXI_FUNCTION(0x0, "gpio_in"), 294 SUNXI_FUNCTION(0x0, "gpio_in"),
295 SUNXI_FUNCTION(0x1, "gpio_out"), 295 SUNXI_FUNCTION(0x1, "gpio_out"),
296 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */ 296 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */
297 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15, 297 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
298 SUNXI_FUNCTION(0x0, "gpio_in"), 298 SUNXI_FUNCTION(0x0, "gpio_in"),
299 SUNXI_FUNCTION(0x1, "gpio_out"), 299 SUNXI_FUNCTION(0x1, "gpio_out"),
300 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */ 300 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */
301 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16, 301 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
302 SUNXI_FUNCTION(0x0, "gpio_in"), 302 SUNXI_FUNCTION(0x0, "gpio_in"),
303 SUNXI_FUNCTION(0x1, "gpio_out"), 303 SUNXI_FUNCTION(0x1, "gpio_out"),
304 SUNXI_FUNCTION(0x2, "nand0")), /* NWP */ 304 SUNXI_FUNCTION(0x2, "nand0")), /* NWP */
305 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17, 305 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
306 SUNXI_FUNCTION(0x0, "gpio_in"), 306 SUNXI_FUNCTION(0x0, "gpio_in"),
307 SUNXI_FUNCTION(0x1, "gpio_out"), 307 SUNXI_FUNCTION(0x1, "gpio_out"),
308 SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */ 308 SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */
309 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18, 309 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
310 SUNXI_FUNCTION(0x0, "gpio_in"), 310 SUNXI_FUNCTION(0x0, "gpio_in"),
311 SUNXI_FUNCTION(0x1, "gpio_out"), 311 SUNXI_FUNCTION(0x1, "gpio_out"),
312 SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */ 312 SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */
313 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19, 313 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
314 SUNXI_FUNCTION(0x0, "gpio_in"), 314 SUNXI_FUNCTION(0x0, "gpio_in"),
315 SUNXI_FUNCTION(0x1, "gpio_out"), 315 SUNXI_FUNCTION(0x1, "gpio_out"),
316 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */ 316 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
317 SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */ 317 SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */
318 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20, 318 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20),
319 SUNXI_FUNCTION(0x0, "gpio_in"), 319 SUNXI_FUNCTION(0x0, "gpio_in"),
320 SUNXI_FUNCTION(0x1, "gpio_out"), 320 SUNXI_FUNCTION(0x1, "gpio_out"),
321 SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */ 321 SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
322 SUNXI_FUNCTION(0x3, "spi2")), /* CLK */ 322 SUNXI_FUNCTION(0x3, "spi2")), /* CLK */
323 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21, 323 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21),
324 SUNXI_FUNCTION(0x0, "gpio_in"), 324 SUNXI_FUNCTION(0x0, "gpio_in"),
325 SUNXI_FUNCTION(0x1, "gpio_out"), 325 SUNXI_FUNCTION(0x1, "gpio_out"),
326 SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */ 326 SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
327 SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */ 327 SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */
328 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22, 328 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22),
329 SUNXI_FUNCTION(0x0, "gpio_in"), 329 SUNXI_FUNCTION(0x0, "gpio_in"),
330 SUNXI_FUNCTION(0x1, "gpio_out"), 330 SUNXI_FUNCTION(0x1, "gpio_out"),
331 SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */ 331 SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
332 SUNXI_FUNCTION(0x3, "spi2")), /* MISO */ 332 SUNXI_FUNCTION(0x3, "spi2")), /* MISO */
333 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23, 333 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23),
334 SUNXI_FUNCTION(0x0, "gpio_in"), 334 SUNXI_FUNCTION(0x0, "gpio_in"),
335 SUNXI_FUNCTION(0x1, "gpio_out"), 335 SUNXI_FUNCTION(0x1, "gpio_out"),
336 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ 336 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
337 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24, 337 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24),
338 SUNXI_FUNCTION(0x0, "gpio_in"), 338 SUNXI_FUNCTION(0x0, "gpio_in"),
339 SUNXI_FUNCTION(0x1, "gpio_out"), 339 SUNXI_FUNCTION(0x1, "gpio_out"),
340 SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */ 340 SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */
341 /* Hole */ 341 /* Hole */
342 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0, 342 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
343 SUNXI_FUNCTION(0x0, "gpio_in"), 343 SUNXI_FUNCTION(0x0, "gpio_in"),
344 SUNXI_FUNCTION(0x1, "gpio_out"), 344 SUNXI_FUNCTION(0x1, "gpio_out"),
345 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */ 345 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
346 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */ 346 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
347 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1, 347 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
348 SUNXI_FUNCTION(0x0, "gpio_in"), 348 SUNXI_FUNCTION(0x0, "gpio_in"),
349 SUNXI_FUNCTION(0x1, "gpio_out"), 349 SUNXI_FUNCTION(0x1, "gpio_out"),
350 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */ 350 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
351 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */ 351 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
352 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2, 352 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
353 SUNXI_FUNCTION(0x0, "gpio_in"), 353 SUNXI_FUNCTION(0x0, "gpio_in"),
354 SUNXI_FUNCTION(0x1, "gpio_out"), 354 SUNXI_FUNCTION(0x1, "gpio_out"),
355 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ 355 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
356 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */ 356 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
357 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3, 357 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
358 SUNXI_FUNCTION(0x0, "gpio_in"), 358 SUNXI_FUNCTION(0x0, "gpio_in"),
359 SUNXI_FUNCTION(0x1, "gpio_out"), 359 SUNXI_FUNCTION(0x1, "gpio_out"),
360 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ 360 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
361 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */ 361 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
362 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4, 362 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
363 SUNXI_FUNCTION(0x0, "gpio_in"), 363 SUNXI_FUNCTION(0x0, "gpio_in"),
364 SUNXI_FUNCTION(0x1, "gpio_out"), 364 SUNXI_FUNCTION(0x1, "gpio_out"),
365 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ 365 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
366 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */ 366 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
367 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5, 367 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
368 SUNXI_FUNCTION(0x0, "gpio_in"), 368 SUNXI_FUNCTION(0x0, "gpio_in"),
369 SUNXI_FUNCTION(0x1, "gpio_out"), 369 SUNXI_FUNCTION(0x1, "gpio_out"),
370 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ 370 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
371 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */ 371 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
372 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6, 372 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
373 SUNXI_FUNCTION(0x0, "gpio_in"), 373 SUNXI_FUNCTION(0x0, "gpio_in"),
374 SUNXI_FUNCTION(0x1, "gpio_out"), 374 SUNXI_FUNCTION(0x1, "gpio_out"),
375 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ 375 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
376 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */ 376 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
377 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7, 377 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
378 SUNXI_FUNCTION(0x0, "gpio_in"), 378 SUNXI_FUNCTION(0x0, "gpio_in"),
379 SUNXI_FUNCTION(0x1, "gpio_out"), 379 SUNXI_FUNCTION(0x1, "gpio_out"),
380 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ 380 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
381 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */ 381 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
382 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8, 382 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
383 SUNXI_FUNCTION(0x0, "gpio_in"), 383 SUNXI_FUNCTION(0x0, "gpio_in"),
384 SUNXI_FUNCTION(0x1, "gpio_out"), 384 SUNXI_FUNCTION(0x1, "gpio_out"),
385 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */ 385 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
386 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */ 386 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
387 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9, 387 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
388 SUNXI_FUNCTION(0x0, "gpio_in"), 388 SUNXI_FUNCTION(0x0, "gpio_in"),
389 SUNXI_FUNCTION(0x1, "gpio_out"), 389 SUNXI_FUNCTION(0x1, "gpio_out"),
390 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */ 390 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
391 SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */ 391 SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */
392 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10, 392 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
393 SUNXI_FUNCTION(0x0, "gpio_in"), 393 SUNXI_FUNCTION(0x0, "gpio_in"),
394 SUNXI_FUNCTION(0x1, "gpio_out"), 394 SUNXI_FUNCTION(0x1, "gpio_out"),
395 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ 395 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
396 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */ 396 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
397 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11, 397 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
398 SUNXI_FUNCTION(0x0, "gpio_in"), 398 SUNXI_FUNCTION(0x0, "gpio_in"),
399 SUNXI_FUNCTION(0x1, "gpio_out"), 399 SUNXI_FUNCTION(0x1, "gpio_out"),
400 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ 400 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
401 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */ 401 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
402 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12, 402 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
403 SUNXI_FUNCTION(0x0, "gpio_in"), 403 SUNXI_FUNCTION(0x0, "gpio_in"),
404 SUNXI_FUNCTION(0x1, "gpio_out"), 404 SUNXI_FUNCTION(0x1, "gpio_out"),
405 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ 405 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
406 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */ 406 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
407 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13, 407 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
408 SUNXI_FUNCTION(0x0, "gpio_in"), 408 SUNXI_FUNCTION(0x0, "gpio_in"),
409 SUNXI_FUNCTION(0x1, "gpio_out"), 409 SUNXI_FUNCTION(0x1, "gpio_out"),
410 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ 410 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
411 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */ 411 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
412 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14, 412 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
413 SUNXI_FUNCTION(0x0, "gpio_in"), 413 SUNXI_FUNCTION(0x0, "gpio_in"),
414 SUNXI_FUNCTION(0x1, "gpio_out"), 414 SUNXI_FUNCTION(0x1, "gpio_out"),
415 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ 415 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
416 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */ 416 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
417 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15, 417 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
418 SUNXI_FUNCTION(0x0, "gpio_in"), 418 SUNXI_FUNCTION(0x0, "gpio_in"),
419 SUNXI_FUNCTION(0x1, "gpio_out"), 419 SUNXI_FUNCTION(0x1, "gpio_out"),
420 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ 420 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
421 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */ 421 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
422 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16, 422 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
423 SUNXI_FUNCTION(0x0, "gpio_in"), 423 SUNXI_FUNCTION(0x0, "gpio_in"),
424 SUNXI_FUNCTION(0x1, "gpio_out"), 424 SUNXI_FUNCTION(0x1, "gpio_out"),
425 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */ 425 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
426 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */ 426 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
427 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17, 427 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
428 SUNXI_FUNCTION(0x0, "gpio_in"), 428 SUNXI_FUNCTION(0x0, "gpio_in"),
429 SUNXI_FUNCTION(0x1, "gpio_out"), 429 SUNXI_FUNCTION(0x1, "gpio_out"),
430 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */ 430 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
431 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */ 431 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
432 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18, 432 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
433 SUNXI_FUNCTION(0x0, "gpio_in"), 433 SUNXI_FUNCTION(0x0, "gpio_in"),
434 SUNXI_FUNCTION(0x1, "gpio_out"), 434 SUNXI_FUNCTION(0x1, "gpio_out"),
435 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ 435 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
436 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */ 436 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
437 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19, 437 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
438 SUNXI_FUNCTION(0x0, "gpio_in"), 438 SUNXI_FUNCTION(0x0, "gpio_in"),
439 SUNXI_FUNCTION(0x1, "gpio_out"), 439 SUNXI_FUNCTION(0x1, "gpio_out"),
440 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ 440 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
441 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */ 441 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
442 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20, 442 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
443 SUNXI_FUNCTION(0x0, "gpio_in"), 443 SUNXI_FUNCTION(0x0, "gpio_in"),
444 SUNXI_FUNCTION(0x1, "gpio_out"), 444 SUNXI_FUNCTION(0x1, "gpio_out"),
445 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ 445 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
446 SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */ 446 SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */
447 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21, 447 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
448 SUNXI_FUNCTION(0x0, "gpio_in"), 448 SUNXI_FUNCTION(0x0, "gpio_in"),
449 SUNXI_FUNCTION(0x1, "gpio_out"), 449 SUNXI_FUNCTION(0x1, "gpio_out"),
450 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ 450 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
451 SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */ 451 SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */
452 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22, 452 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
453 SUNXI_FUNCTION(0x0, "gpio_in"), 453 SUNXI_FUNCTION(0x0, "gpio_in"),
454 SUNXI_FUNCTION(0x1, "gpio_out"), 454 SUNXI_FUNCTION(0x1, "gpio_out"),
455 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ 455 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
456 SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */ 456 SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */
457 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23, 457 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
458 SUNXI_FUNCTION(0x0, "gpio_in"), 458 SUNXI_FUNCTION(0x0, "gpio_in"),
459 SUNXI_FUNCTION(0x1, "gpio_out"), 459 SUNXI_FUNCTION(0x1, "gpio_out"),
460 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ 460 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
461 SUNXI_FUNCTION(0x3, "sim")), /* DET */ 461 SUNXI_FUNCTION(0x3, "sim")), /* DET */
462 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24, 462 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
463 SUNXI_FUNCTION(0x0, "gpio_in"), 463 SUNXI_FUNCTION(0x0, "gpio_in"),
464 SUNXI_FUNCTION(0x1, "gpio_out"), 464 SUNXI_FUNCTION(0x1, "gpio_out"),
465 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ 465 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
466 SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */ 466 SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */
467 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25, 467 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
468 SUNXI_FUNCTION(0x0, "gpio_in"), 468 SUNXI_FUNCTION(0x0, "gpio_in"),
469 SUNXI_FUNCTION(0x1, "gpio_out"), 469 SUNXI_FUNCTION(0x1, "gpio_out"),
470 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ 470 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
471 SUNXI_FUNCTION(0x3, "sim")), /* RST */ 471 SUNXI_FUNCTION(0x3, "sim")), /* RST */
472 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26, 472 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
473 SUNXI_FUNCTION(0x0, "gpio_in"), 473 SUNXI_FUNCTION(0x0, "gpio_in"),
474 SUNXI_FUNCTION(0x1, "gpio_out"), 474 SUNXI_FUNCTION(0x1, "gpio_out"),
475 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ 475 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
476 SUNXI_FUNCTION(0x3, "sim")), /* SCK */ 476 SUNXI_FUNCTION(0x3, "sim")), /* SCK */
477 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27, 477 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
478 SUNXI_FUNCTION(0x0, "gpio_in"), 478 SUNXI_FUNCTION(0x0, "gpio_in"),
479 SUNXI_FUNCTION(0x1, "gpio_out"), 479 SUNXI_FUNCTION(0x1, "gpio_out"),
480 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ 480 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
481 SUNXI_FUNCTION(0x3, "sim")), /* SDA */ 481 SUNXI_FUNCTION(0x3, "sim")), /* SDA */
482 /* Hole */ 482 /* Hole */
483 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0, 483 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
484 SUNXI_FUNCTION(0x0, "gpio_in"), 484 SUNXI_FUNCTION(0x0, "gpio_in"),
485 SUNXI_FUNCTION(0x1, "gpio_out"), 485 SUNXI_FUNCTION(0x1, "gpio_out"),
486 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */ 486 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
487 SUNXI_FUNCTION(0x3, "csi0")), /* PCK */ 487 SUNXI_FUNCTION(0x3, "csi0")), /* PCK */
488 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1, 488 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
489 SUNXI_FUNCTION(0x0, "gpio_in"), 489 SUNXI_FUNCTION(0x0, "gpio_in"),
490 SUNXI_FUNCTION(0x1, "gpio_out"), 490 SUNXI_FUNCTION(0x1, "gpio_out"),
491 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */ 491 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
492 SUNXI_FUNCTION(0x3, "csi0")), /* CK */ 492 SUNXI_FUNCTION(0x3, "csi0")), /* CK */
493 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2, 493 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
494 SUNXI_FUNCTION(0x0, "gpio_in"), 494 SUNXI_FUNCTION(0x0, "gpio_in"),
495 SUNXI_FUNCTION(0x1, "gpio_out"), 495 SUNXI_FUNCTION(0x1, "gpio_out"),
496 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */ 496 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
497 SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */ 497 SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */
498 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3, 498 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
499 SUNXI_FUNCTION(0x0, "gpio_in"), 499 SUNXI_FUNCTION(0x0, "gpio_in"),
500 SUNXI_FUNCTION(0x1, "gpio_out"), 500 SUNXI_FUNCTION(0x1, "gpio_out"),
501 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */ 501 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
502 SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */ 502 SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */
503 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4, 503 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
504 SUNXI_FUNCTION(0x0, "gpio_in"), 504 SUNXI_FUNCTION(0x0, "gpio_in"),
505 SUNXI_FUNCTION(0x1, "gpio_out"), 505 SUNXI_FUNCTION(0x1, "gpio_out"),
506 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */ 506 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
507 SUNXI_FUNCTION(0x3, "csi0")), /* D0 */ 507 SUNXI_FUNCTION(0x3, "csi0")), /* D0 */
508 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5, 508 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
509 SUNXI_FUNCTION(0x0, "gpio_in"), 509 SUNXI_FUNCTION(0x0, "gpio_in"),
510 SUNXI_FUNCTION(0x1, "gpio_out"), 510 SUNXI_FUNCTION(0x1, "gpio_out"),
511 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */ 511 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
512 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */ 512 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
513 SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */ 513 SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */
514 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6, 514 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
515 SUNXI_FUNCTION(0x0, "gpio_in"), 515 SUNXI_FUNCTION(0x0, "gpio_in"),
516 SUNXI_FUNCTION(0x1, "gpio_out"), 516 SUNXI_FUNCTION(0x1, "gpio_out"),
517 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */ 517 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
518 SUNXI_FUNCTION(0x3, "csi0")), /* D2 */ 518 SUNXI_FUNCTION(0x3, "csi0")), /* D2 */
519 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7, 519 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
520 SUNXI_FUNCTION(0x0, "gpio_in"), 520 SUNXI_FUNCTION(0x0, "gpio_in"),
521 SUNXI_FUNCTION(0x1, "gpio_out"), 521 SUNXI_FUNCTION(0x1, "gpio_out"),
522 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */ 522 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
523 SUNXI_FUNCTION(0x3, "csi0")), /* D3 */ 523 SUNXI_FUNCTION(0x3, "csi0")), /* D3 */
524 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8, 524 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
525 SUNXI_FUNCTION(0x0, "gpio_in"), 525 SUNXI_FUNCTION(0x0, "gpio_in"),
526 SUNXI_FUNCTION(0x1, "gpio_out"), 526 SUNXI_FUNCTION(0x1, "gpio_out"),
527 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */ 527 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
528 SUNXI_FUNCTION(0x3, "csi0")), /* D4 */ 528 SUNXI_FUNCTION(0x3, "csi0")), /* D4 */
529 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9, 529 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
530 SUNXI_FUNCTION(0x0, "gpio_in"), 530 SUNXI_FUNCTION(0x0, "gpio_in"),
531 SUNXI_FUNCTION(0x1, "gpio_out"), 531 SUNXI_FUNCTION(0x1, "gpio_out"),
532 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */ 532 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
533 SUNXI_FUNCTION(0x3, "csi0")), /* D5 */ 533 SUNXI_FUNCTION(0x3, "csi0")), /* D5 */
534 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10, 534 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
535 SUNXI_FUNCTION(0x0, "gpio_in"), 535 SUNXI_FUNCTION(0x0, "gpio_in"),
536 SUNXI_FUNCTION(0x1, "gpio_out"), 536 SUNXI_FUNCTION(0x1, "gpio_out"),
537 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */ 537 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
538 SUNXI_FUNCTION(0x3, "csi0")), /* D6 */ 538 SUNXI_FUNCTION(0x3, "csi0")), /* D6 */
539 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11, 539 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
540 SUNXI_FUNCTION(0x0, "gpio_in"), 540 SUNXI_FUNCTION(0x0, "gpio_in"),
541 SUNXI_FUNCTION(0x1, "gpio_out"), 541 SUNXI_FUNCTION(0x1, "gpio_out"),
542 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */ 542 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
543 SUNXI_FUNCTION(0x3, "csi0")), /* D7 */ 543 SUNXI_FUNCTION(0x3, "csi0")), /* D7 */
544 /* Hole */ 544 /* Hole */
545 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0, 545 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
546 SUNXI_FUNCTION(0x0, "gpio_in"), 546 SUNXI_FUNCTION(0x0, "gpio_in"),
547 SUNXI_FUNCTION(0x1, "gpio_out"), 547 SUNXI_FUNCTION(0x1, "gpio_out"),
548 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ 548 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
549 SUNXI_FUNCTION(0x4, "jtag")), /* MSI */ 549 SUNXI_FUNCTION(0x4, "jtag")), /* MSI */
550 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1, 550 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
551 SUNXI_FUNCTION(0x0, "gpio_in"), 551 SUNXI_FUNCTION(0x0, "gpio_in"),
552 SUNXI_FUNCTION(0x1, "gpio_out"), 552 SUNXI_FUNCTION(0x1, "gpio_out"),
553 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ 553 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
554 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */ 554 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
555 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2, 555 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
556 SUNXI_FUNCTION(0x0, "gpio_in"), 556 SUNXI_FUNCTION(0x0, "gpio_in"),
557 SUNXI_FUNCTION(0x1, "gpio_out"), 557 SUNXI_FUNCTION(0x1, "gpio_out"),
558 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ 558 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
559 SUNXI_FUNCTION(0x4, "uart0")), /* TX */ 559 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
560 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3, 560 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
561 SUNXI_FUNCTION(0x0, "gpio_in"), 561 SUNXI_FUNCTION(0x0, "gpio_in"),
562 SUNXI_FUNCTION(0x1, "gpio_out"), 562 SUNXI_FUNCTION(0x1, "gpio_out"),
563 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ 563 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
564 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */ 564 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
565 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4, 565 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
566 SUNXI_FUNCTION(0x0, "gpio_in"), 566 SUNXI_FUNCTION(0x0, "gpio_in"),
567 SUNXI_FUNCTION(0x1, "gpio_out"), 567 SUNXI_FUNCTION(0x1, "gpio_out"),
568 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ 568 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
569 SUNXI_FUNCTION(0x4, "uart0")), /* RX */ 569 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
570 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5, 570 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
571 SUNXI_FUNCTION(0x0, "gpio_in"), 571 SUNXI_FUNCTION(0x0, "gpio_in"),
572 SUNXI_FUNCTION(0x1, "gpio_out"), 572 SUNXI_FUNCTION(0x1, "gpio_out"),
573 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ 573 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
574 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */ 574 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
575 /* Hole */ 575 /* Hole */
576 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0, 576 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
577 SUNXI_FUNCTION(0x0, "gpio_in"), 577 SUNXI_FUNCTION(0x0, "gpio_in"),
578 SUNXI_FUNCTION(0x1, "gpio_out"), 578 SUNXI_FUNCTION(0x1, "gpio_out"),
579 SUNXI_FUNCTION(0x2, "ts1"), /* CLK */ 579 SUNXI_FUNCTION(0x2, "ts1"), /* CLK */
580 SUNXI_FUNCTION(0x3, "csi1"), /* PCK */ 580 SUNXI_FUNCTION(0x3, "csi1"), /* PCK */
581 SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */ 581 SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */
582 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1, 582 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
583 SUNXI_FUNCTION(0x0, "gpio_in"), 583 SUNXI_FUNCTION(0x0, "gpio_in"),
584 SUNXI_FUNCTION(0x1, "gpio_out"), 584 SUNXI_FUNCTION(0x1, "gpio_out"),
585 SUNXI_FUNCTION(0x2, "ts1"), /* ERR */ 585 SUNXI_FUNCTION(0x2, "ts1"), /* ERR */
586 SUNXI_FUNCTION(0x3, "csi1"), /* CK */ 586 SUNXI_FUNCTION(0x3, "csi1"), /* CK */
587 SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */ 587 SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */
588 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2, 588 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
589 SUNXI_FUNCTION(0x0, "gpio_in"), 589 SUNXI_FUNCTION(0x0, "gpio_in"),
590 SUNXI_FUNCTION(0x1, "gpio_out"), 590 SUNXI_FUNCTION(0x1, "gpio_out"),
591 SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */ 591 SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */
592 SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */ 592 SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */
593 SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */ 593 SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */
594 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3, 594 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
595 SUNXI_FUNCTION(0x0, "gpio_in"), 595 SUNXI_FUNCTION(0x0, "gpio_in"),
596 SUNXI_FUNCTION(0x1, "gpio_out"), 596 SUNXI_FUNCTION(0x1, "gpio_out"),
597 SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */ 597 SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */
598 SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */ 598 SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */
599 SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */ 599 SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */
600 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4, 600 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
601 SUNXI_FUNCTION(0x0, "gpio_in"), 601 SUNXI_FUNCTION(0x0, "gpio_in"),
602 SUNXI_FUNCTION(0x1, "gpio_out"), 602 SUNXI_FUNCTION(0x1, "gpio_out"),
603 SUNXI_FUNCTION(0x2, "ts1"), /* D0 */ 603 SUNXI_FUNCTION(0x2, "ts1"), /* D0 */
604 SUNXI_FUNCTION(0x3, "csi1"), /* D0 */ 604 SUNXI_FUNCTION(0x3, "csi1"), /* D0 */
605 SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */ 605 SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */
606 SUNXI_FUNCTION(0x5, "csi0")), /* D8 */ 606 SUNXI_FUNCTION(0x5, "csi0")), /* D8 */
607 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5, 607 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
608 SUNXI_FUNCTION(0x0, "gpio_in"), 608 SUNXI_FUNCTION(0x0, "gpio_in"),
609 SUNXI_FUNCTION(0x1, "gpio_out"), 609 SUNXI_FUNCTION(0x1, "gpio_out"),
610 SUNXI_FUNCTION(0x2, "ts1"), /* D1 */ 610 SUNXI_FUNCTION(0x2, "ts1"), /* D1 */
611 SUNXI_FUNCTION(0x3, "csi1"), /* D1 */ 611 SUNXI_FUNCTION(0x3, "csi1"), /* D1 */
612 SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */ 612 SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */
613 SUNXI_FUNCTION(0x5, "csi0")), /* D9 */ 613 SUNXI_FUNCTION(0x5, "csi0")), /* D9 */
614 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6, 614 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
615 SUNXI_FUNCTION(0x0, "gpio_in"), 615 SUNXI_FUNCTION(0x0, "gpio_in"),
616 SUNXI_FUNCTION(0x1, "gpio_out"), 616 SUNXI_FUNCTION(0x1, "gpio_out"),
617 SUNXI_FUNCTION(0x2, "ts1"), /* D2 */ 617 SUNXI_FUNCTION(0x2, "ts1"), /* D2 */
618 SUNXI_FUNCTION(0x3, "csi1"), /* D2 */ 618 SUNXI_FUNCTION(0x3, "csi1"), /* D2 */
619 SUNXI_FUNCTION(0x4, "uart3"), /* TX */ 619 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
620 SUNXI_FUNCTION(0x5, "csi0")), /* D10 */ 620 SUNXI_FUNCTION(0x5, "csi0")), /* D10 */
621 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7, 621 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
622 SUNXI_FUNCTION(0x0, "gpio_in"), 622 SUNXI_FUNCTION(0x0, "gpio_in"),
623 SUNXI_FUNCTION(0x1, "gpio_out"), 623 SUNXI_FUNCTION(0x1, "gpio_out"),
624 SUNXI_FUNCTION(0x2, "ts1"), /* D3 */ 624 SUNXI_FUNCTION(0x2, "ts1"), /* D3 */
625 SUNXI_FUNCTION(0x3, "csi1"), /* D3 */ 625 SUNXI_FUNCTION(0x3, "csi1"), /* D3 */
626 SUNXI_FUNCTION(0x4, "uart3"), /* RX */ 626 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
627 SUNXI_FUNCTION(0x5, "csi0")), /* D11 */ 627 SUNXI_FUNCTION(0x5, "csi0")), /* D11 */
628 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8, 628 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
629 SUNXI_FUNCTION(0x0, "gpio_in"), 629 SUNXI_FUNCTION(0x0, "gpio_in"),
630 SUNXI_FUNCTION(0x1, "gpio_out"), 630 SUNXI_FUNCTION(0x1, "gpio_out"),
631 SUNXI_FUNCTION(0x2, "ts1"), /* D4 */ 631 SUNXI_FUNCTION(0x2, "ts1"), /* D4 */
632 SUNXI_FUNCTION(0x3, "csi1"), /* D4 */ 632 SUNXI_FUNCTION(0x3, "csi1"), /* D4 */
633 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ 633 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
634 SUNXI_FUNCTION(0x5, "csi0")), /* D12 */ 634 SUNXI_FUNCTION(0x5, "csi0")), /* D12 */
635 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9, 635 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
636 SUNXI_FUNCTION(0x0, "gpio_in"), 636 SUNXI_FUNCTION(0x0, "gpio_in"),
637 SUNXI_FUNCTION(0x1, "gpio_out"), 637 SUNXI_FUNCTION(0x1, "gpio_out"),
638 SUNXI_FUNCTION(0x2, "ts1"), /* D5 */ 638 SUNXI_FUNCTION(0x2, "ts1"), /* D5 */
639 SUNXI_FUNCTION(0x3, "csi1"), /* D5 */ 639 SUNXI_FUNCTION(0x3, "csi1"), /* D5 */
640 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ 640 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
641 SUNXI_FUNCTION(0x5, "csi0")), /* D13 */ 641 SUNXI_FUNCTION(0x5, "csi0")), /* D13 */
642 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10, 642 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
643 SUNXI_FUNCTION(0x0, "gpio_in"), 643 SUNXI_FUNCTION(0x0, "gpio_in"),
644 SUNXI_FUNCTION(0x1, "gpio_out"), 644 SUNXI_FUNCTION(0x1, "gpio_out"),
645 SUNXI_FUNCTION(0x2, "ts1"), /* D6 */ 645 SUNXI_FUNCTION(0x2, "ts1"), /* D6 */
646 SUNXI_FUNCTION(0x3, "csi1"), /* D6 */ 646 SUNXI_FUNCTION(0x3, "csi1"), /* D6 */
647 SUNXI_FUNCTION(0x4, "uart4"), /* TX */ 647 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
648 SUNXI_FUNCTION(0x5, "csi0")), /* D14 */ 648 SUNXI_FUNCTION(0x5, "csi0")), /* D14 */
649 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11, 649 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
650 SUNXI_FUNCTION(0x0, "gpio_in"), 650 SUNXI_FUNCTION(0x0, "gpio_in"),
651 SUNXI_FUNCTION(0x1, "gpio_out"), 651 SUNXI_FUNCTION(0x1, "gpio_out"),
652 SUNXI_FUNCTION(0x2, "ts1"), /* D7 */ 652 SUNXI_FUNCTION(0x2, "ts1"), /* D7 */
@@ -654,7 +654,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
654 SUNXI_FUNCTION(0x4, "uart4"), /* RX */ 654 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
655 SUNXI_FUNCTION(0x5, "csi0")), /* D15 */ 655 SUNXI_FUNCTION(0x5, "csi0")), /* D15 */
656 /* Hole */ 656 /* Hole */
657 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0, 657 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
658 SUNXI_FUNCTION(0x0, "gpio_in"), 658 SUNXI_FUNCTION(0x0, "gpio_in"),
659 SUNXI_FUNCTION(0x1, "gpio_out"), 659 SUNXI_FUNCTION(0x1, "gpio_out"),
660 SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */ 660 SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */
@@ -662,7 +662,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
662 SUNXI_FUNCTION(0x4, "uart3"), /* TX */ 662 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
663 SUNXI_FUNCTION_IRQ(0x6, 0), /* EINT0 */ 663 SUNXI_FUNCTION_IRQ(0x6, 0), /* EINT0 */
664 SUNXI_FUNCTION(0x7, "csi1")), /* D0 */ 664 SUNXI_FUNCTION(0x7, "csi1")), /* D0 */
665 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1, 665 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
666 SUNXI_FUNCTION(0x0, "gpio_in"), 666 SUNXI_FUNCTION(0x0, "gpio_in"),
667 SUNXI_FUNCTION(0x1, "gpio_out"), 667 SUNXI_FUNCTION(0x1, "gpio_out"),
668 SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */ 668 SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */
@@ -670,7 +670,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
670 SUNXI_FUNCTION(0x4, "uart3"), /* RX */ 670 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
671 SUNXI_FUNCTION_IRQ(0x6, 1), /* EINT1 */ 671 SUNXI_FUNCTION_IRQ(0x6, 1), /* EINT1 */
672 SUNXI_FUNCTION(0x7, "csi1")), /* D1 */ 672 SUNXI_FUNCTION(0x7, "csi1")), /* D1 */
673 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2, 673 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
674 SUNXI_FUNCTION(0x0, "gpio_in"), 674 SUNXI_FUNCTION(0x0, "gpio_in"),
675 SUNXI_FUNCTION(0x1, "gpio_out"), 675 SUNXI_FUNCTION(0x1, "gpio_out"),
676 SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */ 676 SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */
@@ -678,7 +678,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
678 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ 678 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
679 SUNXI_FUNCTION_IRQ(0x6, 2), /* EINT2 */ 679 SUNXI_FUNCTION_IRQ(0x6, 2), /* EINT2 */
680 SUNXI_FUNCTION(0x7, "csi1")), /* D2 */ 680 SUNXI_FUNCTION(0x7, "csi1")), /* D2 */
681 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3, 681 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
682 SUNXI_FUNCTION(0x0, "gpio_in"), 682 SUNXI_FUNCTION(0x0, "gpio_in"),
683 SUNXI_FUNCTION(0x1, "gpio_out"), 683 SUNXI_FUNCTION(0x1, "gpio_out"),
684 SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */ 684 SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */
@@ -686,7 +686,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
686 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ 686 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
687 SUNXI_FUNCTION_IRQ(0x6, 3), /* EINT3 */ 687 SUNXI_FUNCTION_IRQ(0x6, 3), /* EINT3 */
688 SUNXI_FUNCTION(0x7, "csi1")), /* D3 */ 688 SUNXI_FUNCTION(0x7, "csi1")), /* D3 */
689 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4, 689 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
690 SUNXI_FUNCTION(0x0, "gpio_in"), 690 SUNXI_FUNCTION(0x0, "gpio_in"),
691 SUNXI_FUNCTION(0x1, "gpio_out"), 691 SUNXI_FUNCTION(0x1, "gpio_out"),
692 SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */ 692 SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */
@@ -694,7 +694,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
694 SUNXI_FUNCTION(0x4, "uart4"), /* TX */ 694 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
695 SUNXI_FUNCTION_IRQ(0x6, 4), /* EINT4 */ 695 SUNXI_FUNCTION_IRQ(0x6, 4), /* EINT4 */
696 SUNXI_FUNCTION(0x7, "csi1")), /* D4 */ 696 SUNXI_FUNCTION(0x7, "csi1")), /* D4 */
697 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5, 697 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
698 SUNXI_FUNCTION(0x0, "gpio_in"), 698 SUNXI_FUNCTION(0x0, "gpio_in"),
699 SUNXI_FUNCTION(0x1, "gpio_out"), 699 SUNXI_FUNCTION(0x1, "gpio_out"),
700 SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */ 700 SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */
@@ -702,7 +702,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
702 SUNXI_FUNCTION(0x4, "uart4"), /* RX */ 702 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
703 SUNXI_FUNCTION_IRQ(0x6, 5), /* EINT5 */ 703 SUNXI_FUNCTION_IRQ(0x6, 5), /* EINT5 */
704 SUNXI_FUNCTION(0x7, "csi1")), /* D5 */ 704 SUNXI_FUNCTION(0x7, "csi1")), /* D5 */
705 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6, 705 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
706 SUNXI_FUNCTION(0x0, "gpio_in"), 706 SUNXI_FUNCTION(0x0, "gpio_in"),
707 SUNXI_FUNCTION(0x1, "gpio_out"), 707 SUNXI_FUNCTION(0x1, "gpio_out"),
708 SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */ 708 SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */
@@ -711,7 +711,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
711 SUNXI_FUNCTION(0x5, "ms"), /* BS */ 711 SUNXI_FUNCTION(0x5, "ms"), /* BS */
712 SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */ 712 SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */
713 SUNXI_FUNCTION(0x7, "csi1")), /* D6 */ 713 SUNXI_FUNCTION(0x7, "csi1")), /* D6 */
714 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7, 714 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
715 SUNXI_FUNCTION(0x0, "gpio_in"), 715 SUNXI_FUNCTION(0x0, "gpio_in"),
716 SUNXI_FUNCTION(0x1, "gpio_out"), 716 SUNXI_FUNCTION(0x1, "gpio_out"),
717 SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */ 717 SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */
@@ -720,7 +720,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
720 SUNXI_FUNCTION(0x5, "ms"), /* CLK */ 720 SUNXI_FUNCTION(0x5, "ms"), /* CLK */
721 SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */ 721 SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */
722 SUNXI_FUNCTION(0x7, "csi1")), /* D7 */ 722 SUNXI_FUNCTION(0x7, "csi1")), /* D7 */
723 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8, 723 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
724 SUNXI_FUNCTION(0x0, "gpio_in"), 724 SUNXI_FUNCTION(0x0, "gpio_in"),
725 SUNXI_FUNCTION(0x1, "gpio_out"), 725 SUNXI_FUNCTION(0x1, "gpio_out"),
726 SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */ 726 SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */
@@ -729,7 +729,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
729 SUNXI_FUNCTION(0x5, "ms"), /* D0 */ 729 SUNXI_FUNCTION(0x5, "ms"), /* D0 */
730 SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */ 730 SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */
731 SUNXI_FUNCTION(0x7, "csi1")), /* D8 */ 731 SUNXI_FUNCTION(0x7, "csi1")), /* D8 */
732 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9, 732 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
733 SUNXI_FUNCTION(0x0, "gpio_in"), 733 SUNXI_FUNCTION(0x0, "gpio_in"),
734 SUNXI_FUNCTION(0x1, "gpio_out"), 734 SUNXI_FUNCTION(0x1, "gpio_out"),
735 SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */ 735 SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */
@@ -738,7 +738,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
738 SUNXI_FUNCTION(0x5, "ms"), /* D1 */ 738 SUNXI_FUNCTION(0x5, "ms"), /* D1 */
739 SUNXI_FUNCTION_IRQ(0x6, 9), /* EINT9 */ 739 SUNXI_FUNCTION_IRQ(0x6, 9), /* EINT9 */
740 SUNXI_FUNCTION(0x7, "csi1")), /* D9 */ 740 SUNXI_FUNCTION(0x7, "csi1")), /* D9 */
741 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10, 741 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
742 SUNXI_FUNCTION(0x0, "gpio_in"), 742 SUNXI_FUNCTION(0x0, "gpio_in"),
743 SUNXI_FUNCTION(0x1, "gpio_out"), 743 SUNXI_FUNCTION(0x1, "gpio_out"),
744 SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */ 744 SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */
@@ -747,7 +747,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
747 SUNXI_FUNCTION(0x5, "ms"), /* D2 */ 747 SUNXI_FUNCTION(0x5, "ms"), /* D2 */
748 SUNXI_FUNCTION_IRQ(0x6, 10), /* EINT10 */ 748 SUNXI_FUNCTION_IRQ(0x6, 10), /* EINT10 */
749 SUNXI_FUNCTION(0x7, "csi1")), /* D10 */ 749 SUNXI_FUNCTION(0x7, "csi1")), /* D10 */
750 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11, 750 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
751 SUNXI_FUNCTION(0x0, "gpio_in"), 751 SUNXI_FUNCTION(0x0, "gpio_in"),
752 SUNXI_FUNCTION(0x1, "gpio_out"), 752 SUNXI_FUNCTION(0x1, "gpio_out"),
753 SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */ 753 SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */
@@ -756,7 +756,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
756 SUNXI_FUNCTION(0x5, "ms"), /* D3 */ 756 SUNXI_FUNCTION(0x5, "ms"), /* D3 */
757 SUNXI_FUNCTION_IRQ(0x6, 11), /* EINT11 */ 757 SUNXI_FUNCTION_IRQ(0x6, 11), /* EINT11 */
758 SUNXI_FUNCTION(0x7, "csi1")), /* D11 */ 758 SUNXI_FUNCTION(0x7, "csi1")), /* D11 */
759 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12, 759 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
760 SUNXI_FUNCTION(0x0, "gpio_in"), 760 SUNXI_FUNCTION(0x0, "gpio_in"),
761 SUNXI_FUNCTION(0x1, "gpio_out"), 761 SUNXI_FUNCTION(0x1, "gpio_out"),
762 SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */ 762 SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */
@@ -764,7 +764,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
764 SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */ 764 SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */
765 SUNXI_FUNCTION_IRQ(0x6, 12), /* EINT12 */ 765 SUNXI_FUNCTION_IRQ(0x6, 12), /* EINT12 */
766 SUNXI_FUNCTION(0x7, "csi1")), /* D12 */ 766 SUNXI_FUNCTION(0x7, "csi1")), /* D12 */
767 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13, 767 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
768 SUNXI_FUNCTION(0x0, "gpio_in"), 768 SUNXI_FUNCTION(0x0, "gpio_in"),
769 SUNXI_FUNCTION(0x1, "gpio_out"), 769 SUNXI_FUNCTION(0x1, "gpio_out"),
770 SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */ 770 SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */
@@ -773,7 +773,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
773 SUNXI_FUNCTION(0x5, "sim"), /* RST */ 773 SUNXI_FUNCTION(0x5, "sim"), /* RST */
774 SUNXI_FUNCTION_IRQ(0x6, 13), /* EINT13 */ 774 SUNXI_FUNCTION_IRQ(0x6, 13), /* EINT13 */
775 SUNXI_FUNCTION(0x7, "csi1")), /* D13 */ 775 SUNXI_FUNCTION(0x7, "csi1")), /* D13 */
776 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14, 776 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
777 SUNXI_FUNCTION(0x0, "gpio_in"), 777 SUNXI_FUNCTION(0x0, "gpio_in"),
778 SUNXI_FUNCTION(0x1, "gpio_out"), 778 SUNXI_FUNCTION(0x1, "gpio_out"),
779 SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */ 779 SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */
@@ -782,7 +782,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
782 SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */ 782 SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */
783 SUNXI_FUNCTION_IRQ(0x6, 14), /* EINT14 */ 783 SUNXI_FUNCTION_IRQ(0x6, 14), /* EINT14 */
784 SUNXI_FUNCTION(0x7, "csi1")), /* D14 */ 784 SUNXI_FUNCTION(0x7, "csi1")), /* D14 */
785 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15, 785 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
786 SUNXI_FUNCTION(0x0, "gpio_in"), 786 SUNXI_FUNCTION(0x0, "gpio_in"),
787 SUNXI_FUNCTION(0x1, "gpio_out"), 787 SUNXI_FUNCTION(0x1, "gpio_out"),
788 SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */ 788 SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */
@@ -791,7 +791,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
791 SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */ 791 SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */
792 SUNXI_FUNCTION_IRQ(0x6, 15), /* EINT15 */ 792 SUNXI_FUNCTION_IRQ(0x6, 15), /* EINT15 */
793 SUNXI_FUNCTION(0x7, "csi1")), /* D15 */ 793 SUNXI_FUNCTION(0x7, "csi1")), /* D15 */
794 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16, 794 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
795 SUNXI_FUNCTION(0x0, "gpio_in"), 795 SUNXI_FUNCTION(0x0, "gpio_in"),
796 SUNXI_FUNCTION(0x1, "gpio_out"), 796 SUNXI_FUNCTION(0x1, "gpio_out"),
797 SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */ 797 SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */
@@ -799,7 +799,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
799 SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */ 799 SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */
800 SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */ 800 SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */
801 SUNXI_FUNCTION(0x7, "csi1")), /* D16 */ 801 SUNXI_FUNCTION(0x7, "csi1")), /* D16 */
802 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17, 802 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
803 SUNXI_FUNCTION(0x0, "gpio_in"), 803 SUNXI_FUNCTION(0x0, "gpio_in"),
804 SUNXI_FUNCTION(0x1, "gpio_out"), 804 SUNXI_FUNCTION(0x1, "gpio_out"),
805 SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */ 805 SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */
@@ -808,7 +808,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
808 SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */ 808 SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */
809 SUNXI_FUNCTION_IRQ(0x6, 17), /* EINT17 */ 809 SUNXI_FUNCTION_IRQ(0x6, 17), /* EINT17 */
810 SUNXI_FUNCTION(0x7, "csi1")), /* D17 */ 810 SUNXI_FUNCTION(0x7, "csi1")), /* D17 */
811 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18, 811 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
812 SUNXI_FUNCTION(0x0, "gpio_in"), 812 SUNXI_FUNCTION(0x0, "gpio_in"),
813 SUNXI_FUNCTION(0x1, "gpio_out"), 813 SUNXI_FUNCTION(0x1, "gpio_out"),
814 SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */ 814 SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */
@@ -817,7 +817,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
817 SUNXI_FUNCTION(0x5, "sim"), /* SCK */ 817 SUNXI_FUNCTION(0x5, "sim"), /* SCK */
818 SUNXI_FUNCTION_IRQ(0x6, 18), /* EINT18 */ 818 SUNXI_FUNCTION_IRQ(0x6, 18), /* EINT18 */
819 SUNXI_FUNCTION(0x7, "csi1")), /* D18 */ 819 SUNXI_FUNCTION(0x7, "csi1")), /* D18 */
820 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19, 820 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
821 SUNXI_FUNCTION(0x0, "gpio_in"), 821 SUNXI_FUNCTION(0x0, "gpio_in"),
822 SUNXI_FUNCTION(0x1, "gpio_out"), 822 SUNXI_FUNCTION(0x1, "gpio_out"),
823 SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */ 823 SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */
@@ -826,7 +826,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
826 SUNXI_FUNCTION(0x5, "sim"), /* SDA */ 826 SUNXI_FUNCTION(0x5, "sim"), /* SDA */
827 SUNXI_FUNCTION_IRQ(0x6, 19), /* EINT19 */ 827 SUNXI_FUNCTION_IRQ(0x6, 19), /* EINT19 */
828 SUNXI_FUNCTION(0x7, "csi1")), /* D19 */ 828 SUNXI_FUNCTION(0x7, "csi1")), /* D19 */
829 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20, 829 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
830 SUNXI_FUNCTION(0x0, "gpio_in"), 830 SUNXI_FUNCTION(0x0, "gpio_in"),
831 SUNXI_FUNCTION(0x1, "gpio_out"), 831 SUNXI_FUNCTION(0x1, "gpio_out"),
832 SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */ 832 SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */
@@ -834,7 +834,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
834 SUNXI_FUNCTION(0x4, "can"), /* TX */ 834 SUNXI_FUNCTION(0x4, "can"), /* TX */
835 SUNXI_FUNCTION_IRQ(0x6, 20), /* EINT20 */ 835 SUNXI_FUNCTION_IRQ(0x6, 20), /* EINT20 */
836 SUNXI_FUNCTION(0x7, "csi1")), /* D20 */ 836 SUNXI_FUNCTION(0x7, "csi1")), /* D20 */
837 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21, 837 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
838 SUNXI_FUNCTION(0x0, "gpio_in"), 838 SUNXI_FUNCTION(0x0, "gpio_in"),
839 SUNXI_FUNCTION(0x1, "gpio_out"), 839 SUNXI_FUNCTION(0x1, "gpio_out"),
840 SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */ 840 SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */
@@ -842,7 +842,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
842 SUNXI_FUNCTION(0x4, "can"), /* RX */ 842 SUNXI_FUNCTION(0x4, "can"), /* RX */
843 SUNXI_FUNCTION_IRQ(0x6, 21), /* EINT21 */ 843 SUNXI_FUNCTION_IRQ(0x6, 21), /* EINT21 */
844 SUNXI_FUNCTION(0x7, "csi1")), /* D21 */ 844 SUNXI_FUNCTION(0x7, "csi1")), /* D21 */
845 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22, 845 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22),
846 SUNXI_FUNCTION(0x0, "gpio_in"), 846 SUNXI_FUNCTION(0x0, "gpio_in"),
847 SUNXI_FUNCTION(0x1, "gpio_out"), 847 SUNXI_FUNCTION(0x1, "gpio_out"),
848 SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */ 848 SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */
@@ -850,7 +850,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
850 SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */ 850 SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */
851 SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */ 851 SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */
852 SUNXI_FUNCTION(0x7, "csi1")), /* D22 */ 852 SUNXI_FUNCTION(0x7, "csi1")), /* D22 */
853 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23, 853 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23),
854 SUNXI_FUNCTION(0x0, "gpio_in"), 854 SUNXI_FUNCTION(0x0, "gpio_in"),
855 SUNXI_FUNCTION(0x1, "gpio_out"), 855 SUNXI_FUNCTION(0x1, "gpio_out"),
856 SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */ 856 SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */
@@ -858,7 +858,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
858 SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */ 858 SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */
859 SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */ 859 SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */
860 SUNXI_FUNCTION(0x7, "csi1")), /* D23 */ 860 SUNXI_FUNCTION(0x7, "csi1")), /* D23 */
861 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24, 861 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24),
862 SUNXI_FUNCTION(0x0, "gpio_in"), 862 SUNXI_FUNCTION(0x0, "gpio_in"),
863 SUNXI_FUNCTION(0x1, "gpio_out"), 863 SUNXI_FUNCTION(0x1, "gpio_out"),
864 SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */ 864 SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */
@@ -866,7 +866,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
866 SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */ 866 SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */
867 SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */ 867 SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */
868 SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */ 868 SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */
869 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25, 869 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25),
870 SUNXI_FUNCTION(0x0, "gpio_in"), 870 SUNXI_FUNCTION(0x0, "gpio_in"),
871 SUNXI_FUNCTION(0x1, "gpio_out"), 871 SUNXI_FUNCTION(0x1, "gpio_out"),
872 SUNXI_FUNCTION(0x2, "lcd1"), /* DE */ 872 SUNXI_FUNCTION(0x2, "lcd1"), /* DE */
@@ -874,7 +874,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
874 SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */ 874 SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */
875 SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */ 875 SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */
876 SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */ 876 SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */
877 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26, 877 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26),
878 SUNXI_FUNCTION(0x0, "gpio_in"), 878 SUNXI_FUNCTION(0x0, "gpio_in"),
879 SUNXI_FUNCTION(0x1, "gpio_out"), 879 SUNXI_FUNCTION(0x1, "gpio_out"),
880 SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */ 880 SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */
@@ -882,7 +882,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
882 SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */ 882 SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */
883 SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */ 883 SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */
884 SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */ 884 SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */
885 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27, 885 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27),
886 SUNXI_FUNCTION(0x0, "gpio_in"), 886 SUNXI_FUNCTION(0x0, "gpio_in"),
887 SUNXI_FUNCTION(0x1, "gpio_out"), 887 SUNXI_FUNCTION(0x1, "gpio_out"),
888 SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */ 888 SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */
@@ -891,112 +891,112 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
891 SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */ 891 SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */
892 SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */ 892 SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */
893 /* Hole */ 893 /* Hole */
894 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0, 894 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 0),
895 SUNXI_FUNCTION(0x0, "gpio_in"), 895 SUNXI_FUNCTION(0x0, "gpio_in"),
896 SUNXI_FUNCTION(0x1, "gpio_out")), 896 SUNXI_FUNCTION(0x1, "gpio_out")),
897 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI1, 897 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 1),
898 SUNXI_FUNCTION(0x0, "gpio_in"), 898 SUNXI_FUNCTION(0x0, "gpio_in"),
899 SUNXI_FUNCTION(0x1, "gpio_out")), 899 SUNXI_FUNCTION(0x1, "gpio_out")),
900 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI2, 900 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 2),
901 SUNXI_FUNCTION(0x0, "gpio_in"), 901 SUNXI_FUNCTION(0x0, "gpio_in"),
902 SUNXI_FUNCTION(0x1, "gpio_out")), 902 SUNXI_FUNCTION(0x1, "gpio_out")),
903 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3, 903 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 3),
904 SUNXI_FUNCTION(0x0, "gpio_in"), 904 SUNXI_FUNCTION(0x0, "gpio_in"),
905 SUNXI_FUNCTION(0x1, "gpio_out"), 905 SUNXI_FUNCTION(0x1, "gpio_out"),
906 SUNXI_FUNCTION(0x2, "pwm")), /* PWM1 */ 906 SUNXI_FUNCTION(0x2, "pwm")), /* PWM1 */
907 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4, 907 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 4),
908 SUNXI_FUNCTION(0x0, "gpio_in"), 908 SUNXI_FUNCTION(0x0, "gpio_in"),
909 SUNXI_FUNCTION(0x1, "gpio_out"), 909 SUNXI_FUNCTION(0x1, "gpio_out"),
910 SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */ 910 SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */
911 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5, 911 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 5),
912 SUNXI_FUNCTION(0x0, "gpio_in"), 912 SUNXI_FUNCTION(0x0, "gpio_in"),
913 SUNXI_FUNCTION(0x1, "gpio_out"), 913 SUNXI_FUNCTION(0x1, "gpio_out"),
914 SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */ 914 SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */
915 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6, 915 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 6),
916 SUNXI_FUNCTION(0x0, "gpio_in"), 916 SUNXI_FUNCTION(0x0, "gpio_in"),
917 SUNXI_FUNCTION(0x1, "gpio_out"), 917 SUNXI_FUNCTION(0x1, "gpio_out"),
918 SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */ 918 SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */
919 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7, 919 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 7),
920 SUNXI_FUNCTION(0x0, "gpio_in"), 920 SUNXI_FUNCTION(0x0, "gpio_in"),
921 SUNXI_FUNCTION(0x1, "gpio_out"), 921 SUNXI_FUNCTION(0x1, "gpio_out"),
922 SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */ 922 SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */
923 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8, 923 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 8),
924 SUNXI_FUNCTION(0x0, "gpio_in"), 924 SUNXI_FUNCTION(0x0, "gpio_in"),
925 SUNXI_FUNCTION(0x1, "gpio_out"), 925 SUNXI_FUNCTION(0x1, "gpio_out"),
926 SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */ 926 SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */
927 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9, 927 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 9),
928 SUNXI_FUNCTION(0x0, "gpio_in"), 928 SUNXI_FUNCTION(0x0, "gpio_in"),
929 SUNXI_FUNCTION(0x1, "gpio_out"), 929 SUNXI_FUNCTION(0x1, "gpio_out"),
930 SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */ 930 SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */
931 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10, 931 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 10),
932 SUNXI_FUNCTION(0x0, "gpio_in"), 932 SUNXI_FUNCTION(0x0, "gpio_in"),
933 SUNXI_FUNCTION(0x1, "gpio_out"), 933 SUNXI_FUNCTION(0x1, "gpio_out"),
934 SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */ 934 SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
935 SUNXI_FUNCTION(0x3, "uart5"), /* TX */ 935 SUNXI_FUNCTION(0x3, "uart5"), /* TX */
936 SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */ 936 SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
937 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11, 937 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11),
938 SUNXI_FUNCTION(0x0, "gpio_in"), 938 SUNXI_FUNCTION(0x0, "gpio_in"),
939 SUNXI_FUNCTION(0x1, "gpio_out"), 939 SUNXI_FUNCTION(0x1, "gpio_out"),
940 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */ 940 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
941 SUNXI_FUNCTION(0x3, "uart5"), /* RX */ 941 SUNXI_FUNCTION(0x3, "uart5"), /* RX */
942 SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */ 942 SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
943 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12, 943 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12),
944 SUNXI_FUNCTION(0x0, "gpio_in"), 944 SUNXI_FUNCTION(0x0, "gpio_in"),
945 SUNXI_FUNCTION(0x1, "gpio_out"), 945 SUNXI_FUNCTION(0x1, "gpio_out"),
946 SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */ 946 SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
947 SUNXI_FUNCTION(0x3, "uart6"), /* TX */ 947 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
948 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */ 948 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
949 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13, 949 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
950 SUNXI_FUNCTION(0x0, "gpio_in"), 950 SUNXI_FUNCTION(0x0, "gpio_in"),
951 SUNXI_FUNCTION(0x1, "gpio_out"), 951 SUNXI_FUNCTION(0x1, "gpio_out"),
952 SUNXI_FUNCTION(0x2, "spi0"), /* MISO */ 952 SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
953 SUNXI_FUNCTION(0x3, "uart6"), /* RX */ 953 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
954 SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */ 954 SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
955 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14, 955 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
956 SUNXI_FUNCTION(0x0, "gpio_in"), 956 SUNXI_FUNCTION(0x0, "gpio_in"),
957 SUNXI_FUNCTION(0x1, "gpio_out"), 957 SUNXI_FUNCTION(0x1, "gpio_out"),
958 SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */ 958 SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
959 SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */ 959 SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
960 SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */ 960 SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */
961 SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */ 961 SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
962 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15, 962 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15),
963 SUNXI_FUNCTION(0x0, "gpio_in"), 963 SUNXI_FUNCTION(0x0, "gpio_in"),
964 SUNXI_FUNCTION(0x1, "gpio_out"), 964 SUNXI_FUNCTION(0x1, "gpio_out"),
965 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ 965 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
966 SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */ 966 SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
967 SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */ 967 SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */
968 SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */ 968 SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
969 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16, 969 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16),
970 SUNXI_FUNCTION(0x0, "gpio_in"), 970 SUNXI_FUNCTION(0x0, "gpio_in"),
971 SUNXI_FUNCTION(0x1, "gpio_out"), 971 SUNXI_FUNCTION(0x1, "gpio_out"),
972 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ 972 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
973 SUNXI_FUNCTION(0x3, "uart2"), /* RTS */ 973 SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
974 SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */ 974 SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
975 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17, 975 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 17),
976 SUNXI_FUNCTION(0x0, "gpio_in"), 976 SUNXI_FUNCTION(0x0, "gpio_in"),
977 SUNXI_FUNCTION(0x1, "gpio_out"), 977 SUNXI_FUNCTION(0x1, "gpio_out"),
978 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ 978 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
979 SUNXI_FUNCTION(0x3, "uart2"), /* CTS */ 979 SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
980 SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */ 980 SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */
981 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18, 981 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18),
982 SUNXI_FUNCTION(0x0, "gpio_in"), 982 SUNXI_FUNCTION(0x0, "gpio_in"),
983 SUNXI_FUNCTION(0x1, "gpio_out"), 983 SUNXI_FUNCTION(0x1, "gpio_out"),
984 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ 984 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
985 SUNXI_FUNCTION(0x3, "uart2"), /* TX */ 985 SUNXI_FUNCTION(0x3, "uart2"), /* TX */
986 SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */ 986 SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */
987 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19, 987 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19),
988 SUNXI_FUNCTION(0x0, "gpio_in"), 988 SUNXI_FUNCTION(0x0, "gpio_in"),
989 SUNXI_FUNCTION(0x1, "gpio_out"), 989 SUNXI_FUNCTION(0x1, "gpio_out"),
990 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ 990 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
991 SUNXI_FUNCTION(0x3, "uart2"), /* RX */ 991 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
992 SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */ 992 SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */
993 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20, 993 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 20),
994 SUNXI_FUNCTION(0x0, "gpio_in"), 994 SUNXI_FUNCTION(0x0, "gpio_in"),
995 SUNXI_FUNCTION(0x1, "gpio_out"), 995 SUNXI_FUNCTION(0x1, "gpio_out"),
996 SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */ 996 SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */
997 SUNXI_FUNCTION(0x3, "uart7"), /* TX */ 997 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
998 SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */ 998 SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */
999 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21, 999 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 21),
1000 SUNXI_FUNCTION(0x0, "gpio_in"), 1000 SUNXI_FUNCTION(0x0, "gpio_in"),
1001 SUNXI_FUNCTION(0x1, "gpio_out"), 1001 SUNXI_FUNCTION(0x1, "gpio_out"),
1002 SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */ 1002 SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */
@@ -1005,637 +1005,637 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
1005}; 1005};
1006 1006
1007static const struct sunxi_desc_pin sun5i_a10s_pins[] = { 1007static const struct sunxi_desc_pin sun5i_a10s_pins[] = {
1008 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0, 1008 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
1009 SUNXI_FUNCTION(0x0, "gpio_in"), 1009 SUNXI_FUNCTION(0x0, "gpio_in"),
1010 SUNXI_FUNCTION(0x1, "gpio_out"), 1010 SUNXI_FUNCTION(0x1, "gpio_out"),
1011 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */ 1011 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
1012 SUNXI_FUNCTION(0x3, "ts0"), /* CLK */ 1012 SUNXI_FUNCTION(0x3, "ts0"), /* CLK */
1013 SUNXI_FUNCTION(0x5, "keypad")), /* IN0 */ 1013 SUNXI_FUNCTION(0x5, "keypad")), /* IN0 */
1014 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1, 1014 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
1015 SUNXI_FUNCTION(0x0, "gpio_in"), 1015 SUNXI_FUNCTION(0x0, "gpio_in"),
1016 SUNXI_FUNCTION(0x1, "gpio_out"), 1016 SUNXI_FUNCTION(0x1, "gpio_out"),
1017 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */ 1017 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
1018 SUNXI_FUNCTION(0x3, "ts0"), /* ERR */ 1018 SUNXI_FUNCTION(0x3, "ts0"), /* ERR */
1019 SUNXI_FUNCTION(0x5, "keypad")), /* IN1 */ 1019 SUNXI_FUNCTION(0x5, "keypad")), /* IN1 */
1020 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2, 1020 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
1021 SUNXI_FUNCTION(0x0, "gpio_in"), 1021 SUNXI_FUNCTION(0x0, "gpio_in"),
1022 SUNXI_FUNCTION(0x1, "gpio_out"), 1022 SUNXI_FUNCTION(0x1, "gpio_out"),
1023 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */ 1023 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
1024 SUNXI_FUNCTION(0x3, "ts0"), /* SYNC */ 1024 SUNXI_FUNCTION(0x3, "ts0"), /* SYNC */
1025 SUNXI_FUNCTION(0x5, "keypad")), /* IN2 */ 1025 SUNXI_FUNCTION(0x5, "keypad")), /* IN2 */
1026 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3, 1026 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
1027 SUNXI_FUNCTION(0x0, "gpio_in"), 1027 SUNXI_FUNCTION(0x0, "gpio_in"),
1028 SUNXI_FUNCTION(0x1, "gpio_out"), 1028 SUNXI_FUNCTION(0x1, "gpio_out"),
1029 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */ 1029 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
1030 SUNXI_FUNCTION(0x3, "ts0"), /* DLVD */ 1030 SUNXI_FUNCTION(0x3, "ts0"), /* DLVD */
1031 SUNXI_FUNCTION(0x5, "keypad")), /* IN3 */ 1031 SUNXI_FUNCTION(0x5, "keypad")), /* IN3 */
1032 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4, 1032 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
1033 SUNXI_FUNCTION(0x0, "gpio_in"), 1033 SUNXI_FUNCTION(0x0, "gpio_in"),
1034 SUNXI_FUNCTION(0x1, "gpio_out"), 1034 SUNXI_FUNCTION(0x1, "gpio_out"),
1035 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */ 1035 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
1036 SUNXI_FUNCTION(0x3, "ts0"), /* D0 */ 1036 SUNXI_FUNCTION(0x3, "ts0"), /* D0 */
1037 SUNXI_FUNCTION(0x5, "keypad")), /* IN4 */ 1037 SUNXI_FUNCTION(0x5, "keypad")), /* IN4 */
1038 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5, 1038 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
1039 SUNXI_FUNCTION(0x0, "gpio_in"), 1039 SUNXI_FUNCTION(0x0, "gpio_in"),
1040 SUNXI_FUNCTION(0x1, "gpio_out"), 1040 SUNXI_FUNCTION(0x1, "gpio_out"),
1041 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */ 1041 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
1042 SUNXI_FUNCTION(0x3, "ts0"), /* D1 */ 1042 SUNXI_FUNCTION(0x3, "ts0"), /* D1 */
1043 SUNXI_FUNCTION(0x5, "keypad")), /* IN5 */ 1043 SUNXI_FUNCTION(0x5, "keypad")), /* IN5 */
1044 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6, 1044 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
1045 SUNXI_FUNCTION(0x0, "gpio_in"), 1045 SUNXI_FUNCTION(0x0, "gpio_in"),
1046 SUNXI_FUNCTION(0x1, "gpio_out"), 1046 SUNXI_FUNCTION(0x1, "gpio_out"),
1047 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */ 1047 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
1048 SUNXI_FUNCTION(0x3, "ts0"), /* D2 */ 1048 SUNXI_FUNCTION(0x3, "ts0"), /* D2 */
1049 SUNXI_FUNCTION(0x5, "keypad")), /* IN6 */ 1049 SUNXI_FUNCTION(0x5, "keypad")), /* IN6 */
1050 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7, 1050 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
1051 SUNXI_FUNCTION(0x0, "gpio_in"), 1051 SUNXI_FUNCTION(0x0, "gpio_in"),
1052 SUNXI_FUNCTION(0x1, "gpio_out"), 1052 SUNXI_FUNCTION(0x1, "gpio_out"),
1053 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */ 1053 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
1054 SUNXI_FUNCTION(0x3, "ts0"), /* D3 */ 1054 SUNXI_FUNCTION(0x3, "ts0"), /* D3 */
1055 SUNXI_FUNCTION(0x5, "keypad")), /* IN7 */ 1055 SUNXI_FUNCTION(0x5, "keypad")), /* IN7 */
1056 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8, 1056 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
1057 SUNXI_FUNCTION(0x0, "gpio_in"), 1057 SUNXI_FUNCTION(0x0, "gpio_in"),
1058 SUNXI_FUNCTION(0x1, "gpio_out"), 1058 SUNXI_FUNCTION(0x1, "gpio_out"),
1059 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */ 1059 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
1060 SUNXI_FUNCTION(0x3, "ts0"), /* D4 */ 1060 SUNXI_FUNCTION(0x3, "ts0"), /* D4 */
1061 SUNXI_FUNCTION(0x4, "uart1"), /* DTR */ 1061 SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
1062 SUNXI_FUNCTION(0x5, "keypad")), /* OUT0 */ 1062 SUNXI_FUNCTION(0x5, "keypad")), /* OUT0 */
1063 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9, 1063 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
1064 SUNXI_FUNCTION(0x0, "gpio_in"), 1064 SUNXI_FUNCTION(0x0, "gpio_in"),
1065 SUNXI_FUNCTION(0x1, "gpio_out"), 1065 SUNXI_FUNCTION(0x1, "gpio_out"),
1066 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */ 1066 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
1067 SUNXI_FUNCTION(0x3, "ts0"), /* D5 */ 1067 SUNXI_FUNCTION(0x3, "ts0"), /* D5 */
1068 SUNXI_FUNCTION(0x4, "uart1"), /* DSR */ 1068 SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
1069 SUNXI_FUNCTION(0x5, "keypad")), /* OUT1 */ 1069 SUNXI_FUNCTION(0x5, "keypad")), /* OUT1 */
1070 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10, 1070 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
1071 SUNXI_FUNCTION(0x0, "gpio_in"), 1071 SUNXI_FUNCTION(0x0, "gpio_in"),
1072 SUNXI_FUNCTION(0x1, "gpio_out"), 1072 SUNXI_FUNCTION(0x1, "gpio_out"),
1073 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */ 1073 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
1074 SUNXI_FUNCTION(0x3, "ts0"), /* D6 */ 1074 SUNXI_FUNCTION(0x3, "ts0"), /* D6 */
1075 SUNXI_FUNCTION(0x4, "uart1"), /* DCD */ 1075 SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
1076 SUNXI_FUNCTION(0x5, "keypad")), /* OUT2 */ 1076 SUNXI_FUNCTION(0x5, "keypad")), /* OUT2 */
1077 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11, 1077 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
1078 SUNXI_FUNCTION(0x0, "gpio_in"), 1078 SUNXI_FUNCTION(0x0, "gpio_in"),
1079 SUNXI_FUNCTION(0x1, "gpio_out"), 1079 SUNXI_FUNCTION(0x1, "gpio_out"),
1080 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */ 1080 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
1081 SUNXI_FUNCTION(0x3, "ts0"), /* D7 */ 1081 SUNXI_FUNCTION(0x3, "ts0"), /* D7 */
1082 SUNXI_FUNCTION(0x4, "uart1"), /* RING */ 1082 SUNXI_FUNCTION(0x4, "uart1"), /* RING */
1083 SUNXI_FUNCTION(0x5, "keypad")), /* OUT3 */ 1083 SUNXI_FUNCTION(0x5, "keypad")), /* OUT3 */
1084 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12, 1084 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
1085 SUNXI_FUNCTION(0x0, "gpio_in"), 1085 SUNXI_FUNCTION(0x0, "gpio_in"),
1086 SUNXI_FUNCTION(0x1, "gpio_out"), 1086 SUNXI_FUNCTION(0x1, "gpio_out"),
1087 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */ 1087 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
1088 SUNXI_FUNCTION(0x3, "uart1"), /* TX */ 1088 SUNXI_FUNCTION(0x3, "uart1"), /* TX */
1089 SUNXI_FUNCTION(0x5, "keypad")), /* OUT4 */ 1089 SUNXI_FUNCTION(0x5, "keypad")), /* OUT4 */
1090 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13, 1090 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
1091 SUNXI_FUNCTION(0x0, "gpio_in"), 1091 SUNXI_FUNCTION(0x0, "gpio_in"),
1092 SUNXI_FUNCTION(0x1, "gpio_out"), 1092 SUNXI_FUNCTION(0x1, "gpio_out"),
1093 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */ 1093 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
1094 SUNXI_FUNCTION(0x3, "uart1"), /* RX */ 1094 SUNXI_FUNCTION(0x3, "uart1"), /* RX */
1095 SUNXI_FUNCTION(0x5, "keypad")), /* OUT5 */ 1095 SUNXI_FUNCTION(0x5, "keypad")), /* OUT5 */
1096 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14, 1096 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
1097 SUNXI_FUNCTION(0x0, "gpio_in"), 1097 SUNXI_FUNCTION(0x0, "gpio_in"),
1098 SUNXI_FUNCTION(0x1, "gpio_out"), 1098 SUNXI_FUNCTION(0x1, "gpio_out"),
1099 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */ 1099 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
1100 SUNXI_FUNCTION(0x3, "uart1"), /* CTS */ 1100 SUNXI_FUNCTION(0x3, "uart1"), /* CTS */
1101 SUNXI_FUNCTION(0x4, "uart3"), /* TX */ 1101 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
1102 SUNXI_FUNCTION(0x5, "keypad")), /* OUT6 */ 1102 SUNXI_FUNCTION(0x5, "keypad")), /* OUT6 */
1103 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15, 1103 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
1104 SUNXI_FUNCTION(0x0, "gpio_in"), 1104 SUNXI_FUNCTION(0x0, "gpio_in"),
1105 SUNXI_FUNCTION(0x1, "gpio_out"), 1105 SUNXI_FUNCTION(0x1, "gpio_out"),
1106 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */ 1106 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
1107 SUNXI_FUNCTION(0x3, "uart1"), /* RTS */ 1107 SUNXI_FUNCTION(0x3, "uart1"), /* RTS */
1108 SUNXI_FUNCTION(0x4, "uart3"), /* RX */ 1108 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
1109 SUNXI_FUNCTION(0x5, "keypad")), /* OUT7 */ 1109 SUNXI_FUNCTION(0x5, "keypad")), /* OUT7 */
1110 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16, 1110 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
1111 SUNXI_FUNCTION(0x0, "gpio_in"), 1111 SUNXI_FUNCTION(0x0, "gpio_in"),
1112 SUNXI_FUNCTION(0x1, "gpio_out"), 1112 SUNXI_FUNCTION(0x1, "gpio_out"),
1113 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */ 1113 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
1114 SUNXI_FUNCTION(0x3, "uart2")), /* TX */ 1114 SUNXI_FUNCTION(0x3, "uart2")), /* TX */
1115 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17, 1115 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
1116 SUNXI_FUNCTION(0x0, "gpio_in"), 1116 SUNXI_FUNCTION(0x0, "gpio_in"),
1117 SUNXI_FUNCTION(0x1, "gpio_out"), 1117 SUNXI_FUNCTION(0x1, "gpio_out"),
1118 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */ 1118 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
1119 SUNXI_FUNCTION(0x3, "uart2"), /* RX */ 1119 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
1120 SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */ 1120 SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */
1121 /* Hole */ 1121 /* Hole */
1122 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0, 1122 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
1123 SUNXI_FUNCTION(0x0, "gpio_in"), 1123 SUNXI_FUNCTION(0x0, "gpio_in"),
1124 SUNXI_FUNCTION(0x1, "gpio_out"), 1124 SUNXI_FUNCTION(0x1, "gpio_out"),
1125 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ 1125 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
1126 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1, 1126 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
1127 SUNXI_FUNCTION(0x0, "gpio_in"), 1127 SUNXI_FUNCTION(0x0, "gpio_in"),
1128 SUNXI_FUNCTION(0x1, "gpio_out"), 1128 SUNXI_FUNCTION(0x1, "gpio_out"),
1129 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ 1129 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
1130 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2, 1130 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
1131 SUNXI_FUNCTION(0x0, "gpio_in"), 1131 SUNXI_FUNCTION(0x0, "gpio_in"),
1132 SUNXI_FUNCTION(0x1, "gpio_out"), 1132 SUNXI_FUNCTION(0x1, "gpio_out"),
1133 SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */ 1133 SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */
1134 SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */ 1134 SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */
1135 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3, 1135 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
1136 SUNXI_FUNCTION(0x0, "gpio_in"), 1136 SUNXI_FUNCTION(0x0, "gpio_in"),
1137 SUNXI_FUNCTION(0x1, "gpio_out"), 1137 SUNXI_FUNCTION(0x1, "gpio_out"),
1138 SUNXI_FUNCTION(0x2, "ir0"), /* TX */ 1138 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
1139 SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */ 1139 SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */
1140 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4, 1140 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
1141 SUNXI_FUNCTION(0x0, "gpio_in"), 1141 SUNXI_FUNCTION(0x0, "gpio_in"),
1142 SUNXI_FUNCTION(0x1, "gpio_out"), 1142 SUNXI_FUNCTION(0x1, "gpio_out"),
1143 SUNXI_FUNCTION(0x2, "ir0"), /* RX */ 1143 SUNXI_FUNCTION(0x2, "ir0"), /* RX */
1144 SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */ 1144 SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */
1145 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5, 1145 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
1146 SUNXI_FUNCTION(0x0, "gpio_in"), 1146 SUNXI_FUNCTION(0x0, "gpio_in"),
1147 SUNXI_FUNCTION(0x1, "gpio_out"), 1147 SUNXI_FUNCTION(0x1, "gpio_out"),
1148 SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */ 1148 SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
1149 SUNXI_FUNCTION_IRQ(0x6, 19)), /* EINT19 */ 1149 SUNXI_FUNCTION_IRQ(0x6, 19)), /* EINT19 */
1150 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6, 1150 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
1151 SUNXI_FUNCTION(0x0, "gpio_in"), 1151 SUNXI_FUNCTION(0x0, "gpio_in"),
1152 SUNXI_FUNCTION(0x1, "gpio_out"), 1152 SUNXI_FUNCTION(0x1, "gpio_out"),
1153 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */ 1153 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
1154 SUNXI_FUNCTION_IRQ(0x6, 20)), /* EINT20 */ 1154 SUNXI_FUNCTION_IRQ(0x6, 20)), /* EINT20 */
1155 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7, 1155 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
1156 SUNXI_FUNCTION(0x0, "gpio_in"), 1156 SUNXI_FUNCTION(0x0, "gpio_in"),
1157 SUNXI_FUNCTION(0x1, "gpio_out"), 1157 SUNXI_FUNCTION(0x1, "gpio_out"),
1158 SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */ 1158 SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */
1159 SUNXI_FUNCTION_IRQ(0x6, 21)), /* EINT21 */ 1159 SUNXI_FUNCTION_IRQ(0x6, 21)), /* EINT21 */
1160 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8, 1160 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
1161 SUNXI_FUNCTION(0x0, "gpio_in"), 1161 SUNXI_FUNCTION(0x0, "gpio_in"),
1162 SUNXI_FUNCTION(0x1, "gpio_out"), 1162 SUNXI_FUNCTION(0x1, "gpio_out"),
1163 SUNXI_FUNCTION(0x2, "i2s"), /* DO */ 1163 SUNXI_FUNCTION(0x2, "i2s"), /* DO */
1164 SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */ 1164 SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
1165 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9, 1165 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
1166 SUNXI_FUNCTION(0x0, "gpio_in"), 1166 SUNXI_FUNCTION(0x0, "gpio_in"),
1167 SUNXI_FUNCTION(0x1, "gpio_out"), 1167 SUNXI_FUNCTION(0x1, "gpio_out"),
1168 SUNXI_FUNCTION(0x2, "i2s"), /* DI */ 1168 SUNXI_FUNCTION(0x2, "i2s"), /* DI */
1169 SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */ 1169 SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
1170 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10, 1170 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
1171 SUNXI_FUNCTION(0x0, "gpio_in"), 1171 SUNXI_FUNCTION(0x0, "gpio_in"),
1172 SUNXI_FUNCTION(0x1, "gpio_out"), 1172 SUNXI_FUNCTION(0x1, "gpio_out"),
1173 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */ 1173 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
1174 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */ 1174 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
1175 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11, 1175 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
1176 SUNXI_FUNCTION(0x0, "gpio_in"), 1176 SUNXI_FUNCTION(0x0, "gpio_in"),
1177 SUNXI_FUNCTION(0x1, "gpio_out"), 1177 SUNXI_FUNCTION(0x1, "gpio_out"),
1178 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */ 1178 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
1179 SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */ 1179 SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
1180 SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */ 1180 SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
1181 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12, 1181 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
1182 SUNXI_FUNCTION(0x0, "gpio_in"), 1182 SUNXI_FUNCTION(0x0, "gpio_in"),
1183 SUNXI_FUNCTION(0x1, "gpio_out"), 1183 SUNXI_FUNCTION(0x1, "gpio_out"),
1184 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */ 1184 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
1185 SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */ 1185 SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
1186 SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */ 1186 SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
1187 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13, 1187 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
1188 SUNXI_FUNCTION(0x0, "gpio_in"), 1188 SUNXI_FUNCTION(0x0, "gpio_in"),
1189 SUNXI_FUNCTION(0x1, "gpio_out"), 1189 SUNXI_FUNCTION(0x1, "gpio_out"),
1190 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */ 1190 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
1191 SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */ 1191 SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
1192 SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */ 1192 SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
1193 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14, 1193 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
1194 SUNXI_FUNCTION(0x0, "gpio_in"), 1194 SUNXI_FUNCTION(0x0, "gpio_in"),
1195 SUNXI_FUNCTION(0x1, "gpio_out"), 1195 SUNXI_FUNCTION(0x1, "gpio_out"),
1196 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */ 1196 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
1197 SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */ 1197 SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
1198 SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */ 1198 SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
1199 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15, 1199 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
1200 SUNXI_FUNCTION(0x0, "gpio_in"), 1200 SUNXI_FUNCTION(0x0, "gpio_in"),
1201 SUNXI_FUNCTION(0x1, "gpio_out"), 1201 SUNXI_FUNCTION(0x1, "gpio_out"),
1202 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ 1202 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
1203 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16, 1203 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
1204 SUNXI_FUNCTION(0x0, "gpio_in"), 1204 SUNXI_FUNCTION(0x0, "gpio_in"),
1205 SUNXI_FUNCTION(0x1, "gpio_out"), 1205 SUNXI_FUNCTION(0x1, "gpio_out"),
1206 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ 1206 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
1207 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17, 1207 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
1208 SUNXI_FUNCTION(0x0, "gpio_in"), 1208 SUNXI_FUNCTION(0x0, "gpio_in"),
1209 SUNXI_FUNCTION(0x1, "gpio_out"), 1209 SUNXI_FUNCTION(0x1, "gpio_out"),
1210 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ 1210 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
1211 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18, 1211 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
1212 SUNXI_FUNCTION(0x0, "gpio_in"), 1212 SUNXI_FUNCTION(0x0, "gpio_in"),
1213 SUNXI_FUNCTION(0x1, "gpio_out"), 1213 SUNXI_FUNCTION(0x1, "gpio_out"),
1214 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ 1214 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
1215 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19, 1215 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 19),
1216 SUNXI_FUNCTION(0x0, "gpio_in"), 1216 SUNXI_FUNCTION(0x0, "gpio_in"),
1217 SUNXI_FUNCTION(0x1, "gpio_out"), 1217 SUNXI_FUNCTION(0x1, "gpio_out"),
1218 SUNXI_FUNCTION(0x2, "uart0"), /* TX */ 1218 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
1219 SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */ 1219 SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */
1220 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20, 1220 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20),
1221 SUNXI_FUNCTION(0x0, "gpio_in"), 1221 SUNXI_FUNCTION(0x0, "gpio_in"),
1222 SUNXI_FUNCTION(0x1, "gpio_out"), 1222 SUNXI_FUNCTION(0x1, "gpio_out"),
1223 SUNXI_FUNCTION(0x2, "uart0"), /* RX */ 1223 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
1224 SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */ 1224 SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */
1225 /* Hole */ 1225 /* Hole */
1226 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0, 1226 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
1227 SUNXI_FUNCTION(0x0, "gpio_in"), 1227 SUNXI_FUNCTION(0x0, "gpio_in"),
1228 SUNXI_FUNCTION(0x1, "gpio_out"), 1228 SUNXI_FUNCTION(0x1, "gpio_out"),
1229 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ 1229 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
1230 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ 1230 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
1231 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1, 1231 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
1232 SUNXI_FUNCTION(0x0, "gpio_in"), 1232 SUNXI_FUNCTION(0x0, "gpio_in"),
1233 SUNXI_FUNCTION(0x1, "gpio_out"), 1233 SUNXI_FUNCTION(0x1, "gpio_out"),
1234 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ 1234 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
1235 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ 1235 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
1236 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2, 1236 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
1237 SUNXI_FUNCTION(0x0, "gpio_in"), 1237 SUNXI_FUNCTION(0x0, "gpio_in"),
1238 SUNXI_FUNCTION(0x1, "gpio_out"), 1238 SUNXI_FUNCTION(0x1, "gpio_out"),
1239 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ 1239 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
1240 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */ 1240 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
1241 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3, 1241 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
1242 SUNXI_FUNCTION(0x0, "gpio_in"), 1242 SUNXI_FUNCTION(0x0, "gpio_in"),
1243 SUNXI_FUNCTION(0x1, "gpio_out"), 1243 SUNXI_FUNCTION(0x1, "gpio_out"),
1244 SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */ 1244 SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
1245 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ 1245 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
1246 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4, 1246 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
1247 SUNXI_FUNCTION(0x0, "gpio_in"), 1247 SUNXI_FUNCTION(0x0, "gpio_in"),
1248 SUNXI_FUNCTION(0x1, "gpio_out"), 1248 SUNXI_FUNCTION(0x1, "gpio_out"),
1249 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ 1249 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
1250 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5, 1250 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
1251 SUNXI_FUNCTION(0x0, "gpio_in"), 1251 SUNXI_FUNCTION(0x0, "gpio_in"),
1252 SUNXI_FUNCTION(0x1, "gpio_out"), 1252 SUNXI_FUNCTION(0x1, "gpio_out"),
1253 SUNXI_FUNCTION(0x2, "nand0")), /* NRE */ 1253 SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
1254 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6, 1254 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
1255 SUNXI_FUNCTION(0x0, "gpio_in"), 1255 SUNXI_FUNCTION(0x0, "gpio_in"),
1256 SUNXI_FUNCTION(0x1, "gpio_out"), 1256 SUNXI_FUNCTION(0x1, "gpio_out"),
1257 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ 1257 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
1258 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ 1258 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
1259 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7, 1259 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
1260 SUNXI_FUNCTION(0x0, "gpio_in"), 1260 SUNXI_FUNCTION(0x0, "gpio_in"),
1261 SUNXI_FUNCTION(0x1, "gpio_out"), 1261 SUNXI_FUNCTION(0x1, "gpio_out"),
1262 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */ 1262 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
1263 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ 1263 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
1264 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8, 1264 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
1265 SUNXI_FUNCTION(0x0, "gpio_in"), 1265 SUNXI_FUNCTION(0x0, "gpio_in"),
1266 SUNXI_FUNCTION(0x1, "gpio_out"), 1266 SUNXI_FUNCTION(0x1, "gpio_out"),
1267 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ 1267 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
1268 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ 1268 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
1269 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9, 1269 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
1270 SUNXI_FUNCTION(0x0, "gpio_in"), 1270 SUNXI_FUNCTION(0x0, "gpio_in"),
1271 SUNXI_FUNCTION(0x1, "gpio_out"), 1271 SUNXI_FUNCTION(0x1, "gpio_out"),
1272 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ 1272 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
1273 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ 1273 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
1274 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10, 1274 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
1275 SUNXI_FUNCTION(0x0, "gpio_in"), 1275 SUNXI_FUNCTION(0x0, "gpio_in"),
1276 SUNXI_FUNCTION(0x1, "gpio_out"), 1276 SUNXI_FUNCTION(0x1, "gpio_out"),
1277 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ 1277 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
1278 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ 1278 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
1279 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11, 1279 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
1280 SUNXI_FUNCTION(0x0, "gpio_in"), 1280 SUNXI_FUNCTION(0x0, "gpio_in"),
1281 SUNXI_FUNCTION(0x1, "gpio_out"), 1281 SUNXI_FUNCTION(0x1, "gpio_out"),
1282 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ 1282 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
1283 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ 1283 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
1284 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12, 1284 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
1285 SUNXI_FUNCTION(0x0, "gpio_in"), 1285 SUNXI_FUNCTION(0x0, "gpio_in"),
1286 SUNXI_FUNCTION(0x1, "gpio_out"), 1286 SUNXI_FUNCTION(0x1, "gpio_out"),
1287 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */ 1287 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
1288 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ 1288 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
1289 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13, 1289 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
1290 SUNXI_FUNCTION(0x0, "gpio_in"), 1290 SUNXI_FUNCTION(0x0, "gpio_in"),
1291 SUNXI_FUNCTION(0x1, "gpio_out"), 1291 SUNXI_FUNCTION(0x1, "gpio_out"),
1292 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */ 1292 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
1293 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ 1293 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
1294 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14, 1294 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
1295 SUNXI_FUNCTION(0x0, "gpio_in"), 1295 SUNXI_FUNCTION(0x0, "gpio_in"),
1296 SUNXI_FUNCTION(0x1, "gpio_out"), 1296 SUNXI_FUNCTION(0x1, "gpio_out"),
1297 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */ 1297 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
1298 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ 1298 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
1299 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15, 1299 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
1300 SUNXI_FUNCTION(0x0, "gpio_in"), 1300 SUNXI_FUNCTION(0x0, "gpio_in"),
1301 SUNXI_FUNCTION(0x1, "gpio_out"), 1301 SUNXI_FUNCTION(0x1, "gpio_out"),
1302 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */ 1302 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
1303 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ 1303 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
1304 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16, 1304 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
1305 SUNXI_FUNCTION(0x0, "gpio_in"), 1305 SUNXI_FUNCTION(0x0, "gpio_in"),
1306 SUNXI_FUNCTION(0x1, "gpio_out"), 1306 SUNXI_FUNCTION(0x1, "gpio_out"),
1307 SUNXI_FUNCTION(0x2, "nand0"), /* NWP */ 1307 SUNXI_FUNCTION(0x2, "nand0"), /* NWP */
1308 SUNXI_FUNCTION(0x4, "uart3")), /* TX */ 1308 SUNXI_FUNCTION(0x4, "uart3")), /* TX */
1309 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17, 1309 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
1310 SUNXI_FUNCTION(0x0, "gpio_in"), 1310 SUNXI_FUNCTION(0x0, "gpio_in"),
1311 SUNXI_FUNCTION(0x1, "gpio_out"), 1311 SUNXI_FUNCTION(0x1, "gpio_out"),
1312 SUNXI_FUNCTION(0x2, "nand0"), /* NCE2 */ 1312 SUNXI_FUNCTION(0x2, "nand0"), /* NCE2 */
1313 SUNXI_FUNCTION(0x4, "uart3")), /* RX */ 1313 SUNXI_FUNCTION(0x4, "uart3")), /* RX */
1314 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18, 1314 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
1315 SUNXI_FUNCTION(0x0, "gpio_in"), 1315 SUNXI_FUNCTION(0x0, "gpio_in"),
1316 SUNXI_FUNCTION(0x1, "gpio_out"), 1316 SUNXI_FUNCTION(0x1, "gpio_out"),
1317 SUNXI_FUNCTION(0x2, "nand0"), /* NCE3 */ 1317 SUNXI_FUNCTION(0x2, "nand0"), /* NCE3 */
1318 SUNXI_FUNCTION(0x3, "uart2"), /* TX */ 1318 SUNXI_FUNCTION(0x3, "uart2"), /* TX */
1319 SUNXI_FUNCTION(0x4, "uart3")), /* CTS */ 1319 SUNXI_FUNCTION(0x4, "uart3")), /* CTS */
1320 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19, 1320 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
1321 SUNXI_FUNCTION(0x0, "gpio_in"), 1321 SUNXI_FUNCTION(0x0, "gpio_in"),
1322 SUNXI_FUNCTION(0x1, "gpio_out"), 1322 SUNXI_FUNCTION(0x1, "gpio_out"),
1323 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */ 1323 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
1324 SUNXI_FUNCTION(0x3, "uart2"), /* RX */ 1324 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
1325 SUNXI_FUNCTION(0x4, "uart3")), /* RTS */ 1325 SUNXI_FUNCTION(0x4, "uart3")), /* RTS */
1326 /* Hole */ 1326 /* Hole */
1327 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0, 1327 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
1328 SUNXI_FUNCTION(0x0, "gpio_in"), 1328 SUNXI_FUNCTION(0x0, "gpio_in"),
1329 SUNXI_FUNCTION(0x1, "gpio_out"), 1329 SUNXI_FUNCTION(0x1, "gpio_out"),
1330 SUNXI_FUNCTION(0x2, "lcd0")), /* D0 */ 1330 SUNXI_FUNCTION(0x2, "lcd0")), /* D0 */
1331 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1, 1331 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
1332 SUNXI_FUNCTION(0x0, "gpio_in"), 1332 SUNXI_FUNCTION(0x0, "gpio_in"),
1333 SUNXI_FUNCTION(0x1, "gpio_out"), 1333 SUNXI_FUNCTION(0x1, "gpio_out"),
1334 SUNXI_FUNCTION(0x2, "lcd0")), /* D1 */ 1334 SUNXI_FUNCTION(0x2, "lcd0")), /* D1 */
1335 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2, 1335 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
1336 SUNXI_FUNCTION(0x0, "gpio_in"), 1336 SUNXI_FUNCTION(0x0, "gpio_in"),
1337 SUNXI_FUNCTION(0x1, "gpio_out"), 1337 SUNXI_FUNCTION(0x1, "gpio_out"),
1338 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ 1338 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
1339 SUNXI_FUNCTION(0x3, "uart2")), /* TX */ 1339 SUNXI_FUNCTION(0x3, "uart2")), /* TX */
1340 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3, 1340 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
1341 SUNXI_FUNCTION(0x0, "gpio_in"), 1341 SUNXI_FUNCTION(0x0, "gpio_in"),
1342 SUNXI_FUNCTION(0x1, "gpio_out"), 1342 SUNXI_FUNCTION(0x1, "gpio_out"),
1343 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ 1343 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
1344 SUNXI_FUNCTION(0x3, "uart2")), /* RX */ 1344 SUNXI_FUNCTION(0x3, "uart2")), /* RX */
1345 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4, 1345 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
1346 SUNXI_FUNCTION(0x0, "gpio_in"), 1346 SUNXI_FUNCTION(0x0, "gpio_in"),
1347 SUNXI_FUNCTION(0x1, "gpio_out"), 1347 SUNXI_FUNCTION(0x1, "gpio_out"),
1348 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ 1348 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
1349 SUNXI_FUNCTION(0x3, "uart2")), /* CTS */ 1349 SUNXI_FUNCTION(0x3, "uart2")), /* CTS */
1350 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5, 1350 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
1351 SUNXI_FUNCTION(0x0, "gpio_in"), 1351 SUNXI_FUNCTION(0x0, "gpio_in"),
1352 SUNXI_FUNCTION(0x1, "gpio_out"), 1352 SUNXI_FUNCTION(0x1, "gpio_out"),
1353 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ 1353 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
1354 SUNXI_FUNCTION(0x3, "uart2")), /* RTS */ 1354 SUNXI_FUNCTION(0x3, "uart2")), /* RTS */
1355 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6, 1355 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
1356 SUNXI_FUNCTION(0x0, "gpio_in"), 1356 SUNXI_FUNCTION(0x0, "gpio_in"),
1357 SUNXI_FUNCTION(0x1, "gpio_out"), 1357 SUNXI_FUNCTION(0x1, "gpio_out"),
1358 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ 1358 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
1359 SUNXI_FUNCTION(0x3, "emac")), /* ECRS */ 1359 SUNXI_FUNCTION(0x3, "emac")), /* ECRS */
1360 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7, 1360 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
1361 SUNXI_FUNCTION(0x0, "gpio_in"), 1361 SUNXI_FUNCTION(0x0, "gpio_in"),
1362 SUNXI_FUNCTION(0x1, "gpio_out"), 1362 SUNXI_FUNCTION(0x1, "gpio_out"),
1363 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ 1363 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
1364 SUNXI_FUNCTION(0x3, "emac")), /* ECOL */ 1364 SUNXI_FUNCTION(0x3, "emac")), /* ECOL */
1365 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8, 1365 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
1366 SUNXI_FUNCTION(0x0, "gpio_in"), 1366 SUNXI_FUNCTION(0x0, "gpio_in"),
1367 SUNXI_FUNCTION(0x1, "gpio_out"), 1367 SUNXI_FUNCTION(0x1, "gpio_out"),
1368 SUNXI_FUNCTION(0x2, "lcd0")), /* D8 */ 1368 SUNXI_FUNCTION(0x2, "lcd0")), /* D8 */
1369 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9, 1369 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
1370 SUNXI_FUNCTION(0x0, "gpio_in"), 1370 SUNXI_FUNCTION(0x0, "gpio_in"),
1371 SUNXI_FUNCTION(0x1, "gpio_out"), 1371 SUNXI_FUNCTION(0x1, "gpio_out"),
1372 SUNXI_FUNCTION(0x2, "lcd0")), /* D9 */ 1372 SUNXI_FUNCTION(0x2, "lcd0")), /* D9 */
1373 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10, 1373 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
1374 SUNXI_FUNCTION(0x0, "gpio_in"), 1374 SUNXI_FUNCTION(0x0, "gpio_in"),
1375 SUNXI_FUNCTION(0x1, "gpio_out"), 1375 SUNXI_FUNCTION(0x1, "gpio_out"),
1376 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ 1376 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
1377 SUNXI_FUNCTION(0x3, "emac")), /* ERXD0 */ 1377 SUNXI_FUNCTION(0x3, "emac")), /* ERXD0 */
1378 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11, 1378 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
1379 SUNXI_FUNCTION(0x0, "gpio_in"), 1379 SUNXI_FUNCTION(0x0, "gpio_in"),
1380 SUNXI_FUNCTION(0x1, "gpio_out"), 1380 SUNXI_FUNCTION(0x1, "gpio_out"),
1381 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ 1381 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
1382 SUNXI_FUNCTION(0x3, "emac")), /* ERXD1 */ 1382 SUNXI_FUNCTION(0x3, "emac")), /* ERXD1 */
1383 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12, 1383 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
1384 SUNXI_FUNCTION(0x0, "gpio_in"), 1384 SUNXI_FUNCTION(0x0, "gpio_in"),
1385 SUNXI_FUNCTION(0x1, "gpio_out"), 1385 SUNXI_FUNCTION(0x1, "gpio_out"),
1386 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ 1386 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
1387 SUNXI_FUNCTION(0x3, "emac")), /* ERXD2 */ 1387 SUNXI_FUNCTION(0x3, "emac")), /* ERXD2 */
1388 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13, 1388 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
1389 SUNXI_FUNCTION(0x0, "gpio_in"), 1389 SUNXI_FUNCTION(0x0, "gpio_in"),
1390 SUNXI_FUNCTION(0x1, "gpio_out"), 1390 SUNXI_FUNCTION(0x1, "gpio_out"),
1391 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ 1391 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
1392 SUNXI_FUNCTION(0x3, "emac")), /* ERXD3 */ 1392 SUNXI_FUNCTION(0x3, "emac")), /* ERXD3 */
1393 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14, 1393 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
1394 SUNXI_FUNCTION(0x0, "gpio_in"), 1394 SUNXI_FUNCTION(0x0, "gpio_in"),
1395 SUNXI_FUNCTION(0x1, "gpio_out"), 1395 SUNXI_FUNCTION(0x1, "gpio_out"),
1396 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ 1396 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
1397 SUNXI_FUNCTION(0x3, "emac")), /* ERXCK */ 1397 SUNXI_FUNCTION(0x3, "emac")), /* ERXCK */
1398 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15, 1398 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
1399 SUNXI_FUNCTION(0x0, "gpio_in"), 1399 SUNXI_FUNCTION(0x0, "gpio_in"),
1400 SUNXI_FUNCTION(0x1, "gpio_out"), 1400 SUNXI_FUNCTION(0x1, "gpio_out"),
1401 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ 1401 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
1402 SUNXI_FUNCTION(0x3, "emac")), /* ERXERR */ 1402 SUNXI_FUNCTION(0x3, "emac")), /* ERXERR */
1403 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16, 1403 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
1404 SUNXI_FUNCTION(0x0, "gpio_in"), 1404 SUNXI_FUNCTION(0x0, "gpio_in"),
1405 SUNXI_FUNCTION(0x1, "gpio_out"), 1405 SUNXI_FUNCTION(0x1, "gpio_out"),
1406 SUNXI_FUNCTION(0x2, "lcd0")), /* D16 */ 1406 SUNXI_FUNCTION(0x2, "lcd0")), /* D16 */
1407 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17, 1407 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
1408 SUNXI_FUNCTION(0x0, "gpio_in"), 1408 SUNXI_FUNCTION(0x0, "gpio_in"),
1409 SUNXI_FUNCTION(0x1, "gpio_out"), 1409 SUNXI_FUNCTION(0x1, "gpio_out"),
1410 SUNXI_FUNCTION(0x2, "lcd0")), /* D17 */ 1410 SUNXI_FUNCTION(0x2, "lcd0")), /* D17 */
1411 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18, 1411 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
1412 SUNXI_FUNCTION(0x0, "gpio_in"), 1412 SUNXI_FUNCTION(0x0, "gpio_in"),
1413 SUNXI_FUNCTION(0x1, "gpio_out"), 1413 SUNXI_FUNCTION(0x1, "gpio_out"),
1414 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ 1414 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
1415 SUNXI_FUNCTION(0x3, "emac")), /* ERXDV */ 1415 SUNXI_FUNCTION(0x3, "emac")), /* ERXDV */
1416 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19, 1416 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
1417 SUNXI_FUNCTION(0x0, "gpio_in"), 1417 SUNXI_FUNCTION(0x0, "gpio_in"),
1418 SUNXI_FUNCTION(0x1, "gpio_out"), 1418 SUNXI_FUNCTION(0x1, "gpio_out"),
1419 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ 1419 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
1420 SUNXI_FUNCTION(0x3, "emac")), /* ETXD0 */ 1420 SUNXI_FUNCTION(0x3, "emac")), /* ETXD0 */
1421 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20, 1421 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
1422 SUNXI_FUNCTION(0x0, "gpio_in"), 1422 SUNXI_FUNCTION(0x0, "gpio_in"),
1423 SUNXI_FUNCTION(0x1, "gpio_out"), 1423 SUNXI_FUNCTION(0x1, "gpio_out"),
1424 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ 1424 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
1425 SUNXI_FUNCTION(0x3, "emac")), /* ETXD1 */ 1425 SUNXI_FUNCTION(0x3, "emac")), /* ETXD1 */
1426 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21, 1426 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
1427 SUNXI_FUNCTION(0x0, "gpio_in"), 1427 SUNXI_FUNCTION(0x0, "gpio_in"),
1428 SUNXI_FUNCTION(0x1, "gpio_out"), 1428 SUNXI_FUNCTION(0x1, "gpio_out"),
1429 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ 1429 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
1430 SUNXI_FUNCTION(0x3, "emac")), /* ETXD2 */ 1430 SUNXI_FUNCTION(0x3, "emac")), /* ETXD2 */
1431 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22, 1431 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
1432 SUNXI_FUNCTION(0x0, "gpio_in"), 1432 SUNXI_FUNCTION(0x0, "gpio_in"),
1433 SUNXI_FUNCTION(0x1, "gpio_out"), 1433 SUNXI_FUNCTION(0x1, "gpio_out"),
1434 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ 1434 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
1435 SUNXI_FUNCTION(0x3, "emac")), /* ETXD3 */ 1435 SUNXI_FUNCTION(0x3, "emac")), /* ETXD3 */
1436 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23, 1436 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
1437 SUNXI_FUNCTION(0x0, "gpio_in"), 1437 SUNXI_FUNCTION(0x0, "gpio_in"),
1438 SUNXI_FUNCTION(0x1, "gpio_out"), 1438 SUNXI_FUNCTION(0x1, "gpio_out"),
1439 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ 1439 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
1440 SUNXI_FUNCTION(0x3, "emac")), /* ETXEN */ 1440 SUNXI_FUNCTION(0x3, "emac")), /* ETXEN */
1441 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24, 1441 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
1442 SUNXI_FUNCTION(0x0, "gpio_in"), 1442 SUNXI_FUNCTION(0x0, "gpio_in"),
1443 SUNXI_FUNCTION(0x1, "gpio_out"), 1443 SUNXI_FUNCTION(0x1, "gpio_out"),
1444 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ 1444 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
1445 SUNXI_FUNCTION(0x3, "emac")), /* ETXCK */ 1445 SUNXI_FUNCTION(0x3, "emac")), /* ETXCK */
1446 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25, 1446 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
1447 SUNXI_FUNCTION(0x0, "gpio_in"), 1447 SUNXI_FUNCTION(0x0, "gpio_in"),
1448 SUNXI_FUNCTION(0x1, "gpio_out"), 1448 SUNXI_FUNCTION(0x1, "gpio_out"),
1449 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ 1449 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
1450 SUNXI_FUNCTION(0x3, "emac")), /* ETXERR */ 1450 SUNXI_FUNCTION(0x3, "emac")), /* ETXERR */
1451 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26, 1451 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
1452 SUNXI_FUNCTION(0x0, "gpio_in"), 1452 SUNXI_FUNCTION(0x0, "gpio_in"),
1453 SUNXI_FUNCTION(0x1, "gpio_out"), 1453 SUNXI_FUNCTION(0x1, "gpio_out"),
1454 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ 1454 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
1455 SUNXI_FUNCTION(0x3, "emac")), /* EMDC */ 1455 SUNXI_FUNCTION(0x3, "emac")), /* EMDC */
1456 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27, 1456 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
1457 SUNXI_FUNCTION(0x0, "gpio_in"), 1457 SUNXI_FUNCTION(0x0, "gpio_in"),
1458 SUNXI_FUNCTION(0x1, "gpio_out"), 1458 SUNXI_FUNCTION(0x1, "gpio_out"),
1459 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ 1459 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
1460 SUNXI_FUNCTION(0x3, "emac")), /* EMDIO */ 1460 SUNXI_FUNCTION(0x3, "emac")), /* EMDIO */
1461 /* Hole */ 1461 /* Hole */
1462 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0, 1462 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
1463 SUNXI_FUNCTION(0x0, "gpio_in"), 1463 SUNXI_FUNCTION(0x0, "gpio_in"),
1464 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */ 1464 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
1465 SUNXI_FUNCTION(0x3, "csi0"), /* PCK */ 1465 SUNXI_FUNCTION(0x3, "csi0"), /* PCK */
1466 SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */ 1466 SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */
1467 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */ 1467 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
1468 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1, 1468 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
1469 SUNXI_FUNCTION(0x0, "gpio_in"), 1469 SUNXI_FUNCTION(0x0, "gpio_in"),
1470 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */ 1470 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
1471 SUNXI_FUNCTION(0x3, "csi0"), /* CK */ 1471 SUNXI_FUNCTION(0x3, "csi0"), /* CK */
1472 SUNXI_FUNCTION(0x4, "spi2"), /* CLK */ 1472 SUNXI_FUNCTION(0x4, "spi2"), /* CLK */
1473 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */ 1473 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
1474 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2, 1474 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
1475 SUNXI_FUNCTION(0x0, "gpio_in"), 1475 SUNXI_FUNCTION(0x0, "gpio_in"),
1476 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */ 1476 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
1477 SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */ 1477 SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */
1478 SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */ 1478 SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */
1479 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3, 1479 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
1480 SUNXI_FUNCTION(0x0, "gpio_in"), 1480 SUNXI_FUNCTION(0x0, "gpio_in"),
1481 SUNXI_FUNCTION(0x1, "gpio_out"), 1481 SUNXI_FUNCTION(0x1, "gpio_out"),
1482 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */ 1482 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
1483 SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */ 1483 SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */
1484 SUNXI_FUNCTION(0x4, "spi2")), /* MISO */ 1484 SUNXI_FUNCTION(0x4, "spi2")), /* MISO */
1485 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4, 1485 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
1486 SUNXI_FUNCTION(0x0, "gpio_in"), 1486 SUNXI_FUNCTION(0x0, "gpio_in"),
1487 SUNXI_FUNCTION(0x1, "gpio_out"), 1487 SUNXI_FUNCTION(0x1, "gpio_out"),
1488 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */ 1488 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
1489 SUNXI_FUNCTION(0x3, "csi0"), /* D0 */ 1489 SUNXI_FUNCTION(0x3, "csi0"), /* D0 */
1490 SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */ 1490 SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */
1491 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5, 1491 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
1492 SUNXI_FUNCTION(0x0, "gpio_in"), 1492 SUNXI_FUNCTION(0x0, "gpio_in"),
1493 SUNXI_FUNCTION(0x1, "gpio_out"), 1493 SUNXI_FUNCTION(0x1, "gpio_out"),
1494 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */ 1494 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
1495 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */ 1495 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
1496 SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */ 1496 SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */
1497 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6, 1497 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
1498 SUNXI_FUNCTION(0x0, "gpio_in"), 1498 SUNXI_FUNCTION(0x0, "gpio_in"),
1499 SUNXI_FUNCTION(0x1, "gpio_out"), 1499 SUNXI_FUNCTION(0x1, "gpio_out"),
1500 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */ 1500 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
1501 SUNXI_FUNCTION(0x3, "csi0"), /* D2 */ 1501 SUNXI_FUNCTION(0x3, "csi0"), /* D2 */
1502 SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */ 1502 SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */
1503 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7, 1503 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
1504 SUNXI_FUNCTION(0x0, "gpio_in"), 1504 SUNXI_FUNCTION(0x0, "gpio_in"),
1505 SUNXI_FUNCTION(0x1, "gpio_out"), 1505 SUNXI_FUNCTION(0x1, "gpio_out"),
1506 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */ 1506 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
1507 SUNXI_FUNCTION(0x3, "csi0"), /* D3 */ 1507 SUNXI_FUNCTION(0x3, "csi0"), /* D3 */
1508 SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */ 1508 SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */
1509 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8, 1509 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
1510 SUNXI_FUNCTION(0x0, "gpio_in"), 1510 SUNXI_FUNCTION(0x0, "gpio_in"),
1511 SUNXI_FUNCTION(0x1, "gpio_out"), 1511 SUNXI_FUNCTION(0x1, "gpio_out"),
1512 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */ 1512 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
1513 SUNXI_FUNCTION(0x3, "csi0"), /* D4 */ 1513 SUNXI_FUNCTION(0x3, "csi0"), /* D4 */
1514 SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */ 1514 SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */
1515 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9, 1515 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
1516 SUNXI_FUNCTION(0x0, "gpio_in"), 1516 SUNXI_FUNCTION(0x0, "gpio_in"),
1517 SUNXI_FUNCTION(0x1, "gpio_out"), 1517 SUNXI_FUNCTION(0x1, "gpio_out"),
1518 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */ 1518 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
1519 SUNXI_FUNCTION(0x3, "csi0"), /* D5 */ 1519 SUNXI_FUNCTION(0x3, "csi0"), /* D5 */
1520 SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */ 1520 SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */
1521 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10, 1521 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
1522 SUNXI_FUNCTION(0x0, "gpio_in"), 1522 SUNXI_FUNCTION(0x0, "gpio_in"),
1523 SUNXI_FUNCTION(0x1, "gpio_out"), 1523 SUNXI_FUNCTION(0x1, "gpio_out"),
1524 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */ 1524 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
1525 SUNXI_FUNCTION(0x3, "csi0"), /* D6 */ 1525 SUNXI_FUNCTION(0x3, "csi0"), /* D6 */
1526 SUNXI_FUNCTION(0x4, "uart1")), /* TX */ 1526 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
1527 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11, 1527 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
1528 SUNXI_FUNCTION(0x0, "gpio_in"), 1528 SUNXI_FUNCTION(0x0, "gpio_in"),
1529 SUNXI_FUNCTION(0x1, "gpio_out"), 1529 SUNXI_FUNCTION(0x1, "gpio_out"),
1530 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */ 1530 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
1531 SUNXI_FUNCTION(0x3, "csi0"), /* D7 */ 1531 SUNXI_FUNCTION(0x3, "csi0"), /* D7 */
1532 SUNXI_FUNCTION(0x4, "uart1")), /* RX */ 1532 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
1533 /* Hole */ 1533 /* Hole */
1534 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0, 1534 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
1535 SUNXI_FUNCTION(0x0, "gpio_in"), 1535 SUNXI_FUNCTION(0x0, "gpio_in"),
1536 SUNXI_FUNCTION(0x1, "gpio_out"), 1536 SUNXI_FUNCTION(0x1, "gpio_out"),
1537 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ 1537 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
1538 SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */ 1538 SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
1539 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1, 1539 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
1540 SUNXI_FUNCTION(0x0, "gpio_in"), 1540 SUNXI_FUNCTION(0x0, "gpio_in"),
1541 SUNXI_FUNCTION(0x1, "gpio_out"), 1541 SUNXI_FUNCTION(0x1, "gpio_out"),
1542 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ 1542 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
1543 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */ 1543 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
1544 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2, 1544 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
1545 SUNXI_FUNCTION(0x0, "gpio_in"), 1545 SUNXI_FUNCTION(0x0, "gpio_in"),
1546 SUNXI_FUNCTION(0x1, "gpio_out"), 1546 SUNXI_FUNCTION(0x1, "gpio_out"),
1547 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ 1547 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
1548 SUNXI_FUNCTION(0x4, "uart0")), /* TX */ 1548 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
1549 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3, 1549 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
1550 SUNXI_FUNCTION(0x0, "gpio_in"), 1550 SUNXI_FUNCTION(0x0, "gpio_in"),
1551 SUNXI_FUNCTION(0x1, "gpio_out"), 1551 SUNXI_FUNCTION(0x1, "gpio_out"),
1552 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ 1552 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
1553 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */ 1553 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
1554 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4, 1554 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
1555 SUNXI_FUNCTION(0x0, "gpio_in"), 1555 SUNXI_FUNCTION(0x0, "gpio_in"),
1556 SUNXI_FUNCTION(0x1, "gpio_out"), 1556 SUNXI_FUNCTION(0x1, "gpio_out"),
1557 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ 1557 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
1558 SUNXI_FUNCTION(0x4, "uart0")), /* RX */ 1558 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
1559 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5, 1559 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
1560 SUNXI_FUNCTION(0x0, "gpio_in"), 1560 SUNXI_FUNCTION(0x0, "gpio_in"),
1561 SUNXI_FUNCTION(0x1, "gpio_out"), 1561 SUNXI_FUNCTION(0x1, "gpio_out"),
1562 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ 1562 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
1563 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */ 1563 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
1564 /* Hole */ 1564 /* Hole */
1565 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0, 1565 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
1566 SUNXI_FUNCTION(0x0, "gpio_in"), 1566 SUNXI_FUNCTION(0x0, "gpio_in"),
1567 SUNXI_FUNCTION(0x2, "gps"), /* CLK */ 1567 SUNXI_FUNCTION(0x2, "gps"), /* CLK */
1568 SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */ 1568 SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */
1569 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1, 1569 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
1570 SUNXI_FUNCTION(0x0, "gpio_in"), 1570 SUNXI_FUNCTION(0x0, "gpio_in"),
1571 SUNXI_FUNCTION(0x2, "gps"), /* SIGN */ 1571 SUNXI_FUNCTION(0x2, "gps"), /* SIGN */
1572 SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */ 1572 SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */
1573 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2, 1573 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
1574 SUNXI_FUNCTION(0x0, "gpio_in"), 1574 SUNXI_FUNCTION(0x0, "gpio_in"),
1575 SUNXI_FUNCTION(0x2, "gps"), /* MAG */ 1575 SUNXI_FUNCTION(0x2, "gps"), /* MAG */
1576 SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */ 1576 SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */
1577 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3, 1577 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
1578 SUNXI_FUNCTION(0x0, "gpio_in"), 1578 SUNXI_FUNCTION(0x0, "gpio_in"),
1579 SUNXI_FUNCTION(0x1, "gpio_out"), 1579 SUNXI_FUNCTION(0x1, "gpio_out"),
1580 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ 1580 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
1581 SUNXI_FUNCTION(0x4, "uart1"), /* TX */ 1581 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
1582 SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */ 1582 SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */
1583 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4, 1583 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
1584 SUNXI_FUNCTION(0x0, "gpio_in"), 1584 SUNXI_FUNCTION(0x0, "gpio_in"),
1585 SUNXI_FUNCTION(0x1, "gpio_out"), 1585 SUNXI_FUNCTION(0x1, "gpio_out"),
1586 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ 1586 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
1587 SUNXI_FUNCTION(0x4, "uart1"), /* RX */ 1587 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
1588 SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */ 1588 SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */
1589 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5, 1589 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
1590 SUNXI_FUNCTION(0x0, "gpio_in"), 1590 SUNXI_FUNCTION(0x0, "gpio_in"),
1591 SUNXI_FUNCTION(0x1, "gpio_out"), 1591 SUNXI_FUNCTION(0x1, "gpio_out"),
1592 SUNXI_FUNCTION(0x2, "mmc1"), /* DO */ 1592 SUNXI_FUNCTION(0x2, "mmc1"), /* DO */
1593 SUNXI_FUNCTION(0x4, "uart1"), /* CTS */ 1593 SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
1594 SUNXI_FUNCTION_IRQ(0x6, 5)), /* EINT5 */ 1594 SUNXI_FUNCTION_IRQ(0x6, 5)), /* EINT5 */
1595 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6, 1595 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
1596 SUNXI_FUNCTION(0x0, "gpio_in"), 1596 SUNXI_FUNCTION(0x0, "gpio_in"),
1597 SUNXI_FUNCTION(0x1, "gpio_out"), 1597 SUNXI_FUNCTION(0x1, "gpio_out"),
1598 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ 1598 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
1599 SUNXI_FUNCTION(0x4, "uart1"), /* RTS */ 1599 SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
1600 SUNXI_FUNCTION(0x5, "uart2"), /* RTS */ 1600 SUNXI_FUNCTION(0x5, "uart2"), /* RTS */
1601 SUNXI_FUNCTION_IRQ(0x6, 6)), /* EINT6 */ 1601 SUNXI_FUNCTION_IRQ(0x6, 6)), /* EINT6 */
1602 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7, 1602 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
1603 SUNXI_FUNCTION(0x0, "gpio_in"), 1603 SUNXI_FUNCTION(0x0, "gpio_in"),
1604 SUNXI_FUNCTION(0x1, "gpio_out"), 1604 SUNXI_FUNCTION(0x1, "gpio_out"),
1605 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ 1605 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
1606 SUNXI_FUNCTION(0x5, "uart2"), /* TX */ 1606 SUNXI_FUNCTION(0x5, "uart2"), /* TX */
1607 SUNXI_FUNCTION_IRQ(0x6, 7)), /* EINT7 */ 1607 SUNXI_FUNCTION_IRQ(0x6, 7)), /* EINT7 */
1608 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8, 1608 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
1609 SUNXI_FUNCTION(0x0, "gpio_in"), 1609 SUNXI_FUNCTION(0x0, "gpio_in"),
1610 SUNXI_FUNCTION(0x1, "gpio_out"), 1610 SUNXI_FUNCTION(0x1, "gpio_out"),
1611 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ 1611 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
1612 SUNXI_FUNCTION(0x5, "uart2"), /* RX */ 1612 SUNXI_FUNCTION(0x5, "uart2"), /* RX */
1613 SUNXI_FUNCTION_IRQ(0x6, 8)), /* EINT8 */ 1613 SUNXI_FUNCTION_IRQ(0x6, 8)), /* EINT8 */
1614 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9, 1614 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
1615 SUNXI_FUNCTION(0x0, "gpio_in"), 1615 SUNXI_FUNCTION(0x0, "gpio_in"),
1616 SUNXI_FUNCTION(0x1, "gpio_out"), 1616 SUNXI_FUNCTION(0x1, "gpio_out"),
1617 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ 1617 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
1618 SUNXI_FUNCTION(0x3, "uart3"), /* TX */ 1618 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
1619 SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */ 1619 SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */
1620 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10, 1620 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
1621 SUNXI_FUNCTION(0x0, "gpio_in"), 1621 SUNXI_FUNCTION(0x0, "gpio_in"),
1622 SUNXI_FUNCTION(0x1, "gpio_out"), 1622 SUNXI_FUNCTION(0x1, "gpio_out"),
1623 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ 1623 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
1624 SUNXI_FUNCTION(0x3, "uart3"), /* RX */ 1624 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
1625 SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */ 1625 SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */
1626 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11, 1626 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
1627 SUNXI_FUNCTION(0x0, "gpio_in"), 1627 SUNXI_FUNCTION(0x0, "gpio_in"),
1628 SUNXI_FUNCTION(0x1, "gpio_out"), 1628 SUNXI_FUNCTION(0x1, "gpio_out"),
1629 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ 1629 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
1630 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ 1630 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
1631 SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */ 1631 SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */
1632 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12, 1632 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
1633 SUNXI_FUNCTION(0x0, "gpio_in"), 1633 SUNXI_FUNCTION(0x0, "gpio_in"),
1634 SUNXI_FUNCTION(0x1, "gpio_out"), 1634 SUNXI_FUNCTION(0x1, "gpio_out"),
1635 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ 1635 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
1636 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */ 1636 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
1637 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */ 1637 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
1638 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG13, 1638 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
1639 SUNXI_FUNCTION(0x0, "gpio_in"), 1639 SUNXI_FUNCTION(0x0, "gpio_in"),
1640 SUNXI_FUNCTION(0x1, "gpio_out"), 1640 SUNXI_FUNCTION(0x1, "gpio_out"),
1641 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ 1641 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
@@ -1646,358 +1646,358 @@ static const struct sunxi_desc_pin sun5i_a10s_pins[] = {
1646 1646
1647static const struct sunxi_desc_pin sun5i_a13_pins[] = { 1647static const struct sunxi_desc_pin sun5i_a13_pins[] = {
1648 /* Hole */ 1648 /* Hole */
1649 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0, 1649 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
1650 SUNXI_FUNCTION(0x0, "gpio_in"), 1650 SUNXI_FUNCTION(0x0, "gpio_in"),
1651 SUNXI_FUNCTION(0x1, "gpio_out"), 1651 SUNXI_FUNCTION(0x1, "gpio_out"),
1652 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ 1652 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
1653 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1, 1653 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
1654 SUNXI_FUNCTION(0x0, "gpio_in"), 1654 SUNXI_FUNCTION(0x0, "gpio_in"),
1655 SUNXI_FUNCTION(0x1, "gpio_out"), 1655 SUNXI_FUNCTION(0x1, "gpio_out"),
1656 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ 1656 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
1657 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2, 1657 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
1658 SUNXI_FUNCTION(0x0, "gpio_in"), 1658 SUNXI_FUNCTION(0x0, "gpio_in"),
1659 SUNXI_FUNCTION(0x1, "gpio_out"), 1659 SUNXI_FUNCTION(0x1, "gpio_out"),
1660 SUNXI_FUNCTION(0x2, "pwm"), 1660 SUNXI_FUNCTION(0x2, "pwm"),
1661 SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */ 1661 SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */
1662 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3, 1662 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
1663 SUNXI_FUNCTION(0x0, "gpio_in"), 1663 SUNXI_FUNCTION(0x0, "gpio_in"),
1664 SUNXI_FUNCTION(0x1, "gpio_out"), 1664 SUNXI_FUNCTION(0x1, "gpio_out"),
1665 SUNXI_FUNCTION(0x2, "ir0"), /* TX */ 1665 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
1666 SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */ 1666 SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */
1667 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4, 1667 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
1668 SUNXI_FUNCTION(0x0, "gpio_in"), 1668 SUNXI_FUNCTION(0x0, "gpio_in"),
1669 SUNXI_FUNCTION(0x1, "gpio_out"), 1669 SUNXI_FUNCTION(0x1, "gpio_out"),
1670 SUNXI_FUNCTION(0x2, "ir0"), /* RX */ 1670 SUNXI_FUNCTION(0x2, "ir0"), /* RX */
1671 SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */ 1671 SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */
1672 /* Hole */ 1672 /* Hole */
1673 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10, 1673 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
1674 SUNXI_FUNCTION(0x0, "gpio_in"), 1674 SUNXI_FUNCTION(0x0, "gpio_in"),
1675 SUNXI_FUNCTION(0x1, "gpio_out"), 1675 SUNXI_FUNCTION(0x1, "gpio_out"),
1676 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */ 1676 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
1677 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */ 1677 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
1678 /* Hole */ 1678 /* Hole */
1679 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15, 1679 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
1680 SUNXI_FUNCTION(0x0, "gpio_in"), 1680 SUNXI_FUNCTION(0x0, "gpio_in"),
1681 SUNXI_FUNCTION(0x1, "gpio_out"), 1681 SUNXI_FUNCTION(0x1, "gpio_out"),
1682 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ 1682 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
1683 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16, 1683 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
1684 SUNXI_FUNCTION(0x0, "gpio_in"), 1684 SUNXI_FUNCTION(0x0, "gpio_in"),
1685 SUNXI_FUNCTION(0x1, "gpio_out"), 1685 SUNXI_FUNCTION(0x1, "gpio_out"),
1686 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ 1686 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
1687 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17, 1687 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
1688 SUNXI_FUNCTION(0x0, "gpio_in"), 1688 SUNXI_FUNCTION(0x0, "gpio_in"),
1689 SUNXI_FUNCTION(0x1, "gpio_out"), 1689 SUNXI_FUNCTION(0x1, "gpio_out"),
1690 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ 1690 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
1691 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18, 1691 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
1692 SUNXI_FUNCTION(0x0, "gpio_in"), 1692 SUNXI_FUNCTION(0x0, "gpio_in"),
1693 SUNXI_FUNCTION(0x1, "gpio_out"), 1693 SUNXI_FUNCTION(0x1, "gpio_out"),
1694 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ 1694 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
1695 /* Hole */ 1695 /* Hole */
1696 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0, 1696 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
1697 SUNXI_FUNCTION(0x0, "gpio_in"), 1697 SUNXI_FUNCTION(0x0, "gpio_in"),
1698 SUNXI_FUNCTION(0x1, "gpio_out"), 1698 SUNXI_FUNCTION(0x1, "gpio_out"),
1699 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ 1699 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
1700 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ 1700 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
1701 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1, 1701 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
1702 SUNXI_FUNCTION(0x0, "gpio_in"), 1702 SUNXI_FUNCTION(0x0, "gpio_in"),
1703 SUNXI_FUNCTION(0x1, "gpio_out"), 1703 SUNXI_FUNCTION(0x1, "gpio_out"),
1704 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ 1704 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
1705 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ 1705 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
1706 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2, 1706 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
1707 SUNXI_FUNCTION(0x0, "gpio_in"), 1707 SUNXI_FUNCTION(0x0, "gpio_in"),
1708 SUNXI_FUNCTION(0x1, "gpio_out"), 1708 SUNXI_FUNCTION(0x1, "gpio_out"),
1709 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ 1709 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
1710 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ 1710 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
1711 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3, 1711 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
1712 SUNXI_FUNCTION(0x0, "gpio_in"), 1712 SUNXI_FUNCTION(0x0, "gpio_in"),
1713 SUNXI_FUNCTION(0x1, "gpio_out"), 1713 SUNXI_FUNCTION(0x1, "gpio_out"),
1714 SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */ 1714 SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
1715 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ 1715 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
1716 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4, 1716 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
1717 SUNXI_FUNCTION(0x0, "gpio_in"), 1717 SUNXI_FUNCTION(0x0, "gpio_in"),
1718 SUNXI_FUNCTION(0x1, "gpio_out"), 1718 SUNXI_FUNCTION(0x1, "gpio_out"),
1719 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ 1719 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
1720 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5, 1720 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
1721 SUNXI_FUNCTION(0x0, "gpio_in"), 1721 SUNXI_FUNCTION(0x0, "gpio_in"),
1722 SUNXI_FUNCTION(0x1, "gpio_out"), 1722 SUNXI_FUNCTION(0x1, "gpio_out"),
1723 SUNXI_FUNCTION(0x2, "nand0")), /* NRE */ 1723 SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
1724 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6, 1724 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
1725 SUNXI_FUNCTION(0x0, "gpio_in"), 1725 SUNXI_FUNCTION(0x0, "gpio_in"),
1726 SUNXI_FUNCTION(0x1, "gpio_out"), 1726 SUNXI_FUNCTION(0x1, "gpio_out"),
1727 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ 1727 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
1728 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ 1728 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
1729 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7, 1729 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
1730 SUNXI_FUNCTION(0x0, "gpio_in"), 1730 SUNXI_FUNCTION(0x0, "gpio_in"),
1731 SUNXI_FUNCTION(0x1, "gpio_out"), 1731 SUNXI_FUNCTION(0x1, "gpio_out"),
1732 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */ 1732 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
1733 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ 1733 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
1734 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8, 1734 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
1735 SUNXI_FUNCTION(0x0, "gpio_in"), 1735 SUNXI_FUNCTION(0x0, "gpio_in"),
1736 SUNXI_FUNCTION(0x1, "gpio_out"), 1736 SUNXI_FUNCTION(0x1, "gpio_out"),
1737 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ 1737 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
1738 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ 1738 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
1739 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9, 1739 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
1740 SUNXI_FUNCTION(0x0, "gpio_in"), 1740 SUNXI_FUNCTION(0x0, "gpio_in"),
1741 SUNXI_FUNCTION(0x1, "gpio_out"), 1741 SUNXI_FUNCTION(0x1, "gpio_out"),
1742 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ 1742 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
1743 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ 1743 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
1744 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10, 1744 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
1745 SUNXI_FUNCTION(0x0, "gpio_in"), 1745 SUNXI_FUNCTION(0x0, "gpio_in"),
1746 SUNXI_FUNCTION(0x1, "gpio_out"), 1746 SUNXI_FUNCTION(0x1, "gpio_out"),
1747 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ 1747 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
1748 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ 1748 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
1749 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11, 1749 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
1750 SUNXI_FUNCTION(0x0, "gpio_in"), 1750 SUNXI_FUNCTION(0x0, "gpio_in"),
1751 SUNXI_FUNCTION(0x1, "gpio_out"), 1751 SUNXI_FUNCTION(0x1, "gpio_out"),
1752 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ 1752 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
1753 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ 1753 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
1754 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12, 1754 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
1755 SUNXI_FUNCTION(0x0, "gpio_in"), 1755 SUNXI_FUNCTION(0x0, "gpio_in"),
1756 SUNXI_FUNCTION(0x1, "gpio_out"), 1756 SUNXI_FUNCTION(0x1, "gpio_out"),
1757 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */ 1757 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
1758 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ 1758 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
1759 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13, 1759 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
1760 SUNXI_FUNCTION(0x0, "gpio_in"), 1760 SUNXI_FUNCTION(0x0, "gpio_in"),
1761 SUNXI_FUNCTION(0x1, "gpio_out"), 1761 SUNXI_FUNCTION(0x1, "gpio_out"),
1762 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */ 1762 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
1763 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ 1763 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
1764 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14, 1764 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
1765 SUNXI_FUNCTION(0x0, "gpio_in"), 1765 SUNXI_FUNCTION(0x0, "gpio_in"),
1766 SUNXI_FUNCTION(0x1, "gpio_out"), 1766 SUNXI_FUNCTION(0x1, "gpio_out"),
1767 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */ 1767 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
1768 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ 1768 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
1769 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15, 1769 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
1770 SUNXI_FUNCTION(0x0, "gpio_in"), 1770 SUNXI_FUNCTION(0x0, "gpio_in"),
1771 SUNXI_FUNCTION(0x1, "gpio_out"), 1771 SUNXI_FUNCTION(0x1, "gpio_out"),
1772 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */ 1772 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
1773 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ 1773 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
1774 /* Hole */ 1774 /* Hole */
1775 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19, 1775 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
1776 SUNXI_FUNCTION(0x0, "gpio_in"), 1776 SUNXI_FUNCTION(0x0, "gpio_in"),
1777 SUNXI_FUNCTION(0x1, "gpio_out"), 1777 SUNXI_FUNCTION(0x1, "gpio_out"),
1778 SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */ 1778 SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */
1779 SUNXI_FUNCTION(0x4, "uart3")), /* RTS */ 1779 SUNXI_FUNCTION(0x4, "uart3")), /* RTS */
1780 /* Hole */ 1780 /* Hole */
1781 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2, 1781 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
1782 SUNXI_FUNCTION(0x0, "gpio_in"), 1782 SUNXI_FUNCTION(0x0, "gpio_in"),
1783 SUNXI_FUNCTION(0x1, "gpio_out"), 1783 SUNXI_FUNCTION(0x1, "gpio_out"),
1784 SUNXI_FUNCTION(0x2, "lcd0")), /* D2 */ 1784 SUNXI_FUNCTION(0x2, "lcd0")), /* D2 */
1785 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3, 1785 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
1786 SUNXI_FUNCTION(0x0, "gpio_in"), 1786 SUNXI_FUNCTION(0x0, "gpio_in"),
1787 SUNXI_FUNCTION(0x1, "gpio_out"), 1787 SUNXI_FUNCTION(0x1, "gpio_out"),
1788 SUNXI_FUNCTION(0x2, "lcd0")), /* D3 */ 1788 SUNXI_FUNCTION(0x2, "lcd0")), /* D3 */
1789 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4, 1789 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
1790 SUNXI_FUNCTION(0x0, "gpio_in"), 1790 SUNXI_FUNCTION(0x0, "gpio_in"),
1791 SUNXI_FUNCTION(0x1, "gpio_out"), 1791 SUNXI_FUNCTION(0x1, "gpio_out"),
1792 SUNXI_FUNCTION(0x2, "lcd0")), /* D4 */ 1792 SUNXI_FUNCTION(0x2, "lcd0")), /* D4 */
1793 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5, 1793 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
1794 SUNXI_FUNCTION(0x0, "gpio_in"), 1794 SUNXI_FUNCTION(0x0, "gpio_in"),
1795 SUNXI_FUNCTION(0x1, "gpio_out"), 1795 SUNXI_FUNCTION(0x1, "gpio_out"),
1796 SUNXI_FUNCTION(0x2, "lcd0")), /* D5 */ 1796 SUNXI_FUNCTION(0x2, "lcd0")), /* D5 */
1797 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6, 1797 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
1798 SUNXI_FUNCTION(0x0, "gpio_in"), 1798 SUNXI_FUNCTION(0x0, "gpio_in"),
1799 SUNXI_FUNCTION(0x1, "gpio_out"), 1799 SUNXI_FUNCTION(0x1, "gpio_out"),
1800 SUNXI_FUNCTION(0x2, "lcd0")), /* D6 */ 1800 SUNXI_FUNCTION(0x2, "lcd0")), /* D6 */
1801 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7, 1801 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
1802 SUNXI_FUNCTION(0x0, "gpio_in"), 1802 SUNXI_FUNCTION(0x0, "gpio_in"),
1803 SUNXI_FUNCTION(0x1, "gpio_out"), 1803 SUNXI_FUNCTION(0x1, "gpio_out"),
1804 SUNXI_FUNCTION(0x2, "lcd0")), /* D7 */ 1804 SUNXI_FUNCTION(0x2, "lcd0")), /* D7 */
1805 /* Hole */ 1805 /* Hole */
1806 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10, 1806 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
1807 SUNXI_FUNCTION(0x0, "gpio_in"), 1807 SUNXI_FUNCTION(0x0, "gpio_in"),
1808 SUNXI_FUNCTION(0x1, "gpio_out"), 1808 SUNXI_FUNCTION(0x1, "gpio_out"),
1809 SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */ 1809 SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */
1810 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11, 1810 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
1811 SUNXI_FUNCTION(0x0, "gpio_in"), 1811 SUNXI_FUNCTION(0x0, "gpio_in"),
1812 SUNXI_FUNCTION(0x1, "gpio_out"), 1812 SUNXI_FUNCTION(0x1, "gpio_out"),
1813 SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */ 1813 SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */
1814 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12, 1814 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
1815 SUNXI_FUNCTION(0x0, "gpio_in"), 1815 SUNXI_FUNCTION(0x0, "gpio_in"),
1816 SUNXI_FUNCTION(0x1, "gpio_out"), 1816 SUNXI_FUNCTION(0x1, "gpio_out"),
1817 SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */ 1817 SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */
1818 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13, 1818 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
1819 SUNXI_FUNCTION(0x0, "gpio_in"), 1819 SUNXI_FUNCTION(0x0, "gpio_in"),
1820 SUNXI_FUNCTION(0x1, "gpio_out"), 1820 SUNXI_FUNCTION(0x1, "gpio_out"),
1821 SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */ 1821 SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */
1822 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14, 1822 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
1823 SUNXI_FUNCTION(0x0, "gpio_in"), 1823 SUNXI_FUNCTION(0x0, "gpio_in"),
1824 SUNXI_FUNCTION(0x1, "gpio_out"), 1824 SUNXI_FUNCTION(0x1, "gpio_out"),
1825 SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */ 1825 SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
1826 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15, 1826 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
1827 SUNXI_FUNCTION(0x0, "gpio_in"), 1827 SUNXI_FUNCTION(0x0, "gpio_in"),
1828 SUNXI_FUNCTION(0x1, "gpio_out"), 1828 SUNXI_FUNCTION(0x1, "gpio_out"),
1829 SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */ 1829 SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
1830 /* Hole */ 1830 /* Hole */
1831 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18, 1831 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
1832 SUNXI_FUNCTION(0x0, "gpio_in"), 1832 SUNXI_FUNCTION(0x0, "gpio_in"),
1833 SUNXI_FUNCTION(0x1, "gpio_out"), 1833 SUNXI_FUNCTION(0x1, "gpio_out"),
1834 SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */ 1834 SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */
1835 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19, 1835 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
1836 SUNXI_FUNCTION(0x0, "gpio_in"), 1836 SUNXI_FUNCTION(0x0, "gpio_in"),
1837 SUNXI_FUNCTION(0x1, "gpio_out"), 1837 SUNXI_FUNCTION(0x1, "gpio_out"),
1838 SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */ 1838 SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */
1839 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20, 1839 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
1840 SUNXI_FUNCTION(0x0, "gpio_in"), 1840 SUNXI_FUNCTION(0x0, "gpio_in"),
1841 SUNXI_FUNCTION(0x1, "gpio_out"), 1841 SUNXI_FUNCTION(0x1, "gpio_out"),
1842 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */ 1842 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
1843 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21, 1843 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
1844 SUNXI_FUNCTION(0x0, "gpio_in"), 1844 SUNXI_FUNCTION(0x0, "gpio_in"),
1845 SUNXI_FUNCTION(0x1, "gpio_out"), 1845 SUNXI_FUNCTION(0x1, "gpio_out"),
1846 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */ 1846 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
1847 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22, 1847 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
1848 SUNXI_FUNCTION(0x0, "gpio_in"), 1848 SUNXI_FUNCTION(0x0, "gpio_in"),
1849 SUNXI_FUNCTION(0x1, "gpio_out"), 1849 SUNXI_FUNCTION(0x1, "gpio_out"),
1850 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */ 1850 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
1851 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23, 1851 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
1852 SUNXI_FUNCTION(0x0, "gpio_in"), 1852 SUNXI_FUNCTION(0x0, "gpio_in"),
1853 SUNXI_FUNCTION(0x1, "gpio_out"), 1853 SUNXI_FUNCTION(0x1, "gpio_out"),
1854 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */ 1854 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
1855 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24, 1855 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
1856 SUNXI_FUNCTION(0x0, "gpio_in"), 1856 SUNXI_FUNCTION(0x0, "gpio_in"),
1857 SUNXI_FUNCTION(0x1, "gpio_out"), 1857 SUNXI_FUNCTION(0x1, "gpio_out"),
1858 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */ 1858 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
1859 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25, 1859 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
1860 SUNXI_FUNCTION(0x0, "gpio_in"), 1860 SUNXI_FUNCTION(0x0, "gpio_in"),
1861 SUNXI_FUNCTION(0x1, "gpio_out"), 1861 SUNXI_FUNCTION(0x1, "gpio_out"),
1862 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */ 1862 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
1863 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26, 1863 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
1864 SUNXI_FUNCTION(0x0, "gpio_in"), 1864 SUNXI_FUNCTION(0x0, "gpio_in"),
1865 SUNXI_FUNCTION(0x1, "gpio_out"), 1865 SUNXI_FUNCTION(0x1, "gpio_out"),
1866 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */ 1866 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
1867 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27, 1867 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
1868 SUNXI_FUNCTION(0x0, "gpio_in"), 1868 SUNXI_FUNCTION(0x0, "gpio_in"),
1869 SUNXI_FUNCTION(0x1, "gpio_out"), 1869 SUNXI_FUNCTION(0x1, "gpio_out"),
1870 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */ 1870 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
1871 /* Hole */ 1871 /* Hole */
1872 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0, 1872 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
1873 SUNXI_FUNCTION(0x0, "gpio_in"), 1873 SUNXI_FUNCTION(0x0, "gpio_in"),
1874 SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */ 1874 SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */
1875 SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */ 1875 SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */
1876 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */ 1876 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
1877 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1, 1877 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
1878 SUNXI_FUNCTION(0x0, "gpio_in"), 1878 SUNXI_FUNCTION(0x0, "gpio_in"),
1879 SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */ 1879 SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */
1880 SUNXI_FUNCTION(0x4, "spi2"), /* CLK */ 1880 SUNXI_FUNCTION(0x4, "spi2"), /* CLK */
1881 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */ 1881 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
1882 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2, 1882 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
1883 SUNXI_FUNCTION(0x0, "gpio_in"), 1883 SUNXI_FUNCTION(0x0, "gpio_in"),
1884 SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */ 1884 SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */
1885 SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */ 1885 SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */
1886 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3, 1886 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
1887 SUNXI_FUNCTION(0x0, "gpio_in"), 1887 SUNXI_FUNCTION(0x0, "gpio_in"),
1888 SUNXI_FUNCTION(0x1, "gpio_out"), 1888 SUNXI_FUNCTION(0x1, "gpio_out"),
1889 SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */ 1889 SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */
1890 SUNXI_FUNCTION(0x4, "spi2")), /* MISO */ 1890 SUNXI_FUNCTION(0x4, "spi2")), /* MISO */
1891 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4, 1891 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
1892 SUNXI_FUNCTION(0x0, "gpio_in"), 1892 SUNXI_FUNCTION(0x0, "gpio_in"),
1893 SUNXI_FUNCTION(0x1, "gpio_out"), 1893 SUNXI_FUNCTION(0x1, "gpio_out"),
1894 SUNXI_FUNCTION(0x3, "csi0"), /* D0 */ 1894 SUNXI_FUNCTION(0x3, "csi0"), /* D0 */
1895 SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */ 1895 SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */
1896 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5, 1896 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
1897 SUNXI_FUNCTION(0x0, "gpio_in"), 1897 SUNXI_FUNCTION(0x0, "gpio_in"),
1898 SUNXI_FUNCTION(0x1, "gpio_out"), 1898 SUNXI_FUNCTION(0x1, "gpio_out"),
1899 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */ 1899 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
1900 SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */ 1900 SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */
1901 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6, 1901 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
1902 SUNXI_FUNCTION(0x0, "gpio_in"), 1902 SUNXI_FUNCTION(0x0, "gpio_in"),
1903 SUNXI_FUNCTION(0x1, "gpio_out"), 1903 SUNXI_FUNCTION(0x1, "gpio_out"),
1904 SUNXI_FUNCTION(0x3, "csi0"), /* D2 */ 1904 SUNXI_FUNCTION(0x3, "csi0"), /* D2 */
1905 SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */ 1905 SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */
1906 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7, 1906 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
1907 SUNXI_FUNCTION(0x0, "gpio_in"), 1907 SUNXI_FUNCTION(0x0, "gpio_in"),
1908 SUNXI_FUNCTION(0x1, "gpio_out"), 1908 SUNXI_FUNCTION(0x1, "gpio_out"),
1909 SUNXI_FUNCTION(0x3, "csi0"), /* D3 */ 1909 SUNXI_FUNCTION(0x3, "csi0"), /* D3 */
1910 SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */ 1910 SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */
1911 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8, 1911 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
1912 SUNXI_FUNCTION(0x0, "gpio_in"), 1912 SUNXI_FUNCTION(0x0, "gpio_in"),
1913 SUNXI_FUNCTION(0x1, "gpio_out"), 1913 SUNXI_FUNCTION(0x1, "gpio_out"),
1914 SUNXI_FUNCTION(0x3, "csi0"), /* D4 */ 1914 SUNXI_FUNCTION(0x3, "csi0"), /* D4 */
1915 SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */ 1915 SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */
1916 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9, 1916 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
1917 SUNXI_FUNCTION(0x0, "gpio_in"), 1917 SUNXI_FUNCTION(0x0, "gpio_in"),
1918 SUNXI_FUNCTION(0x1, "gpio_out"), 1918 SUNXI_FUNCTION(0x1, "gpio_out"),
1919 SUNXI_FUNCTION(0x3, "csi0"), /* D5 */ 1919 SUNXI_FUNCTION(0x3, "csi0"), /* D5 */
1920 SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */ 1920 SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */
1921 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10, 1921 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
1922 SUNXI_FUNCTION(0x0, "gpio_in"), 1922 SUNXI_FUNCTION(0x0, "gpio_in"),
1923 SUNXI_FUNCTION(0x1, "gpio_out"), 1923 SUNXI_FUNCTION(0x1, "gpio_out"),
1924 SUNXI_FUNCTION(0x3, "csi0"), /* D6 */ 1924 SUNXI_FUNCTION(0x3, "csi0"), /* D6 */
1925 SUNXI_FUNCTION(0x4, "uart1")), /* TX */ 1925 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
1926 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11, 1926 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
1927 SUNXI_FUNCTION(0x0, "gpio_in"), 1927 SUNXI_FUNCTION(0x0, "gpio_in"),
1928 SUNXI_FUNCTION(0x1, "gpio_out"), 1928 SUNXI_FUNCTION(0x1, "gpio_out"),
1929 SUNXI_FUNCTION(0x3, "csi0"), /* D7 */ 1929 SUNXI_FUNCTION(0x3, "csi0"), /* D7 */
1930 SUNXI_FUNCTION(0x4, "uart1")), /* RX */ 1930 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
1931 /* Hole */ 1931 /* Hole */
1932 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0, 1932 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
1933 SUNXI_FUNCTION(0x0, "gpio_in"), 1933 SUNXI_FUNCTION(0x0, "gpio_in"),
1934 SUNXI_FUNCTION(0x1, "gpio_out"), 1934 SUNXI_FUNCTION(0x1, "gpio_out"),
1935 SUNXI_FUNCTION(0x2, "mmc0")), /* D1 */ 1935 SUNXI_FUNCTION(0x2, "mmc0")), /* D1 */
1936 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1, 1936 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
1937 SUNXI_FUNCTION(0x0, "gpio_in"), 1937 SUNXI_FUNCTION(0x0, "gpio_in"),
1938 SUNXI_FUNCTION(0x1, "gpio_out"), 1938 SUNXI_FUNCTION(0x1, "gpio_out"),
1939 SUNXI_FUNCTION(0x2, "mmc0")), /* D0 */ 1939 SUNXI_FUNCTION(0x2, "mmc0")), /* D0 */
1940 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2, 1940 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
1941 SUNXI_FUNCTION(0x0, "gpio_in"), 1941 SUNXI_FUNCTION(0x0, "gpio_in"),
1942 SUNXI_FUNCTION(0x1, "gpio_out"), 1942 SUNXI_FUNCTION(0x1, "gpio_out"),
1943 SUNXI_FUNCTION(0x2, "mmc0")), /* CLK */ 1943 SUNXI_FUNCTION(0x2, "mmc0")), /* CLK */
1944 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3, 1944 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
1945 SUNXI_FUNCTION(0x0, "gpio_in"), 1945 SUNXI_FUNCTION(0x0, "gpio_in"),
1946 SUNXI_FUNCTION(0x1, "gpio_out"), 1946 SUNXI_FUNCTION(0x1, "gpio_out"),
1947 SUNXI_FUNCTION(0x2, "mmc0")), /* CMD */ 1947 SUNXI_FUNCTION(0x2, "mmc0")), /* CMD */
1948 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4, 1948 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
1949 SUNXI_FUNCTION(0x0, "gpio_in"), 1949 SUNXI_FUNCTION(0x0, "gpio_in"),
1950 SUNXI_FUNCTION(0x1, "gpio_out"), 1950 SUNXI_FUNCTION(0x1, "gpio_out"),
1951 SUNXI_FUNCTION(0x2, "mmc0")), /* D3 */ 1951 SUNXI_FUNCTION(0x2, "mmc0")), /* D3 */
1952 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5, 1952 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
1953 SUNXI_FUNCTION(0x0, "gpio_in"), 1953 SUNXI_FUNCTION(0x0, "gpio_in"),
1954 SUNXI_FUNCTION(0x1, "gpio_out"), 1954 SUNXI_FUNCTION(0x1, "gpio_out"),
1955 SUNXI_FUNCTION(0x2, "mmc0")), /* D2 */ 1955 SUNXI_FUNCTION(0x2, "mmc0")), /* D2 */
1956 /* Hole */ 1956 /* Hole */
1957 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0, 1957 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
1958 SUNXI_FUNCTION(0x0, "gpio_in"), 1958 SUNXI_FUNCTION(0x0, "gpio_in"),
1959 SUNXI_FUNCTION(0x1, "gpio_out"), 1959 SUNXI_FUNCTION(0x1, "gpio_out"),
1960 SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */ 1960 SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */
1961 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1, 1961 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
1962 SUNXI_FUNCTION(0x0, "gpio_in"), 1962 SUNXI_FUNCTION(0x0, "gpio_in"),
1963 SUNXI_FUNCTION(0x1, "gpio_out"), 1963 SUNXI_FUNCTION(0x1, "gpio_out"),
1964 SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */ 1964 SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */
1965 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2, 1965 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
1966 SUNXI_FUNCTION(0x0, "gpio_in"), 1966 SUNXI_FUNCTION(0x0, "gpio_in"),
1967 SUNXI_FUNCTION(0x1, "gpio_out"), 1967 SUNXI_FUNCTION(0x1, "gpio_out"),
1968 SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */ 1968 SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */
1969 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3, 1969 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
1970 SUNXI_FUNCTION(0x0, "gpio_in"), 1970 SUNXI_FUNCTION(0x0, "gpio_in"),
1971 SUNXI_FUNCTION(0x1, "gpio_out"), 1971 SUNXI_FUNCTION(0x1, "gpio_out"),
1972 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ 1972 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
1973 SUNXI_FUNCTION(0x4, "uart1"), /* TX */ 1973 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
1974 SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */ 1974 SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */
1975 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4, 1975 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
1976 SUNXI_FUNCTION(0x0, "gpio_in"), 1976 SUNXI_FUNCTION(0x0, "gpio_in"),
1977 SUNXI_FUNCTION(0x1, "gpio_out"), 1977 SUNXI_FUNCTION(0x1, "gpio_out"),
1978 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ 1978 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
1979 SUNXI_FUNCTION(0x4, "uart1"), /* RX */ 1979 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
1980 SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */ 1980 SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */
1981 /* Hole */ 1981 /* Hole */
1982 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9, 1982 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
1983 SUNXI_FUNCTION(0x0, "gpio_in"), 1983 SUNXI_FUNCTION(0x0, "gpio_in"),
1984 SUNXI_FUNCTION(0x1, "gpio_out"), 1984 SUNXI_FUNCTION(0x1, "gpio_out"),
1985 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ 1985 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
1986 SUNXI_FUNCTION(0x3, "uart3"), /* TX */ 1986 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
1987 SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */ 1987 SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */
1988 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10, 1988 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
1989 SUNXI_FUNCTION(0x0, "gpio_in"), 1989 SUNXI_FUNCTION(0x0, "gpio_in"),
1990 SUNXI_FUNCTION(0x1, "gpio_out"), 1990 SUNXI_FUNCTION(0x1, "gpio_out"),
1991 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ 1991 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
1992 SUNXI_FUNCTION(0x3, "uart3"), /* RX */ 1992 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
1993 SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */ 1993 SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */
1994 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11, 1994 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
1995 SUNXI_FUNCTION(0x0, "gpio_in"), 1995 SUNXI_FUNCTION(0x0, "gpio_in"),
1996 SUNXI_FUNCTION(0x1, "gpio_out"), 1996 SUNXI_FUNCTION(0x1, "gpio_out"),
1997 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ 1997 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
1998 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ 1998 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
1999 SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */ 1999 SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */
2000 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12, 2000 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
2001 SUNXI_FUNCTION(0x0, "gpio_in"), 2001 SUNXI_FUNCTION(0x0, "gpio_in"),
2002 SUNXI_FUNCTION(0x1, "gpio_out"), 2002 SUNXI_FUNCTION(0x1, "gpio_out"),
2003 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ 2003 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
@@ -2006,981 +2006,981 @@ static const struct sunxi_desc_pin sun5i_a13_pins[] = {
2006}; 2006};
2007 2007
2008static const struct sunxi_desc_pin sun6i_a31_pins[] = { 2008static const struct sunxi_desc_pin sun6i_a31_pins[] = {
2009 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0, 2009 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
2010 SUNXI_FUNCTION(0x0, "gpio_in"), 2010 SUNXI_FUNCTION(0x0, "gpio_in"),
2011 SUNXI_FUNCTION(0x1, "gpio_out"), 2011 SUNXI_FUNCTION(0x1, "gpio_out"),
2012 SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */ 2012 SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */
2013 SUNXI_FUNCTION(0x3, "lcd1"), /* D0 */ 2013 SUNXI_FUNCTION(0x3, "lcd1"), /* D0 */
2014 SUNXI_FUNCTION(0x4, "uart1")), /* DTR */ 2014 SUNXI_FUNCTION(0x4, "uart1")), /* DTR */
2015 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1, 2015 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
2016 SUNXI_FUNCTION(0x0, "gpio_in"), 2016 SUNXI_FUNCTION(0x0, "gpio_in"),
2017 SUNXI_FUNCTION(0x1, "gpio_out"), 2017 SUNXI_FUNCTION(0x1, "gpio_out"),
2018 SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */ 2018 SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */
2019 SUNXI_FUNCTION(0x3, "lcd1"), /* D1 */ 2019 SUNXI_FUNCTION(0x3, "lcd1"), /* D1 */
2020 SUNXI_FUNCTION(0x4, "uart1")), /* DSR */ 2020 SUNXI_FUNCTION(0x4, "uart1")), /* DSR */
2021 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2, 2021 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
2022 SUNXI_FUNCTION(0x0, "gpio_in"), 2022 SUNXI_FUNCTION(0x0, "gpio_in"),
2023 SUNXI_FUNCTION(0x1, "gpio_out"), 2023 SUNXI_FUNCTION(0x1, "gpio_out"),
2024 SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */ 2024 SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
2025 SUNXI_FUNCTION(0x3, "lcd1"), /* D2 */ 2025 SUNXI_FUNCTION(0x3, "lcd1"), /* D2 */
2026 SUNXI_FUNCTION(0x4, "uart1")), /* DCD */ 2026 SUNXI_FUNCTION(0x4, "uart1")), /* DCD */
2027 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3, 2027 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
2028 SUNXI_FUNCTION(0x0, "gpio_in"), 2028 SUNXI_FUNCTION(0x0, "gpio_in"),
2029 SUNXI_FUNCTION(0x1, "gpio_out"), 2029 SUNXI_FUNCTION(0x1, "gpio_out"),
2030 SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */ 2030 SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
2031 SUNXI_FUNCTION(0x3, "lcd1"), /* D3 */ 2031 SUNXI_FUNCTION(0x3, "lcd1"), /* D3 */
2032 SUNXI_FUNCTION(0x4, "uart1")), /* RING */ 2032 SUNXI_FUNCTION(0x4, "uart1")), /* RING */
2033 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4, 2033 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
2034 SUNXI_FUNCTION(0x0, "gpio_in"), 2034 SUNXI_FUNCTION(0x0, "gpio_in"),
2035 SUNXI_FUNCTION(0x1, "gpio_out"), 2035 SUNXI_FUNCTION(0x1, "gpio_out"),
2036 SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */ 2036 SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */
2037 SUNXI_FUNCTION(0x3, "lcd1"), /* D4 */ 2037 SUNXI_FUNCTION(0x3, "lcd1"), /* D4 */
2038 SUNXI_FUNCTION(0x4, "uart1")), /* TX */ 2038 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
2039 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5, 2039 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
2040 SUNXI_FUNCTION(0x0, "gpio_in"), 2040 SUNXI_FUNCTION(0x0, "gpio_in"),
2041 SUNXI_FUNCTION(0x1, "gpio_out"), 2041 SUNXI_FUNCTION(0x1, "gpio_out"),
2042 SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */ 2042 SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */
2043 SUNXI_FUNCTION(0x3, "lcd1"), /* D5 */ 2043 SUNXI_FUNCTION(0x3, "lcd1"), /* D5 */
2044 SUNXI_FUNCTION(0x4, "uart1")), /* RX */ 2044 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
2045 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6, 2045 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
2046 SUNXI_FUNCTION(0x0, "gpio_in"), 2046 SUNXI_FUNCTION(0x0, "gpio_in"),
2047 SUNXI_FUNCTION(0x1, "gpio_out"), 2047 SUNXI_FUNCTION(0x1, "gpio_out"),
2048 SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */ 2048 SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */
2049 SUNXI_FUNCTION(0x3, "lcd1"), /* D6 */ 2049 SUNXI_FUNCTION(0x3, "lcd1"), /* D6 */
2050 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */ 2050 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */
2051 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7, 2051 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
2052 SUNXI_FUNCTION(0x0, "gpio_in"), 2052 SUNXI_FUNCTION(0x0, "gpio_in"),
2053 SUNXI_FUNCTION(0x1, "gpio_out"), 2053 SUNXI_FUNCTION(0x1, "gpio_out"),
2054 SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */ 2054 SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */
2055 SUNXI_FUNCTION(0x3, "lcd1"), /* D7 */ 2055 SUNXI_FUNCTION(0x3, "lcd1"), /* D7 */
2056 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */ 2056 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */
2057 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8, 2057 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
2058 SUNXI_FUNCTION(0x0, "gpio_in"), 2058 SUNXI_FUNCTION(0x0, "gpio_in"),
2059 SUNXI_FUNCTION(0x1, "gpio_out"), 2059 SUNXI_FUNCTION(0x1, "gpio_out"),
2060 SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */ 2060 SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */
2061 SUNXI_FUNCTION(0x3, "lcd1")), /* D8 */ 2061 SUNXI_FUNCTION(0x3, "lcd1")), /* D8 */
2062 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9, 2062 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
2063 SUNXI_FUNCTION(0x0, "gpio_in"), 2063 SUNXI_FUNCTION(0x0, "gpio_in"),
2064 SUNXI_FUNCTION(0x1, "gpio_out"), 2064 SUNXI_FUNCTION(0x1, "gpio_out"),
2065 SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */ 2065 SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
2066 SUNXI_FUNCTION(0x3, "lcd1"), /* D9 */ 2066 SUNXI_FUNCTION(0x3, "lcd1"), /* D9 */
2067 SUNXI_FUNCTION(0x4, "mmc3"), /* CMD */ 2067 SUNXI_FUNCTION(0x4, "mmc3"), /* CMD */
2068 SUNXI_FUNCTION(0x5, "mmc2")), /* CMD */ 2068 SUNXI_FUNCTION(0x5, "mmc2")), /* CMD */
2069 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10, 2069 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
2070 SUNXI_FUNCTION(0x0, "gpio_in"), 2070 SUNXI_FUNCTION(0x0, "gpio_in"),
2071 SUNXI_FUNCTION(0x1, "gpio_out"), 2071 SUNXI_FUNCTION(0x1, "gpio_out"),
2072 SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */ 2072 SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */
2073 SUNXI_FUNCTION(0x3, "lcd1"), /* D10 */ 2073 SUNXI_FUNCTION(0x3, "lcd1"), /* D10 */
2074 SUNXI_FUNCTION(0x4, "mmc3"), /* CLK */ 2074 SUNXI_FUNCTION(0x4, "mmc3"), /* CLK */
2075 SUNXI_FUNCTION(0x5, "mmc2")), /* CLK */ 2075 SUNXI_FUNCTION(0x5, "mmc2")), /* CLK */
2076 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11, 2076 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
2077 SUNXI_FUNCTION(0x0, "gpio_in"), 2077 SUNXI_FUNCTION(0x0, "gpio_in"),
2078 SUNXI_FUNCTION(0x1, "gpio_out"), 2078 SUNXI_FUNCTION(0x1, "gpio_out"),
2079 SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */ 2079 SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */
2080 SUNXI_FUNCTION(0x3, "lcd1"), /* D11 */ 2080 SUNXI_FUNCTION(0x3, "lcd1"), /* D11 */
2081 SUNXI_FUNCTION(0x4, "mmc3"), /* D0 */ 2081 SUNXI_FUNCTION(0x4, "mmc3"), /* D0 */
2082 SUNXI_FUNCTION(0x5, "mmc2")), /* D0 */ 2082 SUNXI_FUNCTION(0x5, "mmc2")), /* D0 */
2083 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12, 2083 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
2084 SUNXI_FUNCTION(0x0, "gpio_in"), 2084 SUNXI_FUNCTION(0x0, "gpio_in"),
2085 SUNXI_FUNCTION(0x1, "gpio_out"), 2085 SUNXI_FUNCTION(0x1, "gpio_out"),
2086 SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */ 2086 SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */
2087 SUNXI_FUNCTION(0x3, "lcd1"), /* D12 */ 2087 SUNXI_FUNCTION(0x3, "lcd1"), /* D12 */
2088 SUNXI_FUNCTION(0x4, "mmc3"), /* D1 */ 2088 SUNXI_FUNCTION(0x4, "mmc3"), /* D1 */
2089 SUNXI_FUNCTION(0x5, "mmc2")), /* D1 */ 2089 SUNXI_FUNCTION(0x5, "mmc2")), /* D1 */
2090 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13, 2090 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
2091 SUNXI_FUNCTION(0x0, "gpio_in"), 2091 SUNXI_FUNCTION(0x0, "gpio_in"),
2092 SUNXI_FUNCTION(0x1, "gpio_out"), 2092 SUNXI_FUNCTION(0x1, "gpio_out"),
2093 SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */ 2093 SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */
2094 SUNXI_FUNCTION(0x3, "lcd1"), /* D13 */ 2094 SUNXI_FUNCTION(0x3, "lcd1"), /* D13 */
2095 SUNXI_FUNCTION(0x4, "mmc3"), /* D2 */ 2095 SUNXI_FUNCTION(0x4, "mmc3"), /* D2 */
2096 SUNXI_FUNCTION(0x5, "mmc2")), /* D2 */ 2096 SUNXI_FUNCTION(0x5, "mmc2")), /* D2 */
2097 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14, 2097 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
2098 SUNXI_FUNCTION(0x0, "gpio_in"), 2098 SUNXI_FUNCTION(0x0, "gpio_in"),
2099 SUNXI_FUNCTION(0x1, "gpio_out"), 2099 SUNXI_FUNCTION(0x1, "gpio_out"),
2100 SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */ 2100 SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */
2101 SUNXI_FUNCTION(0x3, "lcd1"), /* D14 */ 2101 SUNXI_FUNCTION(0x3, "lcd1"), /* D14 */
2102 SUNXI_FUNCTION(0x4, "mmc3"), /* D3 */ 2102 SUNXI_FUNCTION(0x4, "mmc3"), /* D3 */
2103 SUNXI_FUNCTION(0x5, "mmc2")), /* D3 */ 2103 SUNXI_FUNCTION(0x5, "mmc2")), /* D3 */
2104 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15, 2104 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
2105 SUNXI_FUNCTION(0x0, "gpio_in"), 2105 SUNXI_FUNCTION(0x0, "gpio_in"),
2106 SUNXI_FUNCTION(0x1, "gpio_out"), 2106 SUNXI_FUNCTION(0x1, "gpio_out"),
2107 SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */ 2107 SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
2108 SUNXI_FUNCTION(0x3, "lcd1")), /* D15 */ 2108 SUNXI_FUNCTION(0x3, "lcd1")), /* D15 */
2109 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16, 2109 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
2110 SUNXI_FUNCTION(0x0, "gpio_in"), 2110 SUNXI_FUNCTION(0x0, "gpio_in"),
2111 SUNXI_FUNCTION(0x1, "gpio_out"), 2111 SUNXI_FUNCTION(0x1, "gpio_out"),
2112 SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */ 2112 SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
2113 SUNXI_FUNCTION(0x3, "lcd1")), /* D16 */ 2113 SUNXI_FUNCTION(0x3, "lcd1")), /* D16 */
2114 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17, 2114 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
2115 SUNXI_FUNCTION(0x0, "gpio_in"), 2115 SUNXI_FUNCTION(0x0, "gpio_in"),
2116 SUNXI_FUNCTION(0x1, "gpio_out"), 2116 SUNXI_FUNCTION(0x1, "gpio_out"),
2117 SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */ 2117 SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
2118 SUNXI_FUNCTION(0x3, "lcd1")), /* D17 */ 2118 SUNXI_FUNCTION(0x3, "lcd1")), /* D17 */
2119 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA18, 2119 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
2120 SUNXI_FUNCTION(0x0, "gpio_in"), 2120 SUNXI_FUNCTION(0x0, "gpio_in"),
2121 SUNXI_FUNCTION(0x1, "gpio_out"), 2121 SUNXI_FUNCTION(0x1, "gpio_out"),
2122 SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */ 2122 SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
2123 SUNXI_FUNCTION(0x3, "lcd1")), /* D18 */ 2123 SUNXI_FUNCTION(0x3, "lcd1")), /* D18 */
2124 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA19, 2124 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
2125 SUNXI_FUNCTION(0x0, "gpio_in"), 2125 SUNXI_FUNCTION(0x0, "gpio_in"),
2126 SUNXI_FUNCTION(0x1, "gpio_out"), 2126 SUNXI_FUNCTION(0x1, "gpio_out"),
2127 SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */ 2127 SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */
2128 SUNXI_FUNCTION(0x3, "lcd1"), /* D19 */ 2128 SUNXI_FUNCTION(0x3, "lcd1"), /* D19 */
2129 SUNXI_FUNCTION(0x4, "pwm3")), /* Positive */ 2129 SUNXI_FUNCTION(0x4, "pwm3")), /* Positive */
2130 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA20, 2130 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),
2131 SUNXI_FUNCTION(0x0, "gpio_in"), 2131 SUNXI_FUNCTION(0x0, "gpio_in"),
2132 SUNXI_FUNCTION(0x1, "gpio_out"), 2132 SUNXI_FUNCTION(0x1, "gpio_out"),
2133 SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */ 2133 SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */
2134 SUNXI_FUNCTION(0x3, "lcd1"), /* D20 */ 2134 SUNXI_FUNCTION(0x3, "lcd1"), /* D20 */
2135 SUNXI_FUNCTION(0x4, "pwm3")), /* Negative */ 2135 SUNXI_FUNCTION(0x4, "pwm3")), /* Negative */
2136 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA21, 2136 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),
2137 SUNXI_FUNCTION(0x0, "gpio_in"), 2137 SUNXI_FUNCTION(0x0, "gpio_in"),
2138 SUNXI_FUNCTION(0x1, "gpio_out"), 2138 SUNXI_FUNCTION(0x1, "gpio_out"),
2139 SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */ 2139 SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */
2140 SUNXI_FUNCTION(0x3, "lcd1"), /* D21 */ 2140 SUNXI_FUNCTION(0x3, "lcd1"), /* D21 */
2141 SUNXI_FUNCTION(0x4, "spi3")), /* CS0 */ 2141 SUNXI_FUNCTION(0x4, "spi3")), /* CS0 */
2142 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA22, 2142 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 22),
2143 SUNXI_FUNCTION(0x0, "gpio_in"), 2143 SUNXI_FUNCTION(0x0, "gpio_in"),
2144 SUNXI_FUNCTION(0x1, "gpio_out"), 2144 SUNXI_FUNCTION(0x1, "gpio_out"),
2145 SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */ 2145 SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */
2146 SUNXI_FUNCTION(0x3, "lcd1"), /* D22 */ 2146 SUNXI_FUNCTION(0x3, "lcd1"), /* D22 */
2147 SUNXI_FUNCTION(0x4, "spi3")), /* CLK */ 2147 SUNXI_FUNCTION(0x4, "spi3")), /* CLK */
2148 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA23, 2148 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 23),
2149 SUNXI_FUNCTION(0x0, "gpio_in"), 2149 SUNXI_FUNCTION(0x0, "gpio_in"),
2150 SUNXI_FUNCTION(0x1, "gpio_out"), 2150 SUNXI_FUNCTION(0x1, "gpio_out"),
2151 SUNXI_FUNCTION(0x2, "gmac"), /* COL */ 2151 SUNXI_FUNCTION(0x2, "gmac"), /* COL */
2152 SUNXI_FUNCTION(0x3, "lcd1"), /* D23 */ 2152 SUNXI_FUNCTION(0x3, "lcd1"), /* D23 */
2153 SUNXI_FUNCTION(0x4, "spi3")), /* MOSI */ 2153 SUNXI_FUNCTION(0x4, "spi3")), /* MOSI */
2154 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA24, 2154 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 24),
2155 SUNXI_FUNCTION(0x0, "gpio_in"), 2155 SUNXI_FUNCTION(0x0, "gpio_in"),
2156 SUNXI_FUNCTION(0x1, "gpio_out"), 2156 SUNXI_FUNCTION(0x1, "gpio_out"),
2157 SUNXI_FUNCTION(0x2, "gmac"), /* CRS */ 2157 SUNXI_FUNCTION(0x2, "gmac"), /* CRS */
2158 SUNXI_FUNCTION(0x3, "lcd1"), /* CLK */ 2158 SUNXI_FUNCTION(0x3, "lcd1"), /* CLK */
2159 SUNXI_FUNCTION(0x4, "spi3")), /* MISO */ 2159 SUNXI_FUNCTION(0x4, "spi3")), /* MISO */
2160 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA25, 2160 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 25),
2161 SUNXI_FUNCTION(0x0, "gpio_in"), 2161 SUNXI_FUNCTION(0x0, "gpio_in"),
2162 SUNXI_FUNCTION(0x1, "gpio_out"), 2162 SUNXI_FUNCTION(0x1, "gpio_out"),
2163 SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */ 2163 SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */
2164 SUNXI_FUNCTION(0x3, "lcd1"), /* DE */ 2164 SUNXI_FUNCTION(0x3, "lcd1"), /* DE */
2165 SUNXI_FUNCTION(0x4, "spi3")), /* CS1 */ 2165 SUNXI_FUNCTION(0x4, "spi3")), /* CS1 */
2166 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA26, 2166 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 26),
2167 SUNXI_FUNCTION(0x0, "gpio_in"), 2167 SUNXI_FUNCTION(0x0, "gpio_in"),
2168 SUNXI_FUNCTION(0x1, "gpio_out"), 2168 SUNXI_FUNCTION(0x1, "gpio_out"),
2169 SUNXI_FUNCTION(0x2, "gmac"), /* MDC */ 2169 SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
2170 SUNXI_FUNCTION(0x3, "lcd1")), /* HSYNC */ 2170 SUNXI_FUNCTION(0x3, "lcd1")), /* HSYNC */
2171 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA27, 2171 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
2172 SUNXI_FUNCTION(0x0, "gpio_in"), 2172 SUNXI_FUNCTION(0x0, "gpio_in"),
2173 SUNXI_FUNCTION(0x1, "gpio_out"), 2173 SUNXI_FUNCTION(0x1, "gpio_out"),
2174 SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */ 2174 SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */
2175 SUNXI_FUNCTION(0x3, "lcd1")), /* VSYNC */ 2175 SUNXI_FUNCTION(0x3, "lcd1")), /* VSYNC */
2176 /* Hole */ 2176 /* Hole */
2177 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0, 2177 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
2178 SUNXI_FUNCTION(0x0, "gpio_in"), 2178 SUNXI_FUNCTION(0x0, "gpio_in"),
2179 SUNXI_FUNCTION(0x1, "gpio_out"), 2179 SUNXI_FUNCTION(0x1, "gpio_out"),
2180 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */ 2180 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
2181 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */ 2181 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
2182 SUNXI_FUNCTION(0x4, "csi")), /* MCLK1 */ 2182 SUNXI_FUNCTION(0x4, "csi")), /* MCLK1 */
2183 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1, 2183 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
2184 SUNXI_FUNCTION(0x0, "gpio_in"), 2184 SUNXI_FUNCTION(0x0, "gpio_in"),
2185 SUNXI_FUNCTION(0x1, "gpio_out"), 2185 SUNXI_FUNCTION(0x1, "gpio_out"),
2186 SUNXI_FUNCTION(0x2, "i2s0")), /* BCLK */ 2186 SUNXI_FUNCTION(0x2, "i2s0")), /* BCLK */
2187 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2, 2187 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
2188 SUNXI_FUNCTION(0x0, "gpio_in"), 2188 SUNXI_FUNCTION(0x0, "gpio_in"),
2189 SUNXI_FUNCTION(0x1, "gpio_out"), 2189 SUNXI_FUNCTION(0x1, "gpio_out"),
2190 SUNXI_FUNCTION(0x2, "i2s0")), /* LRCK */ 2190 SUNXI_FUNCTION(0x2, "i2s0")), /* LRCK */
2191 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3, 2191 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
2192 SUNXI_FUNCTION(0x0, "gpio_in"), 2192 SUNXI_FUNCTION(0x0, "gpio_in"),
2193 SUNXI_FUNCTION(0x1, "gpio_out"), 2193 SUNXI_FUNCTION(0x1, "gpio_out"),
2194 SUNXI_FUNCTION(0x2, "i2s0")), /* DO0 */ 2194 SUNXI_FUNCTION(0x2, "i2s0")), /* DO0 */
2195 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4, 2195 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
2196 SUNXI_FUNCTION(0x0, "gpio_in"), 2196 SUNXI_FUNCTION(0x0, "gpio_in"),
2197 SUNXI_FUNCTION(0x1, "gpio_out"), 2197 SUNXI_FUNCTION(0x1, "gpio_out"),
2198 SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */ 2198 SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
2199 SUNXI_FUNCTION(0x3, "uart3")), /* RTS */ 2199 SUNXI_FUNCTION(0x3, "uart3")), /* RTS */
2200 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5, 2200 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
2201 SUNXI_FUNCTION(0x0, "gpio_in"), 2201 SUNXI_FUNCTION(0x0, "gpio_in"),
2202 SUNXI_FUNCTION(0x1, "gpio_out"), 2202 SUNXI_FUNCTION(0x1, "gpio_out"),
2203 SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */ 2203 SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
2204 SUNXI_FUNCTION(0x3, "uart3"), /* TX */ 2204 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
2205 SUNXI_FUNCTION(0x4, "i2c3")), /* SCK */ 2205 SUNXI_FUNCTION(0x4, "i2c3")), /* SCK */
2206 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6, 2206 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
2207 SUNXI_FUNCTION(0x0, "gpio_in"), 2207 SUNXI_FUNCTION(0x0, "gpio_in"),
2208 SUNXI_FUNCTION(0x1, "gpio_out"), 2208 SUNXI_FUNCTION(0x1, "gpio_out"),
2209 SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */ 2209 SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
2210 SUNXI_FUNCTION(0x3, "uart3"), /* RX */ 2210 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
2211 SUNXI_FUNCTION(0x4, "i2c3")), /* SDA */ 2211 SUNXI_FUNCTION(0x4, "i2c3")), /* SDA */
2212 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7, 2212 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
2213 SUNXI_FUNCTION(0x0, "gpio_in"), 2213 SUNXI_FUNCTION(0x0, "gpio_in"),
2214 SUNXI_FUNCTION(0x1, "gpio_out"), 2214 SUNXI_FUNCTION(0x1, "gpio_out"),
2215 SUNXI_FUNCTION(0x3, "i2s0")), /* DI */ 2215 SUNXI_FUNCTION(0x3, "i2s0")), /* DI */
2216 /* Hole */ 2216 /* Hole */
2217 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0, 2217 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
2218 SUNXI_FUNCTION(0x0, "gpio_in"), 2218 SUNXI_FUNCTION(0x0, "gpio_in"),
2219 SUNXI_FUNCTION(0x1, "gpio_out"), 2219 SUNXI_FUNCTION(0x1, "gpio_out"),
2220 SUNXI_FUNCTION(0x2, "nand0"), /* WE */ 2220 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
2221 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ 2221 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
2222 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1, 2222 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
2223 SUNXI_FUNCTION(0x0, "gpio_in"), 2223 SUNXI_FUNCTION(0x0, "gpio_in"),
2224 SUNXI_FUNCTION(0x1, "gpio_out"), 2224 SUNXI_FUNCTION(0x1, "gpio_out"),
2225 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */ 2225 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
2226 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ 2226 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
2227 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2, 2227 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
2228 SUNXI_FUNCTION(0x0, "gpio_in"), 2228 SUNXI_FUNCTION(0x0, "gpio_in"),
2229 SUNXI_FUNCTION(0x1, "gpio_out"), 2229 SUNXI_FUNCTION(0x1, "gpio_out"),
2230 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */ 2230 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
2231 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */ 2231 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
2232 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3, 2232 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
2233 SUNXI_FUNCTION(0x0, "gpio_in"), 2233 SUNXI_FUNCTION(0x0, "gpio_in"),
2234 SUNXI_FUNCTION(0x1, "gpio_out"), 2234 SUNXI_FUNCTION(0x1, "gpio_out"),
2235 SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */ 2235 SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */
2236 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4, 2236 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
2237 SUNXI_FUNCTION(0x0, "gpio_in"), 2237 SUNXI_FUNCTION(0x0, "gpio_in"),
2238 SUNXI_FUNCTION(0x1, "gpio_out"), 2238 SUNXI_FUNCTION(0x1, "gpio_out"),
2239 SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */ 2239 SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
2240 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5, 2240 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
2241 SUNXI_FUNCTION(0x0, "gpio_in"), 2241 SUNXI_FUNCTION(0x0, "gpio_in"),
2242 SUNXI_FUNCTION(0x1, "gpio_out"), 2242 SUNXI_FUNCTION(0x1, "gpio_out"),
2243 SUNXI_FUNCTION(0x2, "nand0")), /* RE */ 2243 SUNXI_FUNCTION(0x2, "nand0")), /* RE */
2244 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6, 2244 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
2245 SUNXI_FUNCTION(0x0, "gpio_in"), 2245 SUNXI_FUNCTION(0x0, "gpio_in"),
2246 SUNXI_FUNCTION(0x1, "gpio_out"), 2246 SUNXI_FUNCTION(0x1, "gpio_out"),
2247 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */ 2247 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
2248 SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */ 2248 SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */
2249 SUNXI_FUNCTION(0x4, "mmc3")), /* CMD */ 2249 SUNXI_FUNCTION(0x4, "mmc3")), /* CMD */
2250 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7, 2250 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
2251 SUNXI_FUNCTION(0x0, "gpio_in"), 2251 SUNXI_FUNCTION(0x0, "gpio_in"),
2252 SUNXI_FUNCTION(0x1, "gpio_out"), 2252 SUNXI_FUNCTION(0x1, "gpio_out"),
2253 SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */ 2253 SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
2254 SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */ 2254 SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */
2255 SUNXI_FUNCTION(0x4, "mmc3")), /* CLK */ 2255 SUNXI_FUNCTION(0x4, "mmc3")), /* CLK */
2256 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8, 2256 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
2257 SUNXI_FUNCTION(0x0, "gpio_in"), 2257 SUNXI_FUNCTION(0x0, "gpio_in"),
2258 SUNXI_FUNCTION(0x1, "gpio_out"), 2258 SUNXI_FUNCTION(0x1, "gpio_out"),
2259 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */ 2259 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
2260 SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */ 2260 SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
2261 SUNXI_FUNCTION(0x4, "mmc3")), /* D0 */ 2261 SUNXI_FUNCTION(0x4, "mmc3")), /* D0 */
2262 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9, 2262 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
2263 SUNXI_FUNCTION(0x0, "gpio_in"), 2263 SUNXI_FUNCTION(0x0, "gpio_in"),
2264 SUNXI_FUNCTION(0x1, "gpio_out"), 2264 SUNXI_FUNCTION(0x1, "gpio_out"),
2265 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */ 2265 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
2266 SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */ 2266 SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
2267 SUNXI_FUNCTION(0x4, "mmc3")), /* D1 */ 2267 SUNXI_FUNCTION(0x4, "mmc3")), /* D1 */
2268 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10, 2268 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
2269 SUNXI_FUNCTION(0x0, "gpio_in"), 2269 SUNXI_FUNCTION(0x0, "gpio_in"),
2270 SUNXI_FUNCTION(0x1, "gpio_out"), 2270 SUNXI_FUNCTION(0x1, "gpio_out"),
2271 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */ 2271 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
2272 SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */ 2272 SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */
2273 SUNXI_FUNCTION(0x4, "mmc3")), /* D2 */ 2273 SUNXI_FUNCTION(0x4, "mmc3")), /* D2 */
2274 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11, 2274 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
2275 SUNXI_FUNCTION(0x0, "gpio_in"), 2275 SUNXI_FUNCTION(0x0, "gpio_in"),
2276 SUNXI_FUNCTION(0x1, "gpio_out"), 2276 SUNXI_FUNCTION(0x1, "gpio_out"),
2277 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */ 2277 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
2278 SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */ 2278 SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */
2279 SUNXI_FUNCTION(0x4, "mmc3")), /* D3 */ 2279 SUNXI_FUNCTION(0x4, "mmc3")), /* D3 */
2280 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12, 2280 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
2281 SUNXI_FUNCTION(0x0, "gpio_in"), 2281 SUNXI_FUNCTION(0x0, "gpio_in"),
2282 SUNXI_FUNCTION(0x1, "gpio_out"), 2282 SUNXI_FUNCTION(0x1, "gpio_out"),
2283 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */ 2283 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
2284 SUNXI_FUNCTION(0x3, "mmc2"), /* D4 */ 2284 SUNXI_FUNCTION(0x3, "mmc2"), /* D4 */
2285 SUNXI_FUNCTION(0x4, "mmc3")), /* D4 */ 2285 SUNXI_FUNCTION(0x4, "mmc3")), /* D4 */
2286 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13, 2286 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
2287 SUNXI_FUNCTION(0x0, "gpio_in"), 2287 SUNXI_FUNCTION(0x0, "gpio_in"),
2288 SUNXI_FUNCTION(0x1, "gpio_out"), 2288 SUNXI_FUNCTION(0x1, "gpio_out"),
2289 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */ 2289 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
2290 SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */ 2290 SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */
2291 SUNXI_FUNCTION(0x4, "mmc3")), /* D5 */ 2291 SUNXI_FUNCTION(0x4, "mmc3")), /* D5 */
2292 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14, 2292 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
2293 SUNXI_FUNCTION(0x0, "gpio_in"), 2293 SUNXI_FUNCTION(0x0, "gpio_in"),
2294 SUNXI_FUNCTION(0x1, "gpio_out"), 2294 SUNXI_FUNCTION(0x1, "gpio_out"),
2295 SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */ 2295 SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
2296 SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */ 2296 SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */
2297 SUNXI_FUNCTION(0x4, "mmc3")), /* D6 */ 2297 SUNXI_FUNCTION(0x4, "mmc3")), /* D6 */
2298 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15, 2298 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
2299 SUNXI_FUNCTION(0x0, "gpio_in"), 2299 SUNXI_FUNCTION(0x0, "gpio_in"),
2300 SUNXI_FUNCTION(0x1, "gpio_out"), 2300 SUNXI_FUNCTION(0x1, "gpio_out"),
2301 SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */ 2301 SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
2302 SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */ 2302 SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */
2303 SUNXI_FUNCTION(0x4, "mmc3")), /* D7 */ 2303 SUNXI_FUNCTION(0x4, "mmc3")), /* D7 */
2304 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16, 2304 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
2305 SUNXI_FUNCTION(0x0, "gpio_in"), 2305 SUNXI_FUNCTION(0x0, "gpio_in"),
2306 SUNXI_FUNCTION(0x1, "gpio_out"), 2306 SUNXI_FUNCTION(0x1, "gpio_out"),
2307 SUNXI_FUNCTION(0x2, "nand0"), /* DQ8 */ 2307 SUNXI_FUNCTION(0x2, "nand0"), /* DQ8 */
2308 SUNXI_FUNCTION(0x3, "nand1")), /* DQ0 */ 2308 SUNXI_FUNCTION(0x3, "nand1")), /* DQ0 */
2309 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17, 2309 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
2310 SUNXI_FUNCTION(0x0, "gpio_in"), 2310 SUNXI_FUNCTION(0x0, "gpio_in"),
2311 SUNXI_FUNCTION(0x1, "gpio_out"), 2311 SUNXI_FUNCTION(0x1, "gpio_out"),
2312 SUNXI_FUNCTION(0x2, "nand0"), /* DQ9 */ 2312 SUNXI_FUNCTION(0x2, "nand0"), /* DQ9 */
2313 SUNXI_FUNCTION(0x3, "nand1")), /* DQ1 */ 2313 SUNXI_FUNCTION(0x3, "nand1")), /* DQ1 */
2314 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18, 2314 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
2315 SUNXI_FUNCTION(0x0, "gpio_in"), 2315 SUNXI_FUNCTION(0x0, "gpio_in"),
2316 SUNXI_FUNCTION(0x1, "gpio_out"), 2316 SUNXI_FUNCTION(0x1, "gpio_out"),
2317 SUNXI_FUNCTION(0x2, "nand0"), /* DQ10 */ 2317 SUNXI_FUNCTION(0x2, "nand0"), /* DQ10 */
2318 SUNXI_FUNCTION(0x3, "nand1")), /* DQ2 */ 2318 SUNXI_FUNCTION(0x3, "nand1")), /* DQ2 */
2319 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19, 2319 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
2320 SUNXI_FUNCTION(0x0, "gpio_in"), 2320 SUNXI_FUNCTION(0x0, "gpio_in"),
2321 SUNXI_FUNCTION(0x1, "gpio_out"), 2321 SUNXI_FUNCTION(0x1, "gpio_out"),
2322 SUNXI_FUNCTION(0x2, "nand0"), /* DQ11 */ 2322 SUNXI_FUNCTION(0x2, "nand0"), /* DQ11 */
2323 SUNXI_FUNCTION(0x3, "nand1")), /* DQ3 */ 2323 SUNXI_FUNCTION(0x3, "nand1")), /* DQ3 */
2324 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20, 2324 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20),
2325 SUNXI_FUNCTION(0x0, "gpio_in"), 2325 SUNXI_FUNCTION(0x0, "gpio_in"),
2326 SUNXI_FUNCTION(0x1, "gpio_out"), 2326 SUNXI_FUNCTION(0x1, "gpio_out"),
2327 SUNXI_FUNCTION(0x2, "nand0"), /* DQ12 */ 2327 SUNXI_FUNCTION(0x2, "nand0"), /* DQ12 */
2328 SUNXI_FUNCTION(0x3, "nand1")), /* DQ4 */ 2328 SUNXI_FUNCTION(0x3, "nand1")), /* DQ4 */
2329 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21, 2329 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21),
2330 SUNXI_FUNCTION(0x0, "gpio_in"), 2330 SUNXI_FUNCTION(0x0, "gpio_in"),
2331 SUNXI_FUNCTION(0x1, "gpio_out"), 2331 SUNXI_FUNCTION(0x1, "gpio_out"),
2332 SUNXI_FUNCTION(0x2, "nand0"), /* DQ13 */ 2332 SUNXI_FUNCTION(0x2, "nand0"), /* DQ13 */
2333 SUNXI_FUNCTION(0x3, "nand1")), /* DQ5 */ 2333 SUNXI_FUNCTION(0x3, "nand1")), /* DQ5 */
2334 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22, 2334 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22),
2335 SUNXI_FUNCTION(0x0, "gpio_in"), 2335 SUNXI_FUNCTION(0x0, "gpio_in"),
2336 SUNXI_FUNCTION(0x1, "gpio_out"), 2336 SUNXI_FUNCTION(0x1, "gpio_out"),
2337 SUNXI_FUNCTION(0x2, "nand0"), /* DQ14 */ 2337 SUNXI_FUNCTION(0x2, "nand0"), /* DQ14 */
2338 SUNXI_FUNCTION(0x3, "nand1")), /* DQ6 */ 2338 SUNXI_FUNCTION(0x3, "nand1")), /* DQ6 */
2339 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23, 2339 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23),
2340 SUNXI_FUNCTION(0x0, "gpio_in"), 2340 SUNXI_FUNCTION(0x0, "gpio_in"),
2341 SUNXI_FUNCTION(0x1, "gpio_out"), 2341 SUNXI_FUNCTION(0x1, "gpio_out"),
2342 SUNXI_FUNCTION(0x2, "nand0"), /* DQ15 */ 2342 SUNXI_FUNCTION(0x2, "nand0"), /* DQ15 */
2343 SUNXI_FUNCTION(0x3, "nand1")), /* DQ7 */ 2343 SUNXI_FUNCTION(0x3, "nand1")), /* DQ7 */
2344 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24, 2344 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24),
2345 SUNXI_FUNCTION(0x0, "gpio_in"), 2345 SUNXI_FUNCTION(0x0, "gpio_in"),
2346 SUNXI_FUNCTION(0x1, "gpio_out"), 2346 SUNXI_FUNCTION(0x1, "gpio_out"),
2347 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */ 2347 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
2348 SUNXI_FUNCTION(0x3, "mmc2"), /* RST */ 2348 SUNXI_FUNCTION(0x3, "mmc2"), /* RST */
2349 SUNXI_FUNCTION(0x4, "mmc3")), /* RST */ 2349 SUNXI_FUNCTION(0x4, "mmc3")), /* RST */
2350 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC25, 2350 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 25),
2351 SUNXI_FUNCTION(0x0, "gpio_in"), 2351 SUNXI_FUNCTION(0x0, "gpio_in"),
2352 SUNXI_FUNCTION(0x1, "gpio_out"), 2352 SUNXI_FUNCTION(0x1, "gpio_out"),
2353 SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */ 2353 SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */
2354 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC26, 2354 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 26),
2355 SUNXI_FUNCTION(0x0, "gpio_in"), 2355 SUNXI_FUNCTION(0x0, "gpio_in"),
2356 SUNXI_FUNCTION(0x1, "gpio_out"), 2356 SUNXI_FUNCTION(0x1, "gpio_out"),
2357 SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */ 2357 SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */
2358 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC27, 2358 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 27),
2359 SUNXI_FUNCTION(0x0, "gpio_in"), 2359 SUNXI_FUNCTION(0x0, "gpio_in"),
2360 SUNXI_FUNCTION(0x1, "gpio_out"), 2360 SUNXI_FUNCTION(0x1, "gpio_out"),
2361 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ 2361 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
2362 /* Hole */ 2362 /* Hole */
2363 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0, 2363 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
2364 SUNXI_FUNCTION(0x0, "gpio_in"), 2364 SUNXI_FUNCTION(0x0, "gpio_in"),
2365 SUNXI_FUNCTION(0x1, "gpio_out"), 2365 SUNXI_FUNCTION(0x1, "gpio_out"),
2366 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */ 2366 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
2367 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */ 2367 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
2368 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1, 2368 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
2369 SUNXI_FUNCTION(0x0, "gpio_in"), 2369 SUNXI_FUNCTION(0x0, "gpio_in"),
2370 SUNXI_FUNCTION(0x1, "gpio_out"), 2370 SUNXI_FUNCTION(0x1, "gpio_out"),
2371 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */ 2371 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
2372 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */ 2372 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
2373 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2, 2373 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
2374 SUNXI_FUNCTION(0x0, "gpio_in"), 2374 SUNXI_FUNCTION(0x0, "gpio_in"),
2375 SUNXI_FUNCTION(0x1, "gpio_out"), 2375 SUNXI_FUNCTION(0x1, "gpio_out"),
2376 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ 2376 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
2377 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */ 2377 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
2378 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3, 2378 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
2379 SUNXI_FUNCTION(0x0, "gpio_in"), 2379 SUNXI_FUNCTION(0x0, "gpio_in"),
2380 SUNXI_FUNCTION(0x1, "gpio_out"), 2380 SUNXI_FUNCTION(0x1, "gpio_out"),
2381 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ 2381 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
2382 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */ 2382 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
2383 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4, 2383 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
2384 SUNXI_FUNCTION(0x0, "gpio_in"), 2384 SUNXI_FUNCTION(0x0, "gpio_in"),
2385 SUNXI_FUNCTION(0x1, "gpio_out"), 2385 SUNXI_FUNCTION(0x1, "gpio_out"),
2386 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ 2386 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
2387 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */ 2387 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
2388 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5, 2388 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
2389 SUNXI_FUNCTION(0x0, "gpio_in"), 2389 SUNXI_FUNCTION(0x0, "gpio_in"),
2390 SUNXI_FUNCTION(0x1, "gpio_out"), 2390 SUNXI_FUNCTION(0x1, "gpio_out"),
2391 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ 2391 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
2392 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */ 2392 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
2393 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6, 2393 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
2394 SUNXI_FUNCTION(0x0, "gpio_in"), 2394 SUNXI_FUNCTION(0x0, "gpio_in"),
2395 SUNXI_FUNCTION(0x1, "gpio_out"), 2395 SUNXI_FUNCTION(0x1, "gpio_out"),
2396 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ 2396 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
2397 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */ 2397 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
2398 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7, 2398 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
2399 SUNXI_FUNCTION(0x0, "gpio_in"), 2399 SUNXI_FUNCTION(0x0, "gpio_in"),
2400 SUNXI_FUNCTION(0x1, "gpio_out"), 2400 SUNXI_FUNCTION(0x1, "gpio_out"),
2401 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ 2401 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
2402 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */ 2402 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
2403 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8, 2403 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
2404 SUNXI_FUNCTION(0x0, "gpio_in"), 2404 SUNXI_FUNCTION(0x0, "gpio_in"),
2405 SUNXI_FUNCTION(0x1, "gpio_out"), 2405 SUNXI_FUNCTION(0x1, "gpio_out"),
2406 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */ 2406 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
2407 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */ 2407 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
2408 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9, 2408 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
2409 SUNXI_FUNCTION(0x0, "gpio_in"), 2409 SUNXI_FUNCTION(0x0, "gpio_in"),
2410 SUNXI_FUNCTION(0x1, "gpio_out"), 2410 SUNXI_FUNCTION(0x1, "gpio_out"),
2411 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */ 2411 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
2412 SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */ 2412 SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
2413 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10, 2413 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
2414 SUNXI_FUNCTION(0x0, "gpio_in"), 2414 SUNXI_FUNCTION(0x0, "gpio_in"),
2415 SUNXI_FUNCTION(0x1, "gpio_out"), 2415 SUNXI_FUNCTION(0x1, "gpio_out"),
2416 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ 2416 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
2417 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */ 2417 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
2418 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11, 2418 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
2419 SUNXI_FUNCTION(0x0, "gpio_in"), 2419 SUNXI_FUNCTION(0x0, "gpio_in"),
2420 SUNXI_FUNCTION(0x1, "gpio_out"), 2420 SUNXI_FUNCTION(0x1, "gpio_out"),
2421 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ 2421 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
2422 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */ 2422 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
2423 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12, 2423 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
2424 SUNXI_FUNCTION(0x0, "gpio_in"), 2424 SUNXI_FUNCTION(0x0, "gpio_in"),
2425 SUNXI_FUNCTION(0x1, "gpio_out"), 2425 SUNXI_FUNCTION(0x1, "gpio_out"),
2426 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ 2426 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
2427 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */ 2427 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
2428 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13, 2428 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
2429 SUNXI_FUNCTION(0x0, "gpio_in"), 2429 SUNXI_FUNCTION(0x0, "gpio_in"),
2430 SUNXI_FUNCTION(0x1, "gpio_out"), 2430 SUNXI_FUNCTION(0x1, "gpio_out"),
2431 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ 2431 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
2432 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */ 2432 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
2433 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14, 2433 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
2434 SUNXI_FUNCTION(0x0, "gpio_in"), 2434 SUNXI_FUNCTION(0x0, "gpio_in"),
2435 SUNXI_FUNCTION(0x1, "gpio_out"), 2435 SUNXI_FUNCTION(0x1, "gpio_out"),
2436 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ 2436 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
2437 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */ 2437 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
2438 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15, 2438 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
2439 SUNXI_FUNCTION(0x0, "gpio_in"), 2439 SUNXI_FUNCTION(0x0, "gpio_in"),
2440 SUNXI_FUNCTION(0x1, "gpio_out"), 2440 SUNXI_FUNCTION(0x1, "gpio_out"),
2441 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ 2441 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
2442 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */ 2442 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
2443 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16, 2443 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
2444 SUNXI_FUNCTION(0x0, "gpio_in"), 2444 SUNXI_FUNCTION(0x0, "gpio_in"),
2445 SUNXI_FUNCTION(0x1, "gpio_out"), 2445 SUNXI_FUNCTION(0x1, "gpio_out"),
2446 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */ 2446 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
2447 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */ 2447 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
2448 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17, 2448 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
2449 SUNXI_FUNCTION(0x0, "gpio_in"), 2449 SUNXI_FUNCTION(0x0, "gpio_in"),
2450 SUNXI_FUNCTION(0x1, "gpio_out"), 2450 SUNXI_FUNCTION(0x1, "gpio_out"),
2451 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */ 2451 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
2452 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */ 2452 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
2453 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18, 2453 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
2454 SUNXI_FUNCTION(0x0, "gpio_in"), 2454 SUNXI_FUNCTION(0x0, "gpio_in"),
2455 SUNXI_FUNCTION(0x1, "gpio_out"), 2455 SUNXI_FUNCTION(0x1, "gpio_out"),
2456 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ 2456 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
2457 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */ 2457 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
2458 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19, 2458 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
2459 SUNXI_FUNCTION(0x0, "gpio_in"), 2459 SUNXI_FUNCTION(0x0, "gpio_in"),
2460 SUNXI_FUNCTION(0x1, "gpio_out"), 2460 SUNXI_FUNCTION(0x1, "gpio_out"),
2461 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ 2461 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
2462 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */ 2462 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
2463 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20, 2463 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
2464 SUNXI_FUNCTION(0x0, "gpio_in"), 2464 SUNXI_FUNCTION(0x0, "gpio_in"),
2465 SUNXI_FUNCTION(0x1, "gpio_out"), 2465 SUNXI_FUNCTION(0x1, "gpio_out"),
2466 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */ 2466 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
2467 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21, 2467 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
2468 SUNXI_FUNCTION(0x0, "gpio_in"), 2468 SUNXI_FUNCTION(0x0, "gpio_in"),
2469 SUNXI_FUNCTION(0x1, "gpio_out"), 2469 SUNXI_FUNCTION(0x1, "gpio_out"),
2470 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */ 2470 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
2471 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22, 2471 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
2472 SUNXI_FUNCTION(0x0, "gpio_in"), 2472 SUNXI_FUNCTION(0x0, "gpio_in"),
2473 SUNXI_FUNCTION(0x1, "gpio_out"), 2473 SUNXI_FUNCTION(0x1, "gpio_out"),
2474 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */ 2474 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
2475 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23, 2475 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
2476 SUNXI_FUNCTION(0x0, "gpio_in"), 2476 SUNXI_FUNCTION(0x0, "gpio_in"),
2477 SUNXI_FUNCTION(0x1, "gpio_out"), 2477 SUNXI_FUNCTION(0x1, "gpio_out"),
2478 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */ 2478 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
2479 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24, 2479 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
2480 SUNXI_FUNCTION(0x0, "gpio_in"), 2480 SUNXI_FUNCTION(0x0, "gpio_in"),
2481 SUNXI_FUNCTION(0x1, "gpio_out"), 2481 SUNXI_FUNCTION(0x1, "gpio_out"),
2482 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */ 2482 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
2483 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25, 2483 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
2484 SUNXI_FUNCTION(0x0, "gpio_in"), 2484 SUNXI_FUNCTION(0x0, "gpio_in"),
2485 SUNXI_FUNCTION(0x1, "gpio_out"), 2485 SUNXI_FUNCTION(0x1, "gpio_out"),
2486 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */ 2486 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
2487 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26, 2487 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
2488 SUNXI_FUNCTION(0x0, "gpio_in"), 2488 SUNXI_FUNCTION(0x0, "gpio_in"),
2489 SUNXI_FUNCTION(0x1, "gpio_out"), 2489 SUNXI_FUNCTION(0x1, "gpio_out"),
2490 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */ 2490 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
2491 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27, 2491 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
2492 SUNXI_FUNCTION(0x0, "gpio_in"), 2492 SUNXI_FUNCTION(0x0, "gpio_in"),
2493 SUNXI_FUNCTION(0x1, "gpio_out"), 2493 SUNXI_FUNCTION(0x1, "gpio_out"),
2494 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */ 2494 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
2495 /* Hole */ 2495 /* Hole */
2496 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0, 2496 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
2497 SUNXI_FUNCTION(0x0, "gpio_in"), 2497 SUNXI_FUNCTION(0x0, "gpio_in"),
2498 SUNXI_FUNCTION(0x1, "gpio_out"), 2498 SUNXI_FUNCTION(0x1, "gpio_out"),
2499 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */ 2499 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
2500 SUNXI_FUNCTION(0x3, "ts")), /* CLK */ 2500 SUNXI_FUNCTION(0x3, "ts")), /* CLK */
2501 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1, 2501 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
2502 SUNXI_FUNCTION(0x0, "gpio_in"), 2502 SUNXI_FUNCTION(0x0, "gpio_in"),
2503 SUNXI_FUNCTION(0x1, "gpio_out"), 2503 SUNXI_FUNCTION(0x1, "gpio_out"),
2504 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */ 2504 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
2505 SUNXI_FUNCTION(0x3, "ts")), /* ERR */ 2505 SUNXI_FUNCTION(0x3, "ts")), /* ERR */
2506 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2, 2506 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
2507 SUNXI_FUNCTION(0x0, "gpio_in"), 2507 SUNXI_FUNCTION(0x0, "gpio_in"),
2508 SUNXI_FUNCTION(0x1, "gpio_out"), 2508 SUNXI_FUNCTION(0x1, "gpio_out"),
2509 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ 2509 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
2510 SUNXI_FUNCTION(0x3, "ts")), /* SYNC */ 2510 SUNXI_FUNCTION(0x3, "ts")), /* SYNC */
2511 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3, 2511 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
2512 SUNXI_FUNCTION(0x0, "gpio_in"), 2512 SUNXI_FUNCTION(0x0, "gpio_in"),
2513 SUNXI_FUNCTION(0x1, "gpio_out"), 2513 SUNXI_FUNCTION(0x1, "gpio_out"),
2514 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ 2514 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
2515 SUNXI_FUNCTION(0x3, "ts")), /* DVLD */ 2515 SUNXI_FUNCTION(0x3, "ts")), /* DVLD */
2516 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4, 2516 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
2517 SUNXI_FUNCTION(0x0, "gpio_in"), 2517 SUNXI_FUNCTION(0x0, "gpio_in"),
2518 SUNXI_FUNCTION(0x1, "gpio_out"), 2518 SUNXI_FUNCTION(0x1, "gpio_out"),
2519 SUNXI_FUNCTION(0x2, "csi"), /* D0 */ 2519 SUNXI_FUNCTION(0x2, "csi"), /* D0 */
2520 SUNXI_FUNCTION(0x3, "uart5")), /* TX */ 2520 SUNXI_FUNCTION(0x3, "uart5")), /* TX */
2521 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5, 2521 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
2522 SUNXI_FUNCTION(0x0, "gpio_in"), 2522 SUNXI_FUNCTION(0x0, "gpio_in"),
2523 SUNXI_FUNCTION(0x1, "gpio_out"), 2523 SUNXI_FUNCTION(0x1, "gpio_out"),
2524 SUNXI_FUNCTION(0x2, "csi"), /* D1 */ 2524 SUNXI_FUNCTION(0x2, "csi"), /* D1 */
2525 SUNXI_FUNCTION(0x3, "uart5")), /* RX */ 2525 SUNXI_FUNCTION(0x3, "uart5")), /* RX */
2526 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6, 2526 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
2527 SUNXI_FUNCTION(0x0, "gpio_in"), 2527 SUNXI_FUNCTION(0x0, "gpio_in"),
2528 SUNXI_FUNCTION(0x1, "gpio_out"), 2528 SUNXI_FUNCTION(0x1, "gpio_out"),
2529 SUNXI_FUNCTION(0x2, "csi"), /* D2 */ 2529 SUNXI_FUNCTION(0x2, "csi"), /* D2 */
2530 SUNXI_FUNCTION(0x3, "uart5")), /* RTS */ 2530 SUNXI_FUNCTION(0x3, "uart5")), /* RTS */
2531 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7, 2531 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
2532 SUNXI_FUNCTION(0x0, "gpio_in"), 2532 SUNXI_FUNCTION(0x0, "gpio_in"),
2533 SUNXI_FUNCTION(0x1, "gpio_out"), 2533 SUNXI_FUNCTION(0x1, "gpio_out"),
2534 SUNXI_FUNCTION(0x2, "csi"), /* D3 */ 2534 SUNXI_FUNCTION(0x2, "csi"), /* D3 */
2535 SUNXI_FUNCTION(0x3, "uart5")), /* CTS */ 2535 SUNXI_FUNCTION(0x3, "uart5")), /* CTS */
2536 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8, 2536 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
2537 SUNXI_FUNCTION(0x0, "gpio_in"), 2537 SUNXI_FUNCTION(0x0, "gpio_in"),
2538 SUNXI_FUNCTION(0x1, "gpio_out"), 2538 SUNXI_FUNCTION(0x1, "gpio_out"),
2539 SUNXI_FUNCTION(0x2, "csi"), /* D4 */ 2539 SUNXI_FUNCTION(0x2, "csi"), /* D4 */
2540 SUNXI_FUNCTION(0x3, "ts")), /* D0 */ 2540 SUNXI_FUNCTION(0x3, "ts")), /* D0 */
2541 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9, 2541 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
2542 SUNXI_FUNCTION(0x0, "gpio_in"), 2542 SUNXI_FUNCTION(0x0, "gpio_in"),
2543 SUNXI_FUNCTION(0x1, "gpio_out"), 2543 SUNXI_FUNCTION(0x1, "gpio_out"),
2544 SUNXI_FUNCTION(0x2, "csi"), /* D5 */ 2544 SUNXI_FUNCTION(0x2, "csi"), /* D5 */
2545 SUNXI_FUNCTION(0x3, "ts")), /* D1 */ 2545 SUNXI_FUNCTION(0x3, "ts")), /* D1 */
2546 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10, 2546 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
2547 SUNXI_FUNCTION(0x0, "gpio_in"), 2547 SUNXI_FUNCTION(0x0, "gpio_in"),
2548 SUNXI_FUNCTION(0x1, "gpio_out"), 2548 SUNXI_FUNCTION(0x1, "gpio_out"),
2549 SUNXI_FUNCTION(0x2, "csi"), /* D6 */ 2549 SUNXI_FUNCTION(0x2, "csi"), /* D6 */
2550 SUNXI_FUNCTION(0x3, "ts")), /* D2 */ 2550 SUNXI_FUNCTION(0x3, "ts")), /* D2 */
2551 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11, 2551 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
2552 SUNXI_FUNCTION(0x0, "gpio_in"), 2552 SUNXI_FUNCTION(0x0, "gpio_in"),
2553 SUNXI_FUNCTION(0x1, "gpio_out"), 2553 SUNXI_FUNCTION(0x1, "gpio_out"),
2554 SUNXI_FUNCTION(0x2, "csi"), /* D7 */ 2554 SUNXI_FUNCTION(0x2, "csi"), /* D7 */
2555 SUNXI_FUNCTION(0x3, "ts")), /* D3 */ 2555 SUNXI_FUNCTION(0x3, "ts")), /* D3 */
2556 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE12, 2556 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
2557 SUNXI_FUNCTION(0x0, "gpio_in"), 2557 SUNXI_FUNCTION(0x0, "gpio_in"),
2558 SUNXI_FUNCTION(0x1, "gpio_out"), 2558 SUNXI_FUNCTION(0x1, "gpio_out"),
2559 SUNXI_FUNCTION(0x2, "csi"), /* D8 */ 2559 SUNXI_FUNCTION(0x2, "csi"), /* D8 */
2560 SUNXI_FUNCTION(0x3, "ts")), /* D4 */ 2560 SUNXI_FUNCTION(0x3, "ts")), /* D4 */
2561 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE13, 2561 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
2562 SUNXI_FUNCTION(0x0, "gpio_in"), 2562 SUNXI_FUNCTION(0x0, "gpio_in"),
2563 SUNXI_FUNCTION(0x1, "gpio_out"), 2563 SUNXI_FUNCTION(0x1, "gpio_out"),
2564 SUNXI_FUNCTION(0x2, "csi"), /* D9 */ 2564 SUNXI_FUNCTION(0x2, "csi"), /* D9 */
2565 SUNXI_FUNCTION(0x3, "ts")), /* D5 */ 2565 SUNXI_FUNCTION(0x3, "ts")), /* D5 */
2566 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE14, 2566 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
2567 SUNXI_FUNCTION(0x0, "gpio_in"), 2567 SUNXI_FUNCTION(0x0, "gpio_in"),
2568 SUNXI_FUNCTION(0x1, "gpio_out"), 2568 SUNXI_FUNCTION(0x1, "gpio_out"),
2569 SUNXI_FUNCTION(0x2, "csi"), /* D10 */ 2569 SUNXI_FUNCTION(0x2, "csi"), /* D10 */
2570 SUNXI_FUNCTION(0x3, "ts")), /* D6 */ 2570 SUNXI_FUNCTION(0x3, "ts")), /* D6 */
2571 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE15, 2571 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
2572 SUNXI_FUNCTION(0x0, "gpio_in"), 2572 SUNXI_FUNCTION(0x0, "gpio_in"),
2573 SUNXI_FUNCTION(0x1, "gpio_out"), 2573 SUNXI_FUNCTION(0x1, "gpio_out"),
2574 SUNXI_FUNCTION(0x2, "csi"), /* D11 */ 2574 SUNXI_FUNCTION(0x2, "csi"), /* D11 */
2575 SUNXI_FUNCTION(0x3, "ts")), /* D7 */ 2575 SUNXI_FUNCTION(0x3, "ts")), /* D7 */
2576 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE16, 2576 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
2577 SUNXI_FUNCTION(0x0, "gpio_in"), 2577 SUNXI_FUNCTION(0x0, "gpio_in"),
2578 SUNXI_FUNCTION(0x1, "gpio_out"), 2578 SUNXI_FUNCTION(0x1, "gpio_out"),
2579 SUNXI_FUNCTION(0x2, "csi")), /* MIPI CSI MCLK */ 2579 SUNXI_FUNCTION(0x2, "csi")), /* MIPI CSI MCLK */
2580 /* Hole */ 2580 /* Hole */
2581 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0, 2581 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
2582 SUNXI_FUNCTION(0x0, "gpio_in"), 2582 SUNXI_FUNCTION(0x0, "gpio_in"),
2583 SUNXI_FUNCTION(0x1, "gpio_out"), 2583 SUNXI_FUNCTION(0x1, "gpio_out"),
2584 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ 2584 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
2585 SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */ 2585 SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
2586 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1, 2586 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
2587 SUNXI_FUNCTION(0x0, "gpio_in"), 2587 SUNXI_FUNCTION(0x0, "gpio_in"),
2588 SUNXI_FUNCTION(0x1, "gpio_out"), 2588 SUNXI_FUNCTION(0x1, "gpio_out"),
2589 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ 2589 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
2590 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */ 2590 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
2591 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2, 2591 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
2592 SUNXI_FUNCTION(0x0, "gpio_in"), 2592 SUNXI_FUNCTION(0x0, "gpio_in"),
2593 SUNXI_FUNCTION(0x1, "gpio_out"), 2593 SUNXI_FUNCTION(0x1, "gpio_out"),
2594 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ 2594 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
2595 SUNXI_FUNCTION(0x4, "uart0")), /* TX */ 2595 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
2596 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3, 2596 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
2597 SUNXI_FUNCTION(0x0, "gpio_in"), 2597 SUNXI_FUNCTION(0x0, "gpio_in"),
2598 SUNXI_FUNCTION(0x1, "gpio_out"), 2598 SUNXI_FUNCTION(0x1, "gpio_out"),
2599 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ 2599 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
2600 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */ 2600 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
2601 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4, 2601 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
2602 SUNXI_FUNCTION(0x0, "gpio_in"), 2602 SUNXI_FUNCTION(0x0, "gpio_in"),
2603 SUNXI_FUNCTION(0x1, "gpio_out"), 2603 SUNXI_FUNCTION(0x1, "gpio_out"),
2604 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ 2604 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
2605 SUNXI_FUNCTION(0x4, "uart0")), /* RX */ 2605 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
2606 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5, 2606 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
2607 SUNXI_FUNCTION(0x0, "gpio_in"), 2607 SUNXI_FUNCTION(0x0, "gpio_in"),
2608 SUNXI_FUNCTION(0x1, "gpio_out"), 2608 SUNXI_FUNCTION(0x1, "gpio_out"),
2609 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ 2609 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
2610 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */ 2610 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
2611 /* Hole */ 2611 /* Hole */
2612 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0, 2612 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
2613 SUNXI_FUNCTION(0x0, "gpio_in"), 2613 SUNXI_FUNCTION(0x0, "gpio_in"),
2614 SUNXI_FUNCTION(0x1, "gpio_out"), 2614 SUNXI_FUNCTION(0x1, "gpio_out"),
2615 SUNXI_FUNCTION(0x2, "mmc1")), /* CLK */ 2615 SUNXI_FUNCTION(0x2, "mmc1")), /* CLK */
2616 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1, 2616 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
2617 SUNXI_FUNCTION(0x0, "gpio_in"), 2617 SUNXI_FUNCTION(0x0, "gpio_in"),
2618 SUNXI_FUNCTION(0x1, "gpio_out"), 2618 SUNXI_FUNCTION(0x1, "gpio_out"),
2619 SUNXI_FUNCTION(0x2, "mmc1")), /* CMD */ 2619 SUNXI_FUNCTION(0x2, "mmc1")), /* CMD */
2620 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2, 2620 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
2621 SUNXI_FUNCTION(0x0, "gpio_in"), 2621 SUNXI_FUNCTION(0x0, "gpio_in"),
2622 SUNXI_FUNCTION(0x1, "gpio_out"), 2622 SUNXI_FUNCTION(0x1, "gpio_out"),
2623 SUNXI_FUNCTION(0x2, "mmc1")), /* D0 */ 2623 SUNXI_FUNCTION(0x2, "mmc1")), /* D0 */
2624 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3, 2624 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
2625 SUNXI_FUNCTION(0x0, "gpio_in"), 2625 SUNXI_FUNCTION(0x0, "gpio_in"),
2626 SUNXI_FUNCTION(0x1, "gpio_out"), 2626 SUNXI_FUNCTION(0x1, "gpio_out"),
2627 SUNXI_FUNCTION(0x2, "mmc1")), /* D1 */ 2627 SUNXI_FUNCTION(0x2, "mmc1")), /* D1 */
2628 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4, 2628 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
2629 SUNXI_FUNCTION(0x0, "gpio_in"), 2629 SUNXI_FUNCTION(0x0, "gpio_in"),
2630 SUNXI_FUNCTION(0x1, "gpio_out"), 2630 SUNXI_FUNCTION(0x1, "gpio_out"),
2631 SUNXI_FUNCTION(0x2, "mmc1")), /* D2 */ 2631 SUNXI_FUNCTION(0x2, "mmc1")), /* D2 */
2632 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5, 2632 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
2633 SUNXI_FUNCTION(0x0, "gpio_in"), 2633 SUNXI_FUNCTION(0x0, "gpio_in"),
2634 SUNXI_FUNCTION(0x1, "gpio_out"), 2634 SUNXI_FUNCTION(0x1, "gpio_out"),
2635 SUNXI_FUNCTION(0x2, "mmc1")), /* D3 */ 2635 SUNXI_FUNCTION(0x2, "mmc1")), /* D3 */
2636 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6, 2636 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
2637 SUNXI_FUNCTION(0x0, "gpio_in"), 2637 SUNXI_FUNCTION(0x0, "gpio_in"),
2638 SUNXI_FUNCTION(0x1, "gpio_out"), 2638 SUNXI_FUNCTION(0x1, "gpio_out"),
2639 SUNXI_FUNCTION(0x2, "uart2")), /* TX */ 2639 SUNXI_FUNCTION(0x2, "uart2")), /* TX */
2640 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7, 2640 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
2641 SUNXI_FUNCTION(0x0, "gpio_in"), 2641 SUNXI_FUNCTION(0x0, "gpio_in"),
2642 SUNXI_FUNCTION(0x1, "gpio_out"), 2642 SUNXI_FUNCTION(0x1, "gpio_out"),
2643 SUNXI_FUNCTION(0x2, "uart2")), /* RX */ 2643 SUNXI_FUNCTION(0x2, "uart2")), /* RX */
2644 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8, 2644 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
2645 SUNXI_FUNCTION(0x0, "gpio_in"), 2645 SUNXI_FUNCTION(0x0, "gpio_in"),
2646 SUNXI_FUNCTION(0x1, "gpio_out"), 2646 SUNXI_FUNCTION(0x1, "gpio_out"),
2647 SUNXI_FUNCTION(0x2, "uart2")), /* RTS */ 2647 SUNXI_FUNCTION(0x2, "uart2")), /* RTS */
2648 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9, 2648 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
2649 SUNXI_FUNCTION(0x0, "gpio_in"), 2649 SUNXI_FUNCTION(0x0, "gpio_in"),
2650 SUNXI_FUNCTION(0x1, "gpio_out"), 2650 SUNXI_FUNCTION(0x1, "gpio_out"),
2651 SUNXI_FUNCTION(0x2, "uart2")), /* CTS */ 2651 SUNXI_FUNCTION(0x2, "uart2")), /* CTS */
2652 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10, 2652 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
2653 SUNXI_FUNCTION(0x0, "gpio_in"), 2653 SUNXI_FUNCTION(0x0, "gpio_in"),
2654 SUNXI_FUNCTION(0x1, "gpio_out"), 2654 SUNXI_FUNCTION(0x1, "gpio_out"),
2655 SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */ 2655 SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
2656 SUNXI_FUNCTION(0x3, "usb")), /* DP3 */ 2656 SUNXI_FUNCTION(0x3, "usb")), /* DP3 */
2657 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11, 2657 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
2658 SUNXI_FUNCTION(0x0, "gpio_in"), 2658 SUNXI_FUNCTION(0x0, "gpio_in"),
2659 SUNXI_FUNCTION(0x1, "gpio_out"), 2659 SUNXI_FUNCTION(0x1, "gpio_out"),
2660 SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */ 2660 SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
2661 SUNXI_FUNCTION(0x3, "usb")), /* DM3 */ 2661 SUNXI_FUNCTION(0x3, "usb")), /* DM3 */
2662 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12, 2662 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
2663 SUNXI_FUNCTION(0x0, "gpio_in"), 2663 SUNXI_FUNCTION(0x0, "gpio_in"),
2664 SUNXI_FUNCTION(0x1, "gpio_out"), 2664 SUNXI_FUNCTION(0x1, "gpio_out"),
2665 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ 2665 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
2666 SUNXI_FUNCTION(0x3, "i2s1")), /* MCLK */ 2666 SUNXI_FUNCTION(0x3, "i2s1")), /* MCLK */
2667 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG13, 2667 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
2668 SUNXI_FUNCTION(0x0, "gpio_in"), 2668 SUNXI_FUNCTION(0x0, "gpio_in"),
2669 SUNXI_FUNCTION(0x1, "gpio_out"), 2669 SUNXI_FUNCTION(0x1, "gpio_out"),
2670 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ 2670 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
2671 SUNXI_FUNCTION(0x3, "i2s1")), /* BCLK */ 2671 SUNXI_FUNCTION(0x3, "i2s1")), /* BCLK */
2672 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG14, 2672 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
2673 SUNXI_FUNCTION(0x0, "gpio_in"), 2673 SUNXI_FUNCTION(0x0, "gpio_in"),
2674 SUNXI_FUNCTION(0x1, "gpio_out"), 2674 SUNXI_FUNCTION(0x1, "gpio_out"),
2675 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ 2675 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
2676 SUNXI_FUNCTION(0x3, "i2s1")), /* LRCK */ 2676 SUNXI_FUNCTION(0x3, "i2s1")), /* LRCK */
2677 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG15, 2677 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
2678 SUNXI_FUNCTION(0x0, "gpio_in"), 2678 SUNXI_FUNCTION(0x0, "gpio_in"),
2679 SUNXI_FUNCTION(0x1, "gpio_out"), 2679 SUNXI_FUNCTION(0x1, "gpio_out"),
2680 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ 2680 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
2681 SUNXI_FUNCTION(0x3, "i2s1")), /* DIN */ 2681 SUNXI_FUNCTION(0x3, "i2s1")), /* DIN */
2682 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG16, 2682 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16),
2683 SUNXI_FUNCTION(0x0, "gpio_in"), 2683 SUNXI_FUNCTION(0x0, "gpio_in"),
2684 SUNXI_FUNCTION(0x1, "gpio_out"), 2684 SUNXI_FUNCTION(0x1, "gpio_out"),
2685 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ 2685 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
2686 SUNXI_FUNCTION(0x3, "i2s1")), /* DOUT */ 2686 SUNXI_FUNCTION(0x3, "i2s1")), /* DOUT */
2687 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG17, 2687 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17),
2688 SUNXI_FUNCTION(0x0, "gpio_in"), 2688 SUNXI_FUNCTION(0x0, "gpio_in"),
2689 SUNXI_FUNCTION(0x1, "gpio_out"), 2689 SUNXI_FUNCTION(0x1, "gpio_out"),
2690 SUNXI_FUNCTION(0x2, "uart4")), /* TX */ 2690 SUNXI_FUNCTION(0x2, "uart4")), /* TX */
2691 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG18, 2691 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18),
2692 SUNXI_FUNCTION(0x0, "gpio_in"), 2692 SUNXI_FUNCTION(0x0, "gpio_in"),
2693 SUNXI_FUNCTION(0x1, "gpio_out"), 2693 SUNXI_FUNCTION(0x1, "gpio_out"),
2694 SUNXI_FUNCTION(0x2, "uart4")), /* RX */ 2694 SUNXI_FUNCTION(0x2, "uart4")), /* RX */
2695 /* Hole */ 2695 /* Hole */
2696 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0, 2696 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
2697 SUNXI_FUNCTION(0x0, "gpio_in"), 2697 SUNXI_FUNCTION(0x0, "gpio_in"),
2698 SUNXI_FUNCTION(0x1, "gpio_out"), 2698 SUNXI_FUNCTION(0x1, "gpio_out"),
2699 SUNXI_FUNCTION(0x2, "nand1")), /* WE */ 2699 SUNXI_FUNCTION(0x2, "nand1")), /* WE */
2700 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1, 2700 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
2701 SUNXI_FUNCTION(0x0, "gpio_in"), 2701 SUNXI_FUNCTION(0x0, "gpio_in"),
2702 SUNXI_FUNCTION(0x1, "gpio_out"), 2702 SUNXI_FUNCTION(0x1, "gpio_out"),
2703 SUNXI_FUNCTION(0x2, "nand1")), /* ALE */ 2703 SUNXI_FUNCTION(0x2, "nand1")), /* ALE */
2704 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2, 2704 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
2705 SUNXI_FUNCTION(0x0, "gpio_in"), 2705 SUNXI_FUNCTION(0x0, "gpio_in"),
2706 SUNXI_FUNCTION(0x1, "gpio_out"), 2706 SUNXI_FUNCTION(0x1, "gpio_out"),
2707 SUNXI_FUNCTION(0x2, "nand1")), /* CLE */ 2707 SUNXI_FUNCTION(0x2, "nand1")), /* CLE */
2708 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3, 2708 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
2709 SUNXI_FUNCTION(0x0, "gpio_in"), 2709 SUNXI_FUNCTION(0x0, "gpio_in"),
2710 SUNXI_FUNCTION(0x1, "gpio_out"), 2710 SUNXI_FUNCTION(0x1, "gpio_out"),
2711 SUNXI_FUNCTION(0x2, "nand1")), /* CE1 */ 2711 SUNXI_FUNCTION(0x2, "nand1")), /* CE1 */
2712 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4, 2712 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
2713 SUNXI_FUNCTION(0x0, "gpio_in"), 2713 SUNXI_FUNCTION(0x0, "gpio_in"),
2714 SUNXI_FUNCTION(0x1, "gpio_out"), 2714 SUNXI_FUNCTION(0x1, "gpio_out"),
2715 SUNXI_FUNCTION(0x2, "nand1")), /* CE0 */ 2715 SUNXI_FUNCTION(0x2, "nand1")), /* CE0 */
2716 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5, 2716 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
2717 SUNXI_FUNCTION(0x0, "gpio_in"), 2717 SUNXI_FUNCTION(0x0, "gpio_in"),
2718 SUNXI_FUNCTION(0x1, "gpio_out"), 2718 SUNXI_FUNCTION(0x1, "gpio_out"),
2719 SUNXI_FUNCTION(0x2, "nand1")), /* RE */ 2719 SUNXI_FUNCTION(0x2, "nand1")), /* RE */
2720 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6, 2720 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
2721 SUNXI_FUNCTION(0x0, "gpio_in"), 2721 SUNXI_FUNCTION(0x0, "gpio_in"),
2722 SUNXI_FUNCTION(0x1, "gpio_out"), 2722 SUNXI_FUNCTION(0x1, "gpio_out"),
2723 SUNXI_FUNCTION(0x2, "nand1")), /* RB0 */ 2723 SUNXI_FUNCTION(0x2, "nand1")), /* RB0 */
2724 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7, 2724 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
2725 SUNXI_FUNCTION(0x0, "gpio_in"), 2725 SUNXI_FUNCTION(0x0, "gpio_in"),
2726 SUNXI_FUNCTION(0x1, "gpio_out"), 2726 SUNXI_FUNCTION(0x1, "gpio_out"),
2727 SUNXI_FUNCTION(0x2, "nand1")), /* RB1 */ 2727 SUNXI_FUNCTION(0x2, "nand1")), /* RB1 */
2728 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8, 2728 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
2729 SUNXI_FUNCTION(0x0, "gpio_in"), 2729 SUNXI_FUNCTION(0x0, "gpio_in"),
2730 SUNXI_FUNCTION(0x1, "gpio_out"), 2730 SUNXI_FUNCTION(0x1, "gpio_out"),
2731 SUNXI_FUNCTION(0x2, "nand1")), /* DQS */ 2731 SUNXI_FUNCTION(0x2, "nand1")), /* DQS */
2732 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9, 2732 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
2733 SUNXI_FUNCTION(0x0, "gpio_in"), 2733 SUNXI_FUNCTION(0x0, "gpio_in"),
2734 SUNXI_FUNCTION(0x1, "gpio_out"), 2734 SUNXI_FUNCTION(0x1, "gpio_out"),
2735 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */ 2735 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
2736 SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */ 2736 SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
2737 SUNXI_FUNCTION(0x4, "pwm1")), /* Positive */ 2737 SUNXI_FUNCTION(0x4, "pwm1")), /* Positive */
2738 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10, 2738 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
2739 SUNXI_FUNCTION(0x0, "gpio_in"), 2739 SUNXI_FUNCTION(0x0, "gpio_in"),
2740 SUNXI_FUNCTION(0x1, "gpio_out"), 2740 SUNXI_FUNCTION(0x1, "gpio_out"),
2741 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */ 2741 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
2742 SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */ 2742 SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
2743 SUNXI_FUNCTION(0x4, "pwm1")), /* Negative */ 2743 SUNXI_FUNCTION(0x4, "pwm1")), /* Negative */
2744 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11, 2744 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
2745 SUNXI_FUNCTION(0x0, "gpio_in"), 2745 SUNXI_FUNCTION(0x0, "gpio_in"),
2746 SUNXI_FUNCTION(0x1, "gpio_out"), 2746 SUNXI_FUNCTION(0x1, "gpio_out"),
2747 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */ 2747 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
2748 SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */ 2748 SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
2749 SUNXI_FUNCTION(0x4, "pwm2")), /* Positive */ 2749 SUNXI_FUNCTION(0x4, "pwm2")), /* Positive */
2750 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12, 2750 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
2751 SUNXI_FUNCTION(0x0, "gpio_in"), 2751 SUNXI_FUNCTION(0x0, "gpio_in"),
2752 SUNXI_FUNCTION(0x1, "gpio_out"), 2752 SUNXI_FUNCTION(0x1, "gpio_out"),
2753 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */ 2753 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
2754 SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */ 2754 SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
2755 SUNXI_FUNCTION(0x4, "pwm2")), /* Negative */ 2755 SUNXI_FUNCTION(0x4, "pwm2")), /* Negative */
2756 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13, 2756 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
2757 SUNXI_FUNCTION(0x0, "gpio_in"), 2757 SUNXI_FUNCTION(0x0, "gpio_in"),
2758 SUNXI_FUNCTION(0x1, "gpio_out"), 2758 SUNXI_FUNCTION(0x1, "gpio_out"),
2759 SUNXI_FUNCTION(0x2, "pwm0")), 2759 SUNXI_FUNCTION(0x2, "pwm0")),
2760 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14, 2760 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
2761 SUNXI_FUNCTION(0x0, "gpio_in"), 2761 SUNXI_FUNCTION(0x0, "gpio_in"),
2762 SUNXI_FUNCTION(0x1, "gpio_out"), 2762 SUNXI_FUNCTION(0x1, "gpio_out"),
2763 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ 2763 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
2764 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15, 2764 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
2765 SUNXI_FUNCTION(0x0, "gpio_in"), 2765 SUNXI_FUNCTION(0x0, "gpio_in"),
2766 SUNXI_FUNCTION(0x1, "gpio_out"), 2766 SUNXI_FUNCTION(0x1, "gpio_out"),
2767 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ 2767 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
2768 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16, 2768 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
2769 SUNXI_FUNCTION(0x0, "gpio_in"), 2769 SUNXI_FUNCTION(0x0, "gpio_in"),
2770 SUNXI_FUNCTION(0x1, "gpio_out"), 2770 SUNXI_FUNCTION(0x1, "gpio_out"),
2771 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ 2771 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
2772 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17, 2772 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
2773 SUNXI_FUNCTION(0x0, "gpio_in"), 2773 SUNXI_FUNCTION(0x0, "gpio_in"),
2774 SUNXI_FUNCTION(0x1, "gpio_out"), 2774 SUNXI_FUNCTION(0x1, "gpio_out"),
2775 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ 2775 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
2776 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18, 2776 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
2777 SUNXI_FUNCTION(0x0, "gpio_in"), 2777 SUNXI_FUNCTION(0x0, "gpio_in"),
2778 SUNXI_FUNCTION(0x1, "gpio_out"), 2778 SUNXI_FUNCTION(0x1, "gpio_out"),
2779 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ 2779 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
2780 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19, 2780 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
2781 SUNXI_FUNCTION(0x0, "gpio_in"), 2781 SUNXI_FUNCTION(0x0, "gpio_in"),
2782 SUNXI_FUNCTION(0x1, "gpio_out"), 2782 SUNXI_FUNCTION(0x1, "gpio_out"),
2783 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ 2783 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
2784 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20, 2784 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
2785 SUNXI_FUNCTION(0x0, "gpio_in"), 2785 SUNXI_FUNCTION(0x0, "gpio_in"),
2786 SUNXI_FUNCTION(0x1, "gpio_out"), 2786 SUNXI_FUNCTION(0x1, "gpio_out"),
2787 SUNXI_FUNCTION(0x2, "uart0")), /* TX */ 2787 SUNXI_FUNCTION(0x2, "uart0")), /* TX */
2788 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21, 2788 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
2789 SUNXI_FUNCTION(0x0, "gpio_in"), 2789 SUNXI_FUNCTION(0x0, "gpio_in"),
2790 SUNXI_FUNCTION(0x1, "gpio_out"), 2790 SUNXI_FUNCTION(0x1, "gpio_out"),
2791 SUNXI_FUNCTION(0x2, "uart0")), /* RX */ 2791 SUNXI_FUNCTION(0x2, "uart0")), /* RX */
2792 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22, 2792 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22),
2793 SUNXI_FUNCTION(0x0, "gpio_in"), 2793 SUNXI_FUNCTION(0x0, "gpio_in"),
2794 SUNXI_FUNCTION(0x1, "gpio_out")), 2794 SUNXI_FUNCTION(0x1, "gpio_out")),
2795 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23, 2795 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23),
2796 SUNXI_FUNCTION(0x0, "gpio_in"), 2796 SUNXI_FUNCTION(0x0, "gpio_in"),
2797 SUNXI_FUNCTION(0x1, "gpio_out")), 2797 SUNXI_FUNCTION(0x1, "gpio_out")),
2798 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24, 2798 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24),
2799 SUNXI_FUNCTION(0x0, "gpio_in"), 2799 SUNXI_FUNCTION(0x0, "gpio_in"),
2800 SUNXI_FUNCTION(0x1, "gpio_out")), 2800 SUNXI_FUNCTION(0x1, "gpio_out")),
2801 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25, 2801 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25),
2802 SUNXI_FUNCTION(0x0, "gpio_in"), 2802 SUNXI_FUNCTION(0x0, "gpio_in"),
2803 SUNXI_FUNCTION(0x1, "gpio_out")), 2803 SUNXI_FUNCTION(0x1, "gpio_out")),
2804 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26, 2804 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26),
2805 SUNXI_FUNCTION(0x0, "gpio_in"), 2805 SUNXI_FUNCTION(0x0, "gpio_in"),
2806 SUNXI_FUNCTION(0x1, "gpio_out")), 2806 SUNXI_FUNCTION(0x1, "gpio_out")),
2807 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27, 2807 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27),
2808 SUNXI_FUNCTION(0x0, "gpio_in"), 2808 SUNXI_FUNCTION(0x0, "gpio_in"),
2809 SUNXI_FUNCTION(0x1, "gpio_out")), 2809 SUNXI_FUNCTION(0x1, "gpio_out")),
2810 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH28, 2810 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 28),
2811 SUNXI_FUNCTION(0x0, "gpio_in"), 2811 SUNXI_FUNCTION(0x0, "gpio_in"),
2812 SUNXI_FUNCTION(0x1, "gpio_out")), 2812 SUNXI_FUNCTION(0x1, "gpio_out")),
2813 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH29, 2813 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 29),
2814 SUNXI_FUNCTION(0x0, "gpio_in"), 2814 SUNXI_FUNCTION(0x0, "gpio_in"),
2815 SUNXI_FUNCTION(0x1, "gpio_out"), 2815 SUNXI_FUNCTION(0x1, "gpio_out"),
2816 SUNXI_FUNCTION(0x2, "nand1")), /* CE2 */ 2816 SUNXI_FUNCTION(0x2, "nand1")), /* CE2 */
2817 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH30, 2817 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 30),
2818 SUNXI_FUNCTION(0x0, "gpio_in"), 2818 SUNXI_FUNCTION(0x0, "gpio_in"),
2819 SUNXI_FUNCTION(0x1, "gpio_out"), 2819 SUNXI_FUNCTION(0x1, "gpio_out"),
2820 SUNXI_FUNCTION(0x2, "nand1")), /* CE3 */ 2820 SUNXI_FUNCTION(0x2, "nand1")), /* CE3 */
2821}; 2821};
2822 2822
2823static const struct sunxi_desc_pin sun6i_a31_r_pins[] = { 2823static const struct sunxi_desc_pin sun6i_a31_r_pins[] = {
2824 SUNXI_PIN(SUNXI_PINCTRL_PIN_PL0, 2824 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
2825 SUNXI_FUNCTION(0x0, "gpio_in"), 2825 SUNXI_FUNCTION(0x0, "gpio_in"),
2826 SUNXI_FUNCTION(0x1, "gpio_out"), 2826 SUNXI_FUNCTION(0x1, "gpio_out"),
2827 SUNXI_FUNCTION(0x2, "s_twi"), /* SCK */ 2827 SUNXI_FUNCTION(0x2, "s_twi"), /* SCK */
2828 SUNXI_FUNCTION(0x3, "s_p2wi")), /* SCK */ 2828 SUNXI_FUNCTION(0x3, "s_p2wi")), /* SCK */
2829 SUNXI_PIN(SUNXI_PINCTRL_PIN_PL1, 2829 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
2830 SUNXI_FUNCTION(0x0, "gpio_in"), 2830 SUNXI_FUNCTION(0x0, "gpio_in"),
2831 SUNXI_FUNCTION(0x1, "gpio_out"), 2831 SUNXI_FUNCTION(0x1, "gpio_out"),
2832 SUNXI_FUNCTION(0x2, "s_twi"), /* SDA */ 2832 SUNXI_FUNCTION(0x2, "s_twi"), /* SDA */
2833 SUNXI_FUNCTION(0x3, "s_p2wi")), /* SDA */ 2833 SUNXI_FUNCTION(0x3, "s_p2wi")), /* SDA */
2834 SUNXI_PIN(SUNXI_PINCTRL_PIN_PL2, 2834 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
2835 SUNXI_FUNCTION(0x0, "gpio_in"), 2835 SUNXI_FUNCTION(0x0, "gpio_in"),
2836 SUNXI_FUNCTION(0x1, "gpio_out"), 2836 SUNXI_FUNCTION(0x1, "gpio_out"),
2837 SUNXI_FUNCTION(0x2, "s_uart")), /* TX */ 2837 SUNXI_FUNCTION(0x2, "s_uart")), /* TX */
2838 SUNXI_PIN(SUNXI_PINCTRL_PIN_PL3, 2838 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
2839 SUNXI_FUNCTION(0x0, "gpio_in"), 2839 SUNXI_FUNCTION(0x0, "gpio_in"),
2840 SUNXI_FUNCTION(0x1, "gpio_out"), 2840 SUNXI_FUNCTION(0x1, "gpio_out"),
2841 SUNXI_FUNCTION(0x2, "s_uart")), /* RX */ 2841 SUNXI_FUNCTION(0x2, "s_uart")), /* RX */
2842 SUNXI_PIN(SUNXI_PINCTRL_PIN_PL4, 2842 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
2843 SUNXI_FUNCTION(0x0, "gpio_in"), 2843 SUNXI_FUNCTION(0x0, "gpio_in"),
2844 SUNXI_FUNCTION(0x1, "gpio_out"), 2844 SUNXI_FUNCTION(0x1, "gpio_out"),
2845 SUNXI_FUNCTION(0x2, "s_ir")), /* RX */ 2845 SUNXI_FUNCTION(0x2, "s_ir")), /* RX */
2846 SUNXI_PIN(SUNXI_PINCTRL_PIN_PL5, 2846 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
2847 SUNXI_FUNCTION(0x0, "gpio_in"), 2847 SUNXI_FUNCTION(0x0, "gpio_in"),
2848 SUNXI_FUNCTION(0x1, "gpio_out"), 2848 SUNXI_FUNCTION(0x1, "gpio_out"),
2849 SUNXI_FUNCTION(0x3, "s_jtag")), /* MS */ 2849 SUNXI_FUNCTION(0x3, "s_jtag")), /* MS */
2850 SUNXI_PIN(SUNXI_PINCTRL_PIN_PL6, 2850 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
2851 SUNXI_FUNCTION(0x0, "gpio_in"), 2851 SUNXI_FUNCTION(0x0, "gpio_in"),
2852 SUNXI_FUNCTION(0x1, "gpio_out"), 2852 SUNXI_FUNCTION(0x1, "gpio_out"),
2853 SUNXI_FUNCTION(0x3, "s_jtag")), /* CK */ 2853 SUNXI_FUNCTION(0x3, "s_jtag")), /* CK */
2854 SUNXI_PIN(SUNXI_PINCTRL_PIN_PL7, 2854 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
2855 SUNXI_FUNCTION(0x0, "gpio_in"), 2855 SUNXI_FUNCTION(0x0, "gpio_in"),
2856 SUNXI_FUNCTION(0x1, "gpio_out"), 2856 SUNXI_FUNCTION(0x1, "gpio_out"),
2857 SUNXI_FUNCTION(0x3, "s_jtag")), /* DO */ 2857 SUNXI_FUNCTION(0x3, "s_jtag")), /* DO */
2858 SUNXI_PIN(SUNXI_PINCTRL_PIN_PL8, 2858 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
2859 SUNXI_FUNCTION(0x0, "gpio_in"), 2859 SUNXI_FUNCTION(0x0, "gpio_in"),
2860 SUNXI_FUNCTION(0x1, "gpio_out"), 2860 SUNXI_FUNCTION(0x1, "gpio_out"),
2861 SUNXI_FUNCTION(0x3, "s_jtag")), /* DI */ 2861 SUNXI_FUNCTION(0x3, "s_jtag")), /* DI */
2862 /* Hole */ 2862 /* Hole */
2863 SUNXI_PIN(SUNXI_PINCTRL_PIN_PM0, 2863 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0),
2864 SUNXI_FUNCTION(0x0, "gpio_in"), 2864 SUNXI_FUNCTION(0x0, "gpio_in"),
2865 SUNXI_FUNCTION(0x1, "gpio_out")), 2865 SUNXI_FUNCTION(0x1, "gpio_out")),
2866 SUNXI_PIN(SUNXI_PINCTRL_PIN_PM1, 2866 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1),
2867 SUNXI_FUNCTION(0x0, "gpio_in"), 2867 SUNXI_FUNCTION(0x0, "gpio_in"),
2868 SUNXI_FUNCTION(0x1, "gpio_out")), 2868 SUNXI_FUNCTION(0x1, "gpio_out")),
2869 SUNXI_PIN(SUNXI_PINCTRL_PIN_PM2, 2869 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2),
2870 SUNXI_FUNCTION(0x0, "gpio_in"), 2870 SUNXI_FUNCTION(0x0, "gpio_in"),
2871 SUNXI_FUNCTION(0x1, "gpio_out"), 2871 SUNXI_FUNCTION(0x1, "gpio_out"),
2872 SUNXI_FUNCTION(0x3, "1wire")), 2872 SUNXI_FUNCTION(0x3, "1wire")),
2873 SUNXI_PIN(SUNXI_PINCTRL_PIN_PM3, 2873 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3),
2874 SUNXI_FUNCTION(0x0, "gpio_in"), 2874 SUNXI_FUNCTION(0x0, "gpio_in"),
2875 SUNXI_FUNCTION(0x1, "gpio_out")), 2875 SUNXI_FUNCTION(0x1, "gpio_out")),
2876 SUNXI_PIN(SUNXI_PINCTRL_PIN_PM4, 2876 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4),
2877 SUNXI_FUNCTION(0x0, "gpio_in"), 2877 SUNXI_FUNCTION(0x0, "gpio_in"),
2878 SUNXI_FUNCTION(0x1, "gpio_out")), 2878 SUNXI_FUNCTION(0x1, "gpio_out")),
2879 SUNXI_PIN(SUNXI_PINCTRL_PIN_PM5, 2879 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 5),
2880 SUNXI_FUNCTION(0x0, "gpio_in"), 2880 SUNXI_FUNCTION(0x0, "gpio_in"),
2881 SUNXI_FUNCTION(0x1, "gpio_out")), 2881 SUNXI_FUNCTION(0x1, "gpio_out")),
2882 SUNXI_PIN(SUNXI_PINCTRL_PIN_PM6, 2882 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 6),
2883 SUNXI_FUNCTION(0x0, "gpio_in"), 2883 SUNXI_FUNCTION(0x0, "gpio_in"),
2884 SUNXI_FUNCTION(0x1, "gpio_out")), 2884 SUNXI_FUNCTION(0x1, "gpio_out")),
2885 SUNXI_PIN(SUNXI_PINCTRL_PIN_PM7, 2885 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 7),
2886 SUNXI_FUNCTION(0x0, "gpio_in"), 2886 SUNXI_FUNCTION(0x0, "gpio_in"),
2887 SUNXI_FUNCTION(0x1, "gpio_out"), 2887 SUNXI_FUNCTION(0x1, "gpio_out"),
2888 SUNXI_FUNCTION(0x3, "rtc")), /* CLKO */ 2888 SUNXI_FUNCTION(0x3, "rtc")), /* CLKO */
2889}; 2889};
2890 2890
2891static const struct sunxi_desc_pin sun7i_a20_pins[] = { 2891static const struct sunxi_desc_pin sun7i_a20_pins[] = {
2892 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0, 2892 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
2893 SUNXI_FUNCTION(0x0, "gpio_in"), 2893 SUNXI_FUNCTION(0x0, "gpio_in"),
2894 SUNXI_FUNCTION(0x1, "gpio_out"), 2894 SUNXI_FUNCTION(0x1, "gpio_out"),
2895 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */ 2895 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
2896 SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */ 2896 SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
2897 SUNXI_FUNCTION(0x4, "uart2"), /* RTS */ 2897 SUNXI_FUNCTION(0x4, "uart2"), /* RTS */
2898 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD3 */ 2898 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD3 */
2899 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1, 2899 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
2900 SUNXI_FUNCTION(0x0, "gpio_in"), 2900 SUNXI_FUNCTION(0x0, "gpio_in"),
2901 SUNXI_FUNCTION(0x1, "gpio_out"), 2901 SUNXI_FUNCTION(0x1, "gpio_out"),
2902 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */ 2902 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
2903 SUNXI_FUNCTION(0x3, "spi1"), /* CLK */ 2903 SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
2904 SUNXI_FUNCTION(0x4, "uart2"), /* CTS */ 2904 SUNXI_FUNCTION(0x4, "uart2"), /* CTS */
2905 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD2 */ 2905 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD2 */
2906 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2, 2906 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
2907 SUNXI_FUNCTION(0x0, "gpio_in"), 2907 SUNXI_FUNCTION(0x0, "gpio_in"),
2908 SUNXI_FUNCTION(0x1, "gpio_out"), 2908 SUNXI_FUNCTION(0x1, "gpio_out"),
2909 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */ 2909 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
2910 SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */ 2910 SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
2911 SUNXI_FUNCTION(0x4, "uart2"), /* TX */ 2911 SUNXI_FUNCTION(0x4, "uart2"), /* TX */
2912 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD1 */ 2912 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD1 */
2913 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3, 2913 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
2914 SUNXI_FUNCTION(0x0, "gpio_in"), 2914 SUNXI_FUNCTION(0x0, "gpio_in"),
2915 SUNXI_FUNCTION(0x1, "gpio_out"), 2915 SUNXI_FUNCTION(0x1, "gpio_out"),
2916 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */ 2916 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
2917 SUNXI_FUNCTION(0x3, "spi1"), /* MISO */ 2917 SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
2918 SUNXI_FUNCTION(0x4, "uart2"), /* RX */ 2918 SUNXI_FUNCTION(0x4, "uart2"), /* RX */
2919 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD0 */ 2919 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD0 */
2920 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4, 2920 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
2921 SUNXI_FUNCTION(0x0, "gpio_in"), 2921 SUNXI_FUNCTION(0x0, "gpio_in"),
2922 SUNXI_FUNCTION(0x1, "gpio_out"), 2922 SUNXI_FUNCTION(0x1, "gpio_out"),
2923 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */ 2923 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
2924 SUNXI_FUNCTION(0x3, "spi1"), /* CS1 */ 2924 SUNXI_FUNCTION(0x3, "spi1"), /* CS1 */
2925 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD3 */ 2925 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD3 */
2926 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5, 2926 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
2927 SUNXI_FUNCTION(0x0, "gpio_in"), 2927 SUNXI_FUNCTION(0x0, "gpio_in"),
2928 SUNXI_FUNCTION(0x1, "gpio_out"), 2928 SUNXI_FUNCTION(0x1, "gpio_out"),
2929 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */ 2929 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
2930 SUNXI_FUNCTION(0x3, "spi3"), /* CS0 */ 2930 SUNXI_FUNCTION(0x3, "spi3"), /* CS0 */
2931 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD2 */ 2931 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD2 */
2932 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6, 2932 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
2933 SUNXI_FUNCTION(0x0, "gpio_in"), 2933 SUNXI_FUNCTION(0x0, "gpio_in"),
2934 SUNXI_FUNCTION(0x1, "gpio_out"), 2934 SUNXI_FUNCTION(0x1, "gpio_out"),
2935 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */ 2935 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
2936 SUNXI_FUNCTION(0x3, "spi3"), /* CLK */ 2936 SUNXI_FUNCTION(0x3, "spi3"), /* CLK */
2937 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD1 */ 2937 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD1 */
2938 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7, 2938 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
2939 SUNXI_FUNCTION(0x0, "gpio_in"), 2939 SUNXI_FUNCTION(0x0, "gpio_in"),
2940 SUNXI_FUNCTION(0x1, "gpio_out"), 2940 SUNXI_FUNCTION(0x1, "gpio_out"),
2941 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */ 2941 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
2942 SUNXI_FUNCTION(0x3, "spi3"), /* MOSI */ 2942 SUNXI_FUNCTION(0x3, "spi3"), /* MOSI */
2943 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD0 */ 2943 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD0 */
2944 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8, 2944 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
2945 SUNXI_FUNCTION(0x0, "gpio_in"), 2945 SUNXI_FUNCTION(0x0, "gpio_in"),
2946 SUNXI_FUNCTION(0x1, "gpio_out"), 2946 SUNXI_FUNCTION(0x1, "gpio_out"),
2947 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */ 2947 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
2948 SUNXI_FUNCTION(0x3, "spi3"), /* MISO */ 2948 SUNXI_FUNCTION(0x3, "spi3"), /* MISO */
2949 SUNXI_FUNCTION(0x5, "gmac")), /* GRXCK */ 2949 SUNXI_FUNCTION(0x5, "gmac")), /* GRXCK */
2950 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9, 2950 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
2951 SUNXI_FUNCTION(0x0, "gpio_in"), 2951 SUNXI_FUNCTION(0x0, "gpio_in"),
2952 SUNXI_FUNCTION(0x1, "gpio_out"), 2952 SUNXI_FUNCTION(0x1, "gpio_out"),
2953 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */ 2953 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
2954 SUNXI_FUNCTION(0x3, "spi3"), /* CS1 */ 2954 SUNXI_FUNCTION(0x3, "spi3"), /* CS1 */
2955 SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ERXERR */ 2955 SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ERXERR */
2956 SUNXI_FUNCTION(0x6, "i2s1")), /* MCLK */ 2956 SUNXI_FUNCTION(0x6, "i2s1")), /* MCLK */
2957 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10, 2957 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
2958 SUNXI_FUNCTION(0x0, "gpio_in"), 2958 SUNXI_FUNCTION(0x0, "gpio_in"),
2959 SUNXI_FUNCTION(0x1, "gpio_out"), 2959 SUNXI_FUNCTION(0x1, "gpio_out"),
2960 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */ 2960 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
2961 SUNXI_FUNCTION(0x4, "uart1"), /* TX */ 2961 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
2962 SUNXI_FUNCTION(0x5, "gmac")), /* GRXCTL / ERXDV */ 2962 SUNXI_FUNCTION(0x5, "gmac")), /* GRXCTL / ERXDV */
2963 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11, 2963 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
2964 SUNXI_FUNCTION(0x0, "gpio_in"), 2964 SUNXI_FUNCTION(0x0, "gpio_in"),
2965 SUNXI_FUNCTION(0x1, "gpio_out"), 2965 SUNXI_FUNCTION(0x1, "gpio_out"),
2966 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */ 2966 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
2967 SUNXI_FUNCTION(0x4, "uart1"), /* RX */ 2967 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
2968 SUNXI_FUNCTION(0x5, "gmac")), /* EMDC */ 2968 SUNXI_FUNCTION(0x5, "gmac")), /* EMDC */
2969 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12, 2969 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
2970 SUNXI_FUNCTION(0x0, "gpio_in"), 2970 SUNXI_FUNCTION(0x0, "gpio_in"),
2971 SUNXI_FUNCTION(0x1, "gpio_out"), 2971 SUNXI_FUNCTION(0x1, "gpio_out"),
2972 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */ 2972 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
2973 SUNXI_FUNCTION(0x3, "uart6"), /* TX */ 2973 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
2974 SUNXI_FUNCTION(0x4, "uart1"), /* RTS */ 2974 SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
2975 SUNXI_FUNCTION(0x5, "gmac")), /* EMDIO */ 2975 SUNXI_FUNCTION(0x5, "gmac")), /* EMDIO */
2976 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13, 2976 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
2977 SUNXI_FUNCTION(0x0, "gpio_in"), 2977 SUNXI_FUNCTION(0x0, "gpio_in"),
2978 SUNXI_FUNCTION(0x1, "gpio_out"), 2978 SUNXI_FUNCTION(0x1, "gpio_out"),
2979 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */ 2979 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
2980 SUNXI_FUNCTION(0x3, "uart6"), /* RX */ 2980 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
2981 SUNXI_FUNCTION(0x4, "uart1"), /* CTS */ 2981 SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
2982 SUNXI_FUNCTION(0x5, "gmac")), /* GTXCTL / ETXEN */ 2982 SUNXI_FUNCTION(0x5, "gmac")), /* GTXCTL / ETXEN */
2983 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14, 2983 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
2984 SUNXI_FUNCTION(0x0, "gpio_in"), 2984 SUNXI_FUNCTION(0x0, "gpio_in"),
2985 SUNXI_FUNCTION(0x1, "gpio_out"), 2985 SUNXI_FUNCTION(0x1, "gpio_out"),
2986 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */ 2986 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
@@ -2988,7 +2988,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
2988 SUNXI_FUNCTION(0x4, "uart1"), /* DTR */ 2988 SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
2989 SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ETXCK */ 2989 SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ETXCK */
2990 SUNXI_FUNCTION(0x6, "i2s1")), /* BCLK */ 2990 SUNXI_FUNCTION(0x6, "i2s1")), /* BCLK */
2991 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15, 2991 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
2992 SUNXI_FUNCTION(0x0, "gpio_in"), 2992 SUNXI_FUNCTION(0x0, "gpio_in"),
2993 SUNXI_FUNCTION(0x1, "gpio_out"), 2993 SUNXI_FUNCTION(0x1, "gpio_out"),
2994 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */ 2994 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
@@ -2996,7 +2996,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
2996 SUNXI_FUNCTION(0x4, "uart1"), /* DSR */ 2996 SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
2997 SUNXI_FUNCTION(0x5, "gmac"), /* GTXCK / ECRS */ 2997 SUNXI_FUNCTION(0x5, "gmac"), /* GTXCK / ECRS */
2998 SUNXI_FUNCTION(0x6, "i2s1")), /* LRCK */ 2998 SUNXI_FUNCTION(0x6, "i2s1")), /* LRCK */
2999 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16, 2999 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
3000 SUNXI_FUNCTION(0x0, "gpio_in"), 3000 SUNXI_FUNCTION(0x0, "gpio_in"),
3001 SUNXI_FUNCTION(0x1, "gpio_out"), 3001 SUNXI_FUNCTION(0x1, "gpio_out"),
3002 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */ 3002 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
@@ -3004,7 +3004,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
3004 SUNXI_FUNCTION(0x4, "uart1"), /* DCD */ 3004 SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
3005 SUNXI_FUNCTION(0x5, "gmac"), /* GCLKIN / ECOL */ 3005 SUNXI_FUNCTION(0x5, "gmac"), /* GCLKIN / ECOL */
3006 SUNXI_FUNCTION(0x6, "i2s1")), /* DO */ 3006 SUNXI_FUNCTION(0x6, "i2s1")), /* DO */
3007 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17, 3007 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
3008 SUNXI_FUNCTION(0x0, "gpio_in"), 3008 SUNXI_FUNCTION(0x0, "gpio_in"),
3009 SUNXI_FUNCTION(0x1, "gpio_out"), 3009 SUNXI_FUNCTION(0x1, "gpio_out"),
3010 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */ 3010 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
@@ -3013,543 +3013,543 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
3013 SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ETXERR */ 3013 SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ETXERR */
3014 SUNXI_FUNCTION(0x6, "i2s1")), /* LRCK */ 3014 SUNXI_FUNCTION(0x6, "i2s1")), /* LRCK */
3015 /* Hole */ 3015 /* Hole */
3016 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0, 3016 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
3017 SUNXI_FUNCTION(0x0, "gpio_in"), 3017 SUNXI_FUNCTION(0x0, "gpio_in"),
3018 SUNXI_FUNCTION(0x1, "gpio_out"), 3018 SUNXI_FUNCTION(0x1, "gpio_out"),
3019 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ 3019 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
3020 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1, 3020 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
3021 SUNXI_FUNCTION(0x0, "gpio_in"), 3021 SUNXI_FUNCTION(0x0, "gpio_in"),
3022 SUNXI_FUNCTION(0x1, "gpio_out"), 3022 SUNXI_FUNCTION(0x1, "gpio_out"),
3023 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ 3023 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
3024 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2, 3024 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
3025 SUNXI_FUNCTION(0x0, "gpio_in"), 3025 SUNXI_FUNCTION(0x0, "gpio_in"),
3026 SUNXI_FUNCTION(0x1, "gpio_out"), 3026 SUNXI_FUNCTION(0x1, "gpio_out"),
3027 SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */ 3027 SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */
3028 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3, 3028 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
3029 SUNXI_FUNCTION(0x0, "gpio_in"), 3029 SUNXI_FUNCTION(0x0, "gpio_in"),
3030 SUNXI_FUNCTION(0x1, "gpio_out"), 3030 SUNXI_FUNCTION(0x1, "gpio_out"),
3031 SUNXI_FUNCTION(0x2, "ir0"), /* TX */ 3031 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
3032 SUNXI_FUNCTION(0x4, "spdif")), /* MCLK */ 3032 SUNXI_FUNCTION(0x4, "spdif")), /* MCLK */
3033 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4, 3033 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
3034 SUNXI_FUNCTION(0x0, "gpio_in"), 3034 SUNXI_FUNCTION(0x0, "gpio_in"),
3035 SUNXI_FUNCTION(0x1, "gpio_out"), 3035 SUNXI_FUNCTION(0x1, "gpio_out"),
3036 SUNXI_FUNCTION(0x2, "ir0")), /* RX */ 3036 SUNXI_FUNCTION(0x2, "ir0")), /* RX */
3037 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5, 3037 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
3038 SUNXI_FUNCTION(0x0, "gpio_in"), 3038 SUNXI_FUNCTION(0x0, "gpio_in"),
3039 SUNXI_FUNCTION(0x1, "gpio_out"), 3039 SUNXI_FUNCTION(0x1, "gpio_out"),
3040 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */ 3040 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
3041 SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */ 3041 SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */
3042 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6, 3042 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
3043 SUNXI_FUNCTION(0x0, "gpio_in"), 3043 SUNXI_FUNCTION(0x0, "gpio_in"),
3044 SUNXI_FUNCTION(0x1, "gpio_out"), 3044 SUNXI_FUNCTION(0x1, "gpio_out"),
3045 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */ 3045 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
3046 SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */ 3046 SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */
3047 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7, 3047 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
3048 SUNXI_FUNCTION(0x0, "gpio_in"), 3048 SUNXI_FUNCTION(0x0, "gpio_in"),
3049 SUNXI_FUNCTION(0x1, "gpio_out"), 3049 SUNXI_FUNCTION(0x1, "gpio_out"),
3050 SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */ 3050 SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
3051 SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */ 3051 SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */
3052 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8, 3052 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
3053 SUNXI_FUNCTION(0x0, "gpio_in"), 3053 SUNXI_FUNCTION(0x0, "gpio_in"),
3054 SUNXI_FUNCTION(0x1, "gpio_out"), 3054 SUNXI_FUNCTION(0x1, "gpio_out"),
3055 SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */ 3055 SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */
3056 SUNXI_FUNCTION(0x3, "ac97")), /* DO */ 3056 SUNXI_FUNCTION(0x3, "ac97")), /* DO */
3057 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9, 3057 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
3058 SUNXI_FUNCTION(0x0, "gpio_in"), 3058 SUNXI_FUNCTION(0x0, "gpio_in"),
3059 SUNXI_FUNCTION(0x1, "gpio_out"), 3059 SUNXI_FUNCTION(0x1, "gpio_out"),
3060 SUNXI_FUNCTION(0x2, "i2s0")), /* DO1 */ 3060 SUNXI_FUNCTION(0x2, "i2s0")), /* DO1 */
3061 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10, 3061 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
3062 SUNXI_FUNCTION(0x0, "gpio_in"), 3062 SUNXI_FUNCTION(0x0, "gpio_in"),
3063 SUNXI_FUNCTION(0x1, "gpio_out"), 3063 SUNXI_FUNCTION(0x1, "gpio_out"),
3064 SUNXI_FUNCTION(0x2, "i2s0")), /* DO2 */ 3064 SUNXI_FUNCTION(0x2, "i2s0")), /* DO2 */
3065 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11, 3065 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
3066 SUNXI_FUNCTION(0x0, "gpio_in"), 3066 SUNXI_FUNCTION(0x0, "gpio_in"),
3067 SUNXI_FUNCTION(0x1, "gpio_out"), 3067 SUNXI_FUNCTION(0x1, "gpio_out"),
3068 SUNXI_FUNCTION(0x2, "i2s0")), /* DO3 */ 3068 SUNXI_FUNCTION(0x2, "i2s0")), /* DO3 */
3069 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12, 3069 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
3070 SUNXI_FUNCTION(0x0, "gpio_in"), 3070 SUNXI_FUNCTION(0x0, "gpio_in"),
3071 SUNXI_FUNCTION(0x1, "gpio_out"), 3071 SUNXI_FUNCTION(0x1, "gpio_out"),
3072 SUNXI_FUNCTION(0x2, "i2s0"), /* DI */ 3072 SUNXI_FUNCTION(0x2, "i2s0"), /* DI */
3073 SUNXI_FUNCTION(0x3, "ac97"), /* DI */ 3073 SUNXI_FUNCTION(0x3, "ac97"), /* DI */
3074 SUNXI_FUNCTION(0x4, "spdif")), /* DI */ 3074 SUNXI_FUNCTION(0x4, "spdif")), /* DI */
3075 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13, 3075 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
3076 SUNXI_FUNCTION(0x0, "gpio_in"), 3076 SUNXI_FUNCTION(0x0, "gpio_in"),
3077 SUNXI_FUNCTION(0x1, "gpio_out"), 3077 SUNXI_FUNCTION(0x1, "gpio_out"),
3078 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */ 3078 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
3079 SUNXI_FUNCTION(0x4, "spdif")), /* DO */ 3079 SUNXI_FUNCTION(0x4, "spdif")), /* DO */
3080 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14, 3080 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
3081 SUNXI_FUNCTION(0x0, "gpio_in"), 3081 SUNXI_FUNCTION(0x0, "gpio_in"),
3082 SUNXI_FUNCTION(0x1, "gpio_out"), 3082 SUNXI_FUNCTION(0x1, "gpio_out"),
3083 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */ 3083 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
3084 SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */ 3084 SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */
3085 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15, 3085 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
3086 SUNXI_FUNCTION(0x0, "gpio_in"), 3086 SUNXI_FUNCTION(0x0, "gpio_in"),
3087 SUNXI_FUNCTION(0x1, "gpio_out"), 3087 SUNXI_FUNCTION(0x1, "gpio_out"),
3088 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */ 3088 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
3089 SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */ 3089 SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */
3090 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16, 3090 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
3091 SUNXI_FUNCTION(0x0, "gpio_in"), 3091 SUNXI_FUNCTION(0x0, "gpio_in"),
3092 SUNXI_FUNCTION(0x1, "gpio_out"), 3092 SUNXI_FUNCTION(0x1, "gpio_out"),
3093 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */ 3093 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
3094 SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */ 3094 SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */
3095 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17, 3095 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
3096 SUNXI_FUNCTION(0x0, "gpio_in"), 3096 SUNXI_FUNCTION(0x0, "gpio_in"),
3097 SUNXI_FUNCTION(0x1, "gpio_out"), 3097 SUNXI_FUNCTION(0x1, "gpio_out"),
3098 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */ 3098 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
3099 SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */ 3099 SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */
3100 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18, 3100 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
3101 SUNXI_FUNCTION(0x0, "gpio_in"), 3101 SUNXI_FUNCTION(0x0, "gpio_in"),
3102 SUNXI_FUNCTION(0x1, "gpio_out"), 3102 SUNXI_FUNCTION(0x1, "gpio_out"),
3103 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ 3103 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
3104 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19, 3104 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 19),
3105 SUNXI_FUNCTION(0x0, "gpio_in"), 3105 SUNXI_FUNCTION(0x0, "gpio_in"),
3106 SUNXI_FUNCTION(0x1, "gpio_out"), 3106 SUNXI_FUNCTION(0x1, "gpio_out"),
3107 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ 3107 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
3108 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20, 3108 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20),
3109 SUNXI_FUNCTION(0x0, "gpio_in"), 3109 SUNXI_FUNCTION(0x0, "gpio_in"),
3110 SUNXI_FUNCTION(0x1, "gpio_out"), 3110 SUNXI_FUNCTION(0x1, "gpio_out"),
3111 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ 3111 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
3112 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21, 3112 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 21),
3113 SUNXI_FUNCTION(0x0, "gpio_in"), 3113 SUNXI_FUNCTION(0x0, "gpio_in"),
3114 SUNXI_FUNCTION(0x1, "gpio_out"), 3114 SUNXI_FUNCTION(0x1, "gpio_out"),
3115 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ 3115 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
3116 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22, 3116 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 22),
3117 SUNXI_FUNCTION(0x0, "gpio_in"), 3117 SUNXI_FUNCTION(0x0, "gpio_in"),
3118 SUNXI_FUNCTION(0x1, "gpio_out"), 3118 SUNXI_FUNCTION(0x1, "gpio_out"),
3119 SUNXI_FUNCTION(0x2, "uart0"), /* TX */ 3119 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
3120 SUNXI_FUNCTION(0x3, "ir1")), /* TX */ 3120 SUNXI_FUNCTION(0x3, "ir1")), /* TX */
3121 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23, 3121 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 23),
3122 SUNXI_FUNCTION(0x0, "gpio_in"), 3122 SUNXI_FUNCTION(0x0, "gpio_in"),
3123 SUNXI_FUNCTION(0x1, "gpio_out"), 3123 SUNXI_FUNCTION(0x1, "gpio_out"),
3124 SUNXI_FUNCTION(0x2, "uart0"), /* RX */ 3124 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
3125 SUNXI_FUNCTION(0x3, "ir1")), /* RX */ 3125 SUNXI_FUNCTION(0x3, "ir1")), /* RX */
3126 /* Hole */ 3126 /* Hole */
3127 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0, 3127 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
3128 SUNXI_FUNCTION(0x0, "gpio_in"), 3128 SUNXI_FUNCTION(0x0, "gpio_in"),
3129 SUNXI_FUNCTION(0x1, "gpio_out"), 3129 SUNXI_FUNCTION(0x1, "gpio_out"),
3130 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ 3130 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
3131 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ 3131 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
3132 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1, 3132 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
3133 SUNXI_FUNCTION(0x0, "gpio_in"), 3133 SUNXI_FUNCTION(0x0, "gpio_in"),
3134 SUNXI_FUNCTION(0x1, "gpio_out"), 3134 SUNXI_FUNCTION(0x1, "gpio_out"),
3135 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ 3135 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
3136 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ 3136 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
3137 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2, 3137 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
3138 SUNXI_FUNCTION(0x0, "gpio_in"), 3138 SUNXI_FUNCTION(0x0, "gpio_in"),
3139 SUNXI_FUNCTION(0x1, "gpio_out"), 3139 SUNXI_FUNCTION(0x1, "gpio_out"),
3140 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ 3140 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
3141 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */ 3141 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
3142 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3, 3142 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
3143 SUNXI_FUNCTION(0x0, "gpio_in"), 3143 SUNXI_FUNCTION(0x0, "gpio_in"),
3144 SUNXI_FUNCTION(0x1, "gpio_out"), 3144 SUNXI_FUNCTION(0x1, "gpio_out"),
3145 SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */ 3145 SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */
3146 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4, 3146 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
3147 SUNXI_FUNCTION(0x0, "gpio_in"), 3147 SUNXI_FUNCTION(0x0, "gpio_in"),
3148 SUNXI_FUNCTION(0x1, "gpio_out"), 3148 SUNXI_FUNCTION(0x1, "gpio_out"),
3149 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ 3149 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
3150 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5, 3150 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
3151 SUNXI_FUNCTION(0x0, "gpio_in"), 3151 SUNXI_FUNCTION(0x0, "gpio_in"),
3152 SUNXI_FUNCTION(0x1, "gpio_out"), 3152 SUNXI_FUNCTION(0x1, "gpio_out"),
3153 SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */ 3153 SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */
3154 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6, 3154 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
3155 SUNXI_FUNCTION(0x0, "gpio_in"), 3155 SUNXI_FUNCTION(0x0, "gpio_in"),
3156 SUNXI_FUNCTION(0x1, "gpio_out"), 3156 SUNXI_FUNCTION(0x1, "gpio_out"),
3157 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ 3157 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
3158 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ 3158 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
3159 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7, 3159 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
3160 SUNXI_FUNCTION(0x0, "gpio_in"), 3160 SUNXI_FUNCTION(0x0, "gpio_in"),
3161 SUNXI_FUNCTION(0x1, "gpio_out"), 3161 SUNXI_FUNCTION(0x1, "gpio_out"),
3162 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */ 3162 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
3163 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ 3163 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
3164 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8, 3164 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
3165 SUNXI_FUNCTION(0x0, "gpio_in"), 3165 SUNXI_FUNCTION(0x0, "gpio_in"),
3166 SUNXI_FUNCTION(0x1, "gpio_out"), 3166 SUNXI_FUNCTION(0x1, "gpio_out"),
3167 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ 3167 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
3168 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ 3168 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
3169 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9, 3169 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
3170 SUNXI_FUNCTION(0x0, "gpio_in"), 3170 SUNXI_FUNCTION(0x0, "gpio_in"),
3171 SUNXI_FUNCTION(0x1, "gpio_out"), 3171 SUNXI_FUNCTION(0x1, "gpio_out"),
3172 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ 3172 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
3173 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ 3173 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
3174 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10, 3174 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
3175 SUNXI_FUNCTION(0x0, "gpio_in"), 3175 SUNXI_FUNCTION(0x0, "gpio_in"),
3176 SUNXI_FUNCTION(0x1, "gpio_out"), 3176 SUNXI_FUNCTION(0x1, "gpio_out"),
3177 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ 3177 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
3178 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ 3178 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
3179 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11, 3179 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
3180 SUNXI_FUNCTION(0x0, "gpio_in"), 3180 SUNXI_FUNCTION(0x0, "gpio_in"),
3181 SUNXI_FUNCTION(0x1, "gpio_out"), 3181 SUNXI_FUNCTION(0x1, "gpio_out"),
3182 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ 3182 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
3183 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ 3183 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
3184 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12, 3184 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
3185 SUNXI_FUNCTION(0x0, "gpio_in"), 3185 SUNXI_FUNCTION(0x0, "gpio_in"),
3186 SUNXI_FUNCTION(0x1, "gpio_out"), 3186 SUNXI_FUNCTION(0x1, "gpio_out"),
3187 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */ 3187 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */
3188 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13, 3188 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
3189 SUNXI_FUNCTION(0x0, "gpio_in"), 3189 SUNXI_FUNCTION(0x0, "gpio_in"),
3190 SUNXI_FUNCTION(0x1, "gpio_out"), 3190 SUNXI_FUNCTION(0x1, "gpio_out"),
3191 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */ 3191 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */
3192 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14, 3192 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
3193 SUNXI_FUNCTION(0x0, "gpio_in"), 3193 SUNXI_FUNCTION(0x0, "gpio_in"),
3194 SUNXI_FUNCTION(0x1, "gpio_out"), 3194 SUNXI_FUNCTION(0x1, "gpio_out"),
3195 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */ 3195 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */
3196 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15, 3196 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
3197 SUNXI_FUNCTION(0x0, "gpio_in"), 3197 SUNXI_FUNCTION(0x0, "gpio_in"),
3198 SUNXI_FUNCTION(0x1, "gpio_out"), 3198 SUNXI_FUNCTION(0x1, "gpio_out"),
3199 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */ 3199 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */
3200 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16, 3200 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
3201 SUNXI_FUNCTION(0x0, "gpio_in"), 3201 SUNXI_FUNCTION(0x0, "gpio_in"),
3202 SUNXI_FUNCTION(0x1, "gpio_out"), 3202 SUNXI_FUNCTION(0x1, "gpio_out"),
3203 SUNXI_FUNCTION(0x2, "nand0")), /* NWP */ 3203 SUNXI_FUNCTION(0x2, "nand0")), /* NWP */
3204 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17, 3204 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
3205 SUNXI_FUNCTION(0x0, "gpio_in"), 3205 SUNXI_FUNCTION(0x0, "gpio_in"),
3206 SUNXI_FUNCTION(0x1, "gpio_out"), 3206 SUNXI_FUNCTION(0x1, "gpio_out"),
3207 SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */ 3207 SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */
3208 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18, 3208 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
3209 SUNXI_FUNCTION(0x0, "gpio_in"), 3209 SUNXI_FUNCTION(0x0, "gpio_in"),
3210 SUNXI_FUNCTION(0x1, "gpio_out"), 3210 SUNXI_FUNCTION(0x1, "gpio_out"),
3211 SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */ 3211 SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */
3212 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19, 3212 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
3213 SUNXI_FUNCTION(0x0, "gpio_in"), 3213 SUNXI_FUNCTION(0x0, "gpio_in"),
3214 SUNXI_FUNCTION(0x1, "gpio_out"), 3214 SUNXI_FUNCTION(0x1, "gpio_out"),
3215 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */ 3215 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
3216 SUNXI_FUNCTION(0x3, "spi2"), /* CS0 */ 3216 SUNXI_FUNCTION(0x3, "spi2"), /* CS0 */
3217 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */ 3217 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
3218 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20, 3218 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20),
3219 SUNXI_FUNCTION(0x0, "gpio_in"), 3219 SUNXI_FUNCTION(0x0, "gpio_in"),
3220 SUNXI_FUNCTION(0x1, "gpio_out"), 3220 SUNXI_FUNCTION(0x1, "gpio_out"),
3221 SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */ 3221 SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
3222 SUNXI_FUNCTION(0x3, "spi2"), /* CLK */ 3222 SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
3223 SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */ 3223 SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
3224 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21, 3224 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21),
3225 SUNXI_FUNCTION(0x0, "gpio_in"), 3225 SUNXI_FUNCTION(0x0, "gpio_in"),
3226 SUNXI_FUNCTION(0x1, "gpio_out"), 3226 SUNXI_FUNCTION(0x1, "gpio_out"),
3227 SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */ 3227 SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
3228 SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */ 3228 SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
3229 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */ 3229 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
3230 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22, 3230 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22),
3231 SUNXI_FUNCTION(0x0, "gpio_in"), 3231 SUNXI_FUNCTION(0x0, "gpio_in"),
3232 SUNXI_FUNCTION(0x1, "gpio_out"), 3232 SUNXI_FUNCTION(0x1, "gpio_out"),
3233 SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */ 3233 SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
3234 SUNXI_FUNCTION(0x3, "spi2"), /* MISO */ 3234 SUNXI_FUNCTION(0x3, "spi2"), /* MISO */
3235 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */ 3235 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
3236 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23, 3236 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23),
3237 SUNXI_FUNCTION(0x0, "gpio_in"), 3237 SUNXI_FUNCTION(0x0, "gpio_in"),
3238 SUNXI_FUNCTION(0x1, "gpio_out"), 3238 SUNXI_FUNCTION(0x1, "gpio_out"),
3239 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ 3239 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
3240 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24, 3240 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24),
3241 SUNXI_FUNCTION(0x0, "gpio_in"), 3241 SUNXI_FUNCTION(0x0, "gpio_in"),
3242 SUNXI_FUNCTION(0x1, "gpio_out"), 3242 SUNXI_FUNCTION(0x1, "gpio_out"),
3243 SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */ 3243 SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */
3244 /* Hole */ 3244 /* Hole */
3245 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0, 3245 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
3246 SUNXI_FUNCTION(0x0, "gpio_in"), 3246 SUNXI_FUNCTION(0x0, "gpio_in"),
3247 SUNXI_FUNCTION(0x1, "gpio_out"), 3247 SUNXI_FUNCTION(0x1, "gpio_out"),
3248 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */ 3248 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
3249 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */ 3249 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
3250 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1, 3250 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
3251 SUNXI_FUNCTION(0x0, "gpio_in"), 3251 SUNXI_FUNCTION(0x0, "gpio_in"),
3252 SUNXI_FUNCTION(0x1, "gpio_out"), 3252 SUNXI_FUNCTION(0x1, "gpio_out"),
3253 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */ 3253 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
3254 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */ 3254 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
3255 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2, 3255 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
3256 SUNXI_FUNCTION(0x0, "gpio_in"), 3256 SUNXI_FUNCTION(0x0, "gpio_in"),
3257 SUNXI_FUNCTION(0x1, "gpio_out"), 3257 SUNXI_FUNCTION(0x1, "gpio_out"),
3258 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ 3258 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
3259 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */ 3259 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
3260 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3, 3260 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
3261 SUNXI_FUNCTION(0x0, "gpio_in"), 3261 SUNXI_FUNCTION(0x0, "gpio_in"),
3262 SUNXI_FUNCTION(0x1, "gpio_out"), 3262 SUNXI_FUNCTION(0x1, "gpio_out"),
3263 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ 3263 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
3264 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */ 3264 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
3265 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4, 3265 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
3266 SUNXI_FUNCTION(0x0, "gpio_in"), 3266 SUNXI_FUNCTION(0x0, "gpio_in"),
3267 SUNXI_FUNCTION(0x1, "gpio_out"), 3267 SUNXI_FUNCTION(0x1, "gpio_out"),
3268 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ 3268 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
3269 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */ 3269 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
3270 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5, 3270 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
3271 SUNXI_FUNCTION(0x0, "gpio_in"), 3271 SUNXI_FUNCTION(0x0, "gpio_in"),
3272 SUNXI_FUNCTION(0x1, "gpio_out"), 3272 SUNXI_FUNCTION(0x1, "gpio_out"),
3273 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ 3273 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
3274 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */ 3274 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
3275 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6, 3275 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
3276 SUNXI_FUNCTION(0x0, "gpio_in"), 3276 SUNXI_FUNCTION(0x0, "gpio_in"),
3277 SUNXI_FUNCTION(0x1, "gpio_out"), 3277 SUNXI_FUNCTION(0x1, "gpio_out"),
3278 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ 3278 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
3279 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */ 3279 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
3280 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7, 3280 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
3281 SUNXI_FUNCTION(0x0, "gpio_in"), 3281 SUNXI_FUNCTION(0x0, "gpio_in"),
3282 SUNXI_FUNCTION(0x1, "gpio_out"), 3282 SUNXI_FUNCTION(0x1, "gpio_out"),
3283 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ 3283 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
3284 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */ 3284 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
3285 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8, 3285 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
3286 SUNXI_FUNCTION(0x0, "gpio_in"), 3286 SUNXI_FUNCTION(0x0, "gpio_in"),
3287 SUNXI_FUNCTION(0x1, "gpio_out"), 3287 SUNXI_FUNCTION(0x1, "gpio_out"),
3288 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */ 3288 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
3289 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */ 3289 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
3290 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9, 3290 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
3291 SUNXI_FUNCTION(0x0, "gpio_in"), 3291 SUNXI_FUNCTION(0x0, "gpio_in"),
3292 SUNXI_FUNCTION(0x1, "gpio_out"), 3292 SUNXI_FUNCTION(0x1, "gpio_out"),
3293 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */ 3293 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
3294 SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */ 3294 SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */
3295 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10, 3295 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
3296 SUNXI_FUNCTION(0x0, "gpio_in"), 3296 SUNXI_FUNCTION(0x0, "gpio_in"),
3297 SUNXI_FUNCTION(0x1, "gpio_out"), 3297 SUNXI_FUNCTION(0x1, "gpio_out"),
3298 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ 3298 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
3299 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */ 3299 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
3300 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11, 3300 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
3301 SUNXI_FUNCTION(0x0, "gpio_in"), 3301 SUNXI_FUNCTION(0x0, "gpio_in"),
3302 SUNXI_FUNCTION(0x1, "gpio_out"), 3302 SUNXI_FUNCTION(0x1, "gpio_out"),
3303 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ 3303 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
3304 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */ 3304 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
3305 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12, 3305 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
3306 SUNXI_FUNCTION(0x0, "gpio_in"), 3306 SUNXI_FUNCTION(0x0, "gpio_in"),
3307 SUNXI_FUNCTION(0x1, "gpio_out"), 3307 SUNXI_FUNCTION(0x1, "gpio_out"),
3308 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ 3308 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
3309 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */ 3309 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
3310 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13, 3310 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
3311 SUNXI_FUNCTION(0x0, "gpio_in"), 3311 SUNXI_FUNCTION(0x0, "gpio_in"),
3312 SUNXI_FUNCTION(0x1, "gpio_out"), 3312 SUNXI_FUNCTION(0x1, "gpio_out"),
3313 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ 3313 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
3314 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */ 3314 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
3315 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14, 3315 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
3316 SUNXI_FUNCTION(0x0, "gpio_in"), 3316 SUNXI_FUNCTION(0x0, "gpio_in"),
3317 SUNXI_FUNCTION(0x1, "gpio_out"), 3317 SUNXI_FUNCTION(0x1, "gpio_out"),
3318 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ 3318 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
3319 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */ 3319 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
3320 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15, 3320 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
3321 SUNXI_FUNCTION(0x0, "gpio_in"), 3321 SUNXI_FUNCTION(0x0, "gpio_in"),
3322 SUNXI_FUNCTION(0x1, "gpio_out"), 3322 SUNXI_FUNCTION(0x1, "gpio_out"),
3323 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ 3323 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
3324 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */ 3324 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
3325 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16, 3325 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
3326 SUNXI_FUNCTION(0x0, "gpio_in"), 3326 SUNXI_FUNCTION(0x0, "gpio_in"),
3327 SUNXI_FUNCTION(0x1, "gpio_out"), 3327 SUNXI_FUNCTION(0x1, "gpio_out"),
3328 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */ 3328 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
3329 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */ 3329 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
3330 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17, 3330 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
3331 SUNXI_FUNCTION(0x0, "gpio_in"), 3331 SUNXI_FUNCTION(0x0, "gpio_in"),
3332 SUNXI_FUNCTION(0x1, "gpio_out"), 3332 SUNXI_FUNCTION(0x1, "gpio_out"),
3333 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */ 3333 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
3334 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */ 3334 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
3335 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18, 3335 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
3336 SUNXI_FUNCTION(0x0, "gpio_in"), 3336 SUNXI_FUNCTION(0x0, "gpio_in"),
3337 SUNXI_FUNCTION(0x1, "gpio_out"), 3337 SUNXI_FUNCTION(0x1, "gpio_out"),
3338 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ 3338 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
3339 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */ 3339 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
3340 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19, 3340 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
3341 SUNXI_FUNCTION(0x0, "gpio_in"), 3341 SUNXI_FUNCTION(0x0, "gpio_in"),
3342 SUNXI_FUNCTION(0x1, "gpio_out"), 3342 SUNXI_FUNCTION(0x1, "gpio_out"),
3343 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ 3343 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
3344 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */ 3344 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
3345 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20, 3345 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
3346 SUNXI_FUNCTION(0x0, "gpio_in"), 3346 SUNXI_FUNCTION(0x0, "gpio_in"),
3347 SUNXI_FUNCTION(0x1, "gpio_out"), 3347 SUNXI_FUNCTION(0x1, "gpio_out"),
3348 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ 3348 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
3349 SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */ 3349 SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */
3350 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21, 3350 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
3351 SUNXI_FUNCTION(0x0, "gpio_in"), 3351 SUNXI_FUNCTION(0x0, "gpio_in"),
3352 SUNXI_FUNCTION(0x1, "gpio_out"), 3352 SUNXI_FUNCTION(0x1, "gpio_out"),
3353 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ 3353 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
3354 SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */ 3354 SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */
3355 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22, 3355 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
3356 SUNXI_FUNCTION(0x0, "gpio_in"), 3356 SUNXI_FUNCTION(0x0, "gpio_in"),
3357 SUNXI_FUNCTION(0x1, "gpio_out"), 3357 SUNXI_FUNCTION(0x1, "gpio_out"),
3358 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ 3358 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
3359 SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */ 3359 SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */
3360 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23, 3360 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
3361 SUNXI_FUNCTION(0x0, "gpio_in"), 3361 SUNXI_FUNCTION(0x0, "gpio_in"),
3362 SUNXI_FUNCTION(0x1, "gpio_out"), 3362 SUNXI_FUNCTION(0x1, "gpio_out"),
3363 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ 3363 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
3364 SUNXI_FUNCTION(0x3, "sim")), /* DET */ 3364 SUNXI_FUNCTION(0x3, "sim")), /* DET */
3365 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24, 3365 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
3366 SUNXI_FUNCTION(0x0, "gpio_in"), 3366 SUNXI_FUNCTION(0x0, "gpio_in"),
3367 SUNXI_FUNCTION(0x1, "gpio_out"), 3367 SUNXI_FUNCTION(0x1, "gpio_out"),
3368 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ 3368 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
3369 SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */ 3369 SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */
3370 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25, 3370 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
3371 SUNXI_FUNCTION(0x0, "gpio_in"), 3371 SUNXI_FUNCTION(0x0, "gpio_in"),
3372 SUNXI_FUNCTION(0x1, "gpio_out"), 3372 SUNXI_FUNCTION(0x1, "gpio_out"),
3373 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ 3373 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
3374 SUNXI_FUNCTION(0x3, "sim")), /* RST */ 3374 SUNXI_FUNCTION(0x3, "sim")), /* RST */
3375 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26, 3375 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
3376 SUNXI_FUNCTION(0x0, "gpio_in"), 3376 SUNXI_FUNCTION(0x0, "gpio_in"),
3377 SUNXI_FUNCTION(0x1, "gpio_out"), 3377 SUNXI_FUNCTION(0x1, "gpio_out"),
3378 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ 3378 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
3379 SUNXI_FUNCTION(0x3, "sim")), /* SCK */ 3379 SUNXI_FUNCTION(0x3, "sim")), /* SCK */
3380 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27, 3380 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
3381 SUNXI_FUNCTION(0x0, "gpio_in"), 3381 SUNXI_FUNCTION(0x0, "gpio_in"),
3382 SUNXI_FUNCTION(0x1, "gpio_out"), 3382 SUNXI_FUNCTION(0x1, "gpio_out"),
3383 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ 3383 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
3384 SUNXI_FUNCTION(0x3, "sim")), /* SDA */ 3384 SUNXI_FUNCTION(0x3, "sim")), /* SDA */
3385 /* Hole */ 3385 /* Hole */
3386 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0, 3386 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
3387 SUNXI_FUNCTION(0x0, "gpio_in"), 3387 SUNXI_FUNCTION(0x0, "gpio_in"),
3388 SUNXI_FUNCTION(0x1, "gpio_out"), 3388 SUNXI_FUNCTION(0x1, "gpio_out"),
3389 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */ 3389 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
3390 SUNXI_FUNCTION(0x3, "csi0")), /* PCK */ 3390 SUNXI_FUNCTION(0x3, "csi0")), /* PCK */
3391 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1, 3391 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
3392 SUNXI_FUNCTION(0x0, "gpio_in"), 3392 SUNXI_FUNCTION(0x0, "gpio_in"),
3393 SUNXI_FUNCTION(0x1, "gpio_out"), 3393 SUNXI_FUNCTION(0x1, "gpio_out"),
3394 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */ 3394 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
3395 SUNXI_FUNCTION(0x3, "csi0")), /* CK */ 3395 SUNXI_FUNCTION(0x3, "csi0")), /* CK */
3396 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2, 3396 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
3397 SUNXI_FUNCTION(0x0, "gpio_in"), 3397 SUNXI_FUNCTION(0x0, "gpio_in"),
3398 SUNXI_FUNCTION(0x1, "gpio_out"), 3398 SUNXI_FUNCTION(0x1, "gpio_out"),
3399 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */ 3399 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
3400 SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */ 3400 SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */
3401 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3, 3401 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
3402 SUNXI_FUNCTION(0x0, "gpio_in"), 3402 SUNXI_FUNCTION(0x0, "gpio_in"),
3403 SUNXI_FUNCTION(0x1, "gpio_out"), 3403 SUNXI_FUNCTION(0x1, "gpio_out"),
3404 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */ 3404 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
3405 SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */ 3405 SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */
3406 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4, 3406 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
3407 SUNXI_FUNCTION(0x0, "gpio_in"), 3407 SUNXI_FUNCTION(0x0, "gpio_in"),
3408 SUNXI_FUNCTION(0x1, "gpio_out"), 3408 SUNXI_FUNCTION(0x1, "gpio_out"),
3409 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */ 3409 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
3410 SUNXI_FUNCTION(0x3, "csi0")), /* D0 */ 3410 SUNXI_FUNCTION(0x3, "csi0")), /* D0 */
3411 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5, 3411 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
3412 SUNXI_FUNCTION(0x0, "gpio_in"), 3412 SUNXI_FUNCTION(0x0, "gpio_in"),
3413 SUNXI_FUNCTION(0x1, "gpio_out"), 3413 SUNXI_FUNCTION(0x1, "gpio_out"),
3414 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */ 3414 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
3415 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */ 3415 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
3416 SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */ 3416 SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */
3417 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6, 3417 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
3418 SUNXI_FUNCTION(0x0, "gpio_in"), 3418 SUNXI_FUNCTION(0x0, "gpio_in"),
3419 SUNXI_FUNCTION(0x1, "gpio_out"), 3419 SUNXI_FUNCTION(0x1, "gpio_out"),
3420 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */ 3420 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
3421 SUNXI_FUNCTION(0x3, "csi0")), /* D2 */ 3421 SUNXI_FUNCTION(0x3, "csi0")), /* D2 */
3422 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7, 3422 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
3423 SUNXI_FUNCTION(0x0, "gpio_in"), 3423 SUNXI_FUNCTION(0x0, "gpio_in"),
3424 SUNXI_FUNCTION(0x1, "gpio_out"), 3424 SUNXI_FUNCTION(0x1, "gpio_out"),
3425 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */ 3425 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
3426 SUNXI_FUNCTION(0x3, "csi0")), /* D3 */ 3426 SUNXI_FUNCTION(0x3, "csi0")), /* D3 */
3427 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8, 3427 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
3428 SUNXI_FUNCTION(0x0, "gpio_in"), 3428 SUNXI_FUNCTION(0x0, "gpio_in"),
3429 SUNXI_FUNCTION(0x1, "gpio_out"), 3429 SUNXI_FUNCTION(0x1, "gpio_out"),
3430 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */ 3430 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
3431 SUNXI_FUNCTION(0x3, "csi0")), /* D4 */ 3431 SUNXI_FUNCTION(0x3, "csi0")), /* D4 */
3432 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9, 3432 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
3433 SUNXI_FUNCTION(0x0, "gpio_in"), 3433 SUNXI_FUNCTION(0x0, "gpio_in"),
3434 SUNXI_FUNCTION(0x1, "gpio_out"), 3434 SUNXI_FUNCTION(0x1, "gpio_out"),
3435 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */ 3435 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
3436 SUNXI_FUNCTION(0x3, "csi0")), /* D5 */ 3436 SUNXI_FUNCTION(0x3, "csi0")), /* D5 */
3437 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10, 3437 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
3438 SUNXI_FUNCTION(0x0, "gpio_in"), 3438 SUNXI_FUNCTION(0x0, "gpio_in"),
3439 SUNXI_FUNCTION(0x1, "gpio_out"), 3439 SUNXI_FUNCTION(0x1, "gpio_out"),
3440 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */ 3440 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
3441 SUNXI_FUNCTION(0x3, "csi0")), /* D6 */ 3441 SUNXI_FUNCTION(0x3, "csi0")), /* D6 */
3442 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11, 3442 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
3443 SUNXI_FUNCTION(0x0, "gpio_in"), 3443 SUNXI_FUNCTION(0x0, "gpio_in"),
3444 SUNXI_FUNCTION(0x1, "gpio_out"), 3444 SUNXI_FUNCTION(0x1, "gpio_out"),
3445 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */ 3445 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
3446 SUNXI_FUNCTION(0x3, "csi0")), /* D7 */ 3446 SUNXI_FUNCTION(0x3, "csi0")), /* D7 */
3447 /* Hole */ 3447 /* Hole */
3448 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0, 3448 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
3449 SUNXI_FUNCTION(0x0, "gpio_in"), 3449 SUNXI_FUNCTION(0x0, "gpio_in"),
3450 SUNXI_FUNCTION(0x1, "gpio_out"), 3450 SUNXI_FUNCTION(0x1, "gpio_out"),
3451 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ 3451 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
3452 SUNXI_FUNCTION(0x4, "jtag")), /* MSI */ 3452 SUNXI_FUNCTION(0x4, "jtag")), /* MSI */
3453 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1, 3453 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
3454 SUNXI_FUNCTION(0x0, "gpio_in"), 3454 SUNXI_FUNCTION(0x0, "gpio_in"),
3455 SUNXI_FUNCTION(0x1, "gpio_out"), 3455 SUNXI_FUNCTION(0x1, "gpio_out"),
3456 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ 3456 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
3457 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */ 3457 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
3458 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2, 3458 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
3459 SUNXI_FUNCTION(0x0, "gpio_in"), 3459 SUNXI_FUNCTION(0x0, "gpio_in"),
3460 SUNXI_FUNCTION(0x1, "gpio_out"), 3460 SUNXI_FUNCTION(0x1, "gpio_out"),
3461 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ 3461 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
3462 SUNXI_FUNCTION(0x4, "uart0")), /* TX */ 3462 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
3463 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3, 3463 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
3464 SUNXI_FUNCTION(0x0, "gpio_in"), 3464 SUNXI_FUNCTION(0x0, "gpio_in"),
3465 SUNXI_FUNCTION(0x1, "gpio_out"), 3465 SUNXI_FUNCTION(0x1, "gpio_out"),
3466 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ 3466 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
3467 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */ 3467 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
3468 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4, 3468 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
3469 SUNXI_FUNCTION(0x0, "gpio_in"), 3469 SUNXI_FUNCTION(0x0, "gpio_in"),
3470 SUNXI_FUNCTION(0x1, "gpio_out"), 3470 SUNXI_FUNCTION(0x1, "gpio_out"),
3471 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ 3471 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
3472 SUNXI_FUNCTION(0x4, "uart0")), /* RX */ 3472 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
3473 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5, 3473 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
3474 SUNXI_FUNCTION(0x0, "gpio_in"), 3474 SUNXI_FUNCTION(0x0, "gpio_in"),
3475 SUNXI_FUNCTION(0x1, "gpio_out"), 3475 SUNXI_FUNCTION(0x1, "gpio_out"),
3476 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ 3476 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
3477 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */ 3477 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
3478 /* Hole */ 3478 /* Hole */
3479 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0, 3479 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
3480 SUNXI_FUNCTION(0x0, "gpio_in"), 3480 SUNXI_FUNCTION(0x0, "gpio_in"),
3481 SUNXI_FUNCTION(0x1, "gpio_out"), 3481 SUNXI_FUNCTION(0x1, "gpio_out"),
3482 SUNXI_FUNCTION(0x2, "ts1"), /* CLK */ 3482 SUNXI_FUNCTION(0x2, "ts1"), /* CLK */
3483 SUNXI_FUNCTION(0x3, "csi1"), /* PCK */ 3483 SUNXI_FUNCTION(0x3, "csi1"), /* PCK */
3484 SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */ 3484 SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */
3485 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1, 3485 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
3486 SUNXI_FUNCTION(0x0, "gpio_in"), 3486 SUNXI_FUNCTION(0x0, "gpio_in"),
3487 SUNXI_FUNCTION(0x1, "gpio_out"), 3487 SUNXI_FUNCTION(0x1, "gpio_out"),
3488 SUNXI_FUNCTION(0x2, "ts1"), /* ERR */ 3488 SUNXI_FUNCTION(0x2, "ts1"), /* ERR */
3489 SUNXI_FUNCTION(0x3, "csi1"), /* CK */ 3489 SUNXI_FUNCTION(0x3, "csi1"), /* CK */
3490 SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */ 3490 SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */
3491 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2, 3491 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
3492 SUNXI_FUNCTION(0x0, "gpio_in"), 3492 SUNXI_FUNCTION(0x0, "gpio_in"),
3493 SUNXI_FUNCTION(0x1, "gpio_out"), 3493 SUNXI_FUNCTION(0x1, "gpio_out"),
3494 SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */ 3494 SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */
3495 SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */ 3495 SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */
3496 SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */ 3496 SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */
3497 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3, 3497 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
3498 SUNXI_FUNCTION(0x0, "gpio_in"), 3498 SUNXI_FUNCTION(0x0, "gpio_in"),
3499 SUNXI_FUNCTION(0x1, "gpio_out"), 3499 SUNXI_FUNCTION(0x1, "gpio_out"),
3500 SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */ 3500 SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */
3501 SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */ 3501 SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */
3502 SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */ 3502 SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */
3503 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4, 3503 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
3504 SUNXI_FUNCTION(0x0, "gpio_in"), 3504 SUNXI_FUNCTION(0x0, "gpio_in"),
3505 SUNXI_FUNCTION(0x1, "gpio_out"), 3505 SUNXI_FUNCTION(0x1, "gpio_out"),
3506 SUNXI_FUNCTION(0x2, "ts1"), /* D0 */ 3506 SUNXI_FUNCTION(0x2, "ts1"), /* D0 */
3507 SUNXI_FUNCTION(0x3, "csi1"), /* D0 */ 3507 SUNXI_FUNCTION(0x3, "csi1"), /* D0 */
3508 SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */ 3508 SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */
3509 SUNXI_FUNCTION(0x5, "csi0")), /* D8 */ 3509 SUNXI_FUNCTION(0x5, "csi0")), /* D8 */
3510 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5, 3510 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
3511 SUNXI_FUNCTION(0x0, "gpio_in"), 3511 SUNXI_FUNCTION(0x0, "gpio_in"),
3512 SUNXI_FUNCTION(0x1, "gpio_out"), 3512 SUNXI_FUNCTION(0x1, "gpio_out"),
3513 SUNXI_FUNCTION(0x2, "ts1"), /* D1 */ 3513 SUNXI_FUNCTION(0x2, "ts1"), /* D1 */
3514 SUNXI_FUNCTION(0x3, "csi1"), /* D1 */ 3514 SUNXI_FUNCTION(0x3, "csi1"), /* D1 */
3515 SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */ 3515 SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */
3516 SUNXI_FUNCTION(0x5, "csi0")), /* D9 */ 3516 SUNXI_FUNCTION(0x5, "csi0")), /* D9 */
3517 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6, 3517 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
3518 SUNXI_FUNCTION(0x0, "gpio_in"), 3518 SUNXI_FUNCTION(0x0, "gpio_in"),
3519 SUNXI_FUNCTION(0x1, "gpio_out"), 3519 SUNXI_FUNCTION(0x1, "gpio_out"),
3520 SUNXI_FUNCTION(0x2, "ts1"), /* D2 */ 3520 SUNXI_FUNCTION(0x2, "ts1"), /* D2 */
3521 SUNXI_FUNCTION(0x3, "csi1"), /* D2 */ 3521 SUNXI_FUNCTION(0x3, "csi1"), /* D2 */
3522 SUNXI_FUNCTION(0x4, "uart3"), /* TX */ 3522 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
3523 SUNXI_FUNCTION(0x5, "csi0")), /* D10 */ 3523 SUNXI_FUNCTION(0x5, "csi0")), /* D10 */
3524 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7, 3524 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
3525 SUNXI_FUNCTION(0x0, "gpio_in"), 3525 SUNXI_FUNCTION(0x0, "gpio_in"),
3526 SUNXI_FUNCTION(0x1, "gpio_out"), 3526 SUNXI_FUNCTION(0x1, "gpio_out"),
3527 SUNXI_FUNCTION(0x2, "ts1"), /* D3 */ 3527 SUNXI_FUNCTION(0x2, "ts1"), /* D3 */
3528 SUNXI_FUNCTION(0x3, "csi1"), /* D3 */ 3528 SUNXI_FUNCTION(0x3, "csi1"), /* D3 */
3529 SUNXI_FUNCTION(0x4, "uart3"), /* RX */ 3529 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
3530 SUNXI_FUNCTION(0x5, "csi0")), /* D11 */ 3530 SUNXI_FUNCTION(0x5, "csi0")), /* D11 */
3531 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8, 3531 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
3532 SUNXI_FUNCTION(0x0, "gpio_in"), 3532 SUNXI_FUNCTION(0x0, "gpio_in"),
3533 SUNXI_FUNCTION(0x1, "gpio_out"), 3533 SUNXI_FUNCTION(0x1, "gpio_out"),
3534 SUNXI_FUNCTION(0x2, "ts1"), /* D4 */ 3534 SUNXI_FUNCTION(0x2, "ts1"), /* D4 */
3535 SUNXI_FUNCTION(0x3, "csi1"), /* D4 */ 3535 SUNXI_FUNCTION(0x3, "csi1"), /* D4 */
3536 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ 3536 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
3537 SUNXI_FUNCTION(0x5, "csi0")), /* D12 */ 3537 SUNXI_FUNCTION(0x5, "csi0")), /* D12 */
3538 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9, 3538 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
3539 SUNXI_FUNCTION(0x0, "gpio_in"), 3539 SUNXI_FUNCTION(0x0, "gpio_in"),
3540 SUNXI_FUNCTION(0x1, "gpio_out"), 3540 SUNXI_FUNCTION(0x1, "gpio_out"),
3541 SUNXI_FUNCTION(0x2, "ts1"), /* D5 */ 3541 SUNXI_FUNCTION(0x2, "ts1"), /* D5 */
3542 SUNXI_FUNCTION(0x3, "csi1"), /* D5 */ 3542 SUNXI_FUNCTION(0x3, "csi1"), /* D5 */
3543 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ 3543 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
3544 SUNXI_FUNCTION(0x5, "csi0")), /* D13 */ 3544 SUNXI_FUNCTION(0x5, "csi0")), /* D13 */
3545 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10, 3545 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
3546 SUNXI_FUNCTION(0x0, "gpio_in"), 3546 SUNXI_FUNCTION(0x0, "gpio_in"),
3547 SUNXI_FUNCTION(0x1, "gpio_out"), 3547 SUNXI_FUNCTION(0x1, "gpio_out"),
3548 SUNXI_FUNCTION(0x2, "ts1"), /* D6 */ 3548 SUNXI_FUNCTION(0x2, "ts1"), /* D6 */
3549 SUNXI_FUNCTION(0x3, "csi1"), /* D6 */ 3549 SUNXI_FUNCTION(0x3, "csi1"), /* D6 */
3550 SUNXI_FUNCTION(0x4, "uart4"), /* TX */ 3550 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
3551 SUNXI_FUNCTION(0x5, "csi0")), /* D14 */ 3551 SUNXI_FUNCTION(0x5, "csi0")), /* D14 */
3552 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11, 3552 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
3553 SUNXI_FUNCTION(0x0, "gpio_in"), 3553 SUNXI_FUNCTION(0x0, "gpio_in"),
3554 SUNXI_FUNCTION(0x1, "gpio_out"), 3554 SUNXI_FUNCTION(0x1, "gpio_out"),
3555 SUNXI_FUNCTION(0x2, "ts1"), /* D7 */ 3555 SUNXI_FUNCTION(0x2, "ts1"), /* D7 */
@@ -3557,49 +3557,49 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
3557 SUNXI_FUNCTION(0x4, "uart4"), /* RX */ 3557 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
3558 SUNXI_FUNCTION(0x5, "csi0")), /* D15 */ 3558 SUNXI_FUNCTION(0x5, "csi0")), /* D15 */
3559 /* Hole */ 3559 /* Hole */
3560 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0, 3560 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
3561 SUNXI_FUNCTION(0x0, "gpio_in"), 3561 SUNXI_FUNCTION(0x0, "gpio_in"),
3562 SUNXI_FUNCTION(0x1, "gpio_out"), 3562 SUNXI_FUNCTION(0x1, "gpio_out"),
3563 SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */ 3563 SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */
3564 SUNXI_FUNCTION(0x4, "uart3"), /* TX */ 3564 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
3565 SUNXI_FUNCTION_IRQ(0x6, 0), /* EINT0 */ 3565 SUNXI_FUNCTION_IRQ(0x6, 0), /* EINT0 */
3566 SUNXI_FUNCTION(0x7, "csi1")), /* D0 */ 3566 SUNXI_FUNCTION(0x7, "csi1")), /* D0 */
3567 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1, 3567 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
3568 SUNXI_FUNCTION(0x0, "gpio_in"), 3568 SUNXI_FUNCTION(0x0, "gpio_in"),
3569 SUNXI_FUNCTION(0x1, "gpio_out"), 3569 SUNXI_FUNCTION(0x1, "gpio_out"),
3570 SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */ 3570 SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */
3571 SUNXI_FUNCTION(0x4, "uart3"), /* RX */ 3571 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
3572 SUNXI_FUNCTION_IRQ(0x6, 1), /* EINT1 */ 3572 SUNXI_FUNCTION_IRQ(0x6, 1), /* EINT1 */
3573 SUNXI_FUNCTION(0x7, "csi1")), /* D1 */ 3573 SUNXI_FUNCTION(0x7, "csi1")), /* D1 */
3574 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2, 3574 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
3575 SUNXI_FUNCTION(0x0, "gpio_in"), 3575 SUNXI_FUNCTION(0x0, "gpio_in"),
3576 SUNXI_FUNCTION(0x1, "gpio_out"), 3576 SUNXI_FUNCTION(0x1, "gpio_out"),
3577 SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */ 3577 SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */
3578 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ 3578 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
3579 SUNXI_FUNCTION_IRQ(0x6, 2), /* EINT2 */ 3579 SUNXI_FUNCTION_IRQ(0x6, 2), /* EINT2 */
3580 SUNXI_FUNCTION(0x7, "csi1")), /* D2 */ 3580 SUNXI_FUNCTION(0x7, "csi1")), /* D2 */
3581 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3, 3581 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
3582 SUNXI_FUNCTION(0x0, "gpio_in"), 3582 SUNXI_FUNCTION(0x0, "gpio_in"),
3583 SUNXI_FUNCTION(0x1, "gpio_out"), 3583 SUNXI_FUNCTION(0x1, "gpio_out"),
3584 SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */ 3584 SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */
3585 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ 3585 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
3586 SUNXI_FUNCTION_IRQ(0x6, 3), /* EINT3 */ 3586 SUNXI_FUNCTION_IRQ(0x6, 3), /* EINT3 */
3587 SUNXI_FUNCTION(0x7, "csi1")), /* D3 */ 3587 SUNXI_FUNCTION(0x7, "csi1")), /* D3 */
3588 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4, 3588 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
3589 SUNXI_FUNCTION(0x0, "gpio_in"), 3589 SUNXI_FUNCTION(0x0, "gpio_in"),
3590 SUNXI_FUNCTION(0x1, "gpio_out"), 3590 SUNXI_FUNCTION(0x1, "gpio_out"),
3591 SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */ 3591 SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */
3592 SUNXI_FUNCTION(0x4, "uart4"), /* TX */ 3592 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
3593 SUNXI_FUNCTION_IRQ(0x6, 4), /* EINT4 */ 3593 SUNXI_FUNCTION_IRQ(0x6, 4), /* EINT4 */
3594 SUNXI_FUNCTION(0x7, "csi1")), /* D4 */ 3594 SUNXI_FUNCTION(0x7, "csi1")), /* D4 */
3595 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5, 3595 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
3596 SUNXI_FUNCTION(0x0, "gpio_in"), 3596 SUNXI_FUNCTION(0x0, "gpio_in"),
3597 SUNXI_FUNCTION(0x1, "gpio_out"), 3597 SUNXI_FUNCTION(0x1, "gpio_out"),
3598 SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */ 3598 SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */
3599 SUNXI_FUNCTION(0x4, "uart4"), /* RX */ 3599 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
3600 SUNXI_FUNCTION_IRQ(0x6, 5), /* EINT5 */ 3600 SUNXI_FUNCTION_IRQ(0x6, 5), /* EINT5 */
3601 SUNXI_FUNCTION(0x7, "csi1")), /* D5 */ 3601 SUNXI_FUNCTION(0x7, "csi1")), /* D5 */
3602 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6, 3602 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
3603 SUNXI_FUNCTION(0x0, "gpio_in"), 3603 SUNXI_FUNCTION(0x0, "gpio_in"),
3604 SUNXI_FUNCTION(0x1, "gpio_out"), 3604 SUNXI_FUNCTION(0x1, "gpio_out"),
3605 SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */ 3605 SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */
@@ -3607,7 +3607,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
3607 SUNXI_FUNCTION(0x5, "ms"), /* BS */ 3607 SUNXI_FUNCTION(0x5, "ms"), /* BS */
3608 SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */ 3608 SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */
3609 SUNXI_FUNCTION(0x7, "csi1")), /* D6 */ 3609 SUNXI_FUNCTION(0x7, "csi1")), /* D6 */
3610 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7, 3610 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
3611 SUNXI_FUNCTION(0x0, "gpio_in"), 3611 SUNXI_FUNCTION(0x0, "gpio_in"),
3612 SUNXI_FUNCTION(0x1, "gpio_out"), 3612 SUNXI_FUNCTION(0x1, "gpio_out"),
3613 SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */ 3613 SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */
@@ -3615,7 +3615,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
3615 SUNXI_FUNCTION(0x5, "ms"), /* CLK */ 3615 SUNXI_FUNCTION(0x5, "ms"), /* CLK */
3616 SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */ 3616 SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */
3617 SUNXI_FUNCTION(0x7, "csi1")), /* D7 */ 3617 SUNXI_FUNCTION(0x7, "csi1")), /* D7 */
3618 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8, 3618 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
3619 SUNXI_FUNCTION(0x0, "gpio_in"), 3619 SUNXI_FUNCTION(0x0, "gpio_in"),
3620 SUNXI_FUNCTION(0x1, "gpio_out"), 3620 SUNXI_FUNCTION(0x1, "gpio_out"),
3621 SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */ 3621 SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */
@@ -3624,7 +3624,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
3624 SUNXI_FUNCTION(0x5, "ms"), /* D0 */ 3624 SUNXI_FUNCTION(0x5, "ms"), /* D0 */
3625 SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */ 3625 SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */
3626 SUNXI_FUNCTION(0x7, "csi1")), /* D8 */ 3626 SUNXI_FUNCTION(0x7, "csi1")), /* D8 */
3627 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9, 3627 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
3628 SUNXI_FUNCTION(0x0, "gpio_in"), 3628 SUNXI_FUNCTION(0x0, "gpio_in"),
3629 SUNXI_FUNCTION(0x1, "gpio_out"), 3629 SUNXI_FUNCTION(0x1, "gpio_out"),
3630 SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */ 3630 SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */
@@ -3633,7 +3633,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
3633 SUNXI_FUNCTION(0x5, "ms"), /* D1 */ 3633 SUNXI_FUNCTION(0x5, "ms"), /* D1 */
3634 SUNXI_FUNCTION_IRQ(0x6, 9), /* EINT9 */ 3634 SUNXI_FUNCTION_IRQ(0x6, 9), /* EINT9 */
3635 SUNXI_FUNCTION(0x7, "csi1")), /* D9 */ 3635 SUNXI_FUNCTION(0x7, "csi1")), /* D9 */
3636 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10, 3636 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
3637 SUNXI_FUNCTION(0x0, "gpio_in"), 3637 SUNXI_FUNCTION(0x0, "gpio_in"),
3638 SUNXI_FUNCTION(0x1, "gpio_out"), 3638 SUNXI_FUNCTION(0x1, "gpio_out"),
3639 SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */ 3639 SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */
@@ -3642,7 +3642,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
3642 SUNXI_FUNCTION(0x5, "ms"), /* D2 */ 3642 SUNXI_FUNCTION(0x5, "ms"), /* D2 */
3643 SUNXI_FUNCTION_IRQ(0x6, 10), /* EINT10 */ 3643 SUNXI_FUNCTION_IRQ(0x6, 10), /* EINT10 */
3644 SUNXI_FUNCTION(0x7, "csi1")), /* D10 */ 3644 SUNXI_FUNCTION(0x7, "csi1")), /* D10 */
3645 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11, 3645 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
3646 SUNXI_FUNCTION(0x0, "gpio_in"), 3646 SUNXI_FUNCTION(0x0, "gpio_in"),
3647 SUNXI_FUNCTION(0x1, "gpio_out"), 3647 SUNXI_FUNCTION(0x1, "gpio_out"),
3648 SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */ 3648 SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */
@@ -3651,14 +3651,14 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
3651 SUNXI_FUNCTION(0x5, "ms"), /* D3 */ 3651 SUNXI_FUNCTION(0x5, "ms"), /* D3 */
3652 SUNXI_FUNCTION_IRQ(0x6, 11), /* EINT11 */ 3652 SUNXI_FUNCTION_IRQ(0x6, 11), /* EINT11 */
3653 SUNXI_FUNCTION(0x7, "csi1")), /* D11 */ 3653 SUNXI_FUNCTION(0x7, "csi1")), /* D11 */
3654 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12, 3654 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
3655 SUNXI_FUNCTION(0x0, "gpio_in"), 3655 SUNXI_FUNCTION(0x0, "gpio_in"),
3656 SUNXI_FUNCTION(0x1, "gpio_out"), 3656 SUNXI_FUNCTION(0x1, "gpio_out"),
3657 SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */ 3657 SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */
3658 SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */ 3658 SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */
3659 SUNXI_FUNCTION_IRQ(0x6, 12), /* EINT12 */ 3659 SUNXI_FUNCTION_IRQ(0x6, 12), /* EINT12 */
3660 SUNXI_FUNCTION(0x7, "csi1")), /* D12 */ 3660 SUNXI_FUNCTION(0x7, "csi1")), /* D12 */
3661 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13, 3661 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
3662 SUNXI_FUNCTION(0x0, "gpio_in"), 3662 SUNXI_FUNCTION(0x0, "gpio_in"),
3663 SUNXI_FUNCTION(0x1, "gpio_out"), 3663 SUNXI_FUNCTION(0x1, "gpio_out"),
3664 SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */ 3664 SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */
@@ -3666,7 +3666,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
3666 SUNXI_FUNCTION(0x5, "sim"), /* RST */ 3666 SUNXI_FUNCTION(0x5, "sim"), /* RST */
3667 SUNXI_FUNCTION_IRQ(0x6, 13), /* EINT13 */ 3667 SUNXI_FUNCTION_IRQ(0x6, 13), /* EINT13 */
3668 SUNXI_FUNCTION(0x7, "csi1")), /* D13 */ 3668 SUNXI_FUNCTION(0x7, "csi1")), /* D13 */
3669 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14, 3669 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
3670 SUNXI_FUNCTION(0x0, "gpio_in"), 3670 SUNXI_FUNCTION(0x0, "gpio_in"),
3671 SUNXI_FUNCTION(0x1, "gpio_out"), 3671 SUNXI_FUNCTION(0x1, "gpio_out"),
3672 SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */ 3672 SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */
@@ -3675,7 +3675,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
3675 SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */ 3675 SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */
3676 SUNXI_FUNCTION_IRQ(0x6, 14), /* EINT14 */ 3676 SUNXI_FUNCTION_IRQ(0x6, 14), /* EINT14 */
3677 SUNXI_FUNCTION(0x7, "csi1")), /* D14 */ 3677 SUNXI_FUNCTION(0x7, "csi1")), /* D14 */
3678 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15, 3678 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
3679 SUNXI_FUNCTION(0x0, "gpio_in"), 3679 SUNXI_FUNCTION(0x0, "gpio_in"),
3680 SUNXI_FUNCTION(0x1, "gpio_out"), 3680 SUNXI_FUNCTION(0x1, "gpio_out"),
3681 SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */ 3681 SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */
@@ -3684,7 +3684,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
3684 SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */ 3684 SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */
3685 SUNXI_FUNCTION_IRQ(0x6, 15), /* EINT15 */ 3685 SUNXI_FUNCTION_IRQ(0x6, 15), /* EINT15 */
3686 SUNXI_FUNCTION(0x7, "csi1")), /* D15 */ 3686 SUNXI_FUNCTION(0x7, "csi1")), /* D15 */
3687 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16, 3687 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
3688 SUNXI_FUNCTION(0x0, "gpio_in"), 3688 SUNXI_FUNCTION(0x0, "gpio_in"),
3689 SUNXI_FUNCTION(0x1, "gpio_out"), 3689 SUNXI_FUNCTION(0x1, "gpio_out"),
3690 SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */ 3690 SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */
@@ -3692,7 +3692,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
3692 SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */ 3692 SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */
3693 SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */ 3693 SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */
3694 SUNXI_FUNCTION(0x7, "csi1")), /* D16 */ 3694 SUNXI_FUNCTION(0x7, "csi1")), /* D16 */
3695 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17, 3695 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
3696 SUNXI_FUNCTION(0x0, "gpio_in"), 3696 SUNXI_FUNCTION(0x0, "gpio_in"),
3697 SUNXI_FUNCTION(0x1, "gpio_out"), 3697 SUNXI_FUNCTION(0x1, "gpio_out"),
3698 SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */ 3698 SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */
@@ -3701,7 +3701,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
3701 SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */ 3701 SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */
3702 SUNXI_FUNCTION_IRQ(0x6, 17), /* EINT17 */ 3702 SUNXI_FUNCTION_IRQ(0x6, 17), /* EINT17 */
3703 SUNXI_FUNCTION(0x7, "csi1")), /* D17 */ 3703 SUNXI_FUNCTION(0x7, "csi1")), /* D17 */
3704 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18, 3704 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
3705 SUNXI_FUNCTION(0x0, "gpio_in"), 3705 SUNXI_FUNCTION(0x0, "gpio_in"),
3706 SUNXI_FUNCTION(0x1, "gpio_out"), 3706 SUNXI_FUNCTION(0x1, "gpio_out"),
3707 SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */ 3707 SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */
@@ -3710,7 +3710,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
3710 SUNXI_FUNCTION(0x5, "sim"), /* SCK */ 3710 SUNXI_FUNCTION(0x5, "sim"), /* SCK */
3711 SUNXI_FUNCTION_IRQ(0x6, 18), /* EINT18 */ 3711 SUNXI_FUNCTION_IRQ(0x6, 18), /* EINT18 */
3712 SUNXI_FUNCTION(0x7, "csi1")), /* D18 */ 3712 SUNXI_FUNCTION(0x7, "csi1")), /* D18 */
3713 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19, 3713 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
3714 SUNXI_FUNCTION(0x0, "gpio_in"), 3714 SUNXI_FUNCTION(0x0, "gpio_in"),
3715 SUNXI_FUNCTION(0x1, "gpio_out"), 3715 SUNXI_FUNCTION(0x1, "gpio_out"),
3716 SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */ 3716 SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */
@@ -3719,7 +3719,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
3719 SUNXI_FUNCTION(0x5, "sim"), /* SDA */ 3719 SUNXI_FUNCTION(0x5, "sim"), /* SDA */
3720 SUNXI_FUNCTION_IRQ(0x6, 19), /* EINT19 */ 3720 SUNXI_FUNCTION_IRQ(0x6, 19), /* EINT19 */
3721 SUNXI_FUNCTION(0x7, "csi1")), /* D19 */ 3721 SUNXI_FUNCTION(0x7, "csi1")), /* D19 */
3722 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20, 3722 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
3723 SUNXI_FUNCTION(0x0, "gpio_in"), 3723 SUNXI_FUNCTION(0x0, "gpio_in"),
3724 SUNXI_FUNCTION(0x1, "gpio_out"), 3724 SUNXI_FUNCTION(0x1, "gpio_out"),
3725 SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */ 3725 SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */
@@ -3727,7 +3727,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
3727 SUNXI_FUNCTION(0x4, "can"), /* TX */ 3727 SUNXI_FUNCTION(0x4, "can"), /* TX */
3728 SUNXI_FUNCTION_IRQ(0x6, 20), /* EINT20 */ 3728 SUNXI_FUNCTION_IRQ(0x6, 20), /* EINT20 */
3729 SUNXI_FUNCTION(0x7, "csi1")), /* D20 */ 3729 SUNXI_FUNCTION(0x7, "csi1")), /* D20 */
3730 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21, 3730 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
3731 SUNXI_FUNCTION(0x0, "gpio_in"), 3731 SUNXI_FUNCTION(0x0, "gpio_in"),
3732 SUNXI_FUNCTION(0x1, "gpio_out"), 3732 SUNXI_FUNCTION(0x1, "gpio_out"),
3733 SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */ 3733 SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */
@@ -3735,7 +3735,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
3735 SUNXI_FUNCTION(0x4, "can"), /* RX */ 3735 SUNXI_FUNCTION(0x4, "can"), /* RX */
3736 SUNXI_FUNCTION_IRQ(0x6, 21), /* EINT21 */ 3736 SUNXI_FUNCTION_IRQ(0x6, 21), /* EINT21 */
3737 SUNXI_FUNCTION(0x7, "csi1")), /* D21 */ 3737 SUNXI_FUNCTION(0x7, "csi1")), /* D21 */
3738 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22, 3738 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22),
3739 SUNXI_FUNCTION(0x0, "gpio_in"), 3739 SUNXI_FUNCTION(0x0, "gpio_in"),
3740 SUNXI_FUNCTION(0x1, "gpio_out"), 3740 SUNXI_FUNCTION(0x1, "gpio_out"),
3741 SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */ 3741 SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */
@@ -3743,7 +3743,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
3743 SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */ 3743 SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */
3744 SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */ 3744 SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */
3745 SUNXI_FUNCTION(0x7, "csi1")), /* D22 */ 3745 SUNXI_FUNCTION(0x7, "csi1")), /* D22 */
3746 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23, 3746 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23),
3747 SUNXI_FUNCTION(0x0, "gpio_in"), 3747 SUNXI_FUNCTION(0x0, "gpio_in"),
3748 SUNXI_FUNCTION(0x1, "gpio_out"), 3748 SUNXI_FUNCTION(0x1, "gpio_out"),
3749 SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */ 3749 SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */
@@ -3751,7 +3751,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
3751 SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */ 3751 SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */
3752 SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */ 3752 SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */
3753 SUNXI_FUNCTION(0x7, "csi1")), /* D23 */ 3753 SUNXI_FUNCTION(0x7, "csi1")), /* D23 */
3754 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24, 3754 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24),
3755 SUNXI_FUNCTION(0x0, "gpio_in"), 3755 SUNXI_FUNCTION(0x0, "gpio_in"),
3756 SUNXI_FUNCTION(0x1, "gpio_out"), 3756 SUNXI_FUNCTION(0x1, "gpio_out"),
3757 SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */ 3757 SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */
@@ -3759,7 +3759,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
3759 SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */ 3759 SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */
3760 SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */ 3760 SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */
3761 SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */ 3761 SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */
3762 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25, 3762 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25),
3763 SUNXI_FUNCTION(0x0, "gpio_in"), 3763 SUNXI_FUNCTION(0x0, "gpio_in"),
3764 SUNXI_FUNCTION(0x1, "gpio_out"), 3764 SUNXI_FUNCTION(0x1, "gpio_out"),
3765 SUNXI_FUNCTION(0x2, "lcd1"), /* DE */ 3765 SUNXI_FUNCTION(0x2, "lcd1"), /* DE */
@@ -3767,7 +3767,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
3767 SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */ 3767 SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */
3768 SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */ 3768 SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */
3769 SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */ 3769 SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */
3770 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26, 3770 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26),
3771 SUNXI_FUNCTION(0x0, "gpio_in"), 3771 SUNXI_FUNCTION(0x0, "gpio_in"),
3772 SUNXI_FUNCTION(0x1, "gpio_out"), 3772 SUNXI_FUNCTION(0x1, "gpio_out"),
3773 SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */ 3773 SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */
@@ -3775,7 +3775,7 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
3775 SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */ 3775 SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */
3776 SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */ 3776 SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */
3777 SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */ 3777 SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */
3778 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27, 3778 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27),
3779 SUNXI_FUNCTION(0x0, "gpio_in"), 3779 SUNXI_FUNCTION(0x0, "gpio_in"),
3780 SUNXI_FUNCTION(0x1, "gpio_out"), 3780 SUNXI_FUNCTION(0x1, "gpio_out"),
3781 SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */ 3781 SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */
@@ -3784,118 +3784,118 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
3784 SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */ 3784 SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */
3785 SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */ 3785 SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */
3786 /* Hole */ 3786 /* Hole */
3787 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0, 3787 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 0),
3788 SUNXI_FUNCTION(0x0, "gpio_in"), 3788 SUNXI_FUNCTION(0x0, "gpio_in"),
3789 SUNXI_FUNCTION(0x1, "gpio_out"), 3789 SUNXI_FUNCTION(0x1, "gpio_out"),
3790 SUNXI_FUNCTION(0x3, "i2c3")), /* SCK */ 3790 SUNXI_FUNCTION(0x3, "i2c3")), /* SCK */
3791 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI1, 3791 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 1),
3792 SUNXI_FUNCTION(0x0, "gpio_in"), 3792 SUNXI_FUNCTION(0x0, "gpio_in"),
3793 SUNXI_FUNCTION(0x1, "gpio_out"), 3793 SUNXI_FUNCTION(0x1, "gpio_out"),
3794 SUNXI_FUNCTION(0x3, "i2c3")), /* SDA */ 3794 SUNXI_FUNCTION(0x3, "i2c3")), /* SDA */
3795 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI2, 3795 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 2),
3796 SUNXI_FUNCTION(0x0, "gpio_in"), 3796 SUNXI_FUNCTION(0x0, "gpio_in"),
3797 SUNXI_FUNCTION(0x1, "gpio_out"), 3797 SUNXI_FUNCTION(0x1, "gpio_out"),
3798 SUNXI_FUNCTION(0x3, "i2c4")), /* SCK */ 3798 SUNXI_FUNCTION(0x3, "i2c4")), /* SCK */
3799 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3, 3799 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 3),
3800 SUNXI_FUNCTION(0x0, "gpio_in"), 3800 SUNXI_FUNCTION(0x0, "gpio_in"),
3801 SUNXI_FUNCTION(0x1, "gpio_out"), 3801 SUNXI_FUNCTION(0x1, "gpio_out"),
3802 SUNXI_FUNCTION(0x2, "pwm"), /* PWM1 */ 3802 SUNXI_FUNCTION(0x2, "pwm"), /* PWM1 */
3803 SUNXI_FUNCTION(0x3, "i2c4")), /* SDA */ 3803 SUNXI_FUNCTION(0x3, "i2c4")), /* SDA */
3804 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4, 3804 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 4),
3805 SUNXI_FUNCTION(0x0, "gpio_in"), 3805 SUNXI_FUNCTION(0x0, "gpio_in"),
3806 SUNXI_FUNCTION(0x1, "gpio_out"), 3806 SUNXI_FUNCTION(0x1, "gpio_out"),
3807 SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */ 3807 SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */
3808 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5, 3808 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 5),
3809 SUNXI_FUNCTION(0x0, "gpio_in"), 3809 SUNXI_FUNCTION(0x0, "gpio_in"),
3810 SUNXI_FUNCTION(0x1, "gpio_out"), 3810 SUNXI_FUNCTION(0x1, "gpio_out"),
3811 SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */ 3811 SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */
3812 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6, 3812 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 6),
3813 SUNXI_FUNCTION(0x0, "gpio_in"), 3813 SUNXI_FUNCTION(0x0, "gpio_in"),
3814 SUNXI_FUNCTION(0x1, "gpio_out"), 3814 SUNXI_FUNCTION(0x1, "gpio_out"),
3815 SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */ 3815 SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */
3816 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7, 3816 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 7),
3817 SUNXI_FUNCTION(0x0, "gpio_in"), 3817 SUNXI_FUNCTION(0x0, "gpio_in"),
3818 SUNXI_FUNCTION(0x1, "gpio_out"), 3818 SUNXI_FUNCTION(0x1, "gpio_out"),
3819 SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */ 3819 SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */
3820 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8, 3820 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 8),
3821 SUNXI_FUNCTION(0x0, "gpio_in"), 3821 SUNXI_FUNCTION(0x0, "gpio_in"),
3822 SUNXI_FUNCTION(0x1, "gpio_out"), 3822 SUNXI_FUNCTION(0x1, "gpio_out"),
3823 SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */ 3823 SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */
3824 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9, 3824 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 9),
3825 SUNXI_FUNCTION(0x0, "gpio_in"), 3825 SUNXI_FUNCTION(0x0, "gpio_in"),
3826 SUNXI_FUNCTION(0x1, "gpio_out"), 3826 SUNXI_FUNCTION(0x1, "gpio_out"),
3827 SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */ 3827 SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */
3828 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10, 3828 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 10),
3829 SUNXI_FUNCTION(0x0, "gpio_in"), 3829 SUNXI_FUNCTION(0x0, "gpio_in"),
3830 SUNXI_FUNCTION(0x1, "gpio_out"), 3830 SUNXI_FUNCTION(0x1, "gpio_out"),
3831 SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */ 3831 SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
3832 SUNXI_FUNCTION(0x3, "uart5"), /* TX */ 3832 SUNXI_FUNCTION(0x3, "uart5"), /* TX */
3833 SUNXI_FUNCTION_IRQ(0x5, 22)), /* EINT22 */ 3833 SUNXI_FUNCTION_IRQ(0x5, 22)), /* EINT22 */
3834 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11, 3834 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11),
3835 SUNXI_FUNCTION(0x0, "gpio_in"), 3835 SUNXI_FUNCTION(0x0, "gpio_in"),
3836 SUNXI_FUNCTION(0x1, "gpio_out"), 3836 SUNXI_FUNCTION(0x1, "gpio_out"),
3837 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */ 3837 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
3838 SUNXI_FUNCTION(0x3, "uart5"), /* RX */ 3838 SUNXI_FUNCTION(0x3, "uart5"), /* RX */
3839 SUNXI_FUNCTION_IRQ(0x5, 23)), /* EINT23 */ 3839 SUNXI_FUNCTION_IRQ(0x5, 23)), /* EINT23 */
3840 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12, 3840 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12),
3841 SUNXI_FUNCTION(0x0, "gpio_in"), 3841 SUNXI_FUNCTION(0x0, "gpio_in"),
3842 SUNXI_FUNCTION(0x1, "gpio_out"), 3842 SUNXI_FUNCTION(0x1, "gpio_out"),
3843 SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */ 3843 SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
3844 SUNXI_FUNCTION(0x3, "uart6"), /* TX */ 3844 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
3845 SUNXI_FUNCTION(0x4, "clk_out_a"), /* CLK_OUT_A */ 3845 SUNXI_FUNCTION(0x4, "clk_out_a"), /* CLK_OUT_A */
3846 SUNXI_FUNCTION_IRQ(0x5, 24)), /* EINT24 */ 3846 SUNXI_FUNCTION_IRQ(0x5, 24)), /* EINT24 */
3847 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13, 3847 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
3848 SUNXI_FUNCTION(0x0, "gpio_in"), 3848 SUNXI_FUNCTION(0x0, "gpio_in"),
3849 SUNXI_FUNCTION(0x1, "gpio_out"), 3849 SUNXI_FUNCTION(0x1, "gpio_out"),
3850 SUNXI_FUNCTION(0x2, "spi0"), /* MISO */ 3850 SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
3851 SUNXI_FUNCTION(0x3, "uart6"), /* RX */ 3851 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
3852 SUNXI_FUNCTION(0x4, "clk_out_b"), /* CLK_OUT_B */ 3852 SUNXI_FUNCTION(0x4, "clk_out_b"), /* CLK_OUT_B */
3853 SUNXI_FUNCTION_IRQ(0x5, 25)), /* EINT25 */ 3853 SUNXI_FUNCTION_IRQ(0x5, 25)), /* EINT25 */
3854 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14, 3854 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
3855 SUNXI_FUNCTION(0x0, "gpio_in"), 3855 SUNXI_FUNCTION(0x0, "gpio_in"),
3856 SUNXI_FUNCTION(0x1, "gpio_out"), 3856 SUNXI_FUNCTION(0x1, "gpio_out"),
3857 SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */ 3857 SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
3858 SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */ 3858 SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
3859 SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */ 3859 SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */
3860 SUNXI_FUNCTION_IRQ(0x5, 26)), /* EINT26 */ 3860 SUNXI_FUNCTION_IRQ(0x5, 26)), /* EINT26 */
3861 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15, 3861 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15),
3862 SUNXI_FUNCTION(0x0, "gpio_in"), 3862 SUNXI_FUNCTION(0x0, "gpio_in"),
3863 SUNXI_FUNCTION(0x1, "gpio_out"), 3863 SUNXI_FUNCTION(0x1, "gpio_out"),
3864 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ 3864 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
3865 SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */ 3865 SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
3866 SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */ 3866 SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */
3867 SUNXI_FUNCTION_IRQ(0x5, 27)), /* EINT27 */ 3867 SUNXI_FUNCTION_IRQ(0x5, 27)), /* EINT27 */
3868 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16, 3868 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16),
3869 SUNXI_FUNCTION(0x0, "gpio_in"), 3869 SUNXI_FUNCTION(0x0, "gpio_in"),
3870 SUNXI_FUNCTION(0x1, "gpio_out"), 3870 SUNXI_FUNCTION(0x1, "gpio_out"),
3871 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ 3871 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
3872 SUNXI_FUNCTION(0x3, "uart2"), /* RTS */ 3872 SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
3873 SUNXI_FUNCTION_IRQ(0x5, 28)), /* EINT28 */ 3873 SUNXI_FUNCTION_IRQ(0x5, 28)), /* EINT28 */
3874 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17, 3874 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 17),
3875 SUNXI_FUNCTION(0x0, "gpio_in"), 3875 SUNXI_FUNCTION(0x0, "gpio_in"),
3876 SUNXI_FUNCTION(0x1, "gpio_out"), 3876 SUNXI_FUNCTION(0x1, "gpio_out"),
3877 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ 3877 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
3878 SUNXI_FUNCTION(0x3, "uart2"), /* CTS */ 3878 SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
3879 SUNXI_FUNCTION_IRQ(0x5, 29)), /* EINT29 */ 3879 SUNXI_FUNCTION_IRQ(0x5, 29)), /* EINT29 */
3880 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18, 3880 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18),
3881 SUNXI_FUNCTION(0x0, "gpio_in"), 3881 SUNXI_FUNCTION(0x0, "gpio_in"),
3882 SUNXI_FUNCTION(0x1, "gpio_out"), 3882 SUNXI_FUNCTION(0x1, "gpio_out"),
3883 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ 3883 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
3884 SUNXI_FUNCTION(0x3, "uart2"), /* TX */ 3884 SUNXI_FUNCTION(0x3, "uart2"), /* TX */
3885 SUNXI_FUNCTION_IRQ(0x5, 30)), /* EINT30 */ 3885 SUNXI_FUNCTION_IRQ(0x5, 30)), /* EINT30 */
3886 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19, 3886 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19),
3887 SUNXI_FUNCTION(0x0, "gpio_in"), 3887 SUNXI_FUNCTION(0x0, "gpio_in"),
3888 SUNXI_FUNCTION(0x1, "gpio_out"), 3888 SUNXI_FUNCTION(0x1, "gpio_out"),
3889 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ 3889 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
3890 SUNXI_FUNCTION(0x3, "uart2"), /* RX */ 3890 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
3891 SUNXI_FUNCTION_IRQ(0x5, 31)), /* EINT31 */ 3891 SUNXI_FUNCTION_IRQ(0x5, 31)), /* EINT31 */
3892 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20, 3892 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 20),
3893 SUNXI_FUNCTION(0x0, "gpio_in"), 3893 SUNXI_FUNCTION(0x0, "gpio_in"),
3894 SUNXI_FUNCTION(0x1, "gpio_out"), 3894 SUNXI_FUNCTION(0x1, "gpio_out"),
3895 SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */ 3895 SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */
3896 SUNXI_FUNCTION(0x3, "uart7"), /* TX */ 3896 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
3897 SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */ 3897 SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */
3898 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21, 3898 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 21),
3899 SUNXI_FUNCTION(0x0, "gpio_in"), 3899 SUNXI_FUNCTION(0x0, "gpio_in"),
3900 SUNXI_FUNCTION(0x1, "gpio_out"), 3900 SUNXI_FUNCTION(0x1, "gpio_out"),
3901 SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */ 3901 SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
index 4e24b9b5f12e..9775a5003b01 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
@@ -28,368 +28,8 @@
28#define PL_BASE 352 28#define PL_BASE 352
29#define PM_BASE 384 29#define PM_BASE 384
30 30
31#define SUNXI_PINCTRL_PIN_PA0 PINCTRL_PIN(PA_BASE + 0, "PA0") 31#define SUNXI_PINCTRL_PIN(bank, pin) \
32#define SUNXI_PINCTRL_PIN_PA1 PINCTRL_PIN(PA_BASE + 1, "PA1") 32 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
33#define SUNXI_PINCTRL_PIN_PA2 PINCTRL_PIN(PA_BASE + 2, "PA2")
34#define SUNXI_PINCTRL_PIN_PA3 PINCTRL_PIN(PA_BASE + 3, "PA3")
35#define SUNXI_PINCTRL_PIN_PA4 PINCTRL_PIN(PA_BASE + 4, "PA4")
36#define SUNXI_PINCTRL_PIN_PA5 PINCTRL_PIN(PA_BASE + 5, "PA5")
37#define SUNXI_PINCTRL_PIN_PA6 PINCTRL_PIN(PA_BASE + 6, "PA6")
38#define SUNXI_PINCTRL_PIN_PA7 PINCTRL_PIN(PA_BASE + 7, "PA7")
39#define SUNXI_PINCTRL_PIN_PA8 PINCTRL_PIN(PA_BASE + 8, "PA8")
40#define SUNXI_PINCTRL_PIN_PA9 PINCTRL_PIN(PA_BASE + 9, "PA9")
41#define SUNXI_PINCTRL_PIN_PA10 PINCTRL_PIN(PA_BASE + 10, "PA10")
42#define SUNXI_PINCTRL_PIN_PA11 PINCTRL_PIN(PA_BASE + 11, "PA11")
43#define SUNXI_PINCTRL_PIN_PA12 PINCTRL_PIN(PA_BASE + 12, "PA12")
44#define SUNXI_PINCTRL_PIN_PA13 PINCTRL_PIN(PA_BASE + 13, "PA13")
45#define SUNXI_PINCTRL_PIN_PA14 PINCTRL_PIN(PA_BASE + 14, "PA14")
46#define SUNXI_PINCTRL_PIN_PA15 PINCTRL_PIN(PA_BASE + 15, "PA15")
47#define SUNXI_PINCTRL_PIN_PA16 PINCTRL_PIN(PA_BASE + 16, "PA16")
48#define SUNXI_PINCTRL_PIN_PA17 PINCTRL_PIN(PA_BASE + 17, "PA17")
49#define SUNXI_PINCTRL_PIN_PA18 PINCTRL_PIN(PA_BASE + 18, "PA18")
50#define SUNXI_PINCTRL_PIN_PA19 PINCTRL_PIN(PA_BASE + 19, "PA19")
51#define SUNXI_PINCTRL_PIN_PA20 PINCTRL_PIN(PA_BASE + 20, "PA20")
52#define SUNXI_PINCTRL_PIN_PA21 PINCTRL_PIN(PA_BASE + 21, "PA21")
53#define SUNXI_PINCTRL_PIN_PA22 PINCTRL_PIN(PA_BASE + 22, "PA22")
54#define SUNXI_PINCTRL_PIN_PA23 PINCTRL_PIN(PA_BASE + 23, "PA23")
55#define SUNXI_PINCTRL_PIN_PA24 PINCTRL_PIN(PA_BASE + 24, "PA24")
56#define SUNXI_PINCTRL_PIN_PA25 PINCTRL_PIN(PA_BASE + 25, "PA25")
57#define SUNXI_PINCTRL_PIN_PA26 PINCTRL_PIN(PA_BASE + 26, "PA26")
58#define SUNXI_PINCTRL_PIN_PA27 PINCTRL_PIN(PA_BASE + 27, "PA27")
59#define SUNXI_PINCTRL_PIN_PA28 PINCTRL_PIN(PA_BASE + 28, "PA28")
60#define SUNXI_PINCTRL_PIN_PA29 PINCTRL_PIN(PA_BASE + 29, "PA29")
61#define SUNXI_PINCTRL_PIN_PA30 PINCTRL_PIN(PA_BASE + 30, "PA30")
62#define SUNXI_PINCTRL_PIN_PA31 PINCTRL_PIN(PA_BASE + 31, "PA31")
63
64#define SUNXI_PINCTRL_PIN_PB0 PINCTRL_PIN(PB_BASE + 0, "PB0")
65#define SUNXI_PINCTRL_PIN_PB1 PINCTRL_PIN(PB_BASE + 1, "PB1")
66#define SUNXI_PINCTRL_PIN_PB2 PINCTRL_PIN(PB_BASE + 2, "PB2")
67#define SUNXI_PINCTRL_PIN_PB3 PINCTRL_PIN(PB_BASE + 3, "PB3")
68#define SUNXI_PINCTRL_PIN_PB4 PINCTRL_PIN(PB_BASE + 4, "PB4")
69#define SUNXI_PINCTRL_PIN_PB5 PINCTRL_PIN(PB_BASE + 5, "PB5")
70#define SUNXI_PINCTRL_PIN_PB6 PINCTRL_PIN(PB_BASE + 6, "PB6")
71#define SUNXI_PINCTRL_PIN_PB7 PINCTRL_PIN(PB_BASE + 7, "PB7")
72#define SUNXI_PINCTRL_PIN_PB8 PINCTRL_PIN(PB_BASE + 8, "PB8")
73#define SUNXI_PINCTRL_PIN_PB9 PINCTRL_PIN(PB_BASE + 9, "PB9")
74#define SUNXI_PINCTRL_PIN_PB10 PINCTRL_PIN(PB_BASE + 10, "PB10")
75#define SUNXI_PINCTRL_PIN_PB11 PINCTRL_PIN(PB_BASE + 11, "PB11")
76#define SUNXI_PINCTRL_PIN_PB12 PINCTRL_PIN(PB_BASE + 12, "PB12")
77#define SUNXI_PINCTRL_PIN_PB13 PINCTRL_PIN(PB_BASE + 13, "PB13")
78#define SUNXI_PINCTRL_PIN_PB14 PINCTRL_PIN(PB_BASE + 14, "PB14")
79#define SUNXI_PINCTRL_PIN_PB15 PINCTRL_PIN(PB_BASE + 15, "PB15")
80#define SUNXI_PINCTRL_PIN_PB16 PINCTRL_PIN(PB_BASE + 16, "PB16")
81#define SUNXI_PINCTRL_PIN_PB17 PINCTRL_PIN(PB_BASE + 17, "PB17")
82#define SUNXI_PINCTRL_PIN_PB18 PINCTRL_PIN(PB_BASE + 18, "PB18")
83#define SUNXI_PINCTRL_PIN_PB19 PINCTRL_PIN(PB_BASE + 19, "PB19")
84#define SUNXI_PINCTRL_PIN_PB20 PINCTRL_PIN(PB_BASE + 20, "PB20")
85#define SUNXI_PINCTRL_PIN_PB21 PINCTRL_PIN(PB_BASE + 21, "PB21")
86#define SUNXI_PINCTRL_PIN_PB22 PINCTRL_PIN(PB_BASE + 22, "PB22")
87#define SUNXI_PINCTRL_PIN_PB23 PINCTRL_PIN(PB_BASE + 23, "PB23")
88#define SUNXI_PINCTRL_PIN_PB24 PINCTRL_PIN(PB_BASE + 24, "PB24")
89#define SUNXI_PINCTRL_PIN_PB25 PINCTRL_PIN(PB_BASE + 25, "PB25")
90#define SUNXI_PINCTRL_PIN_PB26 PINCTRL_PIN(PB_BASE + 26, "PB26")
91#define SUNXI_PINCTRL_PIN_PB27 PINCTRL_PIN(PB_BASE + 27, "PB27")
92#define SUNXI_PINCTRL_PIN_PB28 PINCTRL_PIN(PB_BASE + 28, "PB28")
93#define SUNXI_PINCTRL_PIN_PB29 PINCTRL_PIN(PB_BASE + 29, "PB29")
94#define SUNXI_PINCTRL_PIN_PB30 PINCTRL_PIN(PB_BASE + 30, "PB30")
95#define SUNXI_PINCTRL_PIN_PB31 PINCTRL_PIN(PB_BASE + 31, "PB31")
96
97#define SUNXI_PINCTRL_PIN_PC0 PINCTRL_PIN(PC_BASE + 0, "PC0")
98#define SUNXI_PINCTRL_PIN_PC1 PINCTRL_PIN(PC_BASE + 1, "PC1")
99#define SUNXI_PINCTRL_PIN_PC2 PINCTRL_PIN(PC_BASE + 2, "PC2")
100#define SUNXI_PINCTRL_PIN_PC3 PINCTRL_PIN(PC_BASE + 3, "PC3")
101#define SUNXI_PINCTRL_PIN_PC4 PINCTRL_PIN(PC_BASE + 4, "PC4")
102#define SUNXI_PINCTRL_PIN_PC5 PINCTRL_PIN(PC_BASE + 5, "PC5")
103#define SUNXI_PINCTRL_PIN_PC6 PINCTRL_PIN(PC_BASE + 6, "PC6")
104#define SUNXI_PINCTRL_PIN_PC7 PINCTRL_PIN(PC_BASE + 7, "PC7")
105#define SUNXI_PINCTRL_PIN_PC8 PINCTRL_PIN(PC_BASE + 8, "PC8")
106#define SUNXI_PINCTRL_PIN_PC9 PINCTRL_PIN(PC_BASE + 9, "PC9")
107#define SUNXI_PINCTRL_PIN_PC10 PINCTRL_PIN(PC_BASE + 10, "PC10")
108#define SUNXI_PINCTRL_PIN_PC11 PINCTRL_PIN(PC_BASE + 11, "PC11")
109#define SUNXI_PINCTRL_PIN_PC12 PINCTRL_PIN(PC_BASE + 12, "PC12")
110#define SUNXI_PINCTRL_PIN_PC13 PINCTRL_PIN(PC_BASE + 13, "PC13")
111#define SUNXI_PINCTRL_PIN_PC14 PINCTRL_PIN(PC_BASE + 14, "PC14")
112#define SUNXI_PINCTRL_PIN_PC15 PINCTRL_PIN(PC_BASE + 15, "PC15")
113#define SUNXI_PINCTRL_PIN_PC16 PINCTRL_PIN(PC_BASE + 16, "PC16")
114#define SUNXI_PINCTRL_PIN_PC17 PINCTRL_PIN(PC_BASE + 17, "PC17")
115#define SUNXI_PINCTRL_PIN_PC18 PINCTRL_PIN(PC_BASE + 18, "PC18")
116#define SUNXI_PINCTRL_PIN_PC19 PINCTRL_PIN(PC_BASE + 19, "PC19")
117#define SUNXI_PINCTRL_PIN_PC20 PINCTRL_PIN(PC_BASE + 20, "PC20")
118#define SUNXI_PINCTRL_PIN_PC21 PINCTRL_PIN(PC_BASE + 21, "PC21")
119#define SUNXI_PINCTRL_PIN_PC22 PINCTRL_PIN(PC_BASE + 22, "PC22")
120#define SUNXI_PINCTRL_PIN_PC23 PINCTRL_PIN(PC_BASE + 23, "PC23")
121#define SUNXI_PINCTRL_PIN_PC24 PINCTRL_PIN(PC_BASE + 24, "PC24")
122#define SUNXI_PINCTRL_PIN_PC25 PINCTRL_PIN(PC_BASE + 25, "PC25")
123#define SUNXI_PINCTRL_PIN_PC26 PINCTRL_PIN(PC_BASE + 26, "PC26")
124#define SUNXI_PINCTRL_PIN_PC27 PINCTRL_PIN(PC_BASE + 27, "PC27")
125#define SUNXI_PINCTRL_PIN_PC28 PINCTRL_PIN(PC_BASE + 28, "PC28")
126#define SUNXI_PINCTRL_PIN_PC29 PINCTRL_PIN(PC_BASE + 29, "PC29")
127#define SUNXI_PINCTRL_PIN_PC30 PINCTRL_PIN(PC_BASE + 30, "PC30")
128#define SUNXI_PINCTRL_PIN_PC31 PINCTRL_PIN(PC_BASE + 31, "PC31")
129
130#define SUNXI_PINCTRL_PIN_PD0 PINCTRL_PIN(PD_BASE + 0, "PD0")
131#define SUNXI_PINCTRL_PIN_PD1 PINCTRL_PIN(PD_BASE + 1, "PD1")
132#define SUNXI_PINCTRL_PIN_PD2 PINCTRL_PIN(PD_BASE + 2, "PD2")
133#define SUNXI_PINCTRL_PIN_PD3 PINCTRL_PIN(PD_BASE + 3, "PD3")
134#define SUNXI_PINCTRL_PIN_PD4 PINCTRL_PIN(PD_BASE + 4, "PD4")
135#define SUNXI_PINCTRL_PIN_PD5 PINCTRL_PIN(PD_BASE + 5, "PD5")
136#define SUNXI_PINCTRL_PIN_PD6 PINCTRL_PIN(PD_BASE + 6, "PD6")
137#define SUNXI_PINCTRL_PIN_PD7 PINCTRL_PIN(PD_BASE + 7, "PD7")
138#define SUNXI_PINCTRL_PIN_PD8 PINCTRL_PIN(PD_BASE + 8, "PD8")
139#define SUNXI_PINCTRL_PIN_PD9 PINCTRL_PIN(PD_BASE + 9, "PD9")
140#define SUNXI_PINCTRL_PIN_PD10 PINCTRL_PIN(PD_BASE + 10, "PD10")
141#define SUNXI_PINCTRL_PIN_PD11 PINCTRL_PIN(PD_BASE + 11, "PD11")
142#define SUNXI_PINCTRL_PIN_PD12 PINCTRL_PIN(PD_BASE + 12, "PD12")
143#define SUNXI_PINCTRL_PIN_PD13 PINCTRL_PIN(PD_BASE + 13, "PD13")
144#define SUNXI_PINCTRL_PIN_PD14 PINCTRL_PIN(PD_BASE + 14, "PD14")
145#define SUNXI_PINCTRL_PIN_PD15 PINCTRL_PIN(PD_BASE + 15, "PD15")
146#define SUNXI_PINCTRL_PIN_PD16 PINCTRL_PIN(PD_BASE + 16, "PD16")
147#define SUNXI_PINCTRL_PIN_PD17 PINCTRL_PIN(PD_BASE + 17, "PD17")
148#define SUNXI_PINCTRL_PIN_PD18 PINCTRL_PIN(PD_BASE + 18, "PD18")
149#define SUNXI_PINCTRL_PIN_PD19 PINCTRL_PIN(PD_BASE + 19, "PD19")
150#define SUNXI_PINCTRL_PIN_PD20 PINCTRL_PIN(PD_BASE + 20, "PD20")
151#define SUNXI_PINCTRL_PIN_PD21 PINCTRL_PIN(PD_BASE + 21, "PD21")
152#define SUNXI_PINCTRL_PIN_PD22 PINCTRL_PIN(PD_BASE + 22, "PD22")
153#define SUNXI_PINCTRL_PIN_PD23 PINCTRL_PIN(PD_BASE + 23, "PD23")
154#define SUNXI_PINCTRL_PIN_PD24 PINCTRL_PIN(PD_BASE + 24, "PD24")
155#define SUNXI_PINCTRL_PIN_PD25 PINCTRL_PIN(PD_BASE + 25, "PD25")
156#define SUNXI_PINCTRL_PIN_PD26 PINCTRL_PIN(PD_BASE + 26, "PD26")
157#define SUNXI_PINCTRL_PIN_PD27 PINCTRL_PIN(PD_BASE + 27, "PD27")
158#define SUNXI_PINCTRL_PIN_PD28 PINCTRL_PIN(PD_BASE + 28, "PD28")
159#define SUNXI_PINCTRL_PIN_PD29 PINCTRL_PIN(PD_BASE + 29, "PD29")
160#define SUNXI_PINCTRL_PIN_PD30 PINCTRL_PIN(PD_BASE + 30, "PD30")
161#define SUNXI_PINCTRL_PIN_PD31 PINCTRL_PIN(PD_BASE + 31, "PD31")
162
163#define SUNXI_PINCTRL_PIN_PE0 PINCTRL_PIN(PE_BASE + 0, "PE0")
164#define SUNXI_PINCTRL_PIN_PE1 PINCTRL_PIN(PE_BASE + 1, "PE1")
165#define SUNXI_PINCTRL_PIN_PE2 PINCTRL_PIN(PE_BASE + 2, "PE2")
166#define SUNXI_PINCTRL_PIN_PE3 PINCTRL_PIN(PE_BASE + 3, "PE3")
167#define SUNXI_PINCTRL_PIN_PE4 PINCTRL_PIN(PE_BASE + 4, "PE4")
168#define SUNXI_PINCTRL_PIN_PE5 PINCTRL_PIN(PE_BASE + 5, "PE5")
169#define SUNXI_PINCTRL_PIN_PE6 PINCTRL_PIN(PE_BASE + 6, "PE6")
170#define SUNXI_PINCTRL_PIN_PE7 PINCTRL_PIN(PE_BASE + 7, "PE7")
171#define SUNXI_PINCTRL_PIN_PE8 PINCTRL_PIN(PE_BASE + 8, "PE8")
172#define SUNXI_PINCTRL_PIN_PE9 PINCTRL_PIN(PE_BASE + 9, "PE9")
173#define SUNXI_PINCTRL_PIN_PE10 PINCTRL_PIN(PE_BASE + 10, "PE10")
174#define SUNXI_PINCTRL_PIN_PE11 PINCTRL_PIN(PE_BASE + 11, "PE11")
175#define SUNXI_PINCTRL_PIN_PE12 PINCTRL_PIN(PE_BASE + 12, "PE12")
176#define SUNXI_PINCTRL_PIN_PE13 PINCTRL_PIN(PE_BASE + 13, "PE13")
177#define SUNXI_PINCTRL_PIN_PE14 PINCTRL_PIN(PE_BASE + 14, "PE14")
178#define SUNXI_PINCTRL_PIN_PE15 PINCTRL_PIN(PE_BASE + 15, "PE15")
179#define SUNXI_PINCTRL_PIN_PE16 PINCTRL_PIN(PE_BASE + 16, "PE16")
180#define SUNXI_PINCTRL_PIN_PE17 PINCTRL_PIN(PE_BASE + 17, "PE17")
181#define SUNXI_PINCTRL_PIN_PE18 PINCTRL_PIN(PE_BASE + 18, "PE18")
182#define SUNXI_PINCTRL_PIN_PE19 PINCTRL_PIN(PE_BASE + 19, "PE19")
183#define SUNXI_PINCTRL_PIN_PE20 PINCTRL_PIN(PE_BASE + 20, "PE20")
184#define SUNXI_PINCTRL_PIN_PE21 PINCTRL_PIN(PE_BASE + 21, "PE21")
185#define SUNXI_PINCTRL_PIN_PE22 PINCTRL_PIN(PE_BASE + 22, "PE22")
186#define SUNXI_PINCTRL_PIN_PE23 PINCTRL_PIN(PE_BASE + 23, "PE23")
187#define SUNXI_PINCTRL_PIN_PE24 PINCTRL_PIN(PE_BASE + 24, "PE24")
188#define SUNXI_PINCTRL_PIN_PE25 PINCTRL_PIN(PE_BASE + 25, "PE25")
189#define SUNXI_PINCTRL_PIN_PE26 PINCTRL_PIN(PE_BASE + 26, "PE26")
190#define SUNXI_PINCTRL_PIN_PE27 PINCTRL_PIN(PE_BASE + 27, "PE27")
191#define SUNXI_PINCTRL_PIN_PE28 PINCTRL_PIN(PE_BASE + 28, "PE28")
192#define SUNXI_PINCTRL_PIN_PE29 PINCTRL_PIN(PE_BASE + 29, "PE29")
193#define SUNXI_PINCTRL_PIN_PE30 PINCTRL_PIN(PE_BASE + 30, "PE30")
194#define SUNXI_PINCTRL_PIN_PE31 PINCTRL_PIN(PE_BASE + 31, "PE31")
195
196#define SUNXI_PINCTRL_PIN_PF0 PINCTRL_PIN(PF_BASE + 0, "PF0")
197#define SUNXI_PINCTRL_PIN_PF1 PINCTRL_PIN(PF_BASE + 1, "PF1")
198#define SUNXI_PINCTRL_PIN_PF2 PINCTRL_PIN(PF_BASE + 2, "PF2")
199#define SUNXI_PINCTRL_PIN_PF3 PINCTRL_PIN(PF_BASE + 3, "PF3")
200#define SUNXI_PINCTRL_PIN_PF4 PINCTRL_PIN(PF_BASE + 4, "PF4")
201#define SUNXI_PINCTRL_PIN_PF5 PINCTRL_PIN(PF_BASE + 5, "PF5")
202#define SUNXI_PINCTRL_PIN_PF6 PINCTRL_PIN(PF_BASE + 6, "PF6")
203#define SUNXI_PINCTRL_PIN_PF7 PINCTRL_PIN(PF_BASE + 7, "PF7")
204#define SUNXI_PINCTRL_PIN_PF8 PINCTRL_PIN(PF_BASE + 8, "PF8")
205#define SUNXI_PINCTRL_PIN_PF9 PINCTRL_PIN(PF_BASE + 9, "PF9")
206#define SUNXI_PINCTRL_PIN_PF10 PINCTRL_PIN(PF_BASE + 10, "PF10")
207#define SUNXI_PINCTRL_PIN_PF11 PINCTRL_PIN(PF_BASE + 11, "PF11")
208#define SUNXI_PINCTRL_PIN_PF12 PINCTRL_PIN(PF_BASE + 12, "PF12")
209#define SUNXI_PINCTRL_PIN_PF13 PINCTRL_PIN(PF_BASE + 13, "PF13")
210#define SUNXI_PINCTRL_PIN_PF14 PINCTRL_PIN(PF_BASE + 14, "PF14")
211#define SUNXI_PINCTRL_PIN_PF15 PINCTRL_PIN(PF_BASE + 15, "PF15")
212#define SUNXI_PINCTRL_PIN_PF16 PINCTRL_PIN(PF_BASE + 16, "PF16")
213#define SUNXI_PINCTRL_PIN_PF17 PINCTRL_PIN(PF_BASE + 17, "PF17")
214#define SUNXI_PINCTRL_PIN_PF18 PINCTRL_PIN(PF_BASE + 18, "PF18")
215#define SUNXI_PINCTRL_PIN_PF19 PINCTRL_PIN(PF_BASE + 19, "PF19")
216#define SUNXI_PINCTRL_PIN_PF20 PINCTRL_PIN(PF_BASE + 20, "PF20")
217#define SUNXI_PINCTRL_PIN_PF21 PINCTRL_PIN(PF_BASE + 21, "PF21")
218#define SUNXI_PINCTRL_PIN_PF22 PINCTRL_PIN(PF_BASE + 22, "PF22")
219#define SUNXI_PINCTRL_PIN_PF23 PINCTRL_PIN(PF_BASE + 23, "PF23")
220#define SUNXI_PINCTRL_PIN_PF24 PINCTRL_PIN(PF_BASE + 24, "PF24")
221#define SUNXI_PINCTRL_PIN_PF25 PINCTRL_PIN(PF_BASE + 25, "PF25")
222#define SUNXI_PINCTRL_PIN_PF26 PINCTRL_PIN(PF_BASE + 26, "PF26")
223#define SUNXI_PINCTRL_PIN_PF27 PINCTRL_PIN(PF_BASE + 27, "PF27")
224#define SUNXI_PINCTRL_PIN_PF28 PINCTRL_PIN(PF_BASE + 28, "PF28")
225#define SUNXI_PINCTRL_PIN_PF29 PINCTRL_PIN(PF_BASE + 29, "PF29")
226#define SUNXI_PINCTRL_PIN_PF30 PINCTRL_PIN(PF_BASE + 30, "PF30")
227#define SUNXI_PINCTRL_PIN_PF31 PINCTRL_PIN(PF_BASE + 31, "PF31")
228
229#define SUNXI_PINCTRL_PIN_PG0 PINCTRL_PIN(PG_BASE + 0, "PG0")
230#define SUNXI_PINCTRL_PIN_PG1 PINCTRL_PIN(PG_BASE + 1, "PG1")
231#define SUNXI_PINCTRL_PIN_PG2 PINCTRL_PIN(PG_BASE + 2, "PG2")
232#define SUNXI_PINCTRL_PIN_PG3 PINCTRL_PIN(PG_BASE + 3, "PG3")
233#define SUNXI_PINCTRL_PIN_PG4 PINCTRL_PIN(PG_BASE + 4, "PG4")
234#define SUNXI_PINCTRL_PIN_PG5 PINCTRL_PIN(PG_BASE + 5, "PG5")
235#define SUNXI_PINCTRL_PIN_PG6 PINCTRL_PIN(PG_BASE + 6, "PG6")
236#define SUNXI_PINCTRL_PIN_PG7 PINCTRL_PIN(PG_BASE + 7, "PG7")
237#define SUNXI_PINCTRL_PIN_PG8 PINCTRL_PIN(PG_BASE + 8, "PG8")
238#define SUNXI_PINCTRL_PIN_PG9 PINCTRL_PIN(PG_BASE + 9, "PG9")
239#define SUNXI_PINCTRL_PIN_PG10 PINCTRL_PIN(PG_BASE + 10, "PG10")
240#define SUNXI_PINCTRL_PIN_PG11 PINCTRL_PIN(PG_BASE + 11, "PG11")
241#define SUNXI_PINCTRL_PIN_PG12 PINCTRL_PIN(PG_BASE + 12, "PG12")
242#define SUNXI_PINCTRL_PIN_PG13 PINCTRL_PIN(PG_BASE + 13, "PG13")
243#define SUNXI_PINCTRL_PIN_PG14 PINCTRL_PIN(PG_BASE + 14, "PG14")
244#define SUNXI_PINCTRL_PIN_PG15 PINCTRL_PIN(PG_BASE + 15, "PG15")
245#define SUNXI_PINCTRL_PIN_PG16 PINCTRL_PIN(PG_BASE + 16, "PG16")
246#define SUNXI_PINCTRL_PIN_PG17 PINCTRL_PIN(PG_BASE + 17, "PG17")
247#define SUNXI_PINCTRL_PIN_PG18 PINCTRL_PIN(PG_BASE + 18, "PG18")
248#define SUNXI_PINCTRL_PIN_PG19 PINCTRL_PIN(PG_BASE + 19, "PG19")
249#define SUNXI_PINCTRL_PIN_PG20 PINCTRL_PIN(PG_BASE + 20, "PG20")
250#define SUNXI_PINCTRL_PIN_PG21 PINCTRL_PIN(PG_BASE + 21, "PG21")
251#define SUNXI_PINCTRL_PIN_PG22 PINCTRL_PIN(PG_BASE + 22, "PG22")
252#define SUNXI_PINCTRL_PIN_PG23 PINCTRL_PIN(PG_BASE + 23, "PG23")
253#define SUNXI_PINCTRL_PIN_PG24 PINCTRL_PIN(PG_BASE + 24, "PG24")
254#define SUNXI_PINCTRL_PIN_PG25 PINCTRL_PIN(PG_BASE + 25, "PG25")
255#define SUNXI_PINCTRL_PIN_PG26 PINCTRL_PIN(PG_BASE + 26, "PG26")
256#define SUNXI_PINCTRL_PIN_PG27 PINCTRL_PIN(PG_BASE + 27, "PG27")
257#define SUNXI_PINCTRL_PIN_PG28 PINCTRL_PIN(PG_BASE + 28, "PG28")
258#define SUNXI_PINCTRL_PIN_PG29 PINCTRL_PIN(PG_BASE + 29, "PG29")
259#define SUNXI_PINCTRL_PIN_PG30 PINCTRL_PIN(PG_BASE + 30, "PG30")
260#define SUNXI_PINCTRL_PIN_PG31 PINCTRL_PIN(PG_BASE + 31, "PG31")
261
262#define SUNXI_PINCTRL_PIN_PH0 PINCTRL_PIN(PH_BASE + 0, "PH0")
263#define SUNXI_PINCTRL_PIN_PH1 PINCTRL_PIN(PH_BASE + 1, "PH1")
264#define SUNXI_PINCTRL_PIN_PH2 PINCTRL_PIN(PH_BASE + 2, "PH2")
265#define SUNXI_PINCTRL_PIN_PH3 PINCTRL_PIN(PH_BASE + 3, "PH3")
266#define SUNXI_PINCTRL_PIN_PH4 PINCTRL_PIN(PH_BASE + 4, "PH4")
267#define SUNXI_PINCTRL_PIN_PH5 PINCTRL_PIN(PH_BASE + 5, "PH5")
268#define SUNXI_PINCTRL_PIN_PH6 PINCTRL_PIN(PH_BASE + 6, "PH6")
269#define SUNXI_PINCTRL_PIN_PH7 PINCTRL_PIN(PH_BASE + 7, "PH7")
270#define SUNXI_PINCTRL_PIN_PH8 PINCTRL_PIN(PH_BASE + 8, "PH8")
271#define SUNXI_PINCTRL_PIN_PH9 PINCTRL_PIN(PH_BASE + 9, "PH9")
272#define SUNXI_PINCTRL_PIN_PH10 PINCTRL_PIN(PH_BASE + 10, "PH10")
273#define SUNXI_PINCTRL_PIN_PH11 PINCTRL_PIN(PH_BASE + 11, "PH11")
274#define SUNXI_PINCTRL_PIN_PH12 PINCTRL_PIN(PH_BASE + 12, "PH12")
275#define SUNXI_PINCTRL_PIN_PH13 PINCTRL_PIN(PH_BASE + 13, "PH13")
276#define SUNXI_PINCTRL_PIN_PH14 PINCTRL_PIN(PH_BASE + 14, "PH14")
277#define SUNXI_PINCTRL_PIN_PH15 PINCTRL_PIN(PH_BASE + 15, "PH15")
278#define SUNXI_PINCTRL_PIN_PH16 PINCTRL_PIN(PH_BASE + 16, "PH16")
279#define SUNXI_PINCTRL_PIN_PH17 PINCTRL_PIN(PH_BASE + 17, "PH17")
280#define SUNXI_PINCTRL_PIN_PH18 PINCTRL_PIN(PH_BASE + 18, "PH18")
281#define SUNXI_PINCTRL_PIN_PH19 PINCTRL_PIN(PH_BASE + 19, "PH19")
282#define SUNXI_PINCTRL_PIN_PH20 PINCTRL_PIN(PH_BASE + 20, "PH20")
283#define SUNXI_PINCTRL_PIN_PH21 PINCTRL_PIN(PH_BASE + 21, "PH21")
284#define SUNXI_PINCTRL_PIN_PH22 PINCTRL_PIN(PH_BASE + 22, "PH22")
285#define SUNXI_PINCTRL_PIN_PH23 PINCTRL_PIN(PH_BASE + 23, "PH23")
286#define SUNXI_PINCTRL_PIN_PH24 PINCTRL_PIN(PH_BASE + 24, "PH24")
287#define SUNXI_PINCTRL_PIN_PH25 PINCTRL_PIN(PH_BASE + 25, "PH25")
288#define SUNXI_PINCTRL_PIN_PH26 PINCTRL_PIN(PH_BASE + 26, "PH26")
289#define SUNXI_PINCTRL_PIN_PH27 PINCTRL_PIN(PH_BASE + 27, "PH27")
290#define SUNXI_PINCTRL_PIN_PH28 PINCTRL_PIN(PH_BASE + 28, "PH28")
291#define SUNXI_PINCTRL_PIN_PH29 PINCTRL_PIN(PH_BASE + 29, "PH29")
292#define SUNXI_PINCTRL_PIN_PH30 PINCTRL_PIN(PH_BASE + 30, "PH30")
293#define SUNXI_PINCTRL_PIN_PH31 PINCTRL_PIN(PH_BASE + 31, "PH31")
294
295#define SUNXI_PINCTRL_PIN_PI0 PINCTRL_PIN(PI_BASE + 0, "PI0")
296#define SUNXI_PINCTRL_PIN_PI1 PINCTRL_PIN(PI_BASE + 1, "PI1")
297#define SUNXI_PINCTRL_PIN_PI2 PINCTRL_PIN(PI_BASE + 2, "PI2")
298#define SUNXI_PINCTRL_PIN_PI3 PINCTRL_PIN(PI_BASE + 3, "PI3")
299#define SUNXI_PINCTRL_PIN_PI4 PINCTRL_PIN(PI_BASE + 4, "PI4")
300#define SUNXI_PINCTRL_PIN_PI5 PINCTRL_PIN(PI_BASE + 5, "PI5")
301#define SUNXI_PINCTRL_PIN_PI6 PINCTRL_PIN(PI_BASE + 6, "PI6")
302#define SUNXI_PINCTRL_PIN_PI7 PINCTRL_PIN(PI_BASE + 7, "PI7")
303#define SUNXI_PINCTRL_PIN_PI8 PINCTRL_PIN(PI_BASE + 8, "PI8")
304#define SUNXI_PINCTRL_PIN_PI9 PINCTRL_PIN(PI_BASE + 9, "PI9")
305#define SUNXI_PINCTRL_PIN_PI10 PINCTRL_PIN(PI_BASE + 10, "PI10")
306#define SUNXI_PINCTRL_PIN_PI11 PINCTRL_PIN(PI_BASE + 11, "PI11")
307#define SUNXI_PINCTRL_PIN_PI12 PINCTRL_PIN(PI_BASE + 12, "PI12")
308#define SUNXI_PINCTRL_PIN_PI13 PINCTRL_PIN(PI_BASE + 13, "PI13")
309#define SUNXI_PINCTRL_PIN_PI14 PINCTRL_PIN(PI_BASE + 14, "PI14")
310#define SUNXI_PINCTRL_PIN_PI15 PINCTRL_PIN(PI_BASE + 15, "PI15")
311#define SUNXI_PINCTRL_PIN_PI16 PINCTRL_PIN(PI_BASE + 16, "PI16")
312#define SUNXI_PINCTRL_PIN_PI17 PINCTRL_PIN(PI_BASE + 17, "PI17")
313#define SUNXI_PINCTRL_PIN_PI18 PINCTRL_PIN(PI_BASE + 18, "PI18")
314#define SUNXI_PINCTRL_PIN_PI19 PINCTRL_PIN(PI_BASE + 19, "PI19")
315#define SUNXI_PINCTRL_PIN_PI20 PINCTRL_PIN(PI_BASE + 20, "PI20")
316#define SUNXI_PINCTRL_PIN_PI21 PINCTRL_PIN(PI_BASE + 21, "PI21")
317#define SUNXI_PINCTRL_PIN_PI22 PINCTRL_PIN(PI_BASE + 22, "PI22")
318#define SUNXI_PINCTRL_PIN_PI23 PINCTRL_PIN(PI_BASE + 23, "PI23")
319#define SUNXI_PINCTRL_PIN_PI24 PINCTRL_PIN(PI_BASE + 24, "PI24")
320#define SUNXI_PINCTRL_PIN_PI25 PINCTRL_PIN(PI_BASE + 25, "PI25")
321#define SUNXI_PINCTRL_PIN_PI26 PINCTRL_PIN(PI_BASE + 26, "PI26")
322#define SUNXI_PINCTRL_PIN_PI27 PINCTRL_PIN(PI_BASE + 27, "PI27")
323#define SUNXI_PINCTRL_PIN_PI28 PINCTRL_PIN(PI_BASE + 28, "PI28")
324#define SUNXI_PINCTRL_PIN_PI29 PINCTRL_PIN(PI_BASE + 29, "PI29")
325#define SUNXI_PINCTRL_PIN_PI30 PINCTRL_PIN(PI_BASE + 30, "PI30")
326#define SUNXI_PINCTRL_PIN_PI31 PINCTRL_PIN(PI_BASE + 31, "PI31")
327
328#define SUNXI_PINCTRL_PIN_PL0 PINCTRL_PIN(PL_BASE + 0, "PL0")
329#define SUNXI_PINCTRL_PIN_PL1 PINCTRL_PIN(PL_BASE + 1, "PL1")
330#define SUNXI_PINCTRL_PIN_PL2 PINCTRL_PIN(PL_BASE + 2, "PL2")
331#define SUNXI_PINCTRL_PIN_PL3 PINCTRL_PIN(PL_BASE + 3, "PL3")
332#define SUNXI_PINCTRL_PIN_PL4 PINCTRL_PIN(PL_BASE + 4, "PL4")
333#define SUNXI_PINCTRL_PIN_PL5 PINCTRL_PIN(PL_BASE + 5, "PL5")
334#define SUNXI_PINCTRL_PIN_PL6 PINCTRL_PIN(PL_BASE + 6, "PL6")
335#define SUNXI_PINCTRL_PIN_PL7 PINCTRL_PIN(PL_BASE + 7, "PL7")
336#define SUNXI_PINCTRL_PIN_PL8 PINCTRL_PIN(PL_BASE + 8, "PL8")
337#define SUNXI_PINCTRL_PIN_PL9 PINCTRL_PIN(PL_BASE + 9, "PL9")
338#define SUNXI_PINCTRL_PIN_PL10 PINCTRL_PIN(PL_BASE + 10, "PL10")
339#define SUNXI_PINCTRL_PIN_PL11 PINCTRL_PIN(PL_BASE + 11, "PL11")
340#define SUNXI_PINCTRL_PIN_PL12 PINCTRL_PIN(PL_BASE + 12, "PL12")
341#define SUNXI_PINCTRL_PIN_PL13 PINCTRL_PIN(PL_BASE + 13, "PL13")
342#define SUNXI_PINCTRL_PIN_PL14 PINCTRL_PIN(PL_BASE + 14, "PL14")
343#define SUNXI_PINCTRL_PIN_PL15 PINCTRL_PIN(PL_BASE + 15, "PL15")
344#define SUNXI_PINCTRL_PIN_PL16 PINCTRL_PIN(PL_BASE + 16, "PL16")
345#define SUNXI_PINCTRL_PIN_PL17 PINCTRL_PIN(PL_BASE + 17, "PL17")
346#define SUNXI_PINCTRL_PIN_PL18 PINCTRL_PIN(PL_BASE + 18, "PL18")
347#define SUNXI_PINCTRL_PIN_PL19 PINCTRL_PIN(PL_BASE + 19, "PL19")
348#define SUNXI_PINCTRL_PIN_PL20 PINCTRL_PIN(PL_BASE + 20, "PL20")
349#define SUNXI_PINCTRL_PIN_PL21 PINCTRL_PIN(PL_BASE + 21, "PL21")
350#define SUNXI_PINCTRL_PIN_PL22 PINCTRL_PIN(PL_BASE + 22, "PL22")
351#define SUNXI_PINCTRL_PIN_PL23 PINCTRL_PIN(PL_BASE + 23, "PL23")
352#define SUNXI_PINCTRL_PIN_PL24 PINCTRL_PIN(PL_BASE + 24, "PL24")
353#define SUNXI_PINCTRL_PIN_PL25 PINCTRL_PIN(PL_BASE + 25, "PL25")
354#define SUNXI_PINCTRL_PIN_PL26 PINCTRL_PIN(PL_BASE + 26, "PL26")
355#define SUNXI_PINCTRL_PIN_PL27 PINCTRL_PIN(PL_BASE + 27, "PL27")
356#define SUNXI_PINCTRL_PIN_PL28 PINCTRL_PIN(PL_BASE + 28, "PL28")
357#define SUNXI_PINCTRL_PIN_PL29 PINCTRL_PIN(PL_BASE + 29, "PL29")
358#define SUNXI_PINCTRL_PIN_PL30 PINCTRL_PIN(PL_BASE + 30, "PL30")
359#define SUNXI_PINCTRL_PIN_PL31 PINCTRL_PIN(PL_BASE + 31, "PL31")
360
361#define SUNXI_PINCTRL_PIN_PM0 PINCTRL_PIN(PM_BASE + 0, "PM0")
362#define SUNXI_PINCTRL_PIN_PM1 PINCTRL_PIN(PM_BASE + 1, "PM1")
363#define SUNXI_PINCTRL_PIN_PM2 PINCTRL_PIN(PM_BASE + 2, "PM2")
364#define SUNXI_PINCTRL_PIN_PM3 PINCTRL_PIN(PM_BASE + 3, "PM3")
365#define SUNXI_PINCTRL_PIN_PM4 PINCTRL_PIN(PM_BASE + 4, "PM4")
366#define SUNXI_PINCTRL_PIN_PM5 PINCTRL_PIN(PM_BASE + 5, "PM5")
367#define SUNXI_PINCTRL_PIN_PM6 PINCTRL_PIN(PM_BASE + 6, "PM6")
368#define SUNXI_PINCTRL_PIN_PM7 PINCTRL_PIN(PM_BASE + 7, "PM7")
369#define SUNXI_PINCTRL_PIN_PM8 PINCTRL_PIN(PM_BASE + 8, "PM8")
370#define SUNXI_PINCTRL_PIN_PM9 PINCTRL_PIN(PM_BASE + 9, "PM9")
371#define SUNXI_PINCTRL_PIN_PM10 PINCTRL_PIN(PM_BASE + 10, "PM10")
372#define SUNXI_PINCTRL_PIN_PM11 PINCTRL_PIN(PM_BASE + 11, "PM11")
373#define SUNXI_PINCTRL_PIN_PM12 PINCTRL_PIN(PM_BASE + 12, "PM12")
374#define SUNXI_PINCTRL_PIN_PM13 PINCTRL_PIN(PM_BASE + 13, "PM13")
375#define SUNXI_PINCTRL_PIN_PM14 PINCTRL_PIN(PM_BASE + 14, "PM14")
376#define SUNXI_PINCTRL_PIN_PM15 PINCTRL_PIN(PM_BASE + 15, "PM15")
377#define SUNXI_PINCTRL_PIN_PM16 PINCTRL_PIN(PM_BASE + 16, "PM16")
378#define SUNXI_PINCTRL_PIN_PM17 PINCTRL_PIN(PM_BASE + 17, "PM17")
379#define SUNXI_PINCTRL_PIN_PM18 PINCTRL_PIN(PM_BASE + 18, "PM18")
380#define SUNXI_PINCTRL_PIN_PM19 PINCTRL_PIN(PM_BASE + 19, "PM19")
381#define SUNXI_PINCTRL_PIN_PM20 PINCTRL_PIN(PM_BASE + 20, "PM20")
382#define SUNXI_PINCTRL_PIN_PM21 PINCTRL_PIN(PM_BASE + 21, "PM21")
383#define SUNXI_PINCTRL_PIN_PM22 PINCTRL_PIN(PM_BASE + 22, "PM22")
384#define SUNXI_PINCTRL_PIN_PM23 PINCTRL_PIN(PM_BASE + 23, "PM23")
385#define SUNXI_PINCTRL_PIN_PM24 PINCTRL_PIN(PM_BASE + 24, "PM24")
386#define SUNXI_PINCTRL_PIN_PM25 PINCTRL_PIN(PM_BASE + 25, "PM25")
387#define SUNXI_PINCTRL_PIN_PM26 PINCTRL_PIN(PM_BASE + 26, "PM26")
388#define SUNXI_PINCTRL_PIN_PM27 PINCTRL_PIN(PM_BASE + 27, "PM27")
389#define SUNXI_PINCTRL_PIN_PM28 PINCTRL_PIN(PM_BASE + 28, "PM28")
390#define SUNXI_PINCTRL_PIN_PM29 PINCTRL_PIN(PM_BASE + 29, "PM29")
391#define SUNXI_PINCTRL_PIN_PM30 PINCTRL_PIN(PM_BASE + 30, "PM30")
392#define SUNXI_PINCTRL_PIN_PM31 PINCTRL_PIN(PM_BASE + 31, "PM31")
393 33
394#define SUNXI_PIN_NAME_MAX_LEN 5 34#define SUNXI_PIN_NAME_MAX_LEN 5
395 35
generated by cgit v1.2.2 (git 2.25.0) at 2026-05-27 20:46:49 -0400