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authorLinus Torvalds <torvalds@linux-foundation.org>2015-02-11 14:23:13 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2015-02-11 14:23:13 -0500
commitce01e871a1d44cc97cdd7e5ba6cb0c3613c15552 (patch)
treef1f3c8a0022d34d3da54700b0e48a1d7be48fe50 /drivers/pinctrl
parenta1df7efedab047a8ea4d5850737f03d3679726a7 (diff)
parentf724e05baaf0677151c339c0249a05876c779a1d (diff)
Merge tag 'pinctrl-v3.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pincontrol updates from Linus Walleij: :This is the bulk of pin control changes for the v3.20 cycle: Framework changes and enhancements: - Passing -DDEBUG recursively to subdir drivers so we get debug messages properly turned on. - Infer map type from DT property in the groups parsing code in the generic pinconfig code. - Support for custom parameter passing in generic pin config. This is used when you are using the generic pin config, but want to add a few custom properties that no other driver will use. New drivers: - Driver for the Xilinx Zynq - Driver for the AmLogic Meson SoCs New features in drivers: - Sleep support (suspend/resume) for the Cherryview driver - mvebeu a38x can now mux a UART on pins MPP19 and MPP20 - Migrated the qualcomm driver to generic pin config handling of extended config options in the core code. - Support BUS1 and AUDIO in the Exynos pin controller. - Add some missing functions in the sun6i driver. - Add support for the A31S variant in the sun6i driver. - EMEv2 support in the Renesas PFC driver. - Add support for Qualcomm MSM8916 in the qcom driver. Deleted features - Drop support for the SiRF Marco that was never released to the market. - Drop SH7372 support as the support for this platform is removed from the kernel" * tag 'pinctrl-v3.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (40 commits) sh-pfc: emev2 - Fix mangled author name pinctrl: cherryview: Configure HiZ pins to be input when requested as GPIOs pinctrl: imx25: fix numbering for pins pinctrl: pinctrl-imx: don't use invalid value of conf_reg pinctrl: qcom: delete pin_config_get/set pinconf operations pinctrl: qcom: Add msm8916 pinctrl driver DT: pinctrl: Document Qualcomm MSM8916 pinctrl binding pinctrl: qcom: increase variable size for register offsets pinctrl: hide PCONFDUMP in #ifdef pinctrl: rockchip: Only mask interrupts; never disable pinctrl: zynq: Fix usb0 pins pinctrl: sh-pfc: sh7372: Remove DT binding documentation pinctrl: sh-pfc: sh7372: Remove PFC support sh-pfc: Add emev2 pinmux support sh-pfc: add macro to define pinmux without function pinctrl: add driver for Amlogic Meson SoCs staging: drivers: pinctrl: Fixed checkpatch.pl warnings pinctrl: exynos: Add AUDIO pin controller for exynos7 sh-pfc: r8a7790: add MLB+ pin group sh-pfc: r8a7791: add MLB+ pin group ...
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/Kconfig18
-rw-r--r--drivers/pinctrl/Makefile4
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx.c2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx25.c276
-rw-r--r--drivers/pinctrl/intel/pinctrl-cherryview.c122
-rw-r--r--drivers/pinctrl/meson/Makefile2
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson.c761
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson.h209
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson8.c1089
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-armada-38x.c6
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-dove.c4
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-abx500.c2
-rw-r--r--drivers/pinctrl/pinconf-generic.c206
-rw-r--r--drivers/pinctrl/pinconf.c4
-rw-r--r--drivers/pinctrl/pinconf.h22
-rw-r--r--drivers/pinctrl/pinctrl-bcm281xx.c4
-rw-r--r--drivers/pinctrl/pinctrl-falcon.c3
-rw-r--r--drivers/pinctrl/pinctrl-rockchip.c50
-rw-r--r--drivers/pinctrl/pinctrl-tz1090-pdc.c2
-rw-r--r--drivers/pinctrl/pinctrl-tz1090.c2
-rw-r--r--drivers/pinctrl/pinctrl-zynq.c1180
-rw-r--r--drivers/pinctrl/qcom/Kconfig8
-rw-r--r--drivers/pinctrl/qcom/Makefile1
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm.c17
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm.h10
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm8916.c1005
-rw-r--r--drivers/pinctrl/qcom/pinctrl-spmi-gpio.c129
-rw-r--r--drivers/pinctrl/samsung/pinctrl-exynos.c29
-rw-r--r--drivers/pinctrl/sh-pfc/Kconfig10
-rw-r--r--drivers/pinctrl/sh-pfc/Makefile2
-rw-r--r--drivers/pinctrl/sh-pfc/core.c18
-rw-r--r--drivers/pinctrl/sh-pfc/core.h2
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-emev2.c1711
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7790.c13
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7791.c21
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7372.c2645
-rw-r--r--drivers/pinctrl/sh-pfc/pinctrl.c2
-rw-r--r--drivers/pinctrl/sh-pfc/sh_pfc.h2
-rw-r--r--drivers/pinctrl/sirf/pinctrl-sirf.c51
-rw-r--r--drivers/pinctrl/sirf/pinctrl-sirf.h1
-rw-r--r--drivers/pinctrl/sunxi/Kconfig4
-rw-r--r--drivers/pinctrl/sunxi/Makefile1
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c5
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c815
44 files changed, 7335 insertions, 3135 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index d014f22f387a..ee9f44ad7f02 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -96,6 +96,14 @@ config PINCTRL_FALCON
96 depends on SOC_FALCON 96 depends on SOC_FALCON
97 depends on PINCTRL_LANTIQ 97 depends on PINCTRL_LANTIQ
98 98
99config PINCTRL_MESON
100 bool
101 select PINMUX
102 select PINCONF
103 select GENERIC_PINCONF
104 select OF_GPIO
105 select REGMAP_MMIO
106
99config PINCTRL_ROCKCHIP 107config PINCTRL_ROCKCHIP
100 bool 108 bool
101 select PINMUX 109 select PINMUX
@@ -113,7 +121,7 @@ config PINCTRL_SINGLE
113 This selects the device tree based generic pinctrl driver. 121 This selects the device tree based generic pinctrl driver.
114 122
115config PINCTRL_SIRF 123config PINCTRL_SIRF
116 bool "CSR SiRFprimaII/SiRFmarco pin controller driver" 124 bool "CSR SiRFprimaII pin controller driver"
117 depends on ARCH_SIRF 125 depends on ARCH_SIRF
118 select PINMUX 126 select PINMUX
119 select GPIOLIB_IRQCHIP 127 select GPIOLIB_IRQCHIP
@@ -191,6 +199,14 @@ config PINCTRL_PALMAS
191 open drain configuration for the Palmas series devices like 199 open drain configuration for the Palmas series devices like
192 TPS65913, TPS80036 etc. 200 TPS65913, TPS80036 etc.
193 201
202config PINCTRL_ZYNQ
203 bool "Pinctrl driver for Xilinx Zynq"
204 depends on ARCH_ZYNQ
205 select PINMUX
206 select GENERIC_PINCONF
207 help
208 This selectes the pinctrl driver for Xilinx Zynq.
209
194source "drivers/pinctrl/berlin/Kconfig" 210source "drivers/pinctrl/berlin/Kconfig"
195source "drivers/pinctrl/freescale/Kconfig" 211source "drivers/pinctrl/freescale/Kconfig"
196source "drivers/pinctrl/intel/Kconfig" 212source "drivers/pinctrl/intel/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index c030b3db8034..0475206dd600 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -1,6 +1,6 @@
1# generic pinmux support 1# generic pinmux support
2 2
3ccflags-$(CONFIG_DEBUG_PINCTRL) += -DDEBUG 3subdir-ccflags-$(CONFIG_DEBUG_PINCTRL) += -DDEBUG
4 4
5obj-$(CONFIG_PINCTRL) += core.o pinctrl-utils.o 5obj-$(CONFIG_PINCTRL) += core.o pinctrl-utils.o
6obj-$(CONFIG_PINMUX) += pinmux.o 6obj-$(CONFIG_PINMUX) += pinmux.o
@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
17obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o 17obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
18obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o 18obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
19obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o 19obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
20obj-$(CONFIG_PINCTRL_MESON) += meson/
20obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o 21obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
21obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o 22obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
22obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o 23obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
@@ -35,6 +36,7 @@ obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
35obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o 36obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
36obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o 37obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o
37obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o 38obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
39obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o
38 40
39obj-$(CONFIG_ARCH_BERLIN) += berlin/ 41obj-$(CONFIG_ARCH_BERLIN) += berlin/
40obj-y += freescale/ 42obj-y += freescale/
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
index 52f2b9404fe0..448f10986c28 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -437,7 +437,7 @@ static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
437 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; 437 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
438 unsigned long config; 438 unsigned long config;
439 439
440 if (!pin_reg || !pin_reg->conf_reg) { 440 if (!pin_reg || pin_reg->conf_reg == -1) {
441 seq_printf(s, "N/A"); 441 seq_printf(s, "N/A");
442 return; 442 return;
443 } 443 }
diff --git a/drivers/pinctrl/freescale/pinctrl-imx25.c b/drivers/pinctrl/freescale/pinctrl-imx25.c
index 8d1013a040c9..faf635654312 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx25.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx25.c
@@ -27,150 +27,148 @@
27 27
28enum imx25_pads { 28enum imx25_pads {
29 MX25_PAD_RESERVE0 = 1, 29 MX25_PAD_RESERVE0 = 1,
30 MX25_PAD_RESERVE1 = 2, 30 MX25_PAD_A10 = 2,
31 MX25_PAD_A10 = 3, 31 MX25_PAD_A13 = 3,
32 MX25_PAD_A13 = 4, 32 MX25_PAD_A14 = 4,
33 MX25_PAD_A14 = 5, 33 MX25_PAD_A15 = 5,
34 MX25_PAD_A15 = 6, 34 MX25_PAD_A16 = 6,
35 MX25_PAD_A16 = 7, 35 MX25_PAD_A17 = 7,
36 MX25_PAD_A17 = 8, 36 MX25_PAD_A18 = 8,
37 MX25_PAD_A18 = 9, 37 MX25_PAD_A19 = 9,
38 MX25_PAD_A19 = 10, 38 MX25_PAD_A20 = 10,
39 MX25_PAD_A20 = 11, 39 MX25_PAD_A21 = 11,
40 MX25_PAD_A21 = 12, 40 MX25_PAD_A22 = 12,
41 MX25_PAD_A22 = 13, 41 MX25_PAD_A23 = 13,
42 MX25_PAD_A23 = 14, 42 MX25_PAD_A24 = 14,
43 MX25_PAD_A24 = 15, 43 MX25_PAD_A25 = 15,
44 MX25_PAD_A25 = 16, 44 MX25_PAD_EB0 = 16,
45 MX25_PAD_EB0 = 17, 45 MX25_PAD_EB1 = 17,
46 MX25_PAD_EB1 = 18, 46 MX25_PAD_OE = 18,
47 MX25_PAD_OE = 19, 47 MX25_PAD_CS0 = 19,
48 MX25_PAD_CS0 = 20, 48 MX25_PAD_CS1 = 20,
49 MX25_PAD_CS1 = 21, 49 MX25_PAD_CS4 = 21,
50 MX25_PAD_CS4 = 22, 50 MX25_PAD_CS5 = 22,
51 MX25_PAD_CS5 = 23, 51 MX25_PAD_NF_CE0 = 23,
52 MX25_PAD_NF_CE0 = 24, 52 MX25_PAD_ECB = 24,
53 MX25_PAD_ECB = 25, 53 MX25_PAD_LBA = 25,
54 MX25_PAD_LBA = 26, 54 MX25_PAD_BCLK = 26,
55 MX25_PAD_BCLK = 27, 55 MX25_PAD_RW = 27,
56 MX25_PAD_RW = 28, 56 MX25_PAD_NFWE_B = 28,
57 MX25_PAD_NFWE_B = 29, 57 MX25_PAD_NFRE_B = 29,
58 MX25_PAD_NFRE_B = 30, 58 MX25_PAD_NFALE = 30,
59 MX25_PAD_NFALE = 31, 59 MX25_PAD_NFCLE = 31,
60 MX25_PAD_NFCLE = 32, 60 MX25_PAD_NFWP_B = 32,
61 MX25_PAD_NFWP_B = 33, 61 MX25_PAD_NFRB = 33,
62 MX25_PAD_NFRB = 34, 62 MX25_PAD_D15 = 34,
63 MX25_PAD_D15 = 35, 63 MX25_PAD_D14 = 35,
64 MX25_PAD_D14 = 36, 64 MX25_PAD_D13 = 36,
65 MX25_PAD_D13 = 37, 65 MX25_PAD_D12 = 37,
66 MX25_PAD_D12 = 38, 66 MX25_PAD_D11 = 38,
67 MX25_PAD_D11 = 39, 67 MX25_PAD_D10 = 39,
68 MX25_PAD_D10 = 40, 68 MX25_PAD_D9 = 40,
69 MX25_PAD_D9 = 41, 69 MX25_PAD_D8 = 41,
70 MX25_PAD_D8 = 42, 70 MX25_PAD_D7 = 42,
71 MX25_PAD_D7 = 43, 71 MX25_PAD_D6 = 43,
72 MX25_PAD_D6 = 44, 72 MX25_PAD_D5 = 44,
73 MX25_PAD_D5 = 45, 73 MX25_PAD_D4 = 45,
74 MX25_PAD_D4 = 46, 74 MX25_PAD_D3 = 46,
75 MX25_PAD_D3 = 47, 75 MX25_PAD_D2 = 47,
76 MX25_PAD_D2 = 48, 76 MX25_PAD_D1 = 48,
77 MX25_PAD_D1 = 49, 77 MX25_PAD_D0 = 49,
78 MX25_PAD_D0 = 50, 78 MX25_PAD_LD0 = 50,
79 MX25_PAD_LD0 = 51, 79 MX25_PAD_LD1 = 51,
80 MX25_PAD_LD1 = 52, 80 MX25_PAD_LD2 = 52,
81 MX25_PAD_LD2 = 53, 81 MX25_PAD_LD3 = 53,
82 MX25_PAD_LD3 = 54, 82 MX25_PAD_LD4 = 54,
83 MX25_PAD_LD4 = 55, 83 MX25_PAD_LD5 = 55,
84 MX25_PAD_LD5 = 56, 84 MX25_PAD_LD6 = 56,
85 MX25_PAD_LD6 = 57, 85 MX25_PAD_LD7 = 57,
86 MX25_PAD_LD7 = 58, 86 MX25_PAD_LD8 = 58,
87 MX25_PAD_LD8 = 59, 87 MX25_PAD_LD9 = 59,
88 MX25_PAD_LD9 = 60, 88 MX25_PAD_LD10 = 60,
89 MX25_PAD_LD10 = 61, 89 MX25_PAD_LD11 = 61,
90 MX25_PAD_LD11 = 62, 90 MX25_PAD_LD12 = 62,
91 MX25_PAD_LD12 = 63, 91 MX25_PAD_LD13 = 63,
92 MX25_PAD_LD13 = 64, 92 MX25_PAD_LD14 = 64,
93 MX25_PAD_LD14 = 65, 93 MX25_PAD_LD15 = 65,
94 MX25_PAD_LD15 = 66, 94 MX25_PAD_HSYNC = 66,
95 MX25_PAD_HSYNC = 67, 95 MX25_PAD_VSYNC = 67,
96 MX25_PAD_VSYNC = 68, 96 MX25_PAD_LSCLK = 68,
97 MX25_PAD_LSCLK = 69, 97 MX25_PAD_OE_ACD = 69,
98 MX25_PAD_OE_ACD = 70, 98 MX25_PAD_CONTRAST = 70,
99 MX25_PAD_CONTRAST = 71, 99 MX25_PAD_PWM = 71,
100 MX25_PAD_PWM = 72, 100 MX25_PAD_CSI_D2 = 72,
101 MX25_PAD_CSI_D2 = 73, 101 MX25_PAD_CSI_D3 = 73,
102 MX25_PAD_CSI_D3 = 74, 102 MX25_PAD_CSI_D4 = 74,
103 MX25_PAD_CSI_D4 = 75, 103 MX25_PAD_CSI_D5 = 75,
104 MX25_PAD_CSI_D5 = 76, 104 MX25_PAD_CSI_D6 = 76,
105 MX25_PAD_CSI_D6 = 77, 105 MX25_PAD_CSI_D7 = 77,
106 MX25_PAD_CSI_D7 = 78, 106 MX25_PAD_CSI_D8 = 78,
107 MX25_PAD_CSI_D8 = 79, 107 MX25_PAD_CSI_D9 = 79,
108 MX25_PAD_CSI_D9 = 80, 108 MX25_PAD_CSI_MCLK = 80,
109 MX25_PAD_CSI_MCLK = 81, 109 MX25_PAD_CSI_VSYNC = 81,
110 MX25_PAD_CSI_VSYNC = 82, 110 MX25_PAD_CSI_HSYNC = 82,
111 MX25_PAD_CSI_HSYNC = 83, 111 MX25_PAD_CSI_PIXCLK = 83,
112 MX25_PAD_CSI_PIXCLK = 84, 112 MX25_PAD_I2C1_CLK = 84,
113 MX25_PAD_I2C1_CLK = 85, 113 MX25_PAD_I2C1_DAT = 85,
114 MX25_PAD_I2C1_DAT = 86, 114 MX25_PAD_CSPI1_MOSI = 86,
115 MX25_PAD_CSPI1_MOSI = 87, 115 MX25_PAD_CSPI1_MISO = 87,
116 MX25_PAD_CSPI1_MISO = 88, 116 MX25_PAD_CSPI1_SS0 = 88,
117 MX25_PAD_CSPI1_SS0 = 89, 117 MX25_PAD_CSPI1_SS1 = 89,
118 MX25_PAD_CSPI1_SS1 = 90, 118 MX25_PAD_CSPI1_SCLK = 90,
119 MX25_PAD_CSPI1_SCLK = 91, 119 MX25_PAD_CSPI1_RDY = 91,
120 MX25_PAD_CSPI1_RDY = 92, 120 MX25_PAD_UART1_RXD = 92,
121 MX25_PAD_UART1_RXD = 93, 121 MX25_PAD_UART1_TXD = 93,
122 MX25_PAD_UART1_TXD = 94, 122 MX25_PAD_UART1_RTS = 94,
123 MX25_PAD_UART1_RTS = 95, 123 MX25_PAD_UART1_CTS = 95,
124 MX25_PAD_UART1_CTS = 96, 124 MX25_PAD_UART2_RXD = 96,
125 MX25_PAD_UART2_RXD = 97, 125 MX25_PAD_UART2_TXD = 97,
126 MX25_PAD_UART2_TXD = 98, 126 MX25_PAD_UART2_RTS = 98,
127 MX25_PAD_UART2_RTS = 99, 127 MX25_PAD_UART2_CTS = 99,
128 MX25_PAD_UART2_CTS = 100, 128 MX25_PAD_SD1_CMD = 100,
129 MX25_PAD_SD1_CMD = 101, 129 MX25_PAD_SD1_CLK = 101,
130 MX25_PAD_SD1_CLK = 102, 130 MX25_PAD_SD1_DATA0 = 102,
131 MX25_PAD_SD1_DATA0 = 103, 131 MX25_PAD_SD1_DATA1 = 103,
132 MX25_PAD_SD1_DATA1 = 104, 132 MX25_PAD_SD1_DATA2 = 104,
133 MX25_PAD_SD1_DATA2 = 105, 133 MX25_PAD_SD1_DATA3 = 105,
134 MX25_PAD_SD1_DATA3 = 106, 134 MX25_PAD_KPP_ROW0 = 106,
135 MX25_PAD_KPP_ROW0 = 107, 135 MX25_PAD_KPP_ROW1 = 107,
136 MX25_PAD_KPP_ROW1 = 108, 136 MX25_PAD_KPP_ROW2 = 108,
137 MX25_PAD_KPP_ROW2 = 109, 137 MX25_PAD_KPP_ROW3 = 109,
138 MX25_PAD_KPP_ROW3 = 110, 138 MX25_PAD_KPP_COL0 = 110,
139 MX25_PAD_KPP_COL0 = 111, 139 MX25_PAD_KPP_COL1 = 111,
140 MX25_PAD_KPP_COL1 = 112, 140 MX25_PAD_KPP_COL2 = 112,
141 MX25_PAD_KPP_COL2 = 113, 141 MX25_PAD_KPP_COL3 = 113,
142 MX25_PAD_KPP_COL3 = 114, 142 MX25_PAD_FEC_MDC = 114,
143 MX25_PAD_FEC_MDC = 115, 143 MX25_PAD_FEC_MDIO = 115,
144 MX25_PAD_FEC_MDIO = 116, 144 MX25_PAD_FEC_TDATA0 = 116,
145 MX25_PAD_FEC_TDATA0 = 117, 145 MX25_PAD_FEC_TDATA1 = 117,
146 MX25_PAD_FEC_TDATA1 = 118, 146 MX25_PAD_FEC_TX_EN = 118,
147 MX25_PAD_FEC_TX_EN = 119, 147 MX25_PAD_FEC_RDATA0 = 119,
148 MX25_PAD_FEC_RDATA0 = 120, 148 MX25_PAD_FEC_RDATA1 = 120,
149 MX25_PAD_FEC_RDATA1 = 121, 149 MX25_PAD_FEC_RX_DV = 121,
150 MX25_PAD_FEC_RX_DV = 122, 150 MX25_PAD_FEC_TX_CLK = 122,
151 MX25_PAD_FEC_TX_CLK = 123, 151 MX25_PAD_RTCK = 123,
152 MX25_PAD_RTCK = 124, 152 MX25_PAD_DE_B = 124,
153 MX25_PAD_DE_B = 125, 153 MX25_PAD_GPIO_A = 125,
154 MX25_PAD_GPIO_A = 126, 154 MX25_PAD_GPIO_B = 126,
155 MX25_PAD_GPIO_B = 127, 155 MX25_PAD_GPIO_C = 127,
156 MX25_PAD_GPIO_C = 128, 156 MX25_PAD_GPIO_D = 128,
157 MX25_PAD_GPIO_D = 129, 157 MX25_PAD_GPIO_E = 129,
158 MX25_PAD_GPIO_E = 130, 158 MX25_PAD_GPIO_F = 130,
159 MX25_PAD_GPIO_F = 131, 159 MX25_PAD_EXT_ARMCLK = 131,
160 MX25_PAD_EXT_ARMCLK = 132, 160 MX25_PAD_UPLL_BYPCLK = 132,
161 MX25_PAD_UPLL_BYPCLK = 133, 161 MX25_PAD_VSTBY_REQ = 133,
162 MX25_PAD_VSTBY_REQ = 134, 162 MX25_PAD_VSTBY_ACK = 134,
163 MX25_PAD_VSTBY_ACK = 135, 163 MX25_PAD_POWER_FAIL = 135,
164 MX25_PAD_POWER_FAIL = 136, 164 MX25_PAD_CLKO = 136,
165 MX25_PAD_CLKO = 137, 165 MX25_PAD_BOOT_MODE0 = 137,
166 MX25_PAD_BOOT_MODE0 = 138, 166 MX25_PAD_BOOT_MODE1 = 138,
167 MX25_PAD_BOOT_MODE1 = 139,
168}; 167};
169 168
170/* Pad names for the pinmux subsystem */ 169/* Pad names for the pinmux subsystem */
171static const struct pinctrl_pin_desc imx25_pinctrl_pads[] = { 170static const struct pinctrl_pin_desc imx25_pinctrl_pads[] = {
172 IMX_PINCTRL_PIN(MX25_PAD_RESERVE0), 171 IMX_PINCTRL_PIN(MX25_PAD_RESERVE0),
173 IMX_PINCTRL_PIN(MX25_PAD_RESERVE1),
174 IMX_PINCTRL_PIN(MX25_PAD_A10), 172 IMX_PINCTRL_PIN(MX25_PAD_A10),
175 IMX_PINCTRL_PIN(MX25_PAD_A13), 173 IMX_PINCTRL_PIN(MX25_PAD_A13),
176 IMX_PINCTRL_PIN(MX25_PAD_A14), 174 IMX_PINCTRL_PIN(MX25_PAD_A14),
diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c
index e9f8b39d1a9f..3034fd03bced 100644
--- a/drivers/pinctrl/intel/pinctrl-cherryview.c
+++ b/drivers/pinctrl/intel/pinctrl-cherryview.c
@@ -148,6 +148,11 @@ struct chv_community {
148 size_t ngpios; 148 size_t ngpios;
149}; 149};
150 150
151struct chv_pin_context {
152 u32 padctrl0;
153 u32 padctrl1;
154};
155
151/** 156/**
152 * struct chv_pinctrl - CHV pinctrl private structure 157 * struct chv_pinctrl - CHV pinctrl private structure
153 * @dev: Pointer to the parent device 158 * @dev: Pointer to the parent device
@@ -172,6 +177,8 @@ struct chv_pinctrl {
172 spinlock_t lock; 177 spinlock_t lock;
173 unsigned intr_lines[16]; 178 unsigned intr_lines[16];
174 const struct chv_community *community; 179 const struct chv_community *community;
180 u32 saved_intmask;
181 struct chv_pin_context *saved_pin_context;
175}; 182};
176 183
177#define gpiochip_to_pinctrl(c) container_of(c, struct chv_pinctrl, chip) 184#define gpiochip_to_pinctrl(c) container_of(c, struct chv_pinctrl, chip)
@@ -873,9 +880,22 @@ static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
873 value &= ~CHV_PADCTRL1_INVRXTX_MASK; 880 value &= ~CHV_PADCTRL1_INVRXTX_MASK;
874 chv_writel(value, reg); 881 chv_writel(value, reg);
875 882
876 /* Switch to a GPIO mode */
877 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 883 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
878 value = readl(reg) | CHV_PADCTRL0_GPIOEN; 884 value = readl(reg);
885
886 /*
887 * If the pin is in HiZ mode (both TX and RX buffers are
888 * disabled) we turn it to be input now.
889 */
890 if ((value & CHV_PADCTRL0_GPIOCFG_MASK) ==
891 (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) {
892 value &= ~CHV_PADCTRL0_GPIOCFG_MASK;
893 value |= CHV_PADCTRL0_GPIOCFG_GPI <<
894 CHV_PADCTRL0_GPIOCFG_SHIFT;
895 }
896
897 /* Switch to a GPIO mode */
898 value |= CHV_PADCTRL0_GPIOEN;
879 chv_writel(value, reg); 899 chv_writel(value, reg);
880 } 900 }
881 901
@@ -1443,6 +1463,14 @@ static int chv_pinctrl_probe(struct platform_device *pdev)
1443 spin_lock_init(&pctrl->lock); 1463 spin_lock_init(&pctrl->lock);
1444 pctrl->dev = &pdev->dev; 1464 pctrl->dev = &pdev->dev;
1445 1465
1466#ifdef CONFIG_PM_SLEEP
1467 pctrl->saved_pin_context = devm_kcalloc(pctrl->dev,
1468 pctrl->community->npins, sizeof(*pctrl->saved_pin_context),
1469 GFP_KERNEL);
1470 if (!pctrl->saved_pin_context)
1471 return -ENOMEM;
1472#endif
1473
1446 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1474 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1447 pctrl->regs = devm_ioremap_resource(&pdev->dev, res); 1475 pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
1448 if (IS_ERR(pctrl->regs)) 1476 if (IS_ERR(pctrl->regs))
@@ -1486,6 +1514,94 @@ static int chv_pinctrl_remove(struct platform_device *pdev)
1486 return 0; 1514 return 0;
1487} 1515}
1488 1516
1517#ifdef CONFIG_PM_SLEEP
1518static int chv_pinctrl_suspend(struct device *dev)
1519{
1520 struct platform_device *pdev = to_platform_device(dev);
1521 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
1522 int i;
1523
1524 pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK);
1525
1526 for (i = 0; i < pctrl->community->npins; i++) {
1527 const struct pinctrl_pin_desc *desc;
1528 struct chv_pin_context *ctx;
1529 void __iomem *reg;
1530
1531 desc = &pctrl->community->pins[i];
1532 if (chv_pad_locked(pctrl, desc->number))
1533 continue;
1534
1535 ctx = &pctrl->saved_pin_context[i];
1536
1537 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
1538 ctx->padctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
1539
1540 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
1541 ctx->padctrl1 = readl(reg);
1542 }
1543
1544 return 0;
1545}
1546
1547static int chv_pinctrl_resume(struct device *dev)
1548{
1549 struct platform_device *pdev = to_platform_device(dev);
1550 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
1551 int i;
1552
1553 /*
1554 * Mask all interrupts before restoring per-pin configuration
1555 * registers because we don't know in which state BIOS left them
1556 * upon exiting suspend.
1557 */
1558 chv_writel(0, pctrl->regs + CHV_INTMASK);
1559
1560 for (i = 0; i < pctrl->community->npins; i++) {
1561 const struct pinctrl_pin_desc *desc;
1562 const struct chv_pin_context *ctx;
1563 void __iomem *reg;
1564 u32 val;
1565
1566 desc = &pctrl->community->pins[i];
1567 if (chv_pad_locked(pctrl, desc->number))
1568 continue;
1569
1570 ctx = &pctrl->saved_pin_context[i];
1571
1572 /* Only restore if our saved state differs from the current */
1573 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
1574 val = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
1575 if (ctx->padctrl0 != val) {
1576 chv_writel(ctx->padctrl0, reg);
1577 dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n",
1578 desc->number, readl(reg));
1579 }
1580
1581 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
1582 val = readl(reg);
1583 if (ctx->padctrl1 != val) {
1584 chv_writel(ctx->padctrl1, reg);
1585 dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n",
1586 desc->number, readl(reg));
1587 }
1588 }
1589
1590 /*
1591 * Now that all pins are restored to known state, we can restore
1592 * the interrupt mask register as well.
1593 */
1594 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
1595 chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK);
1596
1597 return 0;
1598}
1599#endif
1600
1601static const struct dev_pm_ops chv_pinctrl_pm_ops = {
1602 SET_LATE_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend, chv_pinctrl_resume)
1603};
1604
1489static const struct acpi_device_id chv_pinctrl_acpi_match[] = { 1605static const struct acpi_device_id chv_pinctrl_acpi_match[] = {
1490 { "INT33FF" }, 1606 { "INT33FF" },
1491 { } 1607 { }
@@ -1497,7 +1613,7 @@ static struct platform_driver chv_pinctrl_driver = {
1497 .remove = chv_pinctrl_remove, 1613 .remove = chv_pinctrl_remove,
1498 .driver = { 1614 .driver = {
1499 .name = "cherryview-pinctrl", 1615 .name = "cherryview-pinctrl",
1500 .owner = THIS_MODULE, 1616 .pm = &chv_pinctrl_pm_ops,
1501 .acpi_match_table = chv_pinctrl_acpi_match, 1617 .acpi_match_table = chv_pinctrl_acpi_match,
1502 }, 1618 },
1503}; 1619};
diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
new file mode 100644
index 000000000000..eafc216067a4
--- /dev/null
+++ b/drivers/pinctrl/meson/Makefile
@@ -0,0 +1,2 @@
1obj-y += pinctrl-meson8.o
2obj-y += pinctrl-meson.o
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c
new file mode 100644
index 000000000000..a2bf49ce16e7
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -0,0 +1,761 @@
1/*
2 * Pin controller and GPIO driver for Amlogic Meson SoCs
3 *
4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * You should have received a copy of the GNU General Public License
11 * along with this program. If not, see <http://www.gnu.org/licenses/>.
12 */
13
14/*
15 * The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO,
16 * BOOT,CARD for meson6 and X,Y,DV,H,Z,AO,BOOT,CARD for meson8) and
17 * each bank has a variable number of pins.
18 *
19 * The AO bank is special because it belongs to the Always-On power
20 * domain which can't be powered off; the bank also uses a set of
21 * registers different from the other banks.
22 *
23 * For each of the two power domains (regular and always-on) there are
24 * 4 different register ranges that control the following properties
25 * of the pins:
26 * 1) pin muxing
27 * 2) pull enable/disable
28 * 3) pull up/down
29 * 4) GPIO direction, output value, input value
30 *
31 * In some cases the register ranges for pull enable and pull
32 * direction are the same and thus there are only 3 register ranges.
33 *
34 * Every pinmux group can be enabled by a specific bit in the first
35 * register range of the domain; when all groups for a given pin are
36 * disabled the pin acts as a GPIO.
37 *
38 * For the pull and GPIO configuration every bank uses a contiguous
39 * set of bits in the register sets described above; the same register
40 * can be shared by more banks with different offsets.
41 *
42 * In addition to this there are some registers shared between all
43 * banks that control the IRQ functionality. This feature is not
44 * supported at the moment by the driver.
45 */
46
47#include <linux/device.h>
48#include <linux/gpio.h>
49#include <linux/init.h>
50#include <linux/io.h>
51#include <linux/module.h>
52#include <linux/of.h>
53#include <linux/of_address.h>
54#include <linux/pinctrl/pinconf-generic.h>
55#include <linux/pinctrl/pinconf.h>
56#include <linux/pinctrl/pinctrl.h>
57#include <linux/pinctrl/pinmux.h>
58#include <linux/platform_device.h>
59#include <linux/regmap.h>
60#include <linux/seq_file.h>
61
62#include "../core.h"
63#include "../pinctrl-utils.h"
64#include "pinctrl-meson.h"
65
66/**
67 * meson_get_bank() - find the bank containing a given pin
68 *
69 * @domain: the domain containing the pin
70 * @pin: the pin number
71 * @bank: the found bank
72 *
73 * Return: 0 on success, a negative value on error
74 */
75static int meson_get_bank(struct meson_domain *domain, unsigned int pin,
76 struct meson_bank **bank)
77{
78 int i;
79
80 for (i = 0; i < domain->data->num_banks; i++) {
81 if (pin >= domain->data->banks[i].first &&
82 pin <= domain->data->banks[i].last) {
83 *bank = &domain->data->banks[i];
84 return 0;
85 }
86 }
87
88 return -EINVAL;
89}
90
91/**
92 * meson_get_domain_and_bank() - find domain and bank containing a given pin
93 *
94 * @pc: Meson pin controller device
95 * @pin: the pin number
96 * @domain: the found domain
97 * @bank: the found bank
98 *
99 * Return: 0 on success, a negative value on error
100 */
101static int meson_get_domain_and_bank(struct meson_pinctrl *pc, unsigned int pin,
102 struct meson_domain **domain,
103 struct meson_bank **bank)
104{
105 struct meson_domain *d;
106 int i;
107
108 for (i = 0; i < pc->data->num_domains; i++) {
109 d = &pc->domains[i];
110 if (pin >= d->data->pin_base &&
111 pin < d->data->pin_base + d->data->num_pins) {
112 *domain = d;
113 return meson_get_bank(d, pin, bank);
114 }
115 }
116
117 return -EINVAL;
118}
119
120/**
121 * meson_calc_reg_and_bit() - calculate register and bit for a pin
122 *
123 * @bank: the bank containing the pin
124 * @pin: the pin number
125 * @reg_type: the type of register needed (pull-enable, pull, etc...)
126 * @reg: the computed register offset
127 * @bit: the computed bit
128 */
129static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin,
130 enum meson_reg_type reg_type,
131 unsigned int *reg, unsigned int *bit)
132{
133 struct meson_reg_desc *desc = &bank->regs[reg_type];
134
135 *reg = desc->reg * 4;
136 *bit = desc->bit + pin - bank->first;
137}
138
139static int meson_get_groups_count(struct pinctrl_dev *pcdev)
140{
141 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
142
143 return pc->data->num_groups;
144}
145
146static const char *meson_get_group_name(struct pinctrl_dev *pcdev,
147 unsigned selector)
148{
149 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
150
151 return pc->data->groups[selector].name;
152}
153
154static int meson_get_group_pins(struct pinctrl_dev *pcdev, unsigned selector,
155 const unsigned **pins, unsigned *num_pins)
156{
157 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
158
159 *pins = pc->data->groups[selector].pins;
160 *num_pins = pc->data->groups[selector].num_pins;
161
162 return 0;
163}
164
165static void meson_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s,
166 unsigned offset)
167{
168 seq_printf(s, " %s", dev_name(pcdev->dev));
169}
170
171static const struct pinctrl_ops meson_pctrl_ops = {
172 .get_groups_count = meson_get_groups_count,
173 .get_group_name = meson_get_group_name,
174 .get_group_pins = meson_get_group_pins,
175 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
176 .dt_free_map = pinctrl_utils_dt_free_map,
177 .pin_dbg_show = meson_pin_dbg_show,
178};
179
180/**
181 * meson_pmx_disable_other_groups() - disable other groups using a given pin
182 *
183 * @pc: meson pin controller device
184 * @pin: number of the pin
185 * @sel_group: index of the selected group, or -1 if none
186 *
187 * The function disables all pinmux groups using a pin except the
188 * selected one. If @sel_group is -1 all groups are disabled, leaving
189 * the pin in GPIO mode.
190 */
191static void meson_pmx_disable_other_groups(struct meson_pinctrl *pc,
192 unsigned int pin, int sel_group)
193{
194 struct meson_pmx_group *group;
195 struct meson_domain *domain;
196 int i, j;
197
198 for (i = 0; i < pc->data->num_groups; i++) {
199 group = &pc->data->groups[i];
200 if (group->is_gpio || i == sel_group)
201 continue;
202
203 for (j = 0; j < group->num_pins; j++) {
204 if (group->pins[j] == pin) {
205 /* We have found a group using the pin */
206 domain = &pc->domains[group->domain];
207 regmap_update_bits(domain->reg_mux,
208 group->reg * 4,
209 BIT(group->bit), 0);
210 }
211 }
212 }
213}
214
215static int meson_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned func_num,
216 unsigned group_num)
217{
218 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
219 struct meson_pmx_func *func = &pc->data->funcs[func_num];
220 struct meson_pmx_group *group = &pc->data->groups[group_num];
221 struct meson_domain *domain = &pc->domains[group->domain];
222 int i, ret = 0;
223
224 dev_dbg(pc->dev, "enable function %s, group %s\n", func->name,
225 group->name);
226
227 /*
228 * Disable groups using the same pin.
229 * The selected group is not disabled to avoid glitches.
230 */
231 for (i = 0; i < group->num_pins; i++)
232 meson_pmx_disable_other_groups(pc, group->pins[i], group_num);
233
234 /* Function 0 (GPIO) doesn't need any additional setting */
235 if (func_num)
236 ret = regmap_update_bits(domain->reg_mux, group->reg * 4,
237 BIT(group->bit), BIT(group->bit));
238
239 return ret;
240}
241
242static int meson_pmx_request_gpio(struct pinctrl_dev *pcdev,
243 struct pinctrl_gpio_range *range,
244 unsigned offset)
245{
246 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
247
248 meson_pmx_disable_other_groups(pc, range->pin_base + offset, -1);
249
250 return 0;
251}
252
253static int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev)
254{
255 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
256
257 return pc->data->num_funcs;
258}
259
260static const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev,
261 unsigned selector)
262{
263 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
264
265 return pc->data->funcs[selector].name;
266}
267
268static int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector,
269 const char * const **groups,
270 unsigned * const num_groups)
271{
272 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
273
274 *groups = pc->data->funcs[selector].groups;
275 *num_groups = pc->data->funcs[selector].num_groups;
276
277 return 0;
278}
279
280static const struct pinmux_ops meson_pmx_ops = {
281 .set_mux = meson_pmx_set_mux,
282 .get_functions_count = meson_pmx_get_funcs_count,
283 .get_function_name = meson_pmx_get_func_name,
284 .get_function_groups = meson_pmx_get_groups,
285 .gpio_request_enable = meson_pmx_request_gpio,
286};
287
288static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin,
289 unsigned long *configs, unsigned num_configs)
290{
291 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
292 struct meson_domain *domain;
293 struct meson_bank *bank;
294 enum pin_config_param param;
295 unsigned int reg, bit;
296 int i, ret;
297 u16 arg;
298
299 ret = meson_get_domain_and_bank(pc, pin, &domain, &bank);
300 if (ret)
301 return ret;
302
303 for (i = 0; i < num_configs; i++) {
304 param = pinconf_to_config_param(configs[i]);
305 arg = pinconf_to_config_argument(configs[i]);
306
307 switch (param) {
308 case PIN_CONFIG_BIAS_DISABLE:
309 dev_dbg(pc->dev, "pin %u: disable bias\n", pin);
310
311 meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit);
312 ret = regmap_update_bits(domain->reg_pull, reg,
313 BIT(bit), 0);
314 if (ret)
315 return ret;
316 break;
317 case PIN_CONFIG_BIAS_PULL_UP:
318 dev_dbg(pc->dev, "pin %u: enable pull-up\n", pin);
319
320 meson_calc_reg_and_bit(bank, pin, REG_PULLEN,
321 &reg, &bit);
322 ret = regmap_update_bits(domain->reg_pullen, reg,
323 BIT(bit), BIT(bit));
324 if (ret)
325 return ret;
326
327 meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit);
328 ret = regmap_update_bits(domain->reg_pull, reg,
329 BIT(bit), BIT(bit));
330 if (ret)
331 return ret;
332 break;
333 case PIN_CONFIG_BIAS_PULL_DOWN:
334 dev_dbg(pc->dev, "pin %u: enable pull-down\n", pin);
335
336 meson_calc_reg_and_bit(bank, pin, REG_PULLEN,
337 &reg, &bit);
338 ret = regmap_update_bits(domain->reg_pullen, reg,
339 BIT(bit), BIT(bit));
340 if (ret)
341 return ret;
342
343 meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit);
344 ret = regmap_update_bits(domain->reg_pull, reg,
345 BIT(bit), 0);
346 if (ret)
347 return ret;
348 break;
349 default:
350 return -ENOTSUPP;
351 }
352 }
353
354 return 0;
355}
356
357static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin)
358{
359 struct meson_domain *domain;
360 struct meson_bank *bank;
361 unsigned int reg, bit, val;
362 int ret, conf;
363
364 ret = meson_get_domain_and_bank(pc, pin, &domain, &bank);
365 if (ret)
366 return ret;
367
368 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, &reg, &bit);
369
370 ret = regmap_read(domain->reg_pullen, reg, &val);
371 if (ret)
372 return ret;
373
374 if (!(val & BIT(bit))) {
375 conf = PIN_CONFIG_BIAS_DISABLE;
376 } else {
377 meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit);
378
379 ret = regmap_read(domain->reg_pull, reg, &val);
380 if (ret)
381 return ret;
382
383 if (val & BIT(bit))
384 conf = PIN_CONFIG_BIAS_PULL_UP;
385 else
386 conf = PIN_CONFIG_BIAS_PULL_DOWN;
387 }
388
389 return conf;
390}
391
392static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin,
393 unsigned long *config)
394{
395 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
396 enum pin_config_param param = pinconf_to_config_param(*config);
397 u16 arg;
398
399 switch (param) {
400 case PIN_CONFIG_BIAS_DISABLE:
401 case PIN_CONFIG_BIAS_PULL_DOWN:
402 case PIN_CONFIG_BIAS_PULL_UP:
403 if (meson_pinconf_get_pull(pc, pin) == param)
404 arg = 1;
405 else
406 return -EINVAL;
407 break;
408 default:
409 return -ENOTSUPP;
410 }
411
412 *config = pinconf_to_config_packed(param, arg);
413 dev_dbg(pc->dev, "pinconf for pin %u is %lu\n", pin, *config);
414
415 return 0;
416}
417
418static int meson_pinconf_group_set(struct pinctrl_dev *pcdev,
419 unsigned int num_group,
420 unsigned long *configs, unsigned num_configs)
421{
422 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
423 struct meson_pmx_group *group = &pc->data->groups[num_group];
424 int i;
425
426 dev_dbg(pc->dev, "set pinconf for group %s\n", group->name);
427
428 for (i = 0; i < group->num_pins; i++) {
429 meson_pinconf_set(pcdev, group->pins[i], configs,
430 num_configs);
431 }
432
433 return 0;
434}
435
436static int meson_pinconf_group_get(struct pinctrl_dev *pcdev,
437 unsigned int group, unsigned long *config)
438{
439 return -ENOSYS;
440}
441
442static const struct pinconf_ops meson_pinconf_ops = {
443 .pin_config_get = meson_pinconf_get,
444 .pin_config_set = meson_pinconf_set,
445 .pin_config_group_get = meson_pinconf_group_get,
446 .pin_config_group_set = meson_pinconf_group_set,
447 .is_generic = true,
448};
449
450static inline struct meson_domain *to_meson_domain(struct gpio_chip *chip)
451{
452 return container_of(chip, struct meson_domain, chip);
453}
454
455static int meson_gpio_request(struct gpio_chip *chip, unsigned gpio)
456{
457 return pinctrl_request_gpio(chip->base + gpio);
458}
459
460static void meson_gpio_free(struct gpio_chip *chip, unsigned gpio)
461{
462 struct meson_domain *domain = to_meson_domain(chip);
463
464 pinctrl_free_gpio(domain->data->pin_base + gpio);
465}
466
467static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
468{
469 struct meson_domain *domain = to_meson_domain(chip);
470 unsigned int reg, bit, pin;
471 struct meson_bank *bank;
472 int ret;
473
474 pin = domain->data->pin_base + gpio;
475 ret = meson_get_bank(domain, pin, &bank);
476 if (ret)
477 return ret;
478
479 meson_calc_reg_and_bit(bank, pin, REG_DIR, &reg, &bit);
480
481 return regmap_update_bits(domain->reg_gpio, reg, BIT(bit), BIT(bit));
482}
483
484static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
485 int value)
486{
487 struct meson_domain *domain = to_meson_domain(chip);
488 unsigned int reg, bit, pin;
489 struct meson_bank *bank;
490 int ret;
491
492 pin = domain->data->pin_base + gpio;
493 ret = meson_get_bank(domain, pin, &bank);
494 if (ret)
495 return ret;
496
497 meson_calc_reg_and_bit(bank, pin, REG_DIR, &reg, &bit);
498 ret = regmap_update_bits(domain->reg_gpio, reg, BIT(bit), 0);
499 if (ret)
500 return ret;
501
502 meson_calc_reg_and_bit(bank, pin, REG_OUT, &reg, &bit);
503 return regmap_update_bits(domain->reg_gpio, reg, BIT(bit),
504 value ? BIT(bit) : 0);
505}
506
507static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
508{
509 struct meson_domain *domain = to_meson_domain(chip);
510 unsigned int reg, bit, pin;
511 struct meson_bank *bank;
512 int ret;
513
514 pin = domain->data->pin_base + gpio;
515 ret = meson_get_bank(domain, pin, &bank);
516 if (ret)
517 return;
518
519 meson_calc_reg_and_bit(bank, pin, REG_OUT, &reg, &bit);
520 regmap_update_bits(domain->reg_gpio, reg, BIT(bit),
521 value ? BIT(bit) : 0);
522}
523
524static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio)
525{
526 struct meson_domain *domain = to_meson_domain(chip);
527 unsigned int reg, bit, val, pin;
528 struct meson_bank *bank;
529 int ret;
530
531 pin = domain->data->pin_base + gpio;
532 ret = meson_get_bank(domain, pin, &bank);
533 if (ret)
534 return ret;
535
536 meson_calc_reg_and_bit(bank, pin, REG_IN, &reg, &bit);
537 regmap_read(domain->reg_gpio, reg, &val);
538
539 return !!(val & BIT(bit));
540}
541
542static const struct of_device_id meson_pinctrl_dt_match[] = {
543 {
544 .compatible = "amlogic,meson8-pinctrl",
545 .data = &meson8_pinctrl_data,
546 },
547 { },
548};
549MODULE_DEVICE_TABLE(of, meson_pinctrl_dt_match);
550
551static int meson_gpiolib_register(struct meson_pinctrl *pc)
552{
553 struct meson_domain *domain;
554 int i, ret;
555
556 for (i = 0; i < pc->data->num_domains; i++) {
557 domain = &pc->domains[i];
558
559 domain->chip.label = domain->data->name;
560 domain->chip.dev = pc->dev;
561 domain->chip.request = meson_gpio_request;
562 domain->chip.free = meson_gpio_free;
563 domain->chip.direction_input = meson_gpio_direction_input;
564 domain->chip.direction_output = meson_gpio_direction_output;
565 domain->chip.get = meson_gpio_get;
566 domain->chip.set = meson_gpio_set;
567 domain->chip.base = -1;
568 domain->chip.ngpio = domain->data->num_pins;
569 domain->chip.can_sleep = false;
570 domain->chip.of_node = domain->of_node;
571 domain->chip.of_gpio_n_cells = 2;
572
573 ret = gpiochip_add(&domain->chip);
574 if (ret) {
575 dev_err(pc->dev, "can't add gpio chip %s\n",
576 domain->data->name);
577 goto fail;
578 }
579
580 ret = gpiochip_add_pin_range(&domain->chip, dev_name(pc->dev),
581 0, domain->data->pin_base,
582 domain->chip.ngpio);
583 if (ret) {
584 dev_err(pc->dev, "can't add pin range\n");
585 goto fail;
586 }
587 }
588
589 return 0;
590fail:
591 for (i--; i >= 0; i--)
592 gpiochip_remove(&pc->domains[i].chip);
593
594 return ret;
595}
596
597static struct meson_domain_data *meson_get_domain_data(struct meson_pinctrl *pc,
598 struct device_node *np)
599{
600 int i;
601
602 for (i = 0; i < pc->data->num_domains; i++) {
603 if (!strcmp(np->name, pc->data->domain_data[i].name))
604 return &pc->data->domain_data[i];
605 }
606
607 return NULL;
608}
609
610static struct regmap_config meson_regmap_config = {
611 .reg_bits = 32,
612 .val_bits = 32,
613 .reg_stride = 4,
614};
615
616static struct regmap *meson_map_resource(struct meson_pinctrl *pc,
617 struct device_node *node, char *name)
618{
619 struct resource res;
620 void __iomem *base;
621 int i;
622
623 i = of_property_match_string(node, "reg-names", name);
624 if (of_address_to_resource(node, i, &res))
625 return ERR_PTR(-ENOENT);
626
627 base = devm_ioremap_resource(pc->dev, &res);
628 if (IS_ERR(base))
629 return ERR_CAST(base);
630
631 meson_regmap_config.max_register = resource_size(&res) - 4;
632 meson_regmap_config.name = devm_kasprintf(pc->dev, GFP_KERNEL,
633 "%s-%s", node->name,
634 name);
635 if (!meson_regmap_config.name)
636 return ERR_PTR(-ENOMEM);
637
638 return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config);
639}
640
641static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc,
642 struct device_node *node)
643{
644 struct device_node *np;
645 struct meson_domain *domain;
646 int i = 0, num_domains = 0;
647
648 for_each_child_of_node(node, np) {
649 if (!of_find_property(np, "gpio-controller", NULL))
650 continue;
651 num_domains++;
652 }
653
654 if (num_domains != pc->data->num_domains) {
655 dev_err(pc->dev, "wrong number of subnodes\n");
656 return -EINVAL;
657 }
658
659 pc->domains = devm_kzalloc(pc->dev, num_domains *
660 sizeof(struct meson_domain), GFP_KERNEL);
661 if (!pc->domains)
662 return -ENOMEM;
663
664 for_each_child_of_node(node, np) {
665 if (!of_find_property(np, "gpio-controller", NULL))
666 continue;
667
668 domain = &pc->domains[i];
669
670 domain->data = meson_get_domain_data(pc, np);
671 if (!domain->data) {
672 dev_err(pc->dev, "domain data not found for node %s\n",
673 np->name);
674 return -ENODEV;
675 }
676
677 domain->of_node = np;
678
679 domain->reg_mux = meson_map_resource(pc, np, "mux");
680 if (IS_ERR(domain->reg_mux)) {
681 dev_err(pc->dev, "mux registers not found\n");
682 return PTR_ERR(domain->reg_mux);
683 }
684
685 domain->reg_pull = meson_map_resource(pc, np, "pull");
686 if (IS_ERR(domain->reg_pull)) {
687 dev_err(pc->dev, "pull registers not found\n");
688 return PTR_ERR(domain->reg_pull);
689 }
690
691 domain->reg_pullen = meson_map_resource(pc, np, "pull-enable");
692 /* Use pull region if pull-enable one is not present */
693 if (IS_ERR(domain->reg_pullen))
694 domain->reg_pullen = domain->reg_pull;
695
696 domain->reg_gpio = meson_map_resource(pc, np, "gpio");
697 if (IS_ERR(domain->reg_gpio)) {
698 dev_err(pc->dev, "gpio registers not found\n");
699 return PTR_ERR(domain->reg_gpio);
700 }
701
702 i++;
703 }
704
705 return 0;
706}
707
708static int meson_pinctrl_probe(struct platform_device *pdev)
709{
710 const struct of_device_id *match;
711 struct device *dev = &pdev->dev;
712 struct meson_pinctrl *pc;
713 int ret;
714
715 pc = devm_kzalloc(dev, sizeof(struct meson_pinctrl), GFP_KERNEL);
716 if (!pc)
717 return -ENOMEM;
718
719 pc->dev = dev;
720 match = of_match_node(meson_pinctrl_dt_match, pdev->dev.of_node);
721 pc->data = (struct meson_pinctrl_data *)match->data;
722
723 ret = meson_pinctrl_parse_dt(pc, pdev->dev.of_node);
724 if (ret)
725 return ret;
726
727 pc->desc.name = "pinctrl-meson";
728 pc->desc.owner = THIS_MODULE;
729 pc->desc.pctlops = &meson_pctrl_ops;
730 pc->desc.pmxops = &meson_pmx_ops;
731 pc->desc.confops = &meson_pinconf_ops;
732 pc->desc.pins = pc->data->pins;
733 pc->desc.npins = pc->data->num_pins;
734
735 pc->pcdev = pinctrl_register(&pc->desc, pc->dev, pc);
736 if (!pc->pcdev) {
737 dev_err(pc->dev, "can't register pinctrl device");
738 return -EINVAL;
739 }
740
741 ret = meson_gpiolib_register(pc);
742 if (ret) {
743 pinctrl_unregister(pc->pcdev);
744 return ret;
745 }
746
747 return 0;
748}
749
750static struct platform_driver meson_pinctrl_driver = {
751 .probe = meson_pinctrl_probe,
752 .driver = {
753 .name = "meson-pinctrl",
754 .of_match_table = meson_pinctrl_dt_match,
755 },
756};
757module_platform_driver(meson_pinctrl_driver);
758
759MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
760MODULE_DESCRIPTION("Amlogic Meson pinctrl driver");
761MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h
new file mode 100644
index 000000000000..bfea8adc7953
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson.h
@@ -0,0 +1,209 @@
1/*
2 * Pin controller and GPIO driver for Amlogic Meson SoCs
3 *
4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * You should have received a copy of the GNU General Public License
11 * along with this program. If not, see <http://www.gnu.org/licenses/>.
12 */
13
14#include <linux/gpio.h>
15#include <linux/pinctrl/pinctrl.h>
16#include <linux/regmap.h>
17#include <linux/types.h>
18
19/**
20 * struct meson_pmx_group - a pinmux group
21 *
22 * @name: group name
23 * @pins: pins in the group
24 * @num_pins: number of pins in the group
25 * @is_gpio: whether the group is a single GPIO group
26 * @reg: register offset for the group in the domain mux registers
27 * @bit bit index enabling the group
28 * @domain: index of the domain this group belongs to
29 */
30struct meson_pmx_group {
31 const char *name;
32 const unsigned int *pins;
33 unsigned int num_pins;
34 bool is_gpio;
35 unsigned int reg;
36 unsigned int bit;
37 unsigned int domain;
38};
39
40/**
41 * struct meson_pmx_func - a pinmux function
42 *
43 * @name: function name
44 * @groups: groups in the function
45 * @num_groups: number of groups in the function
46 */
47struct meson_pmx_func {
48 const char *name;
49 const char * const *groups;
50 unsigned int num_groups;
51};
52
53/**
54 * struct meson_reg_desc - a register descriptor
55 *
56 * @reg: register offset in the regmap
57 * @bit: bit index in register
58 *
59 * The structure describes the information needed to control pull,
60 * pull-enable, direction, etc. for a single pin
61 */
62struct meson_reg_desc {
63 unsigned int reg;
64 unsigned int bit;
65};
66
67/**
68 * enum meson_reg_type - type of registers encoded in @meson_reg_desc
69 */
70enum meson_reg_type {
71 REG_PULLEN,
72 REG_PULL,
73 REG_DIR,
74 REG_OUT,
75 REG_IN,
76 NUM_REG,
77};
78
79/**
80 * struct meson bank
81 *
82 * @name: bank name
83 * @first: first pin of the bank
84 * @last: last pin of the bank
85 * @regs: array of register descriptors
86 *
87 * A bank represents a set of pins controlled by a contiguous set of
88 * bits in the domain registers. The structure specifies which bits in
89 * the regmap control the different functionalities. Each member of
90 * the @regs array refers to the first pin of the bank.
91 */
92struct meson_bank {
93 const char *name;
94 unsigned int first;
95 unsigned int last;
96 struct meson_reg_desc regs[NUM_REG];
97};
98
99/**
100 * struct meson_domain_data - domain platform data
101 *
102 * @name: name of the domain
103 * @banks: set of banks belonging to the domain
104 * @num_banks: number of banks in the domain
105 */
106struct meson_domain_data {
107 const char *name;
108 struct meson_bank *banks;
109 unsigned int num_banks;
110 unsigned int pin_base;
111 unsigned int num_pins;
112};
113
114/**
115 * struct meson_domain
116 *
117 * @reg_mux: registers for mux settings
118 * @reg_pullen: registers for pull-enable settings
119 * @reg_pull: registers for pull settings
120 * @reg_gpio: registers for gpio settings
121 * @chip: gpio chip associated with the domain
122 * @data; platform data for the domain
123 * @node: device tree node for the domain
124 *
125 * A domain represents a set of banks controlled by the same set of
126 * registers.
127 */
128struct meson_domain {
129 struct regmap *reg_mux;
130 struct regmap *reg_pullen;
131 struct regmap *reg_pull;
132 struct regmap *reg_gpio;
133
134 struct gpio_chip chip;
135 struct meson_domain_data *data;
136 struct device_node *of_node;
137};
138
139struct meson_pinctrl_data {
140 const struct pinctrl_pin_desc *pins;
141 struct meson_pmx_group *groups;
142 struct meson_pmx_func *funcs;
143 struct meson_domain_data *domain_data;
144 unsigned int num_pins;
145 unsigned int num_groups;
146 unsigned int num_funcs;
147 unsigned int num_domains;
148};
149
150struct meson_pinctrl {
151 struct device *dev;
152 struct pinctrl_dev *pcdev;
153 struct pinctrl_desc desc;
154 struct meson_pinctrl_data *data;
155 struct meson_domain *domains;
156};
157
158#define GROUP(grp, r, b) \
159 { \
160 .name = #grp, \
161 .pins = grp ## _pins, \
162 .num_pins = ARRAY_SIZE(grp ## _pins), \
163 .reg = r, \
164 .bit = b, \
165 .domain = 0, \
166 }
167
168#define GPIO_GROUP(gpio) \
169 { \
170 .name = #gpio, \
171 .pins = (const unsigned int[]){ PIN_ ## gpio}, \
172 .num_pins = 1, \
173 .is_gpio = true, \
174 }
175
176#define GROUP_AO(grp, r, b) \
177 { \
178 .name = #grp, \
179 .pins = grp ## _pins, \
180 .num_pins = ARRAY_SIZE(grp ## _pins), \
181 .reg = r, \
182 .bit = b, \
183 .domain = 1, \
184 }
185
186#define FUNCTION(fn) \
187 { \
188 .name = #fn, \
189 .groups = fn ## _groups, \
190 .num_groups = ARRAY_SIZE(fn ## _groups), \
191 }
192
193#define BANK(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib) \
194 { \
195 .name = n, \
196 .first = f, \
197 .last = l, \
198 .regs = { \
199 [REG_PULLEN] = { per, peb }, \
200 [REG_PULL] = { pr, pb }, \
201 [REG_DIR] = { dr, db }, \
202 [REG_OUT] = { or, ob }, \
203 [REG_IN] = { ir, ib }, \
204 }, \
205 }
206
207#define MESON_PIN(x) PINCTRL_PIN(PIN_ ## x, #x)
208
209extern struct meson_pinctrl_data meson8_pinctrl_data;
diff --git a/drivers/pinctrl/meson/pinctrl-meson8.c b/drivers/pinctrl/meson/pinctrl-meson8.c
new file mode 100644
index 000000000000..f8aa3a281767
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson8.c
@@ -0,0 +1,1089 @@
1/*
2 * Pin controller and GPIO driver for Amlogic Meson8.
3 *
4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * You should have received a copy of the GNU General Public License
11 * along with this program. If not, see <http://www.gnu.org/licenses/>.
12 */
13
14#include <dt-bindings/gpio/meson8-gpio.h>
15#include "pinctrl-meson.h"
16
17#define AO_OFFSET 120
18
19#define PIN_GPIOX_0 GPIOX_0
20#define PIN_GPIOX_1 GPIOX_1
21#define PIN_GPIOX_2 GPIOX_2
22#define PIN_GPIOX_3 GPIOX_3
23#define PIN_GPIOX_4 GPIOX_4
24#define PIN_GPIOX_5 GPIOX_5
25#define PIN_GPIOX_6 GPIOX_6
26#define PIN_GPIOX_7 GPIOX_7
27#define PIN_GPIOX_8 GPIOX_8
28#define PIN_GPIOX_9 GPIOX_9
29#define PIN_GPIOX_10 GPIOX_10
30#define PIN_GPIOX_11 GPIOX_11
31#define PIN_GPIOX_12 GPIOX_12
32#define PIN_GPIOX_13 GPIOX_13
33#define PIN_GPIOX_14 GPIOX_14
34#define PIN_GPIOX_15 GPIOX_15
35#define PIN_GPIOX_16 GPIOX_16
36#define PIN_GPIOX_17 GPIOX_17
37#define PIN_GPIOX_18 GPIOX_18
38#define PIN_GPIOX_19 GPIOX_19
39#define PIN_GPIOX_20 GPIOX_20
40#define PIN_GPIOX_21 GPIOX_21
41#define PIN_GPIOY_0 GPIOY_0
42#define PIN_GPIOY_1 GPIOY_1
43#define PIN_GPIOY_2 GPIOY_2
44#define PIN_GPIOY_3 GPIOY_3
45#define PIN_GPIOY_4 GPIOY_4
46#define PIN_GPIOY_5 GPIOY_5
47#define PIN_GPIOY_6 GPIOY_6
48#define PIN_GPIOY_7 GPIOY_7
49#define PIN_GPIOY_8 GPIOY_8
50#define PIN_GPIOY_9 GPIOY_9
51#define PIN_GPIOY_10 GPIOY_10
52#define PIN_GPIOY_11 GPIOY_11
53#define PIN_GPIOY_12 GPIOY_12
54#define PIN_GPIOY_13 GPIOY_13
55#define PIN_GPIOY_14 GPIOY_14
56#define PIN_GPIOY_15 GPIOY_15
57#define PIN_GPIOY_16 GPIOY_16
58#define PIN_GPIODV_0 GPIODV_0
59#define PIN_GPIODV_1 GPIODV_1
60#define PIN_GPIODV_2 GPIODV_2
61#define PIN_GPIODV_3 GPIODV_3
62#define PIN_GPIODV_4 GPIODV_4
63#define PIN_GPIODV_5 GPIODV_5
64#define PIN_GPIODV_6 GPIODV_6
65#define PIN_GPIODV_7 GPIODV_7
66#define PIN_GPIODV_8 GPIODV_8
67#define PIN_GPIODV_9 GPIODV_9
68#define PIN_GPIODV_10 GPIODV_10
69#define PIN_GPIODV_11 GPIODV_11
70#define PIN_GPIODV_12 GPIODV_12
71#define PIN_GPIODV_13 GPIODV_13
72#define PIN_GPIODV_14 GPIODV_14
73#define PIN_GPIODV_15 GPIODV_15
74#define PIN_GPIODV_16 GPIODV_16
75#define PIN_GPIODV_17 GPIODV_17
76#define PIN_GPIODV_18 GPIODV_18
77#define PIN_GPIODV_19 GPIODV_19
78#define PIN_GPIODV_20 GPIODV_20
79#define PIN_GPIODV_21 GPIODV_21
80#define PIN_GPIODV_22 GPIODV_22
81#define PIN_GPIODV_23 GPIODV_23
82#define PIN_GPIODV_24 GPIODV_24
83#define PIN_GPIODV_25 GPIODV_25
84#define PIN_GPIODV_26 GPIODV_26
85#define PIN_GPIODV_27 GPIODV_27
86#define PIN_GPIODV_28 GPIODV_28
87#define PIN_GPIODV_29 GPIODV_29
88#define PIN_GPIOH_0 GPIOH_0
89#define PIN_GPIOH_1 GPIOH_1
90#define PIN_GPIOH_2 GPIOH_2
91#define PIN_GPIOH_3 GPIOH_3
92#define PIN_GPIOH_4 GPIOH_4
93#define PIN_GPIOH_5 GPIOH_5
94#define PIN_GPIOH_6 GPIOH_6
95#define PIN_GPIOH_7 GPIOH_7
96#define PIN_GPIOH_8 GPIOH_8
97#define PIN_GPIOH_9 GPIOH_9
98#define PIN_GPIOZ_0 GPIOZ_0
99#define PIN_GPIOZ_1 GPIOZ_1
100#define PIN_GPIOZ_2 GPIOZ_2
101#define PIN_GPIOZ_3 GPIOZ_3
102#define PIN_GPIOZ_4 GPIOZ_4
103#define PIN_GPIOZ_5 GPIOZ_5
104#define PIN_GPIOZ_6 GPIOZ_6
105#define PIN_GPIOZ_7 GPIOZ_7
106#define PIN_GPIOZ_8 GPIOZ_8
107#define PIN_GPIOZ_9 GPIOZ_9
108#define PIN_GPIOZ_10 GPIOZ_10
109#define PIN_GPIOZ_11 GPIOZ_11
110#define PIN_GPIOZ_12 GPIOZ_12
111#define PIN_GPIOZ_13 GPIOZ_13
112#define PIN_GPIOZ_14 GPIOZ_14
113#define PIN_CARD_0 CARD_0
114#define PIN_CARD_1 CARD_1
115#define PIN_CARD_2 CARD_2
116#define PIN_CARD_3 CARD_3
117#define PIN_CARD_4 CARD_4
118#define PIN_CARD_5 CARD_5
119#define PIN_CARD_6 CARD_6
120#define PIN_BOOT_0 BOOT_0
121#define PIN_BOOT_1 BOOT_1
122#define PIN_BOOT_2 BOOT_2
123#define PIN_BOOT_3 BOOT_3
124#define PIN_BOOT_4 BOOT_4
125#define PIN_BOOT_5 BOOT_5
126#define PIN_BOOT_6 BOOT_6
127#define PIN_BOOT_7 BOOT_7
128#define PIN_BOOT_8 BOOT_8
129#define PIN_BOOT_9 BOOT_9
130#define PIN_BOOT_10 BOOT_10
131#define PIN_BOOT_11 BOOT_11
132#define PIN_BOOT_12 BOOT_12
133#define PIN_BOOT_13 BOOT_13
134#define PIN_BOOT_14 BOOT_14
135#define PIN_BOOT_15 BOOT_15
136#define PIN_BOOT_16 BOOT_16
137#define PIN_BOOT_17 BOOT_17
138#define PIN_BOOT_18 BOOT_18
139
140#define PIN_GPIOAO_0 (AO_OFFSET + GPIOAO_0)
141#define PIN_GPIOAO_1 (AO_OFFSET + GPIOAO_1)
142#define PIN_GPIOAO_2 (AO_OFFSET + GPIOAO_2)
143#define PIN_GPIOAO_3 (AO_OFFSET + GPIOAO_3)
144#define PIN_GPIOAO_4 (AO_OFFSET + GPIOAO_4)
145#define PIN_GPIOAO_5 (AO_OFFSET + GPIOAO_5)
146#define PIN_GPIOAO_6 (AO_OFFSET + GPIOAO_6)
147#define PIN_GPIOAO_7 (AO_OFFSET + GPIOAO_7)
148#define PIN_GPIOAO_8 (AO_OFFSET + GPIOAO_8)
149#define PIN_GPIOAO_9 (AO_OFFSET + GPIOAO_9)
150#define PIN_GPIOAO_10 (AO_OFFSET + GPIOAO_10)
151#define PIN_GPIOAO_11 (AO_OFFSET + GPIOAO_11)
152#define PIN_GPIOAO_12 (AO_OFFSET + GPIOAO_12)
153#define PIN_GPIOAO_13 (AO_OFFSET + GPIOAO_13)
154#define PIN_GPIO_BSD_EN (AO_OFFSET + GPIO_BSD_EN)
155#define PIN_GPIO_TEST_N (AO_OFFSET + GPIO_TEST_N)
156
157static const struct pinctrl_pin_desc meson8_pins[] = {
158 MESON_PIN(GPIOX_0),
159 MESON_PIN(GPIOX_1),
160 MESON_PIN(GPIOX_2),
161 MESON_PIN(GPIOX_3),
162 MESON_PIN(GPIOX_4),
163 MESON_PIN(GPIOX_5),
164 MESON_PIN(GPIOX_6),
165 MESON_PIN(GPIOX_7),
166 MESON_PIN(GPIOX_8),
167 MESON_PIN(GPIOX_9),
168 MESON_PIN(GPIOX_10),
169 MESON_PIN(GPIOX_11),
170 MESON_PIN(GPIOX_12),
171 MESON_PIN(GPIOX_13),
172 MESON_PIN(GPIOX_14),
173 MESON_PIN(GPIOX_15),
174 MESON_PIN(GPIOX_16),
175 MESON_PIN(GPIOX_17),
176 MESON_PIN(GPIOX_18),
177 MESON_PIN(GPIOX_19),
178 MESON_PIN(GPIOX_20),
179 MESON_PIN(GPIOX_21),
180 MESON_PIN(GPIOY_0),
181 MESON_PIN(GPIOY_1),
182 MESON_PIN(GPIOY_2),
183 MESON_PIN(GPIOY_3),
184 MESON_PIN(GPIOY_4),
185 MESON_PIN(GPIOY_5),
186 MESON_PIN(GPIOY_6),
187 MESON_PIN(GPIOY_7),
188 MESON_PIN(GPIOY_8),
189 MESON_PIN(GPIOY_9),
190 MESON_PIN(GPIOY_10),
191 MESON_PIN(GPIOY_11),
192 MESON_PIN(GPIOY_12),
193 MESON_PIN(GPIOY_13),
194 MESON_PIN(GPIOY_14),
195 MESON_PIN(GPIOY_15),
196 MESON_PIN(GPIOY_16),
197 MESON_PIN(GPIODV_0),
198 MESON_PIN(GPIODV_1),
199 MESON_PIN(GPIODV_2),
200 MESON_PIN(GPIODV_3),
201 MESON_PIN(GPIODV_4),
202 MESON_PIN(GPIODV_5),
203 MESON_PIN(GPIODV_6),
204 MESON_PIN(GPIODV_7),
205 MESON_PIN(GPIODV_8),
206 MESON_PIN(GPIODV_9),
207 MESON_PIN(GPIODV_10),
208 MESON_PIN(GPIODV_11),
209 MESON_PIN(GPIODV_12),
210 MESON_PIN(GPIODV_13),
211 MESON_PIN(GPIODV_14),
212 MESON_PIN(GPIODV_15),
213 MESON_PIN(GPIODV_16),
214 MESON_PIN(GPIODV_17),
215 MESON_PIN(GPIODV_18),
216 MESON_PIN(GPIODV_19),
217 MESON_PIN(GPIODV_20),
218 MESON_PIN(GPIODV_21),
219 MESON_PIN(GPIODV_22),
220 MESON_PIN(GPIODV_23),
221 MESON_PIN(GPIODV_24),
222 MESON_PIN(GPIODV_25),
223 MESON_PIN(GPIODV_26),
224 MESON_PIN(GPIODV_27),
225 MESON_PIN(GPIODV_28),
226 MESON_PIN(GPIODV_29),
227 MESON_PIN(GPIOH_0),
228 MESON_PIN(GPIOH_1),
229 MESON_PIN(GPIOH_2),
230 MESON_PIN(GPIOH_3),
231 MESON_PIN(GPIOH_4),
232 MESON_PIN(GPIOH_5),
233 MESON_PIN(GPIOH_6),
234 MESON_PIN(GPIOH_7),
235 MESON_PIN(GPIOH_8),
236 MESON_PIN(GPIOH_9),
237 MESON_PIN(GPIOZ_0),
238 MESON_PIN(GPIOZ_1),
239 MESON_PIN(GPIOZ_2),
240 MESON_PIN(GPIOZ_3),
241 MESON_PIN(GPIOZ_4),
242 MESON_PIN(GPIOZ_5),
243 MESON_PIN(GPIOZ_6),
244 MESON_PIN(GPIOZ_7),
245 MESON_PIN(GPIOZ_8),
246 MESON_PIN(GPIOZ_9),
247 MESON_PIN(GPIOZ_10),
248 MESON_PIN(GPIOZ_11),
249 MESON_PIN(GPIOZ_12),
250 MESON_PIN(GPIOZ_13),
251 MESON_PIN(GPIOZ_14),
252 MESON_PIN(CARD_0),
253 MESON_PIN(CARD_1),
254 MESON_PIN(CARD_2),
255 MESON_PIN(CARD_3),
256 MESON_PIN(CARD_4),
257 MESON_PIN(CARD_5),
258 MESON_PIN(CARD_6),
259 MESON_PIN(BOOT_0),
260 MESON_PIN(BOOT_1),
261 MESON_PIN(BOOT_2),
262 MESON_PIN(BOOT_3),
263 MESON_PIN(BOOT_4),
264 MESON_PIN(BOOT_5),
265 MESON_PIN(BOOT_6),
266 MESON_PIN(BOOT_7),
267 MESON_PIN(BOOT_8),
268 MESON_PIN(BOOT_9),
269 MESON_PIN(BOOT_10),
270 MESON_PIN(BOOT_11),
271 MESON_PIN(BOOT_12),
272 MESON_PIN(BOOT_13),
273 MESON_PIN(BOOT_14),
274 MESON_PIN(BOOT_15),
275 MESON_PIN(BOOT_16),
276 MESON_PIN(BOOT_17),
277 MESON_PIN(BOOT_18),
278 MESON_PIN(GPIOAO_0),
279 MESON_PIN(GPIOAO_1),
280 MESON_PIN(GPIOAO_2),
281 MESON_PIN(GPIOAO_3),
282 MESON_PIN(GPIOAO_4),
283 MESON_PIN(GPIOAO_5),
284 MESON_PIN(GPIOAO_6),
285 MESON_PIN(GPIOAO_7),
286 MESON_PIN(GPIOAO_8),
287 MESON_PIN(GPIOAO_9),
288 MESON_PIN(GPIOAO_10),
289 MESON_PIN(GPIOAO_11),
290 MESON_PIN(GPIOAO_12),
291 MESON_PIN(GPIOAO_13),
292 MESON_PIN(GPIO_BSD_EN),
293 MESON_PIN(GPIO_TEST_N),
294};
295
296/* bank X */
297static const unsigned int sd_d0_a_pins[] = { PIN_GPIOX_0 };
298static const unsigned int sd_d1_a_pins[] = { PIN_GPIOX_1 };
299static const unsigned int sd_d2_a_pins[] = { PIN_GPIOX_2 };
300static const unsigned int sd_d3_a_pins[] = { PIN_GPIOX_3 };
301static const unsigned int sd_clk_a_pins[] = { PIN_GPIOX_8 };
302static const unsigned int sd_cmd_a_pins[] = { PIN_GPIOX_9 };
303
304static const unsigned int sdxc_d0_a_pins[] = { PIN_GPIOX_0 };
305static const unsigned int sdxc_d13_a_pins[] = { PIN_GPIOX_1, PIN_GPIOX_2,
306 PIN_GPIOX_3 };
307static const unsigned int sdxc_d47_a_pins[] = { PIN_GPIOX_4, PIN_GPIOX_5,
308 PIN_GPIOX_6, PIN_GPIOX_7 };
309static const unsigned int sdxc_clk_a_pins[] = { PIN_GPIOX_8 };
310static const unsigned int sdxc_cmd_a_pins[] = { PIN_GPIOX_9 };
311
312static const unsigned int pcm_out_a_pins[] = { PIN_GPIOX_4 };
313static const unsigned int pcm_in_a_pins[] = { PIN_GPIOX_5 };
314static const unsigned int pcm_fs_a_pins[] = { PIN_GPIOX_6 };
315static const unsigned int pcm_clk_a_pins[] = { PIN_GPIOX_7 };
316
317static const unsigned int uart_tx_a0_pins[] = { PIN_GPIOX_4 };
318static const unsigned int uart_rx_a0_pins[] = { PIN_GPIOX_5 };
319static const unsigned int uart_cts_a0_pins[] = { PIN_GPIOX_6 };
320static const unsigned int uart_rts_a0_pins[] = { PIN_GPIOX_7 };
321
322static const unsigned int uart_tx_a1_pins[] = { PIN_GPIOX_12 };
323static const unsigned int uart_rx_a1_pins[] = { PIN_GPIOX_13 };
324static const unsigned int uart_cts_a1_pins[] = { PIN_GPIOX_14 };
325static const unsigned int uart_rts_a1_pins[] = { PIN_GPIOX_15 };
326
327static const unsigned int uart_tx_b0_pins[] = { PIN_GPIOX_16 };
328static const unsigned int uart_rx_b0_pins[] = { PIN_GPIOX_17 };
329static const unsigned int uart_cts_b0_pins[] = { PIN_GPIOX_18 };
330static const unsigned int uart_rts_b0_pins[] = { PIN_GPIOX_19 };
331
332static const unsigned int iso7816_det_pins[] = { PIN_GPIOX_16 };
333static const unsigned int iso7816_reset_pins[] = { PIN_GPIOX_17 };
334static const unsigned int iso7816_clk_pins[] = { PIN_GPIOX_18 };
335static const unsigned int iso7816_data_pins[] = { PIN_GPIOX_19 };
336
337static const unsigned int i2c_sda_d0_pins[] = { PIN_GPIOX_16 };
338static const unsigned int i2c_sck_d0_pins[] = { PIN_GPIOX_17 };
339
340static const unsigned int xtal_32k_out_pins[] = { PIN_GPIOX_10 };
341static const unsigned int xtal_24m_out_pins[] = { PIN_GPIOX_11 };
342
343/* bank Y */
344static const unsigned int uart_tx_c_pins[] = { PIN_GPIOY_0 };
345static const unsigned int uart_rx_c_pins[] = { PIN_GPIOY_1 };
346static const unsigned int uart_cts_c_pins[] = { PIN_GPIOY_2 };
347static const unsigned int uart_rts_c_pins[] = { PIN_GPIOY_3 };
348
349static const unsigned int pcm_out_b_pins[] = { PIN_GPIOY_4 };
350static const unsigned int pcm_in_b_pins[] = { PIN_GPIOY_5 };
351static const unsigned int pcm_fs_b_pins[] = { PIN_GPIOY_6 };
352static const unsigned int pcm_clk_b_pins[] = { PIN_GPIOY_7 };
353
354static const unsigned int i2c_sda_c0_pins[] = { PIN_GPIOY_0 };
355static const unsigned int i2c_sck_c0_pins[] = { PIN_GPIOY_1 };
356
357/* bank DV */
358static const unsigned int dvin_rgb_pins[] = { PIN_GPIODV_0, PIN_GPIODV_1,
359 PIN_GPIODV_2, PIN_GPIODV_3,
360 PIN_GPIODV_4, PIN_GPIODV_5,
361 PIN_GPIODV_6, PIN_GPIODV_7,
362 PIN_GPIODV_8, PIN_GPIODV_9,
363 PIN_GPIODV_10, PIN_GPIODV_11,
364 PIN_GPIODV_12, PIN_GPIODV_13,
365 PIN_GPIODV_14, PIN_GPIODV_15,
366 PIN_GPIODV_16, PIN_GPIODV_17,
367 PIN_GPIODV_18, PIN_GPIODV_19,
368 PIN_GPIODV_20, PIN_GPIODV_21,
369 PIN_GPIODV_22, PIN_GPIODV_23 };
370static const unsigned int dvin_vs_pins[] = { PIN_GPIODV_24 };
371static const unsigned int dvin_hs_pins[] = { PIN_GPIODV_25 };
372static const unsigned int dvin_clk_pins[] = { PIN_GPIODV_26 };
373static const unsigned int dvin_de_pins[] = { PIN_GPIODV_27 };
374
375static const unsigned int enc_0_pins[] = { PIN_GPIODV_0 };
376static const unsigned int enc_1_pins[] = { PIN_GPIODV_1 };
377static const unsigned int enc_2_pins[] = { PIN_GPIODV_2 };
378static const unsigned int enc_3_pins[] = { PIN_GPIODV_3 };
379static const unsigned int enc_4_pins[] = { PIN_GPIODV_4 };
380static const unsigned int enc_5_pins[] = { PIN_GPIODV_5 };
381static const unsigned int enc_6_pins[] = { PIN_GPIODV_6 };
382static const unsigned int enc_7_pins[] = { PIN_GPIODV_7 };
383static const unsigned int enc_8_pins[] = { PIN_GPIODV_8 };
384static const unsigned int enc_9_pins[] = { PIN_GPIODV_9 };
385static const unsigned int enc_10_pins[] = { PIN_GPIODV_10 };
386static const unsigned int enc_11_pins[] = { PIN_GPIODV_11 };
387static const unsigned int enc_12_pins[] = { PIN_GPIODV_12 };
388static const unsigned int enc_13_pins[] = { PIN_GPIODV_13 };
389static const unsigned int enc_14_pins[] = { PIN_GPIODV_14 };
390static const unsigned int enc_15_pins[] = { PIN_GPIODV_15 };
391static const unsigned int enc_16_pins[] = { PIN_GPIODV_16 };
392static const unsigned int enc_17_pins[] = { PIN_GPIODV_17 };
393
394static const unsigned int uart_tx_b1_pins[] = { PIN_GPIODV_24 };
395static const unsigned int uart_rx_b1_pins[] = { PIN_GPIODV_25 };
396static const unsigned int uart_cts_b1_pins[] = { PIN_GPIODV_26 };
397static const unsigned int uart_rts_b1_pins[] = { PIN_GPIODV_27 };
398
399static const unsigned int vga_vs_pins[] = { PIN_GPIODV_24 };
400static const unsigned int vga_hs_pins[] = { PIN_GPIODV_25 };
401
402/* bank H */
403static const unsigned int hdmi_hpd_pins[] = { PIN_GPIOH_0 };
404static const unsigned int hdmi_sda_pins[] = { PIN_GPIOH_1 };
405static const unsigned int hdmi_scl_pins[] = { PIN_GPIOH_2 };
406static const unsigned int hdmi_cec_pins[] = { PIN_GPIOH_3 };
407
408static const unsigned int spi_ss0_0_pins[] = { PIN_GPIOH_3 };
409static const unsigned int spi_miso_0_pins[] = { PIN_GPIOH_4 };
410static const unsigned int spi_mosi_0_pins[] = { PIN_GPIOH_5 };
411static const unsigned int spi_sclk_0_pins[] = { PIN_GPIOH_6 };
412
413static const unsigned int i2c_sda_d1_pins[] = { PIN_GPIOH_7 };
414static const unsigned int i2c_sck_d1_pins[] = { PIN_GPIOH_8 };
415
416/* bank Z */
417static const unsigned int spi_ss0_1_pins[] = { PIN_GPIOZ_9 };
418static const unsigned int spi_ss1_1_pins[] = { PIN_GPIOZ_10 };
419static const unsigned int spi_sclk_1_pins[] = { PIN_GPIOZ_11 };
420static const unsigned int spi_mosi_1_pins[] = { PIN_GPIOZ_12 };
421static const unsigned int spi_miso_1_pins[] = { PIN_GPIOZ_13 };
422static const unsigned int spi_ss2_1_pins[] = { PIN_GPIOZ_14 };
423
424static const unsigned int eth_tx_clk_50m_pins[] = { PIN_GPIOZ_4 };
425static const unsigned int eth_tx_en_pins[] = { PIN_GPIOZ_5 };
426static const unsigned int eth_txd1_pins[] = { PIN_GPIOZ_6 };
427static const unsigned int eth_txd0_pins[] = { PIN_GPIOZ_7 };
428static const unsigned int eth_rx_clk_in_pins[] = { PIN_GPIOZ_8 };
429static const unsigned int eth_rx_dv_pins[] = { PIN_GPIOZ_9 };
430static const unsigned int eth_rxd1_pins[] = { PIN_GPIOZ_10 };
431static const unsigned int eth_rxd0_pins[] = { PIN_GPIOZ_11 };
432static const unsigned int eth_mdio_pins[] = { PIN_GPIOZ_12 };
433static const unsigned int eth_mdc_pins[] = { PIN_GPIOZ_13 };
434
435static const unsigned int i2c_sda_a0_pins[] = { PIN_GPIOZ_0 };
436static const unsigned int i2c_sck_a0_pins[] = { PIN_GPIOZ_1 };
437
438static const unsigned int i2c_sda_b_pins[] = { PIN_GPIOZ_2 };
439static const unsigned int i2c_sck_b_pins[] = { PIN_GPIOZ_3 };
440
441static const unsigned int i2c_sda_c1_pins[] = { PIN_GPIOZ_4 };
442static const unsigned int i2c_sck_c1_pins[] = { PIN_GPIOZ_5 };
443
444static const unsigned int i2c_sda_a1_pins[] = { PIN_GPIOZ_0 };
445static const unsigned int i2c_sck_a1_pins[] = { PIN_GPIOZ_1 };
446
447static const unsigned int i2c_sda_a2_pins[] = { PIN_GPIOZ_0 };
448static const unsigned int i2c_sck_a2_pins[] = { PIN_GPIOZ_1 };
449
450/* bank BOOT */
451static const unsigned int sd_d0_c_pins[] = { PIN_BOOT_0 };
452static const unsigned int sd_d1_c_pins[] = { PIN_BOOT_1 };
453static const unsigned int sd_d2_c_pins[] = { PIN_BOOT_2 };
454static const unsigned int sd_d3_c_pins[] = { PIN_BOOT_3 };
455static const unsigned int sd_cmd_c_pins[] = { PIN_BOOT_16 };
456static const unsigned int sd_clk_c_pins[] = { PIN_BOOT_17 };
457
458static const unsigned int sdxc_d0_c_pins[] = { PIN_BOOT_0};
459static const unsigned int sdxc_d13_c_pins[] = { PIN_BOOT_1, PIN_BOOT_2,
460 PIN_BOOT_3 };
461static const unsigned int sdxc_d47_c_pins[] = { PIN_BOOT_4, PIN_BOOT_5,
462 PIN_BOOT_6, PIN_BOOT_7 };
463static const unsigned int sdxc_cmd_c_pins[] = { PIN_BOOT_16 };
464static const unsigned int sdxc_clk_c_pins[] = { PIN_BOOT_17 };
465
466static const unsigned int nand_io_pins[] = { PIN_BOOT_0, PIN_BOOT_1,
467 PIN_BOOT_2, PIN_BOOT_3,
468 PIN_BOOT_4, PIN_BOOT_5,
469 PIN_BOOT_6, PIN_BOOT_7 };
470static const unsigned int nand_io_ce0_pins[] = { PIN_BOOT_8 };
471static const unsigned int nand_io_ce1_pins[] = { PIN_BOOT_9 };
472static const unsigned int nand_io_rb0_pins[] = { PIN_BOOT_10 };
473static const unsigned int nand_ale_pins[] = { PIN_BOOT_11 };
474static const unsigned int nand_cle_pins[] = { PIN_BOOT_12 };
475static const unsigned int nand_wen_clk_pins[] = { PIN_BOOT_13 };
476static const unsigned int nand_ren_clk_pins[] = { PIN_BOOT_14 };
477static const unsigned int nand_dqs_pins[] = { PIN_BOOT_15 };
478static const unsigned int nand_ce2_pins[] = { PIN_BOOT_16 };
479static const unsigned int nand_ce3_pins[] = { PIN_BOOT_17 };
480
481static const unsigned int nor_d_pins[] = { PIN_BOOT_11 };
482static const unsigned int nor_q_pins[] = { PIN_BOOT_12 };
483static const unsigned int nor_c_pins[] = { PIN_BOOT_13 };
484static const unsigned int nor_cs_pins[] = { PIN_BOOT_18 };
485
486/* bank CARD */
487static const unsigned int sd_d1_b_pins[] = { PIN_CARD_0 };
488static const unsigned int sd_d0_b_pins[] = { PIN_CARD_1 };
489static const unsigned int sd_clk_b_pins[] = { PIN_CARD_2 };
490static const unsigned int sd_cmd_b_pins[] = { PIN_CARD_3 };
491static const unsigned int sd_d3_b_pins[] = { PIN_CARD_4 };
492static const unsigned int sd_d2_b_pins[] = { PIN_CARD_5 };
493
494static const unsigned int sdxc_d13_b_pins[] = { PIN_CARD_0, PIN_CARD_4,
495 PIN_CARD_5 };
496static const unsigned int sdxc_d0_b_pins[] = { PIN_CARD_1 };
497static const unsigned int sdxc_clk_b_pins[] = { PIN_CARD_2 };
498static const unsigned int sdxc_cmd_b_pins[] = { PIN_CARD_3 };
499
500/* bank AO */
501static const unsigned int uart_tx_ao_a_pins[] = { PIN_GPIOAO_0 };
502static const unsigned int uart_rx_ao_a_pins[] = { PIN_GPIOAO_1 };
503static const unsigned int uart_cts_ao_a_pins[] = { PIN_GPIOAO_2 };
504static const unsigned int uart_rts_ao_a_pins[] = { PIN_GPIOAO_3 };
505
506static const unsigned int remote_input_pins[] = { PIN_GPIOAO_7 };
507
508static const unsigned int i2c_slave_sck_ao_pins[] = { PIN_GPIOAO_4 };
509static const unsigned int i2c_slave_sda_ao_pins[] = { PIN_GPIOAO_5 };
510
511static const unsigned int uart_tx_ao_b0_pins[] = { PIN_GPIOAO_0 };
512static const unsigned int uart_rx_ao_b0_pins[] = { PIN_GPIOAO_1 };
513
514static const unsigned int uart_tx_ao_b1_pins[] = { PIN_GPIOAO_4 };
515static const unsigned int uart_rx_ao_b1_pins[] = { PIN_GPIOAO_5 };
516
517static const unsigned int i2c_mst_sck_ao_pins[] = { PIN_GPIOAO_4 };
518static const unsigned int i2c_mst_sda_ao_pins[] = { PIN_GPIOAO_5 };
519
520static struct meson_pmx_group meson8_groups[] = {
521 GPIO_GROUP(GPIOX_0),
522 GPIO_GROUP(GPIOX_1),
523 GPIO_GROUP(GPIOX_2),
524 GPIO_GROUP(GPIOX_3),
525 GPIO_GROUP(GPIOX_4),
526 GPIO_GROUP(GPIOX_5),
527 GPIO_GROUP(GPIOX_6),
528 GPIO_GROUP(GPIOX_7),
529 GPIO_GROUP(GPIOX_8),
530 GPIO_GROUP(GPIOX_9),
531 GPIO_GROUP(GPIOX_10),
532 GPIO_GROUP(GPIOX_11),
533 GPIO_GROUP(GPIOX_12),
534 GPIO_GROUP(GPIOX_13),
535 GPIO_GROUP(GPIOX_14),
536 GPIO_GROUP(GPIOX_15),
537 GPIO_GROUP(GPIOX_16),
538 GPIO_GROUP(GPIOX_17),
539 GPIO_GROUP(GPIOX_18),
540 GPIO_GROUP(GPIOX_19),
541 GPIO_GROUP(GPIOX_20),
542 GPIO_GROUP(GPIOX_21),
543 GPIO_GROUP(GPIOY_0),
544 GPIO_GROUP(GPIOY_1),
545 GPIO_GROUP(GPIOY_2),
546 GPIO_GROUP(GPIOY_3),
547 GPIO_GROUP(GPIOY_4),
548 GPIO_GROUP(GPIOY_5),
549 GPIO_GROUP(GPIOY_6),
550 GPIO_GROUP(GPIOY_7),
551 GPIO_GROUP(GPIOY_8),
552 GPIO_GROUP(GPIOY_9),
553 GPIO_GROUP(GPIOY_10),
554 GPIO_GROUP(GPIOY_11),
555 GPIO_GROUP(GPIOY_12),
556 GPIO_GROUP(GPIOY_13),
557 GPIO_GROUP(GPIOY_14),
558 GPIO_GROUP(GPIOY_15),
559 GPIO_GROUP(GPIOY_16),
560 GPIO_GROUP(GPIODV_0),
561 GPIO_GROUP(GPIODV_1),
562 GPIO_GROUP(GPIODV_2),
563 GPIO_GROUP(GPIODV_3),
564 GPIO_GROUP(GPIODV_4),
565 GPIO_GROUP(GPIODV_5),
566 GPIO_GROUP(GPIODV_6),
567 GPIO_GROUP(GPIODV_7),
568 GPIO_GROUP(GPIODV_8),
569 GPIO_GROUP(GPIODV_9),
570 GPIO_GROUP(GPIODV_10),
571 GPIO_GROUP(GPIODV_11),
572 GPIO_GROUP(GPIODV_12),
573 GPIO_GROUP(GPIODV_13),
574 GPIO_GROUP(GPIODV_14),
575 GPIO_GROUP(GPIODV_15),
576 GPIO_GROUP(GPIODV_16),
577 GPIO_GROUP(GPIODV_17),
578 GPIO_GROUP(GPIODV_18),
579 GPIO_GROUP(GPIODV_19),
580 GPIO_GROUP(GPIODV_20),
581 GPIO_GROUP(GPIODV_21),
582 GPIO_GROUP(GPIODV_22),
583 GPIO_GROUP(GPIODV_23),
584 GPIO_GROUP(GPIODV_24),
585 GPIO_GROUP(GPIODV_25),
586 GPIO_GROUP(GPIODV_26),
587 GPIO_GROUP(GPIODV_27),
588 GPIO_GROUP(GPIODV_28),
589 GPIO_GROUP(GPIODV_29),
590 GPIO_GROUP(GPIOH_0),
591 GPIO_GROUP(GPIOH_1),
592 GPIO_GROUP(GPIOH_2),
593 GPIO_GROUP(GPIOH_3),
594 GPIO_GROUP(GPIOH_4),
595 GPIO_GROUP(GPIOH_5),
596 GPIO_GROUP(GPIOH_6),
597 GPIO_GROUP(GPIOH_7),
598 GPIO_GROUP(GPIOH_8),
599 GPIO_GROUP(GPIOH_9),
600 GPIO_GROUP(GPIOZ_0),
601 GPIO_GROUP(GPIOZ_1),
602 GPIO_GROUP(GPIOZ_2),
603 GPIO_GROUP(GPIOZ_3),
604 GPIO_GROUP(GPIOZ_4),
605 GPIO_GROUP(GPIOZ_5),
606 GPIO_GROUP(GPIOZ_6),
607 GPIO_GROUP(GPIOZ_7),
608 GPIO_GROUP(GPIOZ_8),
609 GPIO_GROUP(GPIOZ_9),
610 GPIO_GROUP(GPIOZ_10),
611 GPIO_GROUP(GPIOZ_11),
612 GPIO_GROUP(GPIOZ_12),
613 GPIO_GROUP(GPIOZ_13),
614 GPIO_GROUP(GPIOZ_14),
615 GPIO_GROUP(GPIOAO_0),
616 GPIO_GROUP(GPIOAO_1),
617 GPIO_GROUP(GPIOAO_2),
618 GPIO_GROUP(GPIOAO_3),
619 GPIO_GROUP(GPIOAO_4),
620 GPIO_GROUP(GPIOAO_5),
621 GPIO_GROUP(GPIOAO_6),
622 GPIO_GROUP(GPIOAO_7),
623 GPIO_GROUP(GPIOAO_8),
624 GPIO_GROUP(GPIOAO_9),
625 GPIO_GROUP(GPIOAO_10),
626 GPIO_GROUP(GPIOAO_11),
627 GPIO_GROUP(GPIOAO_12),
628 GPIO_GROUP(GPIOAO_13),
629 GPIO_GROUP(GPIO_BSD_EN),
630 GPIO_GROUP(GPIO_TEST_N),
631
632 /* bank X */
633 GROUP(sd_d0_a, 8, 5),
634 GROUP(sd_d1_a, 8, 4),
635 GROUP(sd_d2_a, 8, 3),
636 GROUP(sd_d3_a, 8, 2),
637 GROUP(sd_clk_a, 8, 1),
638 GROUP(sd_cmd_a, 8, 0),
639
640 GROUP(sdxc_d0_a, 5, 14),
641 GROUP(sdxc_d13_a, 5, 13),
642 GROUP(sdxc_d47_a, 5, 12),
643 GROUP(sdxc_clk_a, 5, 11),
644 GROUP(sdxc_cmd_a, 5, 10),
645
646 GROUP(pcm_out_a, 3, 30),
647 GROUP(pcm_in_a, 3, 29),
648 GROUP(pcm_fs_a, 3, 28),
649 GROUP(pcm_clk_a, 3, 27),
650
651 GROUP(uart_tx_a0, 4, 17),
652 GROUP(uart_rx_a0, 4, 16),
653 GROUP(uart_cts_a0, 4, 15),
654 GROUP(uart_rts_a0, 4, 14),
655
656 GROUP(uart_tx_a1, 4, 13),
657 GROUP(uart_rx_a1, 4, 12),
658 GROUP(uart_cts_a1, 4, 11),
659 GROUP(uart_rts_a1, 4, 10),
660
661 GROUP(uart_tx_b0, 4, 9),
662 GROUP(uart_rx_b0, 4, 8),
663 GROUP(uart_cts_b0, 4, 7),
664 GROUP(uart_rts_b0, 4, 6),
665
666 GROUP(iso7816_det, 4, 21),
667 GROUP(iso7816_reset, 4, 20),
668 GROUP(iso7816_clk, 4, 19),
669 GROUP(iso7816_data, 4, 18),
670
671 GROUP(i2c_sda_d0, 4, 5),
672 GROUP(i2c_sck_d0, 4, 4),
673
674 GROUP(xtal_32k_out, 3, 22),
675 GROUP(xtal_24m_out, 3, 23),
676
677 /* bank Y */
678 GROUP(uart_tx_c, 1, 19),
679 GROUP(uart_rx_c, 1, 18),
680 GROUP(uart_cts_c, 1, 17),
681 GROUP(uart_rts_c, 1, 16),
682
683 GROUP(pcm_out_b, 4, 25),
684 GROUP(pcm_in_b, 4, 24),
685 GROUP(pcm_fs_b, 4, 23),
686 GROUP(pcm_clk_b, 4, 22),
687
688 GROUP(i2c_sda_c0, 1, 15),
689 GROUP(i2c_sck_c0, 1, 14),
690
691 /* bank DV */
692 GROUP(dvin_rgb, 0, 6),
693 GROUP(dvin_vs, 0, 9),
694 GROUP(dvin_hs, 0, 8),
695 GROUP(dvin_clk, 0, 7),
696 GROUP(dvin_de, 0, 10),
697
698 GROUP(enc_0, 7, 0),
699 GROUP(enc_1, 7, 1),
700 GROUP(enc_2, 7, 2),
701 GROUP(enc_3, 7, 3),
702 GROUP(enc_4, 7, 4),
703 GROUP(enc_5, 7, 5),
704 GROUP(enc_6, 7, 6),
705 GROUP(enc_7, 7, 7),
706 GROUP(enc_8, 7, 8),
707 GROUP(enc_9, 7, 9),
708 GROUP(enc_10, 7, 10),
709 GROUP(enc_11, 7, 11),
710 GROUP(enc_12, 7, 12),
711 GROUP(enc_13, 7, 13),
712 GROUP(enc_14, 7, 14),
713 GROUP(enc_15, 7, 15),
714 GROUP(enc_16, 7, 16),
715 GROUP(enc_17, 7, 17),
716
717 GROUP(uart_tx_b1, 6, 23),
718 GROUP(uart_rx_b1, 6, 22),
719 GROUP(uart_cts_b1, 6, 21),
720 GROUP(uart_rts_b1, 6, 20),
721
722 GROUP(vga_vs, 0, 21),
723 GROUP(vga_hs, 0, 20),
724
725 /* bank H */
726 GROUP(hdmi_hpd, 1, 26),
727 GROUP(hdmi_sda, 1, 25),
728 GROUP(hdmi_scl, 1, 24),
729 GROUP(hdmi_cec, 1, 23),
730
731 GROUP(spi_ss0_0, 9, 13),
732 GROUP(spi_miso_0, 9, 12),
733 GROUP(spi_mosi_0, 9, 11),
734 GROUP(spi_sclk_0, 9, 10),
735
736 GROUP(i2c_sda_d1, 4, 3),
737 GROUP(i2c_sck_d1, 4, 2),
738
739 /* bank Z */
740 GROUP(spi_ss0_1, 8, 16),
741 GROUP(spi_ss1_1, 8, 12),
742 GROUP(spi_sclk_1, 8, 15),
743 GROUP(spi_mosi_1, 8, 14),
744 GROUP(spi_miso_1, 8, 13),
745 GROUP(spi_ss2_1, 8, 17),
746
747 GROUP(eth_tx_clk_50m, 6, 15),
748 GROUP(eth_tx_en, 6, 14),
749 GROUP(eth_txd1, 6, 13),
750 GROUP(eth_txd0, 6, 12),
751 GROUP(eth_rx_clk_in, 6, 10),
752 GROUP(eth_rx_dv, 6, 11),
753 GROUP(eth_rxd1, 6, 8),
754 GROUP(eth_rxd0, 6, 7),
755 GROUP(eth_mdio, 6, 6),
756 GROUP(eth_mdc, 6, 5),
757
758 GROUP(i2c_sda_a0, 5, 31),
759 GROUP(i2c_sck_a0, 5, 30),
760
761 GROUP(i2c_sda_b, 5, 27),
762 GROUP(i2c_sck_b, 5, 26),
763
764 GROUP(i2c_sda_c1, 5, 25),
765 GROUP(i2c_sck_c1, 5, 24),
766
767 GROUP(i2c_sda_a1, 5, 9),
768 GROUP(i2c_sck_a1, 5, 8),
769
770 GROUP(i2c_sda_a2, 5, 7),
771 GROUP(i2c_sck_a2, 5, 6),
772
773 /* bank BOOT */
774 GROUP(sd_d0_c, 6, 29),
775 GROUP(sd_d1_c, 6, 28),
776 GROUP(sd_d2_c, 6, 27),
777 GROUP(sd_d3_c, 6, 26),
778 GROUP(sd_cmd_c, 6, 25),
779 GROUP(sd_clk_c, 6, 24),
780
781 GROUP(sdxc_d0_c, 4, 30),
782 GROUP(sdxc_d13_c, 4, 29),
783 GROUP(sdxc_d47_c, 4, 28),
784 GROUP(sdxc_cmd_c, 4, 27),
785 GROUP(sdxc_clk_c, 4, 26),
786
787 GROUP(nand_io, 2, 26),
788 GROUP(nand_io_ce0, 2, 25),
789 GROUP(nand_io_ce1, 2, 24),
790 GROUP(nand_io_rb0, 2, 17),
791 GROUP(nand_ale, 2, 21),
792 GROUP(nand_cle, 2, 20),
793 GROUP(nand_wen_clk, 2, 19),
794 GROUP(nand_ren_clk, 2, 18),
795 GROUP(nand_dqs, 2, 27),
796 GROUP(nand_ce2, 2, 23),
797 GROUP(nand_ce3, 2, 22),
798
799 GROUP(nor_d, 5, 1),
800 GROUP(nor_q, 5, 3),
801 GROUP(nor_c, 5, 2),
802 GROUP(nor_cs, 5, 0),
803
804 /* bank CARD */
805 GROUP(sd_d1_b, 2, 14),
806 GROUP(sd_d0_b, 2, 15),
807 GROUP(sd_clk_b, 2, 11),
808 GROUP(sd_cmd_b, 2, 10),
809 GROUP(sd_d3_b, 2, 12),
810 GROUP(sd_d2_b, 2, 13),
811
812 GROUP(sdxc_d13_b, 2, 6),
813 GROUP(sdxc_d0_b, 2, 7),
814 GROUP(sdxc_clk_b, 2, 5),
815 GROUP(sdxc_cmd_b, 2, 4),
816
817 /* bank AO */
818 GROUP_AO(uart_tx_ao_a, 0, 12),
819 GROUP_AO(uart_rx_ao_a, 0, 11),
820 GROUP_AO(uart_cts_ao_a, 0, 10),
821 GROUP_AO(uart_rts_ao_a, 0, 9),
822
823 GROUP_AO(remote_input, 0, 0),
824
825 GROUP_AO(i2c_slave_sck_ao, 0, 2),
826 GROUP_AO(i2c_slave_sda_ao, 0, 1),
827
828 GROUP_AO(uart_tx_ao_b0, 0, 26),
829 GROUP_AO(uart_rx_ao_b0, 0, 25),
830
831 GROUP_AO(uart_tx_ao_b1, 0, 24),
832 GROUP_AO(uart_rx_ao_b1, 0, 23),
833
834 GROUP_AO(i2c_mst_sck_ao, 0, 6),
835 GROUP_AO(i2c_mst_sda_ao, 0, 5),
836};
837
838static const char * const gpio_groups[] = {
839 "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
840 "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
841 "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
842 "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19",
843 "GPIOX_20", "GPIOX_21",
844
845 "GPIOY_0", "GPIOY_1", "GPIOY_2", "GPIOY_3", "GPIOY_4",
846 "GPIOY_5", "GPIOY_6", "GPIOY_7", "GPIOY_8", "GPIOY_9",
847 "GPIOY_10", "GPIOY_11", "GPIOY_12", "GPIOY_13", "GPIOY_14",
848 "GPIOY_15", "GPIOY_16",
849
850 "GPIODV_0", "GPIODV_1", "GPIODV_2", "GPIODV_3", "GPIODV_4",
851 "GPIODV_5", "GPIODV_6", "GPIODV_7", "GPIODV_8", "GPIODV_9",
852 "GPIODV_10", "GPIODV_11", "GPIODV_12", "GPIODV_13", "GPIODV_14",
853 "GPIODV_15", "GPIODV_16", "GPIODV_17", "GPIODV_18", "GPIODV_19",
854 "GPIODV_20", "GPIODV_21", "GPIODV_22", "GPIODV_23", "GPIODV_24",
855 "GPIODV_25", "GPIODV_26", "GPIODV_27", "GPIODV_28", "GPIODV_29",
856
857 "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4",
858 "GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9",
859
860 "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4",
861 "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9",
862 "GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13", "GPIOZ_14",
863
864 "CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4",
865 "CARD_5", "CARD_6",
866
867 "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4",
868 "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9",
869 "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14",
870 "BOOT_15", "BOOT_16", "BOOT_17", "BOOT_18",
871
872 "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3",
873 "GPIOAO_4", "GPIOAO_5", "GPIOAO_6", "GPIOAO_7",
874 "GPIOAO_8", "GPIOAO_9", "GPIOAO_10", "GPIOAO_11",
875 "GPIOAO_12", "GPIOAO_13", "GPIO_BSD_EN", "GPIO_TEST_N"
876};
877
878static const char * const sd_a_groups[] = {
879 "sd_d0_a", "sd_d1_a", "sd_d2_a", "sd_d3_a", "sd_clk_a", "sd_cmd_a"
880};
881
882static const char * const sdxc_a_groups[] = {
883 "sdxc_d0_a", "sdxc_d13_a", "sdxc_d47_a", "sdxc_clk_a", "sdxc_cmd_a"
884};
885
886static const char * const pcm_a_groups[] = {
887 "pcm_out_a", "pcm_in_a", "pcm_fs_a", "pcm_clk_a"
888};
889
890static const char * const uart_a_groups[] = {
891 "uart_tx_a0", "uart_rx_a0", "uart_cts_a0", "uart_rts_a0",
892 "uart_tx_a1", "uart_rx_a1", "uart_cts_a1", "uart_rts_a1"
893};
894
895static const char * const uart_b_groups[] = {
896 "uart_tx_b0", "uart_rx_b0", "uart_cts_b0", "uart_rts_b0",
897 "uart_tx_b1", "uart_rx_b1", "uart_cts_b1", "uart_rts_b1"
898};
899
900static const char * const iso7816_groups[] = {
901 "iso7816_det", "iso7816_reset", "iso7816_clk", "iso7816_data"
902};
903
904static const char * const i2c_d_groups[] = {
905 "i2c_sda_d0", "i2c_sck_d0", "i2c_sda_d1", "i2c_sck_d1"
906};
907
908static const char * const xtal_groups[] = {
909 "xtal_32k_out", "xtal_24m_out"
910};
911
912static const char * const uart_c_groups[] = {
913 "uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c"
914};
915
916static const char * const pcm_b_groups[] = {
917 "pcm_out_b", "pcm_in_b", "pcm_fs_b", "pcm_clk_b"
918};
919
920static const char * const i2c_c_groups[] = {
921 "i2c_sda_c0", "i2c_sck_c0", "i2c_sda_c1", "i2c_sck_c1"
922};
923
924static const char * const dvin_groups[] = {
925 "dvin_rgb", "dvin_vs", "dvin_hs", "dvin_clk", "dvin_de"
926};
927
928static const char * const enc_groups[] = {
929 "enc_0", "enc_1", "enc_2", "enc_3", "enc_4", "enc_5",
930 "enc_6", "enc_7", "enc_8", "enc_9", "enc_10", "enc_11",
931 "enc_12", "enc_13", "enc_14", "enc_15", "enc_16", "enc_17"
932};
933
934static const char * const vga_groups[] = {
935 "vga_vs", "vga_hs"
936};
937
938static const char * const hdmi_groups[] = {
939 "hdmi_hpd", "hdmi_sda", "hdmi_scl", "hdmi_cec"
940};
941
942static const char * const spi_groups[] = {
943 "spi_ss0_0", "spi_miso_0", "spi_mosi_0", "spi_sclk_0",
944 "spi_ss0_1", "spi_ss1_1", "spi_sclk_1", "spi_mosi_1",
945 "spi_miso_1", "spi_ss2_1"
946};
947
948static const char * const ethernet_groups[] = {
949 "eth_tx_clk_50m", "eth_tx_en", "eth_txd1",
950 "eth_txd0", "eth_rx_clk_in", "eth_rx_dv",
951 "eth_rxd1", "eth_rxd0", "eth_mdio", "eth_mdc"
952};
953
954static const char * const i2c_a_groups[] = {
955 "i2c_sda_a0", "i2c_sck_a0", "i2c_sda_a1", "i2c_sck_a1",
956 "i2c_sda_a2", "i2c_sck_a2"
957};
958
959static const char * const i2c_b_groups[] = {
960 "i2c_sda_b", "i2c_sck_b"
961};
962
963static const char * const sd_c_groups[] = {
964 "sd_d0_c", "sd_d1_c", "sd_d2_c", "sd_d3_c",
965 "sd_cmd_c", "sd_clk_c"
966};
967
968static const char * const sdxc_c_groups[] = {
969 "sdxc_d0_c", "sdxc_d13_c", "sdxc_d47_c", "sdxc_cmd_c",
970 "sdxc_clk_c"
971};
972
973static const char * const nand_groups[] = {
974 "nand_io", "nand_io_ce0", "nand_io_ce1",
975 "nand_io_rb0", "nand_ale", "nand_cle",
976 "nand_wen_clk", "nand_ren_clk", "nand_dqs",
977 "nand_ce2", "nand_ce3"
978};
979
980static const char * const nor_groups[] = {
981 "nor_d", "nor_q", "nor_c", "nor_cs"
982};
983
984static const char * const sd_b_groups[] = {
985 "sd_d1_b", "sd_d0_b", "sd_clk_b", "sd_cmd_b",
986 "sd_d3_b", "sd_d2_b"
987};
988
989static const char * const sdxc_b_groups[] = {
990 "sdxc_d13_b", "sdxc_d0_b", "sdxc_clk_b", "sdxc_cmd_b"
991};
992
993static const char * const uart_ao_groups[] = {
994 "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a"
995};
996
997static const char * const remote_groups[] = {
998 "remote_input"
999};
1000
1001static const char * const i2c_slave_ao_groups[] = {
1002 "i2c_slave_sck_ao", "i2c_slave_sda_ao"
1003};
1004
1005static const char * const uart_ao_b_groups[] = {
1006 "uart_tx_ao_b0", "uart_rx_ao_b0", "uart_tx_ao_b1", "uart_rx_ao_b1"
1007};
1008
1009static const char * const i2c_mst_ao_groups[] = {
1010 "i2c_mst_sck_ao", "i2c_mst_sda_ao"
1011};
1012
1013static struct meson_pmx_func meson8_functions[] = {
1014 FUNCTION(gpio),
1015 FUNCTION(sd_a),
1016 FUNCTION(sdxc_a),
1017 FUNCTION(pcm_a),
1018 FUNCTION(uart_a),
1019 FUNCTION(uart_b),
1020 FUNCTION(iso7816),
1021 FUNCTION(i2c_d),
1022 FUNCTION(xtal),
1023 FUNCTION(uart_c),
1024 FUNCTION(pcm_b),
1025 FUNCTION(i2c_c),
1026 FUNCTION(dvin),
1027 FUNCTION(enc),
1028 FUNCTION(vga),
1029 FUNCTION(hdmi),
1030 FUNCTION(spi),
1031 FUNCTION(ethernet),
1032 FUNCTION(i2c_a),
1033 FUNCTION(i2c_b),
1034 FUNCTION(sd_c),
1035 FUNCTION(sdxc_c),
1036 FUNCTION(nand),
1037 FUNCTION(nor),
1038 FUNCTION(sd_b),
1039 FUNCTION(sdxc_b),
1040 FUNCTION(uart_ao),
1041 FUNCTION(remote),
1042 FUNCTION(i2c_slave_ao),
1043 FUNCTION(uart_ao_b),
1044 FUNCTION(i2c_mst_ao),
1045};
1046
1047static struct meson_bank meson8_banks[] = {
1048 /* name first last pullen pull dir out in */
1049 BANK("X", PIN_GPIOX_0, PIN_GPIOX_21, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
1050 BANK("Y", PIN_GPIOY_0, PIN_GPIOY_16, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0),
1051 BANK("DV", PIN_GPIODV_0, PIN_GPIODV_29, 0, 0, 0, 0, 7, 0, 8, 0, 9, 0),
1052 BANK("H", PIN_GPIOH_0, PIN_GPIOH_9, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19),
1053 BANK("Z", PIN_GPIOZ_0, PIN_GPIOZ_14, 1, 0, 1, 0, 3, 17, 4, 17, 5, 17),
1054 BANK("CARD", PIN_CARD_0, PIN_CARD_6, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22),
1055 BANK("BOOT", PIN_BOOT_0, PIN_BOOT_18, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0),
1056};
1057
1058static struct meson_bank meson8_ao_banks[] = {
1059 /* name first last pullen pull dir out in */
1060 BANK("AO", PIN_GPIOAO_0, PIN_GPIO_TEST_N, 0, 0, 0, 16, 0, 0, 0, 16, 1, 0),
1061};
1062
1063static struct meson_domain_data meson8_domain_data[] = {
1064 {
1065 .name = "banks",
1066 .banks = meson8_banks,
1067 .num_banks = ARRAY_SIZE(meson8_banks),
1068 .pin_base = 0,
1069 .num_pins = 120,
1070 },
1071 {
1072 .name = "ao-bank",
1073 .banks = meson8_ao_banks,
1074 .num_banks = ARRAY_SIZE(meson8_ao_banks),
1075 .pin_base = 120,
1076 .num_pins = 16,
1077 },
1078};
1079
1080struct meson_pinctrl_data meson8_pinctrl_data = {
1081 .pins = meson8_pins,
1082 .groups = meson8_groups,
1083 .funcs = meson8_functions,
1084 .domain_data = meson8_domain_data,
1085 .num_pins = ARRAY_SIZE(meson8_pins),
1086 .num_groups = ARRAY_SIZE(meson8_groups),
1087 .num_funcs = ARRAY_SIZE(meson8_functions),
1088 .num_domains = ARRAY_SIZE(meson8_domain_data),
1089};
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c
index 224c6cff6aa2..7302f66f4f19 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c
@@ -145,14 +145,16 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = {
145 MPP_VAR_FUNCTION(2, "ptp", "event_req", V_88F6810_PLUS), 145 MPP_VAR_FUNCTION(2, "ptp", "event_req", V_88F6810_PLUS),
146 MPP_VAR_FUNCTION(3, "pcie0", "clkreq", V_88F6810_PLUS), 146 MPP_VAR_FUNCTION(3, "pcie0", "clkreq", V_88F6810_PLUS),
147 MPP_VAR_FUNCTION(4, "sata1", "prsnt", V_88F6810_PLUS), 147 MPP_VAR_FUNCTION(4, "sata1", "prsnt", V_88F6810_PLUS),
148 MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6810_PLUS)), 148 MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6810_PLUS),
149 MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6810_PLUS)),
149 MPP_MODE(20, 150 MPP_MODE(20,
150 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), 151 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
151 MPP_VAR_FUNCTION(1, "ge0", "txclk", V_88F6810_PLUS), 152 MPP_VAR_FUNCTION(1, "ge0", "txclk", V_88F6810_PLUS),
152 MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS), 153 MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS),
153 MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS), 154 MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS),
154 MPP_VAR_FUNCTION(4, "sata0", "prsnt", V_88F6810_PLUS), 155 MPP_VAR_FUNCTION(4, "sata0", "prsnt", V_88F6810_PLUS),
155 MPP_VAR_FUNCTION(5, "ua0", "rts", V_88F6810_PLUS)), 156 MPP_VAR_FUNCTION(5, "ua0", "rts", V_88F6810_PLUS),
157 MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6810_PLUS)),
156 MPP_MODE(21, 158 MPP_MODE(21,
157 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS), 159 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
158 MPP_VAR_FUNCTION(1, "spi0", "cs1", V_88F6810_PLUS), 160 MPP_VAR_FUNCTION(1, "spi0", "cs1", V_88F6810_PLUS),
diff --git a/drivers/pinctrl/mvebu/pinctrl-dove.c b/drivers/pinctrl/mvebu/pinctrl-dove.c
index 89a52e15f0ae..95bfd0653e8f 100644
--- a/drivers/pinctrl/mvebu/pinctrl-dove.c
+++ b/drivers/pinctrl/mvebu/pinctrl-dove.c
@@ -751,12 +751,12 @@ static struct mvebu_pinctrl_soc_info dove_pinctrl_info = {
751 751
752static struct clk *clk; 752static struct clk *clk;
753 753
754static struct of_device_id dove_pinctrl_of_match[] = { 754static const struct of_device_id dove_pinctrl_of_match[] = {
755 { .compatible = "marvell,dove-pinctrl", .data = &dove_pinctrl_info }, 755 { .compatible = "marvell,dove-pinctrl", .data = &dove_pinctrl_info },
756 { } 756 { }
757}; 757};
758 758
759static struct regmap_config gc_regmap_config = { 759static const struct regmap_config gc_regmap_config = {
760 .reg_bits = 32, 760 .reg_bits = 32,
761 .val_bits = 32, 761 .val_bits = 32,
762 .reg_stride = 4, 762 .reg_stride = 4,
diff --git a/drivers/pinctrl/nomadik/pinctrl-abx500.c b/drivers/pinctrl/nomadik/pinctrl-abx500.c
index 3d6d97228523..1806b24faa14 100644
--- a/drivers/pinctrl/nomadik/pinctrl-abx500.c
+++ b/drivers/pinctrl/nomadik/pinctrl-abx500.c
@@ -914,7 +914,7 @@ static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev,
914 } 914 }
915 } 915 }
916 916
917 ret = pinconf_generic_parse_dt_config(np, &configs, &nconfigs); 917 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &nconfigs);
918 if (nconfigs) { 918 if (nconfigs) {
919 const char *gpio_name; 919 const char *gpio_name;
920 const char *pin; 920 const char *pin;
diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c
index f78b416d7984..4db92f64b4de 100644
--- a/drivers/pinctrl/pinconf-generic.c
+++ b/drivers/pinctrl/pinconf-generic.c
@@ -27,17 +27,6 @@
27#include "pinctrl-utils.h" 27#include "pinctrl-utils.h"
28 28
29#ifdef CONFIG_DEBUG_FS 29#ifdef CONFIG_DEBUG_FS
30
31struct pin_config_item {
32 const enum pin_config_param param;
33 const char * const display;
34 const char * const format;
35 bool has_arg;
36};
37
38#define PCONFDUMP(a, b, c, d) { .param = a, .display = b, .format = c, \
39 .has_arg = d }
40
41static const struct pin_config_item conf_items[] = { 30static const struct pin_config_item conf_items[] = {
42 PCONFDUMP(PIN_CONFIG_BIAS_DISABLE, "input bias disabled", NULL, false), 31 PCONFDUMP(PIN_CONFIG_BIAS_DISABLE, "input bias disabled", NULL, false),
43 PCONFDUMP(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, "input bias high impedance", NULL, false), 32 PCONFDUMP(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, "input bias high impedance", NULL, false),
@@ -60,22 +49,25 @@ static const struct pin_config_item conf_items[] = {
60 PCONFDUMP(PIN_CONFIG_OUTPUT, "pin output", "level", true), 49 PCONFDUMP(PIN_CONFIG_OUTPUT, "pin output", "level", true),
61}; 50};
62 51
63void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev, 52static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev,
64 struct seq_file *s, unsigned pin) 53 struct seq_file *s, const char *gname,
54 unsigned pin,
55 const struct pin_config_item *items,
56 int nitems)
65{ 57{
66 const struct pinconf_ops *ops = pctldev->desc->confops;
67 int i; 58 int i;
68 59
69 if (!ops->is_generic) 60 for (i = 0; i < nitems; i++) {
70 return;
71
72 for (i = 0; i < ARRAY_SIZE(conf_items); i++) {
73 unsigned long config; 61 unsigned long config;
74 int ret; 62 int ret;
75 63
76 /* We want to check out this parameter */ 64 /* We want to check out this parameter */
77 config = pinconf_to_config_packed(conf_items[i].param, 0); 65 config = pinconf_to_config_packed(items[i].param, 0);
78 ret = pin_config_get_for_pin(pctldev, pin, &config); 66 if (gname)
67 ret = pin_config_group_get(dev_name(pctldev->dev),
68 gname, &config);
69 else
70 ret = pin_config_get_for_pin(pctldev, pin, &config);
79 /* These are legal errors */ 71 /* These are legal errors */
80 if (ret == -EINVAL || ret == -ENOTSUPP) 72 if (ret == -EINVAL || ret == -ENOTSUPP)
81 continue; 73 continue;
@@ -85,56 +77,47 @@ void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev,
85 } 77 }
86 /* Space between multiple configs */ 78 /* Space between multiple configs */
87 seq_puts(s, " "); 79 seq_puts(s, " ");
88 seq_puts(s, conf_items[i].display); 80 seq_puts(s, items[i].display);
89 /* Print unit if available */ 81 /* Print unit if available */
90 if (conf_items[i].has_arg) { 82 if (items[i].has_arg) {
91 seq_printf(s, " (%u", 83 seq_printf(s, " (%u",
92 pinconf_to_config_argument(config)); 84 pinconf_to_config_argument(config));
93 if (conf_items[i].format) 85 if (items[i].format)
94 seq_printf(s, " %s)", conf_items[i].format); 86 seq_printf(s, " %s)", items[i].format);
95 else 87 else
96 seq_puts(s, ")"); 88 seq_puts(s, ")");
97 } 89 }
98 } 90 }
99} 91}
100 92
101void pinconf_generic_dump_group(struct pinctrl_dev *pctldev, 93/**
102 struct seq_file *s, const char *gname) 94 * pinconf_generic_dump_pins - Print information about pin or group of pins
95 * @pctldev: Pincontrol device
96 * @s: File to print to
97 * @gname: Group name specifying pins
98 * @pin: Pin number specyfying pin
99 *
100 * Print the pinconf configuration for the requested pin(s) to @s. Pins can be
101 * specified either by pin using @pin or by group using @gname. Only one needs
102 * to be specified the other can be NULL/0.
103 */
104void pinconf_generic_dump_pins(struct pinctrl_dev *pctldev, struct seq_file *s,
105 const char *gname, unsigned pin)
103{ 106{
104 const struct pinconf_ops *ops = pctldev->desc->confops; 107 const struct pinconf_ops *ops = pctldev->desc->confops;
105 int i;
106 108
107 if (!ops->is_generic) 109 if (!ops->is_generic)
108 return; 110 return;
109 111
110 for (i = 0; i < ARRAY_SIZE(conf_items); i++) { 112 /* generic parameters */
111 unsigned long config; 113 pinconf_generic_dump_one(pctldev, s, gname, pin, conf_items,
112 int ret; 114 ARRAY_SIZE(conf_items));
113 115 /* driver-specific parameters */
114 /* We want to check out this parameter */ 116 if (pctldev->desc->num_custom_params &&
115 config = pinconf_to_config_packed(conf_items[i].param, 0); 117 pctldev->desc->custom_conf_items)
116 ret = pin_config_group_get(dev_name(pctldev->dev), gname, 118 pinconf_generic_dump_one(pctldev, s, gname, pin,
117 &config); 119 pctldev->desc->custom_conf_items,
118 /* These are legal errors */ 120 pctldev->desc->num_custom_params);
119 if (ret == -EINVAL || ret == -ENOTSUPP)
120 continue;
121 if (ret) {
122 seq_printf(s, "ERROR READING CONFIG SETTING %d ", i);
123 continue;
124 }
125 /* Space between multiple configs */
126 seq_puts(s, " ");
127 seq_puts(s, conf_items[i].display);
128 /* Print unit if available */
129 if (conf_items[i].has_arg) {
130 seq_printf(s, " (%u",
131 pinconf_to_config_argument(config));
132 if (conf_items[i].format)
133 seq_printf(s, " %s)", conf_items[i].format);
134 else
135 seq_puts(s, ")");
136 }
137 }
138} 121}
139 122
140void pinconf_generic_dump_config(struct pinctrl_dev *pctldev, 123void pinconf_generic_dump_config(struct pinctrl_dev *pctldev,
@@ -148,18 +131,25 @@ void pinconf_generic_dump_config(struct pinctrl_dev *pctldev,
148 seq_printf(s, "%s: 0x%x", conf_items[i].display, 131 seq_printf(s, "%s: 0x%x", conf_items[i].display,
149 pinconf_to_config_argument(config)); 132 pinconf_to_config_argument(config));
150 } 133 }
134
135 if (!pctldev->desc->num_custom_params ||
136 !pctldev->desc->custom_conf_items)
137 return;
138
139 for (i = 0; i < pctldev->desc->num_custom_params; i++) {
140 if (pinconf_to_config_param(config) !=
141 pctldev->desc->custom_conf_items[i].param)
142 continue;
143 seq_printf(s, "%s: 0x%x",
144 pctldev->desc->custom_conf_items[i].display,
145 pinconf_to_config_argument(config));
146 }
151} 147}
152EXPORT_SYMBOL_GPL(pinconf_generic_dump_config); 148EXPORT_SYMBOL_GPL(pinconf_generic_dump_config);
153#endif 149#endif
154 150
155#ifdef CONFIG_OF 151#ifdef CONFIG_OF
156struct pinconf_generic_dt_params { 152static const struct pinconf_generic_params dt_params[] = {
157 const char * const property;
158 enum pin_config_param param;
159 u32 default_value;
160};
161
162static const struct pinconf_generic_dt_params dt_params[] = {
163 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, 153 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
164 { "bias-high-impedance", PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0 }, 154 { "bias-high-impedance", PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0 },
165 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, 155 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 },
@@ -184,6 +174,47 @@ static const struct pinconf_generic_dt_params dt_params[] = {
184}; 174};
185 175
186/** 176/**
177 * parse_dt_cfg() - Parse DT pinconf parameters
178 * @np: DT node
179 * @params: Array of describing generic parameters
180 * @count: Number of entries in @params
181 * @cfg: Array of parsed config options
182 * @ncfg: Number of entries in @cfg
183 *
184 * Parse the config options described in @params from @np and puts the result
185 * in @cfg. @cfg does not need to be empty, entries are added beggining at
186 * @ncfg. @ncfg is updated to reflect the number of entries after parsing. @cfg
187 * needs to have enough memory allocated to hold all possible entries.
188 */
189static void parse_dt_cfg(struct device_node *np,
190 const struct pinconf_generic_params *params,
191 unsigned int count, unsigned long *cfg,
192 unsigned int *ncfg)
193{
194 int i;
195
196 for (i = 0; i < count; i++) {
197 u32 val;
198 int ret;
199 const struct pinconf_generic_params *par = &params[i];
200
201 ret = of_property_read_u32(np, par->property, &val);
202
203 /* property not found */
204 if (ret == -EINVAL)
205 continue;
206
207 /* use default value, when no value is specified */
208 if (ret)
209 val = par->default_value;
210
211 pr_debug("found %s with value %u\n", par->property, val);
212 cfg[*ncfg] = pinconf_to_config_packed(par->param, val);
213 (*ncfg)++;
214 }
215}
216
217/**
187 * pinconf_generic_parse_dt_config() 218 * pinconf_generic_parse_dt_config()
188 * parse the config properties into generic pinconfig values. 219 * parse the config properties into generic pinconfig values.
189 * @np: node containing the pinconfig properties 220 * @np: node containing the pinconfig properties
@@ -191,39 +222,30 @@ static const struct pinconf_generic_dt_params dt_params[] = {
191 * @nconfigs: umber of configurations 222 * @nconfigs: umber of configurations
192 */ 223 */
193int pinconf_generic_parse_dt_config(struct device_node *np, 224int pinconf_generic_parse_dt_config(struct device_node *np,
225 struct pinctrl_dev *pctldev,
194 unsigned long **configs, 226 unsigned long **configs,
195 unsigned int *nconfigs) 227 unsigned int *nconfigs)
196{ 228{
197 unsigned long *cfg; 229 unsigned long *cfg;
198 unsigned int ncfg = 0; 230 unsigned int max_cfg, ncfg = 0;
199 int ret; 231 int ret;
200 int i;
201 u32 val;
202 232
203 if (!np) 233 if (!np)
204 return -EINVAL; 234 return -EINVAL;
205 235
206 /* allocate a temporary array big enough to hold one of each option */ 236 /* allocate a temporary array big enough to hold one of each option */
207 cfg = kzalloc(sizeof(*cfg) * ARRAY_SIZE(dt_params), GFP_KERNEL); 237 max_cfg = ARRAY_SIZE(dt_params);
238 if (pctldev)
239 max_cfg += pctldev->desc->num_custom_params;
240 cfg = kcalloc(max_cfg, sizeof(*cfg), GFP_KERNEL);
208 if (!cfg) 241 if (!cfg)
209 return -ENOMEM; 242 return -ENOMEM;
210 243
211 for (i = 0; i < ARRAY_SIZE(dt_params); i++) { 244 parse_dt_cfg(np, dt_params, ARRAY_SIZE(dt_params), cfg, &ncfg);
212 const struct pinconf_generic_dt_params *par = &dt_params[i]; 245 if (pctldev && pctldev->desc->num_custom_params &&
213 ret = of_property_read_u32(np, par->property, &val); 246 pctldev->desc->custom_params)
214 247 parse_dt_cfg(np, pctldev->desc->custom_params,
215 /* property not found */ 248 pctldev->desc->num_custom_params, cfg, &ncfg);
216 if (ret == -EINVAL)
217 continue;
218
219 /* use default value, when no value is specified */
220 if (ret)
221 val = par->default_value;
222
223 pr_debug("found %s with value %u\n", par->property, val);
224 cfg[ncfg] = pinconf_to_config_packed(par->param, val);
225 ncfg++;
226 }
227 249
228 ret = 0; 250 ret = 0;
229 251
@@ -264,6 +286,7 @@ int pinconf_generic_dt_subnode_to_map(struct pinctrl_dev *pctldev,
264 unsigned reserve; 286 unsigned reserve;
265 struct property *prop; 287 struct property *prop;
266 const char *group; 288 const char *group;
289 const char *subnode_target_type = "pins";
267 290
268 ret = of_property_read_string(np, "function", &function); 291 ret = of_property_read_string(np, "function", &function);
269 if (ret < 0) { 292 if (ret < 0) {
@@ -273,7 +296,8 @@ int pinconf_generic_dt_subnode_to_map(struct pinctrl_dev *pctldev,
273 function = NULL; 296 function = NULL;
274 } 297 }
275 298
276 ret = pinconf_generic_parse_dt_config(np, &configs, &num_configs); 299 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
300 &num_configs);
277 if (ret < 0) { 301 if (ret < 0) {
278 dev_err(dev, "could not parse node property\n"); 302 dev_err(dev, "could not parse node property\n");
279 return ret; 303 return ret;
@@ -284,10 +308,20 @@ int pinconf_generic_dt_subnode_to_map(struct pinctrl_dev *pctldev,
284 reserve++; 308 reserve++;
285 if (num_configs) 309 if (num_configs)
286 reserve++; 310 reserve++;
311
287 ret = of_property_count_strings(np, "pins"); 312 ret = of_property_count_strings(np, "pins");
288 if (ret < 0) { 313 if (ret < 0) {
289 dev_err(dev, "could not parse property pins\n"); 314 ret = of_property_count_strings(np, "groups");
290 goto exit; 315 if (ret < 0) {
316 dev_err(dev, "could not parse property pins/groups\n");
317 goto exit;
318 }
319 if (type == PIN_MAP_TYPE_INVALID)
320 type = PIN_MAP_TYPE_CONFIGS_GROUP;
321 subnode_target_type = "groups";
322 } else {
323 if (type == PIN_MAP_TYPE_INVALID)
324 type = PIN_MAP_TYPE_CONFIGS_PIN;
291 } 325 }
292 reserve *= ret; 326 reserve *= ret;
293 327
@@ -296,7 +330,7 @@ int pinconf_generic_dt_subnode_to_map(struct pinctrl_dev *pctldev,
296 if (ret < 0) 330 if (ret < 0)
297 goto exit; 331 goto exit;
298 332
299 of_property_for_each_string(np, "pins", prop, group) { 333 of_property_for_each_string(np, subnode_target_type, prop, group) {
300 if (function) { 334 if (function) {
301 ret = pinctrl_utils_add_map_mux(pctldev, map, 335 ret = pinctrl_utils_add_map_mux(pctldev, map,
302 reserved_maps, num_maps, group, 336 reserved_maps, num_maps, group,
diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c
index 8bfa0643e5dc..1fc09dc20199 100644
--- a/drivers/pinctrl/pinconf.c
+++ b/drivers/pinctrl/pinconf.c
@@ -288,7 +288,7 @@ static void pinconf_dump_pin(struct pinctrl_dev *pctldev,
288 const struct pinconf_ops *ops = pctldev->desc->confops; 288 const struct pinconf_ops *ops = pctldev->desc->confops;
289 289
290 /* no-op when not using generic pin config */ 290 /* no-op when not using generic pin config */
291 pinconf_generic_dump_pin(pctldev, s, pin); 291 pinconf_generic_dump_pins(pctldev, s, NULL, pin);
292 if (ops && ops->pin_config_dbg_show) 292 if (ops && ops->pin_config_dbg_show)
293 ops->pin_config_dbg_show(pctldev, s, pin); 293 ops->pin_config_dbg_show(pctldev, s, pin);
294} 294}
@@ -333,7 +333,7 @@ static void pinconf_dump_group(struct pinctrl_dev *pctldev,
333 const struct pinconf_ops *ops = pctldev->desc->confops; 333 const struct pinconf_ops *ops = pctldev->desc->confops;
334 334
335 /* no-op when not using generic pin config */ 335 /* no-op when not using generic pin config */
336 pinconf_generic_dump_group(pctldev, s, gname); 336 pinconf_generic_dump_pins(pctldev, s, gname, 0);
337 if (ops && ops->pin_config_group_dbg_show) 337 if (ops && ops->pin_config_group_dbg_show)
338 ops->pin_config_group_dbg_show(pctldev, s, selector); 338 ops->pin_config_group_dbg_show(pctldev, s, selector);
339} 339}
diff --git a/drivers/pinctrl/pinconf.h b/drivers/pinctrl/pinconf.h
index a4a5417e1413..55c75780b3b2 100644
--- a/drivers/pinctrl/pinconf.h
+++ b/drivers/pinctrl/pinconf.h
@@ -92,26 +92,17 @@ static inline void pinconf_init_device_debugfs(struct dentry *devroot,
92 92
93#if defined(CONFIG_GENERIC_PINCONF) && defined(CONFIG_DEBUG_FS) 93#if defined(CONFIG_GENERIC_PINCONF) && defined(CONFIG_DEBUG_FS)
94 94
95void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev, 95void pinconf_generic_dump_pins(struct pinctrl_dev *pctldev,
96 struct seq_file *s, unsigned pin); 96 struct seq_file *s, const char *gname,
97 97 unsigned pin);
98void pinconf_generic_dump_group(struct pinctrl_dev *pctldev,
99 struct seq_file *s, const char *gname);
100 98
101void pinconf_generic_dump_config(struct pinctrl_dev *pctldev, 99void pinconf_generic_dump_config(struct pinctrl_dev *pctldev,
102 struct seq_file *s, unsigned long config); 100 struct seq_file *s, unsigned long config);
103#else 101#else
104 102
105static inline void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev, 103static inline void pinconf_generic_dump_pins(struct pinctrl_dev *pctldev,
106 struct seq_file *s, 104 struct seq_file *s,
107 unsigned pin) 105 const char *gname, unsigned pin)
108{
109 return;
110}
111
112static inline void pinconf_generic_dump_group(struct pinctrl_dev *pctldev,
113 struct seq_file *s,
114 const char *gname)
115{ 106{
116 return; 107 return;
117} 108}
@@ -126,6 +117,7 @@ static inline void pinconf_generic_dump_config(struct pinctrl_dev *pctldev,
126 117
127#if defined(CONFIG_GENERIC_PINCONF) && defined(CONFIG_OF) 118#if defined(CONFIG_GENERIC_PINCONF) && defined(CONFIG_OF)
128int pinconf_generic_parse_dt_config(struct device_node *np, 119int pinconf_generic_parse_dt_config(struct device_node *np,
120 struct pinctrl_dev *pctldev,
129 unsigned long **configs, 121 unsigned long **configs,
130 unsigned int *nconfigs); 122 unsigned int *nconfigs);
131#endif 123#endif
diff --git a/drivers/pinctrl/pinctrl-bcm281xx.c b/drivers/pinctrl/pinctrl-bcm281xx.c
index fa2a00f22ff1..b88cfe5ed55a 100644
--- a/drivers/pinctrl/pinctrl-bcm281xx.c
+++ b/drivers/pinctrl/pinctrl-bcm281xx.c
@@ -976,7 +976,7 @@ static inline void bcm281xx_pin_update(u32 *reg_val, u32 *reg_mask,
976 *reg_mask |= param_mask; 976 *reg_mask |= param_mask;
977} 977}
978 978
979static struct regmap_config bcm281xx_pinctrl_regmap_config = { 979static const struct regmap_config bcm281xx_pinctrl_regmap_config = {
980 .reg_bits = 32, 980 .reg_bits = 32,
981 .reg_stride = 4, 981 .reg_stride = 4,
982 .val_bits = 32, 982 .val_bits = 32,
@@ -1435,7 +1435,7 @@ static int __init bcm281xx_pinctrl_probe(struct platform_device *pdev)
1435 return 0; 1435 return 0;
1436} 1436}
1437 1437
1438static struct of_device_id bcm281xx_pinctrl_of_match[] = { 1438static const struct of_device_id bcm281xx_pinctrl_of_match[] = {
1439 { .compatible = "brcm,bcm11351-pinctrl", }, 1439 { .compatible = "brcm,bcm11351-pinctrl", },
1440 { }, 1440 { },
1441}; 1441};
diff --git a/drivers/pinctrl/pinctrl-falcon.c b/drivers/pinctrl/pinctrl-falcon.c
index 1d21dc226920..0b0fc2eb48e0 100644
--- a/drivers/pinctrl/pinctrl-falcon.c
+++ b/drivers/pinctrl/pinctrl-falcon.c
@@ -101,6 +101,7 @@ static void lantiq_load_pin_desc(struct pinctrl_pin_desc *d, int bank, int len)
101 for (i = 0; i < len; i++) { 101 for (i = 0; i < len; i++) {
102 /* strlen("ioXYZ") + 1 = 6 */ 102 /* strlen("ioXYZ") + 1 = 6 */
103 char *name = kzalloc(6, GFP_KERNEL); 103 char *name = kzalloc(6, GFP_KERNEL);
104
104 snprintf(name, 6, "io%d", base + i); 105 snprintf(name, 6, "io%d", base + i);
105 d[i].number = base + i; 106 d[i].number = base + i;
106 d[i].name = name; 107 d[i].name = name;
@@ -463,7 +464,7 @@ static int pinctrl_falcon_probe(struct platform_device *pdev)
463 &res); 464 &res);
464 if (IS_ERR(falcon_info.membase[*bank])) 465 if (IS_ERR(falcon_info.membase[*bank]))
465 return PTR_ERR(falcon_info.membase[*bank]); 466 return PTR_ERR(falcon_info.membase[*bank]);
466 467
467 avail = pad_r32(falcon_info.membase[*bank], 468 avail = pad_r32(falcon_info.membase[*bank],
468 LTQ_PADC_AVAIL); 469 LTQ_PADC_AVAIL);
469 pins = fls(avail); 470 pins = fls(avail);
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 43eacc924b7e..dee7d5f06c60 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -89,7 +89,7 @@ struct rockchip_iomux {
89 * @reg_pull: optional separate register for additional pull settings 89 * @reg_pull: optional separate register for additional pull settings
90 * @clk: clock of the gpio bank 90 * @clk: clock of the gpio bank
91 * @irq: interrupt of the gpio bank 91 * @irq: interrupt of the gpio bank
92 * @saved_enables: Saved content of GPIO_INTEN at suspend time. 92 * @saved_masks: Saved content of GPIO_INTEN at suspend time.
93 * @pin_base: first pin number 93 * @pin_base: first pin number
94 * @nr_pins: number of pins in this bank 94 * @nr_pins: number of pins in this bank
95 * @name: name of the bank 95 * @name: name of the bank
@@ -108,7 +108,7 @@ struct rockchip_pin_bank {
108 struct regmap *regmap_pull; 108 struct regmap *regmap_pull;
109 struct clk *clk; 109 struct clk *clk;
110 int irq; 110 int irq;
111 u32 saved_enables; 111 u32 saved_masks;
112 u32 pin_base; 112 u32 pin_base;
113 u8 nr_pins; 113 u8 nr_pins;
114 char *name; 114 char *name;
@@ -1142,7 +1142,7 @@ static int rockchip_pinctrl_parse_groups(struct device_node *np,
1142 return -EINVAL; 1142 return -EINVAL;
1143 1143
1144 np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); 1144 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
1145 ret = pinconf_generic_parse_dt_config(np_config, 1145 ret = pinconf_generic_parse_dt_config(np_config, NULL,
1146 &grp->data[j].configs, &grp->data[j].nconfigs); 1146 &grp->data[j].configs, &grp->data[j].nconfigs);
1147 if (ret) 1147 if (ret)
1148 return ret; 1148 return ret;
@@ -1545,8 +1545,8 @@ static void rockchip_irq_suspend(struct irq_data *d)
1545 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 1545 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1546 struct rockchip_pin_bank *bank = gc->private; 1546 struct rockchip_pin_bank *bank = gc->private;
1547 1547
1548 bank->saved_enables = irq_reg_readl(gc, GPIO_INTEN); 1548 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
1549 irq_reg_writel(gc, gc->wake_active, GPIO_INTEN); 1549 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
1550} 1550}
1551 1551
1552static void rockchip_irq_resume(struct irq_data *d) 1552static void rockchip_irq_resume(struct irq_data *d)
@@ -1554,35 +1554,7 @@ static void rockchip_irq_resume(struct irq_data *d)
1554 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 1554 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1555 struct rockchip_pin_bank *bank = gc->private; 1555 struct rockchip_pin_bank *bank = gc->private;
1556 1556
1557 irq_reg_writel(gc, bank->saved_enables, GPIO_INTEN); 1557 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
1558}
1559
1560static void rockchip_irq_disable(struct irq_data *d)
1561{
1562 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1563 u32 val;
1564
1565 irq_gc_lock(gc);
1566
1567 val = irq_reg_readl(gc, GPIO_INTEN);
1568 val &= ~d->mask;
1569 irq_reg_writel(gc, val, GPIO_INTEN);
1570
1571 irq_gc_unlock(gc);
1572}
1573
1574static void rockchip_irq_enable(struct irq_data *d)
1575{
1576 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1577 u32 val;
1578
1579 irq_gc_lock(gc);
1580
1581 val = irq_reg_readl(gc, GPIO_INTEN);
1582 val |= d->mask;
1583 irq_reg_writel(gc, val, GPIO_INTEN);
1584
1585 irq_gc_unlock(gc);
1586} 1558}
1587 1559
1588static int rockchip_interrupts_register(struct platform_device *pdev, 1560static int rockchip_interrupts_register(struct platform_device *pdev,
@@ -1620,6 +1592,14 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
1620 continue; 1592 continue;
1621 } 1593 }
1622 1594
1595 /*
1596 * Linux assumes that all interrupts start out disabled/masked.
1597 * Our driver only uses the concept of masked and always keeps
1598 * things enabled, so for us that's all masked and all enabled.
1599 */
1600 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
1601 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
1602
1623 gc = irq_get_domain_generic_chip(bank->domain, 0); 1603 gc = irq_get_domain_generic_chip(bank->domain, 0);
1624 gc->reg_base = bank->reg_base; 1604 gc->reg_base = bank->reg_base;
1625 gc->private = bank; 1605 gc->private = bank;
@@ -1628,8 +1608,6 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
1628 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; 1608 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
1629 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; 1609 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
1630 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; 1610 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
1631 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
1632 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
1633 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; 1611 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
1634 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; 1612 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
1635 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; 1613 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
diff --git a/drivers/pinctrl/pinctrl-tz1090-pdc.c b/drivers/pinctrl/pinctrl-tz1090-pdc.c
index 146e48a9b839..fab6aafa6a9f 100644
--- a/drivers/pinctrl/pinctrl-tz1090-pdc.c
+++ b/drivers/pinctrl/pinctrl-tz1090-pdc.c
@@ -415,7 +415,7 @@ static int tz1090_pdc_pinctrl_dt_subnode_to_map(struct device *dev,
415 function = NULL; 415 function = NULL;
416 } 416 }
417 417
418 ret = pinconf_generic_parse_dt_config(np, &configs, &num_configs); 418 ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs);
419 if (ret) 419 if (ret)
420 return ret; 420 return ret;
421 421
diff --git a/drivers/pinctrl/pinctrl-tz1090.c b/drivers/pinctrl/pinctrl-tz1090.c
index df8cb1e5b7b4..8bd73075f9dd 100644
--- a/drivers/pinctrl/pinctrl-tz1090.c
+++ b/drivers/pinctrl/pinctrl-tz1090.c
@@ -1131,7 +1131,7 @@ static int tz1090_pinctrl_dt_subnode_to_map(struct device *dev,
1131 function = NULL; 1131 function = NULL;
1132 } 1132 }
1133 1133
1134 ret = pinconf_generic_parse_dt_config(np, &configs, &num_configs); 1134 ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs);
1135 if (ret) 1135 if (ret)
1136 return ret; 1136 return ret;
1137 1137
diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c
new file mode 100644
index 000000000000..22280bddb9e2
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-zynq.c
@@ -0,0 +1,1180 @@
1/*
2 * Zynq pin controller
3 *
4 * Copyright (C) 2014 Xilinx
5 *
6 * Sören Brinkmann <soren.brinkmann@xilinx.com>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21#include <linux/io.h>
22#include <linux/mfd/syscon.h>
23#include <linux/module.h>
24#include <linux/of.h>
25#include <linux/platform_device.h>
26#include <linux/pinctrl/pinctrl.h>
27#include <linux/pinctrl/pinmux.h>
28#include <linux/pinctrl/pinconf.h>
29#include <linux/pinctrl/pinconf-generic.h>
30#include <linux/regmap.h>
31#include "pinctrl-utils.h"
32#include "core.h"
33
34#define ZYNQ_NUM_MIOS 54
35
36#define ZYNQ_PCTRL_MIO_MST_TRI0 0x10c
37#define ZYNQ_PCTRL_MIO_MST_TRI1 0x110
38
39#define ZYNQ_PINMUX_MUX_SHIFT 1
40#define ZYNQ_PINMUX_MUX_MASK (0x7f << ZYNQ_PINMUX_MUX_SHIFT)
41
42/**
43 * struct zynq_pinctrl - driver data
44 * @pctrl: Pinctrl device
45 * @syscon: Syscon regmap
46 * @pctrl_offset: Offset for pinctrl into the @syscon space
47 * @groups: Pingroups
48 * @ngroupos: Number of @groups
49 * @funcs: Pinmux functions
50 * @nfuncs: Number of @funcs
51 */
52struct zynq_pinctrl {
53 struct pinctrl_dev *pctrl;
54 struct regmap *syscon;
55 u32 pctrl_offset;
56 const struct zynq_pctrl_group *groups;
57 unsigned int ngroups;
58 const struct zynq_pinmux_function *funcs;
59 unsigned int nfuncs;
60};
61
62struct zynq_pctrl_group {
63 const char *name;
64 const unsigned int *pins;
65 const unsigned npins;
66};
67
68/**
69 * struct zynq_pinmux_function - a pinmux function
70 * @name: Name of the pinmux function.
71 * @groups: List of pingroups for this function.
72 * @ngroups: Number of entries in @groups.
73 * @mux_val: Selector for this function
74 * @mux: Offset of function specific mux
75 * @mux_mask: Mask for function specific selector
76 * @mux_shift: Shift for function specific selector
77 */
78struct zynq_pinmux_function {
79 const char *name;
80 const char * const *groups;
81 unsigned int ngroups;
82 unsigned int mux_val;
83 u32 mux;
84 u32 mux_mask;
85 u8 mux_shift;
86};
87
88enum zynq_pinmux_functions {
89 ZYNQ_PMUX_can0,
90 ZYNQ_PMUX_can1,
91 ZYNQ_PMUX_ethernet0,
92 ZYNQ_PMUX_ethernet1,
93 ZYNQ_PMUX_gpio0,
94 ZYNQ_PMUX_i2c0,
95 ZYNQ_PMUX_i2c1,
96 ZYNQ_PMUX_mdio0,
97 ZYNQ_PMUX_mdio1,
98 ZYNQ_PMUX_qspi0,
99 ZYNQ_PMUX_qspi1,
100 ZYNQ_PMUX_qspi_fbclk,
101 ZYNQ_PMUX_qspi_cs1,
102 ZYNQ_PMUX_spi0,
103 ZYNQ_PMUX_spi1,
104 ZYNQ_PMUX_sdio0,
105 ZYNQ_PMUX_sdio0_pc,
106 ZYNQ_PMUX_sdio0_cd,
107 ZYNQ_PMUX_sdio0_wp,
108 ZYNQ_PMUX_sdio1,
109 ZYNQ_PMUX_sdio1_pc,
110 ZYNQ_PMUX_sdio1_cd,
111 ZYNQ_PMUX_sdio1_wp,
112 ZYNQ_PMUX_smc0_nor,
113 ZYNQ_PMUX_smc0_nor_cs1,
114 ZYNQ_PMUX_smc0_nor_addr25,
115 ZYNQ_PMUX_smc0_nand,
116 ZYNQ_PMUX_ttc0,
117 ZYNQ_PMUX_ttc1,
118 ZYNQ_PMUX_uart0,
119 ZYNQ_PMUX_uart1,
120 ZYNQ_PMUX_usb0,
121 ZYNQ_PMUX_usb1,
122 ZYNQ_PMUX_swdt0,
123 ZYNQ_PMUX_MAX_FUNC
124};
125
126const struct pinctrl_pin_desc zynq_pins[] = {
127 PINCTRL_PIN(0, "MIO0"),
128 PINCTRL_PIN(1, "MIO1"),
129 PINCTRL_PIN(2, "MIO2"),
130 PINCTRL_PIN(3, "MIO3"),
131 PINCTRL_PIN(4, "MIO4"),
132 PINCTRL_PIN(5, "MIO5"),
133 PINCTRL_PIN(6, "MIO6"),
134 PINCTRL_PIN(7, "MIO7"),
135 PINCTRL_PIN(8, "MIO8"),
136 PINCTRL_PIN(9, "MIO9"),
137 PINCTRL_PIN(10, "MIO10"),
138 PINCTRL_PIN(11, "MIO11"),
139 PINCTRL_PIN(12, "MIO12"),
140 PINCTRL_PIN(13, "MIO13"),
141 PINCTRL_PIN(14, "MIO14"),
142 PINCTRL_PIN(15, "MIO15"),
143 PINCTRL_PIN(16, "MIO16"),
144 PINCTRL_PIN(17, "MIO17"),
145 PINCTRL_PIN(18, "MIO18"),
146 PINCTRL_PIN(19, "MIO19"),
147 PINCTRL_PIN(20, "MIO20"),
148 PINCTRL_PIN(21, "MIO21"),
149 PINCTRL_PIN(22, "MIO22"),
150 PINCTRL_PIN(23, "MIO23"),
151 PINCTRL_PIN(24, "MIO24"),
152 PINCTRL_PIN(25, "MIO25"),
153 PINCTRL_PIN(26, "MIO26"),
154 PINCTRL_PIN(27, "MIO27"),
155 PINCTRL_PIN(28, "MIO28"),
156 PINCTRL_PIN(29, "MIO29"),
157 PINCTRL_PIN(30, "MIO30"),
158 PINCTRL_PIN(31, "MIO31"),
159 PINCTRL_PIN(32, "MIO32"),
160 PINCTRL_PIN(33, "MIO33"),
161 PINCTRL_PIN(34, "MIO34"),
162 PINCTRL_PIN(35, "MIO35"),
163 PINCTRL_PIN(36, "MIO36"),
164 PINCTRL_PIN(37, "MIO37"),
165 PINCTRL_PIN(38, "MIO38"),
166 PINCTRL_PIN(39, "MIO39"),
167 PINCTRL_PIN(40, "MIO40"),
168 PINCTRL_PIN(41, "MIO41"),
169 PINCTRL_PIN(42, "MIO42"),
170 PINCTRL_PIN(43, "MIO43"),
171 PINCTRL_PIN(44, "MIO44"),
172 PINCTRL_PIN(45, "MIO45"),
173 PINCTRL_PIN(46, "MIO46"),
174 PINCTRL_PIN(47, "MIO47"),
175 PINCTRL_PIN(48, "MIO48"),
176 PINCTRL_PIN(49, "MIO49"),
177 PINCTRL_PIN(50, "MIO50"),
178 PINCTRL_PIN(51, "MIO51"),
179 PINCTRL_PIN(52, "MIO52"),
180 PINCTRL_PIN(53, "MIO53"),
181 PINCTRL_PIN(54, "EMIO_SD0_WP"),
182 PINCTRL_PIN(55, "EMIO_SD0_CD"),
183 PINCTRL_PIN(56, "EMIO_SD1_WP"),
184 PINCTRL_PIN(57, "EMIO_SD1_CD"),
185};
186
187/* pin groups */
188static const unsigned int ethernet0_0_pins[] = {16, 17, 18, 19, 20, 21, 22, 23,
189 24, 25, 26, 27};
190static const unsigned int ethernet1_0_pins[] = {28, 29, 30, 31, 32, 33, 34, 35,
191 36, 37, 38, 39};
192static const unsigned int mdio0_0_pins[] = {52, 53};
193static const unsigned int mdio1_0_pins[] = {52, 53};
194static const unsigned int qspi0_0_pins[] = {1, 2, 3, 4, 5, 6};
195
196static const unsigned int qspi1_0_pins[] = {9, 10, 11, 12, 13};
197static const unsigned int qspi_cs1_pins[] = {0};
198static const unsigned int qspi_fbclk_pins[] = {8};
199static const unsigned int spi0_0_pins[] = {16, 17, 18, 19, 20, 21};
200static const unsigned int spi0_1_pins[] = {28, 29, 30, 31, 32, 33};
201static const unsigned int spi0_2_pins[] = {40, 41, 42, 43, 44, 45};
202static const unsigned int spi1_0_pins[] = {10, 11, 12, 13, 14, 15};
203static const unsigned int spi1_1_pins[] = {22, 23, 24, 25, 26, 27};
204static const unsigned int spi1_2_pins[] = {34, 35, 36, 37, 38, 39};
205static const unsigned int spi1_3_pins[] = {46, 47, 48, 49, 40, 51};
206static const unsigned int sdio0_0_pins[] = {16, 17, 18, 19, 20, 21};
207static const unsigned int sdio0_1_pins[] = {28, 29, 30, 31, 32, 33};
208static const unsigned int sdio0_2_pins[] = {40, 41, 42, 43, 44, 45};
209static const unsigned int sdio1_0_pins[] = {10, 11, 12, 13, 14, 15};
210static const unsigned int sdio1_1_pins[] = {22, 23, 24, 25, 26, 27};
211static const unsigned int sdio1_2_pins[] = {34, 35, 36, 37, 38, 39};
212static const unsigned int sdio1_3_pins[] = {46, 47, 48, 49, 40, 51};
213static const unsigned int sdio0_emio_wp_pins[] = {54};
214static const unsigned int sdio0_emio_cd_pins[] = {55};
215static const unsigned int sdio1_emio_wp_pins[] = {56};
216static const unsigned int sdio1_emio_cd_pins[] = {57};
217static const unsigned int smc0_nor_pins[] = {0, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
218 15, 16, 17, 18, 19, 20, 21, 22, 23,
219 24, 25, 26, 27, 28, 29, 30, 31, 32,
220 33, 34, 35, 36, 37, 38, 39};
221static const unsigned int smc0_nor_cs1_pins[] = {1};
222static const unsigned int smc0_nor_addr25_pins[] = {1};
223static const unsigned int smc0_nand_pins[] = {0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,
224 12, 13, 14, 16, 17, 18, 19, 20,
225 21, 22, 23};
226/* Note: CAN MIO clock inputs are modeled in the clock framework */
227static const unsigned int can0_0_pins[] = {10, 11};
228static const unsigned int can0_1_pins[] = {14, 15};
229static const unsigned int can0_2_pins[] = {18, 19};
230static const unsigned int can0_3_pins[] = {22, 23};
231static const unsigned int can0_4_pins[] = {26, 27};
232static const unsigned int can0_5_pins[] = {30, 31};
233static const unsigned int can0_6_pins[] = {34, 35};
234static const unsigned int can0_7_pins[] = {38, 39};
235static const unsigned int can0_8_pins[] = {42, 43};
236static const unsigned int can0_9_pins[] = {46, 47};
237static const unsigned int can0_10_pins[] = {50, 51};
238static const unsigned int can1_0_pins[] = {8, 9};
239static const unsigned int can1_1_pins[] = {12, 13};
240static const unsigned int can1_2_pins[] = {16, 17};
241static const unsigned int can1_3_pins[] = {20, 21};
242static const unsigned int can1_4_pins[] = {24, 25};
243static const unsigned int can1_5_pins[] = {28, 29};
244static const unsigned int can1_6_pins[] = {32, 33};
245static const unsigned int can1_7_pins[] = {36, 37};
246static const unsigned int can1_8_pins[] = {40, 41};
247static const unsigned int can1_9_pins[] = {44, 45};
248static const unsigned int can1_10_pins[] = {48, 49};
249static const unsigned int can1_11_pins[] = {52, 53};
250static const unsigned int uart0_0_pins[] = {10, 11};
251static const unsigned int uart0_1_pins[] = {14, 15};
252static const unsigned int uart0_2_pins[] = {18, 19};
253static const unsigned int uart0_3_pins[] = {22, 23};
254static const unsigned int uart0_4_pins[] = {26, 27};
255static const unsigned int uart0_5_pins[] = {30, 31};
256static const unsigned int uart0_6_pins[] = {34, 35};
257static const unsigned int uart0_7_pins[] = {38, 39};
258static const unsigned int uart0_8_pins[] = {42, 43};
259static const unsigned int uart0_9_pins[] = {46, 47};
260static const unsigned int uart0_10_pins[] = {50, 51};
261static const unsigned int uart1_0_pins[] = {8, 9};
262static const unsigned int uart1_1_pins[] = {12, 13};
263static const unsigned int uart1_2_pins[] = {16, 17};
264static const unsigned int uart1_3_pins[] = {20, 21};
265static const unsigned int uart1_4_pins[] = {24, 25};
266static const unsigned int uart1_5_pins[] = {28, 29};
267static const unsigned int uart1_6_pins[] = {32, 33};
268static const unsigned int uart1_7_pins[] = {36, 37};
269static const unsigned int uart1_8_pins[] = {40, 41};
270static const unsigned int uart1_9_pins[] = {44, 45};
271static const unsigned int uart1_10_pins[] = {48, 49};
272static const unsigned int uart1_11_pins[] = {52, 53};
273static const unsigned int i2c0_0_pins[] = {10, 11};
274static const unsigned int i2c0_1_pins[] = {14, 15};
275static const unsigned int i2c0_2_pins[] = {18, 19};
276static const unsigned int i2c0_3_pins[] = {22, 23};
277static const unsigned int i2c0_4_pins[] = {26, 27};
278static const unsigned int i2c0_5_pins[] = {30, 31};
279static const unsigned int i2c0_6_pins[] = {34, 35};
280static const unsigned int i2c0_7_pins[] = {38, 39};
281static const unsigned int i2c0_8_pins[] = {42, 43};
282static const unsigned int i2c0_9_pins[] = {46, 47};
283static const unsigned int i2c0_10_pins[] = {50, 51};
284static const unsigned int i2c1_0_pins[] = {12, 13};
285static const unsigned int i2c1_1_pins[] = {16, 17};
286static const unsigned int i2c1_2_pins[] = {20, 21};
287static const unsigned int i2c1_3_pins[] = {24, 25};
288static const unsigned int i2c1_4_pins[] = {28, 29};
289static const unsigned int i2c1_5_pins[] = {32, 33};
290static const unsigned int i2c1_6_pins[] = {36, 37};
291static const unsigned int i2c1_7_pins[] = {40, 41};
292static const unsigned int i2c1_8_pins[] = {44, 45};
293static const unsigned int i2c1_9_pins[] = {48, 49};
294static const unsigned int i2c1_10_pins[] = {52, 53};
295static const unsigned int ttc0_0_pins[] = {18, 19};
296static const unsigned int ttc0_1_pins[] = {30, 31};
297static const unsigned int ttc0_2_pins[] = {42, 43};
298static const unsigned int ttc1_0_pins[] = {16, 17};
299static const unsigned int ttc1_1_pins[] = {28, 29};
300static const unsigned int ttc1_2_pins[] = {40, 41};
301static const unsigned int swdt0_0_pins[] = {14, 15};
302static const unsigned int swdt0_1_pins[] = {26, 27};
303static const unsigned int swdt0_2_pins[] = {38, 39};
304static const unsigned int swdt0_3_pins[] = {50, 51};
305static const unsigned int swdt0_4_pins[] = {52, 53};
306static const unsigned int gpio0_0_pins[] = {0};
307static const unsigned int gpio0_1_pins[] = {1};
308static const unsigned int gpio0_2_pins[] = {2};
309static const unsigned int gpio0_3_pins[] = {3};
310static const unsigned int gpio0_4_pins[] = {4};
311static const unsigned int gpio0_5_pins[] = {5};
312static const unsigned int gpio0_6_pins[] = {6};
313static const unsigned int gpio0_7_pins[] = {7};
314static const unsigned int gpio0_8_pins[] = {8};
315static const unsigned int gpio0_9_pins[] = {9};
316static const unsigned int gpio0_10_pins[] = {10};
317static const unsigned int gpio0_11_pins[] = {11};
318static const unsigned int gpio0_12_pins[] = {12};
319static const unsigned int gpio0_13_pins[] = {13};
320static const unsigned int gpio0_14_pins[] = {14};
321static const unsigned int gpio0_15_pins[] = {15};
322static const unsigned int gpio0_16_pins[] = {16};
323static const unsigned int gpio0_17_pins[] = {17};
324static const unsigned int gpio0_18_pins[] = {18};
325static const unsigned int gpio0_19_pins[] = {19};
326static const unsigned int gpio0_20_pins[] = {20};
327static const unsigned int gpio0_21_pins[] = {21};
328static const unsigned int gpio0_22_pins[] = {22};
329static const unsigned int gpio0_23_pins[] = {23};
330static const unsigned int gpio0_24_pins[] = {24};
331static const unsigned int gpio0_25_pins[] = {25};
332static const unsigned int gpio0_26_pins[] = {26};
333static const unsigned int gpio0_27_pins[] = {27};
334static const unsigned int gpio0_28_pins[] = {28};
335static const unsigned int gpio0_29_pins[] = {29};
336static const unsigned int gpio0_30_pins[] = {30};
337static const unsigned int gpio0_31_pins[] = {31};
338static const unsigned int gpio0_32_pins[] = {32};
339static const unsigned int gpio0_33_pins[] = {33};
340static const unsigned int gpio0_34_pins[] = {34};
341static const unsigned int gpio0_35_pins[] = {35};
342static const unsigned int gpio0_36_pins[] = {36};
343static const unsigned int gpio0_37_pins[] = {37};
344static const unsigned int gpio0_38_pins[] = {38};
345static const unsigned int gpio0_39_pins[] = {39};
346static const unsigned int gpio0_40_pins[] = {40};
347static const unsigned int gpio0_41_pins[] = {41};
348static const unsigned int gpio0_42_pins[] = {42};
349static const unsigned int gpio0_43_pins[] = {43};
350static const unsigned int gpio0_44_pins[] = {44};
351static const unsigned int gpio0_45_pins[] = {45};
352static const unsigned int gpio0_46_pins[] = {46};
353static const unsigned int gpio0_47_pins[] = {47};
354static const unsigned int gpio0_48_pins[] = {48};
355static const unsigned int gpio0_49_pins[] = {49};
356static const unsigned int gpio0_50_pins[] = {50};
357static const unsigned int gpio0_51_pins[] = {51};
358static const unsigned int gpio0_52_pins[] = {52};
359static const unsigned int gpio0_53_pins[] = {53};
360static const unsigned int usb0_0_pins[] = {28, 29, 30, 31, 32, 33, 34, 35, 36,
361 37, 38, 39};
362static const unsigned int usb1_0_pins[] = {40, 41, 42, 43, 44, 45, 46, 47, 48,
363 49, 50, 51};
364
365#define DEFINE_ZYNQ_PINCTRL_GRP(nm) \
366 { \
367 .name = #nm "_grp", \
368 .pins = nm ## _pins, \
369 .npins = ARRAY_SIZE(nm ## _pins), \
370 }
371
372struct zynq_pctrl_group zynq_pctrl_groups[] = {
373 DEFINE_ZYNQ_PINCTRL_GRP(ethernet0_0),
374 DEFINE_ZYNQ_PINCTRL_GRP(ethernet1_0),
375 DEFINE_ZYNQ_PINCTRL_GRP(mdio0_0),
376 DEFINE_ZYNQ_PINCTRL_GRP(mdio1_0),
377 DEFINE_ZYNQ_PINCTRL_GRP(qspi0_0),
378 DEFINE_ZYNQ_PINCTRL_GRP(qspi1_0),
379 DEFINE_ZYNQ_PINCTRL_GRP(qspi_fbclk),
380 DEFINE_ZYNQ_PINCTRL_GRP(qspi_cs1),
381 DEFINE_ZYNQ_PINCTRL_GRP(spi0_0),
382 DEFINE_ZYNQ_PINCTRL_GRP(spi0_1),
383 DEFINE_ZYNQ_PINCTRL_GRP(spi0_2),
384 DEFINE_ZYNQ_PINCTRL_GRP(spi1_0),
385 DEFINE_ZYNQ_PINCTRL_GRP(spi1_1),
386 DEFINE_ZYNQ_PINCTRL_GRP(spi1_2),
387 DEFINE_ZYNQ_PINCTRL_GRP(spi1_3),
388 DEFINE_ZYNQ_PINCTRL_GRP(sdio0_0),
389 DEFINE_ZYNQ_PINCTRL_GRP(sdio0_1),
390 DEFINE_ZYNQ_PINCTRL_GRP(sdio0_2),
391 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_0),
392 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_1),
393 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_2),
394 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_3),
395 DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_wp),
396 DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_cd),
397 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_wp),
398 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_cd),
399 DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor),
400 DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_cs1),
401 DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_addr25),
402 DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand),
403 DEFINE_ZYNQ_PINCTRL_GRP(can0_0),
404 DEFINE_ZYNQ_PINCTRL_GRP(can0_1),
405 DEFINE_ZYNQ_PINCTRL_GRP(can0_2),
406 DEFINE_ZYNQ_PINCTRL_GRP(can0_3),
407 DEFINE_ZYNQ_PINCTRL_GRP(can0_4),
408 DEFINE_ZYNQ_PINCTRL_GRP(can0_5),
409 DEFINE_ZYNQ_PINCTRL_GRP(can0_6),
410 DEFINE_ZYNQ_PINCTRL_GRP(can0_7),
411 DEFINE_ZYNQ_PINCTRL_GRP(can0_8),
412 DEFINE_ZYNQ_PINCTRL_GRP(can0_9),
413 DEFINE_ZYNQ_PINCTRL_GRP(can0_10),
414 DEFINE_ZYNQ_PINCTRL_GRP(can1_0),
415 DEFINE_ZYNQ_PINCTRL_GRP(can1_1),
416 DEFINE_ZYNQ_PINCTRL_GRP(can1_2),
417 DEFINE_ZYNQ_PINCTRL_GRP(can1_3),
418 DEFINE_ZYNQ_PINCTRL_GRP(can1_4),
419 DEFINE_ZYNQ_PINCTRL_GRP(can1_5),
420 DEFINE_ZYNQ_PINCTRL_GRP(can1_6),
421 DEFINE_ZYNQ_PINCTRL_GRP(can1_7),
422 DEFINE_ZYNQ_PINCTRL_GRP(can1_8),
423 DEFINE_ZYNQ_PINCTRL_GRP(can1_9),
424 DEFINE_ZYNQ_PINCTRL_GRP(can1_10),
425 DEFINE_ZYNQ_PINCTRL_GRP(can1_11),
426 DEFINE_ZYNQ_PINCTRL_GRP(uart0_0),
427 DEFINE_ZYNQ_PINCTRL_GRP(uart0_1),
428 DEFINE_ZYNQ_PINCTRL_GRP(uart0_2),
429 DEFINE_ZYNQ_PINCTRL_GRP(uart0_3),
430 DEFINE_ZYNQ_PINCTRL_GRP(uart0_4),
431 DEFINE_ZYNQ_PINCTRL_GRP(uart0_5),
432 DEFINE_ZYNQ_PINCTRL_GRP(uart0_6),
433 DEFINE_ZYNQ_PINCTRL_GRP(uart0_7),
434 DEFINE_ZYNQ_PINCTRL_GRP(uart0_8),
435 DEFINE_ZYNQ_PINCTRL_GRP(uart0_9),
436 DEFINE_ZYNQ_PINCTRL_GRP(uart0_10),
437 DEFINE_ZYNQ_PINCTRL_GRP(uart1_0),
438 DEFINE_ZYNQ_PINCTRL_GRP(uart1_1),
439 DEFINE_ZYNQ_PINCTRL_GRP(uart1_2),
440 DEFINE_ZYNQ_PINCTRL_GRP(uart1_3),
441 DEFINE_ZYNQ_PINCTRL_GRP(uart1_4),
442 DEFINE_ZYNQ_PINCTRL_GRP(uart1_5),
443 DEFINE_ZYNQ_PINCTRL_GRP(uart1_6),
444 DEFINE_ZYNQ_PINCTRL_GRP(uart1_7),
445 DEFINE_ZYNQ_PINCTRL_GRP(uart1_8),
446 DEFINE_ZYNQ_PINCTRL_GRP(uart1_9),
447 DEFINE_ZYNQ_PINCTRL_GRP(uart1_10),
448 DEFINE_ZYNQ_PINCTRL_GRP(uart1_11),
449 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_0),
450 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_1),
451 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_2),
452 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_3),
453 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_4),
454 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_5),
455 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_6),
456 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_7),
457 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_8),
458 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_9),
459 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_10),
460 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_0),
461 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_1),
462 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_2),
463 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_3),
464 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_4),
465 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_5),
466 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_6),
467 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_7),
468 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_8),
469 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_9),
470 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_10),
471 DEFINE_ZYNQ_PINCTRL_GRP(ttc0_0),
472 DEFINE_ZYNQ_PINCTRL_GRP(ttc0_1),
473 DEFINE_ZYNQ_PINCTRL_GRP(ttc0_2),
474 DEFINE_ZYNQ_PINCTRL_GRP(ttc1_0),
475 DEFINE_ZYNQ_PINCTRL_GRP(ttc1_1),
476 DEFINE_ZYNQ_PINCTRL_GRP(ttc1_2),
477 DEFINE_ZYNQ_PINCTRL_GRP(swdt0_0),
478 DEFINE_ZYNQ_PINCTRL_GRP(swdt0_1),
479 DEFINE_ZYNQ_PINCTRL_GRP(swdt0_2),
480 DEFINE_ZYNQ_PINCTRL_GRP(swdt0_3),
481 DEFINE_ZYNQ_PINCTRL_GRP(swdt0_4),
482 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_0),
483 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_1),
484 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_2),
485 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_3),
486 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_4),
487 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_5),
488 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_6),
489 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_7),
490 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_8),
491 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_9),
492 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_10),
493 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_11),
494 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_12),
495 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_13),
496 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_14),
497 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_15),
498 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_16),
499 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_17),
500 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_18),
501 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_19),
502 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_20),
503 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_21),
504 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_22),
505 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_23),
506 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_24),
507 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_25),
508 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_26),
509 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_27),
510 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_28),
511 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_29),
512 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_30),
513 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_31),
514 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_32),
515 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_33),
516 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_34),
517 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_35),
518 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_36),
519 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_37),
520 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_38),
521 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_39),
522 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_40),
523 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_41),
524 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_42),
525 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_43),
526 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_44),
527 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_45),
528 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_46),
529 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_47),
530 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_48),
531 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_49),
532 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_50),
533 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_51),
534 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_52),
535 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_53),
536 DEFINE_ZYNQ_PINCTRL_GRP(usb0_0),
537 DEFINE_ZYNQ_PINCTRL_GRP(usb1_0),
538};
539
540/* function groups */
541static const char * const ethernet0_groups[] = {"ethernet0_0_grp"};
542static const char * const ethernet1_groups[] = {"ethernet1_0_grp"};
543static const char * const usb0_groups[] = {"usb0_0_grp"};
544static const char * const usb1_groups[] = {"usb1_0_grp"};
545static const char * const mdio0_groups[] = {"mdio0_0_grp"};
546static const char * const mdio1_groups[] = {"mdio1_0_grp"};
547static const char * const qspi0_groups[] = {"qspi0_0_grp"};
548static const char * const qspi1_groups[] = {"qspi0_1_grp"};
549static const char * const qspi_fbclk_groups[] = {"qspi_fbclk_grp"};
550static const char * const qspi_cs1_groups[] = {"qspi_cs1_grp"};
551static const char * const spi0_groups[] = {"spi0_0_grp", "spi0_1_grp",
552 "spi0_2_grp"};
553static const char * const spi1_groups[] = {"spi1_0_grp", "spi1_1_grp",
554 "spi1_2_grp", "spi1_3_grp"};
555static const char * const sdio0_groups[] = {"sdio0_0_grp", "sdio0_1_grp",
556 "sdio0_2_grp"};
557static const char * const sdio1_groups[] = {"sdio1_0_grp", "sdio1_1_grp",
558 "sdio1_2_grp", "sdio1_3_grp"};
559static const char * const sdio0_pc_groups[] = {"gpio0_0_grp",
560 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
561 "gpio0_8_grp", "gpio0_10_grp", "gpio0_12_grp",
562 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
563 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
564 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
565 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
566 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
567 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
568 "gpio0_50_grp", "gpio0_52_grp"};
569static const char * const sdio1_pc_groups[] = {"gpio0_1_grp",
570 "gpio0_3_grp", "gpio0_5_grp", "gpio0_7_grp",
571 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
572 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
573 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
574 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
575 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
576 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
577 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
578 "gpio0_51_grp", "gpio0_53_grp"};
579static const char * const sdio0_cd_groups[] = {"gpio0_0_grp",
580 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
581 "gpio0_10_grp", "gpio0_12_grp",
582 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
583 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
584 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
585 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
586 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
587 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
588 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
589 "gpio0_3_grp", "gpio0_5_grp",
590 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
591 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
592 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
593 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
594 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
595 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
596 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
597 "gpio0_51_grp", "gpio0_53_grp", "sdio0_emio_cd_grp"};
598static const char * const sdio0_wp_groups[] = {"gpio0_0_grp",
599 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
600 "gpio0_10_grp", "gpio0_12_grp",
601 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
602 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
603 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
604 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
605 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
606 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
607 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
608 "gpio0_3_grp", "gpio0_5_grp",
609 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
610 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
611 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
612 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
613 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
614 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
615 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
616 "gpio0_51_grp", "gpio0_53_grp", "sdio0_emio_wp_grp"};
617static const char * const sdio1_cd_groups[] = {"gpio0_0_grp",
618 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
619 "gpio0_10_grp", "gpio0_12_grp",
620 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
621 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
622 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
623 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
624 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
625 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
626 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
627 "gpio0_3_grp", "gpio0_5_grp",
628 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
629 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
630 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
631 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
632 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
633 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
634 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
635 "gpio0_51_grp", "gpio0_53_grp", "sdio1_emio_cd_grp"};
636static const char * const sdio1_wp_groups[] = {"gpio0_0_grp",
637 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
638 "gpio0_10_grp", "gpio0_12_grp",
639 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
640 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
641 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
642 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
643 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
644 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
645 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
646 "gpio0_3_grp", "gpio0_5_grp",
647 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
648 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
649 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
650 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
651 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
652 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
653 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
654 "gpio0_51_grp", "gpio0_53_grp", "sdio1_emio_wp_grp"};
655static const char * const smc0_nor_groups[] = {"smc0_nor"};
656static const char * const smc0_nor_cs1_groups[] = {"smc0_nor_cs1_grp"};
657static const char * const smc0_nor_addr25_groups[] = {"smc0_nor_addr25_grp"};
658static const char * const smc0_nand_groups[] = {"smc0_nand"};
659static const char * const can0_groups[] = {"can0_0_grp", "can0_1_grp",
660 "can0_2_grp", "can0_3_grp", "can0_4_grp", "can0_5_grp",
661 "can0_6_grp", "can0_7_grp", "can0_8_grp", "can0_9_grp",
662 "can0_10_grp"};
663static const char * const can1_groups[] = {"can1_0_grp", "can1_1_grp",
664 "can1_2_grp", "can1_3_grp", "can1_4_grp", "can1_5_grp",
665 "can1_6_grp", "can1_7_grp", "can1_8_grp", "can1_9_grp",
666 "can1_10_grp", "can1_11_grp"};
667static const char * const uart0_groups[] = {"uart0_0_grp", "uart0_1_grp",
668 "uart0_2_grp", "uart0_3_grp", "uart0_4_grp", "uart0_5_grp",
669 "uart0_6_grp", "uart0_7_grp", "uart0_8_grp", "uart0_9_grp",
670 "uart0_10_grp"};
671static const char * const uart1_groups[] = {"uart1_0_grp", "uart1_1_grp",
672 "uart1_2_grp", "uart1_3_grp", "uart1_4_grp", "uart1_5_grp",
673 "uart1_6_grp", "uart1_7_grp", "uart1_8_grp", "uart1_9_grp",
674 "uart1_10_grp", "uart1_11_grp"};
675static const char * const i2c0_groups[] = {"i2c0_0_grp", "i2c0_1_grp",
676 "i2c0_2_grp", "i2c0_3_grp", "i2c0_4_grp", "i2c0_5_grp",
677 "i2c0_6_grp", "i2c0_7_grp", "i2c0_8_grp", "i2c0_9_grp",
678 "i2c0_10_grp"};
679static const char * const i2c1_groups[] = {"i2c1_0_grp", "i2c1_1_grp",
680 "i2c1_2_grp", "i2c1_3_grp", "i2c1_4_grp", "i2c1_5_grp",
681 "i2c1_6_grp", "i2c1_7_grp", "i2c1_8_grp", "i2c1_9_grp",
682 "i2c1_10_grp"};
683static const char * const ttc0_groups[] = {"ttc0_0_grp", "ttc0_1_grp",
684 "ttc0_2_grp"};
685static const char * const ttc1_groups[] = {"ttc1_0_grp", "ttc1_1_grp",
686 "ttc1_2_grp"};
687static const char * const swdt0_groups[] = {"swdt0_0_grp", "swdt0_1_grp",
688 "swdt0_2_grp", "swdt0_3_grp", "swdt0_4_grp"};
689static const char * const gpio0_groups[] = {"gpio0_0_grp",
690 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
691 "gpio0_8_grp", "gpio0_10_grp", "gpio0_12_grp",
692 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
693 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
694 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
695 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
696 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
697 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
698 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
699 "gpio0_3_grp", "gpio0_5_grp", "gpio0_7_grp",
700 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
701 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
702 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
703 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
704 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
705 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
706 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
707 "gpio0_51_grp", "gpio0_53_grp"};
708
709#define DEFINE_ZYNQ_PINMUX_FUNCTION(fname, mval) \
710 [ZYNQ_PMUX_##fname] = { \
711 .name = #fname, \
712 .groups = fname##_groups, \
713 .ngroups = ARRAY_SIZE(fname##_groups), \
714 .mux_val = mval, \
715 }
716
717#define DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(fname, mval, mux, mask, shift) \
718 [ZYNQ_PMUX_##fname] = { \
719 .name = #fname, \
720 .groups = fname##_groups, \
721 .ngroups = ARRAY_SIZE(fname##_groups), \
722 .mux_val = mval, \
723 .mux_mask = mask, \
724 .mux_shift = shift, \
725 }
726
727#define ZYNQ_SDIO_WP_SHIFT 0
728#define ZYNQ_SDIO_WP_MASK (0x3f << ZYNQ_SDIO_WP_SHIFT)
729#define ZYNQ_SDIO_CD_SHIFT 16
730#define ZYNQ_SDIO_CD_MASK (0x3f << ZYNQ_SDIO_CD_SHIFT)
731
732static const struct zynq_pinmux_function zynq_pmux_functions[] = {
733 DEFINE_ZYNQ_PINMUX_FUNCTION(ethernet0, 1),
734 DEFINE_ZYNQ_PINMUX_FUNCTION(ethernet1, 1),
735 DEFINE_ZYNQ_PINMUX_FUNCTION(usb0, 2),
736 DEFINE_ZYNQ_PINMUX_FUNCTION(usb1, 2),
737 DEFINE_ZYNQ_PINMUX_FUNCTION(mdio0, 0x40),
738 DEFINE_ZYNQ_PINMUX_FUNCTION(mdio1, 0x50),
739 DEFINE_ZYNQ_PINMUX_FUNCTION(qspi0, 1),
740 DEFINE_ZYNQ_PINMUX_FUNCTION(qspi1, 1),
741 DEFINE_ZYNQ_PINMUX_FUNCTION(qspi_fbclk, 1),
742 DEFINE_ZYNQ_PINMUX_FUNCTION(qspi_cs1, 1),
743 DEFINE_ZYNQ_PINMUX_FUNCTION(spi0, 0x50),
744 DEFINE_ZYNQ_PINMUX_FUNCTION(spi1, 0x50),
745 DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0, 0x40),
746 DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0_pc, 0xc),
747 DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_wp, 0, 130, ZYNQ_SDIO_WP_MASK,
748 ZYNQ_SDIO_WP_SHIFT),
749 DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_cd, 0, 130, ZYNQ_SDIO_CD_MASK,
750 ZYNQ_SDIO_CD_SHIFT),
751 DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1, 0x40),
752 DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1_pc, 0xc),
753 DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_wp, 0, 134, ZYNQ_SDIO_WP_MASK,
754 ZYNQ_SDIO_WP_SHIFT),
755 DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_cd, 0, 134, ZYNQ_SDIO_CD_MASK,
756 ZYNQ_SDIO_CD_SHIFT),
757 DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor, 4),
758 DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor_cs1, 8),
759 DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor_addr25, 4),
760 DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nand, 8),
761 DEFINE_ZYNQ_PINMUX_FUNCTION(can0, 0x10),
762 DEFINE_ZYNQ_PINMUX_FUNCTION(can1, 0x10),
763 DEFINE_ZYNQ_PINMUX_FUNCTION(uart0, 0x70),
764 DEFINE_ZYNQ_PINMUX_FUNCTION(uart1, 0x70),
765 DEFINE_ZYNQ_PINMUX_FUNCTION(i2c0, 0x20),
766 DEFINE_ZYNQ_PINMUX_FUNCTION(i2c1, 0x20),
767 DEFINE_ZYNQ_PINMUX_FUNCTION(ttc0, 0x60),
768 DEFINE_ZYNQ_PINMUX_FUNCTION(ttc1, 0x60),
769 DEFINE_ZYNQ_PINMUX_FUNCTION(swdt0, 0x30),
770 DEFINE_ZYNQ_PINMUX_FUNCTION(gpio0, 0),
771};
772
773
774/* pinctrl */
775static int zynq_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
776{
777 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
778
779 return pctrl->ngroups;
780}
781
782static const char *zynq_pctrl_get_group_name(struct pinctrl_dev *pctldev,
783 unsigned selector)
784{
785 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
786
787 return pctrl->groups[selector].name;
788}
789
790static int zynq_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
791 unsigned selector,
792 const unsigned **pins,
793 unsigned *num_pins)
794{
795 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
796
797 *pins = pctrl->groups[selector].pins;
798 *num_pins = pctrl->groups[selector].npins;
799
800 return 0;
801}
802
803static const struct pinctrl_ops zynq_pctrl_ops = {
804 .get_groups_count = zynq_pctrl_get_groups_count,
805 .get_group_name = zynq_pctrl_get_group_name,
806 .get_group_pins = zynq_pctrl_get_group_pins,
807 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
808 .dt_free_map = pinctrl_utils_dt_free_map,
809};
810
811/* pinmux */
812static int zynq_pmux_get_functions_count(struct pinctrl_dev *pctldev)
813{
814 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
815
816 return pctrl->nfuncs;
817}
818
819static const char *zynq_pmux_get_function_name(struct pinctrl_dev *pctldev,
820 unsigned selector)
821{
822 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
823
824 return pctrl->funcs[selector].name;
825}
826
827static int zynq_pmux_get_function_groups(struct pinctrl_dev *pctldev,
828 unsigned selector,
829 const char * const **groups,
830 unsigned * const num_groups)
831{
832 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
833
834 *groups = pctrl->funcs[selector].groups;
835 *num_groups = pctrl->funcs[selector].ngroups;
836 return 0;
837}
838
839static int zynq_pinmux_set_mux(struct pinctrl_dev *pctldev,
840 unsigned function,
841 unsigned group)
842{
843 int i, ret;
844 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
845 const struct zynq_pctrl_group *pgrp = &pctrl->groups[group];
846 const struct zynq_pinmux_function *func = &pctrl->funcs[function];
847
848 /*
849 * SD WP & CD are special. They have dedicated registers
850 * to mux them in
851 */
852 if (function == ZYNQ_PMUX_sdio0_cd || function == ZYNQ_PMUX_sdio0_wp ||
853 function == ZYNQ_PMUX_sdio1_cd ||
854 function == ZYNQ_PMUX_sdio1_wp) {
855 u32 reg;
856
857 ret = regmap_read(pctrl->syscon,
858 pctrl->pctrl_offset + func->mux, &reg);
859 if (ret)
860 return ret;
861
862 reg &= ~func->mux_mask;
863 reg |= pgrp->pins[0] << func->mux_shift;
864 ret = regmap_write(pctrl->syscon,
865 pctrl->pctrl_offset + func->mux, reg);
866 if (ret)
867 return ret;
868 } else {
869 for (i = 0; i < pgrp->npins; i++) {
870 unsigned int pin = pgrp->pins[i];
871 u32 reg, addr = pctrl->pctrl_offset + (4 * pin);
872
873 ret = regmap_read(pctrl->syscon, addr, &reg);
874 if (ret)
875 return ret;
876
877 reg &= ~ZYNQ_PINMUX_MUX_MASK;
878 reg |= func->mux_val << ZYNQ_PINMUX_MUX_SHIFT;
879 ret = regmap_write(pctrl->syscon, addr, reg);
880 if (ret)
881 return ret;
882 }
883 }
884
885 return 0;
886}
887
888static const struct pinmux_ops zynq_pinmux_ops = {
889 .get_functions_count = zynq_pmux_get_functions_count,
890 .get_function_name = zynq_pmux_get_function_name,
891 .get_function_groups = zynq_pmux_get_function_groups,
892 .set_mux = zynq_pinmux_set_mux,
893};
894
895/* pinconfig */
896#define ZYNQ_PINCONF_TRISTATE BIT(0)
897#define ZYNQ_PINCONF_SPEED BIT(8)
898#define ZYNQ_PINCONF_PULLUP BIT(12)
899#define ZYNQ_PINCONF_DISABLE_RECVR BIT(13)
900
901#define ZYNQ_PINCONF_IOTYPE_SHIFT 9
902#define ZYNQ_PINCONF_IOTYPE_MASK (7 << ZYNQ_PINCONF_IOTYPE_SHIFT)
903
904enum zynq_io_standards {
905 zynq_iostd_min,
906 zynq_iostd_lvcmos18,
907 zynq_iostd_lvcmos25,
908 zynq_iostd_lvcmos33,
909 zynq_iostd_hstl,
910 zynq_iostd_max
911};
912
913/**
914 * enum zynq_pin_config_param - possible pin configuration parameters
915 * @PIN_CONFIG_IOSTANDARD: if the pin can select an IO standard, the argument to
916 * this parameter (on a custom format) tells the driver which alternative
917 * IO standard to use.
918 */
919enum zynq_pin_config_param {
920 PIN_CONFIG_IOSTANDARD = PIN_CONFIG_END + 1,
921};
922
923static const struct pinconf_generic_params zynq_dt_params[] = {
924 {"io-standard", PIN_CONFIG_IOSTANDARD, zynq_iostd_lvcmos18},
925};
926
927#ifdef CONFIG_DEBUG_FS
928static const struct pin_config_item zynq_conf_items[ARRAY_SIZE(zynq_dt_params)] = {
929 PCONFDUMP(PIN_CONFIG_IOSTANDARD, "IO-standard", NULL, true),
930};
931#endif
932
933static unsigned int zynq_pinconf_iostd_get(u32 reg)
934{
935 return (reg & ZYNQ_PINCONF_IOTYPE_MASK) >> ZYNQ_PINCONF_IOTYPE_SHIFT;
936}
937
938static int zynq_pinconf_cfg_get(struct pinctrl_dev *pctldev,
939 unsigned pin,
940 unsigned long *config)
941{
942 u32 reg;
943 int ret;
944 unsigned int arg = 0;
945 unsigned int param = pinconf_to_config_param(*config);
946 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
947
948 if (pin >= ZYNQ_NUM_MIOS)
949 return -ENOTSUPP;
950
951 ret = regmap_read(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), &reg);
952 if (ret)
953 return -EIO;
954
955 switch (param) {
956 case PIN_CONFIG_BIAS_PULL_UP:
957 if (!(reg & ZYNQ_PINCONF_PULLUP))
958 return -EINVAL;
959 arg = 1;
960 break;
961 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
962 if (!(reg & ZYNQ_PINCONF_TRISTATE))
963 return -EINVAL;
964 arg = 1;
965 break;
966 case PIN_CONFIG_BIAS_DISABLE:
967 if (reg & ZYNQ_PINCONF_PULLUP || reg & ZYNQ_PINCONF_TRISTATE)
968 return -EINVAL;
969 break;
970 case PIN_CONFIG_SLEW_RATE:
971 arg = !!(reg & ZYNQ_PINCONF_SPEED);
972 break;
973 case PIN_CONFIG_LOW_POWER_MODE:
974 {
975 enum zynq_io_standards iostd = zynq_pinconf_iostd_get(reg);
976
977 if (iostd != zynq_iostd_hstl)
978 return -EINVAL;
979 if (!(reg & ZYNQ_PINCONF_DISABLE_RECVR))
980 return -EINVAL;
981 arg = !!(reg & ZYNQ_PINCONF_DISABLE_RECVR);
982 break;
983 }
984 case PIN_CONFIG_IOSTANDARD:
985 arg = zynq_pinconf_iostd_get(reg);
986 break;
987 default:
988 return -ENOTSUPP;
989 }
990
991 *config = pinconf_to_config_packed(param, arg);
992 return 0;
993}
994
995static int zynq_pinconf_cfg_set(struct pinctrl_dev *pctldev,
996 unsigned pin,
997 unsigned long *configs,
998 unsigned num_configs)
999{
1000 int i, ret;
1001 u32 reg;
1002 u32 pullup = 0;
1003 u32 tristate = 0;
1004 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1005
1006 if (pin >= ZYNQ_NUM_MIOS)
1007 return -ENOTSUPP;
1008
1009 ret = regmap_read(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), &reg);
1010 if (ret)
1011 return -EIO;
1012
1013 for (i = 0; i < num_configs; i++) {
1014 unsigned int param = pinconf_to_config_param(configs[i]);
1015 unsigned int arg = pinconf_to_config_argument(configs[i]);
1016
1017 switch (param) {
1018 case PIN_CONFIG_BIAS_PULL_UP:
1019 pullup = ZYNQ_PINCONF_PULLUP;
1020 break;
1021 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1022 tristate = ZYNQ_PINCONF_TRISTATE;
1023 break;
1024 case PIN_CONFIG_BIAS_DISABLE:
1025 reg &= ~(ZYNQ_PINCONF_PULLUP | ZYNQ_PINCONF_TRISTATE);
1026 break;
1027 case PIN_CONFIG_SLEW_RATE:
1028 if (arg)
1029 reg |= ZYNQ_PINCONF_SPEED;
1030 else
1031 reg &= ~ZYNQ_PINCONF_SPEED;
1032
1033 break;
1034 case PIN_CONFIG_IOSTANDARD:
1035 if (arg <= zynq_iostd_min || arg >= zynq_iostd_max) {
1036 dev_warn(pctldev->dev,
1037 "unsupported IO standard '%u'\n",
1038 param);
1039 break;
1040 }
1041 reg &= ~ZYNQ_PINCONF_IOTYPE_MASK;
1042 reg |= arg << ZYNQ_PINCONF_IOTYPE_SHIFT;
1043 break;
1044 case PIN_CONFIG_LOW_POWER_MODE:
1045 if (arg)
1046 reg |= ZYNQ_PINCONF_DISABLE_RECVR;
1047 else
1048 reg &= ~ZYNQ_PINCONF_DISABLE_RECVR;
1049
1050 break;
1051 default:
1052 dev_warn(pctldev->dev,
1053 "unsupported configuration parameter '%u'\n",
1054 param);
1055 continue;
1056 }
1057 }
1058
1059 if (tristate || pullup) {
1060 reg &= ~(ZYNQ_PINCONF_PULLUP | ZYNQ_PINCONF_TRISTATE);
1061 reg |= tristate | pullup;
1062 }
1063
1064 ret = regmap_write(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), reg);
1065 if (ret)
1066 return -EIO;
1067
1068 return 0;
1069}
1070
1071static int zynq_pinconf_group_set(struct pinctrl_dev *pctldev,
1072 unsigned selector,
1073 unsigned long *configs,
1074 unsigned num_configs)
1075{
1076 int i, ret;
1077 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1078 const struct zynq_pctrl_group *pgrp = &pctrl->groups[selector];
1079
1080 for (i = 0; i < pgrp->npins; i++) {
1081 ret = zynq_pinconf_cfg_set(pctldev, pgrp->pins[i], configs,
1082 num_configs);
1083 if (ret)
1084 return ret;
1085 }
1086
1087 return 0;
1088}
1089
1090static const struct pinconf_ops zynq_pinconf_ops = {
1091 .is_generic = true,
1092 .pin_config_get = zynq_pinconf_cfg_get,
1093 .pin_config_set = zynq_pinconf_cfg_set,
1094 .pin_config_group_set = zynq_pinconf_group_set,
1095};
1096
1097static struct pinctrl_desc zynq_desc = {
1098 .name = "zynq_pinctrl",
1099 .pins = zynq_pins,
1100 .npins = ARRAY_SIZE(zynq_pins),
1101 .pctlops = &zynq_pctrl_ops,
1102 .pmxops = &zynq_pinmux_ops,
1103 .confops = &zynq_pinconf_ops,
1104 .num_custom_params = ARRAY_SIZE(zynq_dt_params),
1105 .custom_params = zynq_dt_params,
1106#ifdef CONFIG_DEBUG_FS
1107 .custom_conf_items = zynq_conf_items,
1108#endif
1109 .owner = THIS_MODULE,
1110};
1111
1112static int zynq_pinctrl_probe(struct platform_device *pdev)
1113
1114{
1115 struct resource *res;
1116 struct zynq_pinctrl *pctrl;
1117
1118 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1119 if (!pctrl)
1120 return -ENOMEM;
1121
1122 pctrl->syscon = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1123 "syscon");
1124 if (IS_ERR(pctrl->syscon)) {
1125 dev_err(&pdev->dev, "unable to get syscon\n");
1126 return PTR_ERR(pctrl->syscon);
1127 }
1128
1129 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1130 if (!res) {
1131 dev_err(&pdev->dev, "missing IO resource\n");
1132 return -ENODEV;
1133 }
1134 pctrl->pctrl_offset = res->start;
1135
1136 pctrl->groups = zynq_pctrl_groups;
1137 pctrl->ngroups = ARRAY_SIZE(zynq_pctrl_groups);
1138 pctrl->funcs = zynq_pmux_functions;
1139 pctrl->nfuncs = ARRAY_SIZE(zynq_pmux_functions);
1140
1141 pctrl->pctrl = pinctrl_register(&zynq_desc, &pdev->dev, pctrl);
1142 if (!pctrl->pctrl)
1143 return -ENOMEM;
1144
1145 platform_set_drvdata(pdev, pctrl);
1146
1147 dev_info(&pdev->dev, "zynq pinctrl initialized\n");
1148
1149 return 0;
1150}
1151
1152int zynq_pinctrl_remove(struct platform_device *pdev)
1153{
1154 struct zynq_pinctrl *pctrl = platform_get_drvdata(pdev);
1155
1156 pinctrl_unregister(pctrl->pctrl);
1157
1158 return 0;
1159}
1160
1161static const struct of_device_id zynq_pinctrl_of_match[] = {
1162 { .compatible = "xlnx,pinctrl-zynq" },
1163 { }
1164};
1165MODULE_DEVICE_TABLE(of, zynq_pinctrl_of_match);
1166
1167static struct platform_driver zynq_pinctrl_driver = {
1168 .driver = {
1169 .name = "zynq-pinctrl",
1170 .of_match_table = zynq_pinctrl_of_match,
1171 },
1172 .probe = zynq_pinctrl_probe,
1173 .remove = zynq_pinctrl_remove,
1174};
1175
1176module_platform_driver(zynq_pinctrl_driver);
1177
1178MODULE_AUTHOR("Sören Brinkmann <soren.brinkmann@xilinx.com>");
1179MODULE_DESCRIPTION("Xilinx Zynq pinctrl driver");
1180MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 3cd243c26b7d..ea575f60f001 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -47,6 +47,14 @@ config PINCTRL_MSM8X74
47 This is the pinctrl, pinmux, pinconf and gpiolib driver for the 47 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
48 Qualcomm TLMM block found in the Qualcomm 8974 platform. 48 Qualcomm TLMM block found in the Qualcomm 8974 platform.
49 49
50config PINCTRL_MSM8916
51 tristate "Qualcomm 8916 pin controller driver"
52 depends on GPIOLIB && OF
53 select PINCTRL_MSM
54 help
55 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
56 Qualcomm TLMM block found on the Qualcomm 8916 platform.
57
50config PINCTRL_QCOM_SPMI_PMIC 58config PINCTRL_QCOM_SPMI_PMIC
51 tristate "Qualcomm SPMI PMIC pin controller driver" 59 tristate "Qualcomm SPMI PMIC pin controller driver"
52 depends on GPIOLIB && OF && SPMI 60 depends on GPIOLIB && OF && SPMI
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index bfd79af5f982..68958702917d 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -5,5 +5,6 @@ obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
5obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o 5obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
6obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o 6obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o
7obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o 7obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
8obj-$(CONFIG_PINCTRL_MSM8916) += pinctrl-msm8916.o
8obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o 9obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o
9obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o 10obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index ed7017df065d..a535f9c23678 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -204,21 +204,6 @@ static int msm_config_reg(struct msm_pinctrl *pctrl,
204 return 0; 204 return 0;
205} 205}
206 206
207static int msm_config_get(struct pinctrl_dev *pctldev,
208 unsigned int pin,
209 unsigned long *config)
210{
211 dev_err(pctldev->dev, "pin_config_set op not supported\n");
212 return -ENOTSUPP;
213}
214
215static int msm_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
216 unsigned long *configs, unsigned num_configs)
217{
218 dev_err(pctldev->dev, "pin_config_set op not supported\n");
219 return -ENOTSUPP;
220}
221
222#define MSM_NO_PULL 0 207#define MSM_NO_PULL 0
223#define MSM_PULL_DOWN 1 208#define MSM_PULL_DOWN 1
224#define MSM_KEEPER 2 209#define MSM_KEEPER 2
@@ -372,8 +357,6 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev,
372} 357}
373 358
374static const struct pinconf_ops msm_pinconf_ops = { 359static const struct pinconf_ops msm_pinconf_ops = {
375 .pin_config_get = msm_config_get,
376 .pin_config_set = msm_config_set,
377 .pin_config_group_get = msm_config_group_get, 360 .pin_config_group_get = msm_config_group_get,
378 .pin_config_group_set = msm_config_group_set, 361 .pin_config_group_set = msm_config_group_set,
379}; 362};
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h
index b952c4b4a8e9..54fdd04ce9d5 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.h
+++ b/drivers/pinctrl/qcom/pinctrl-msm.h
@@ -70,11 +70,11 @@ struct msm_pingroup {
70 unsigned *funcs; 70 unsigned *funcs;
71 unsigned nfuncs; 71 unsigned nfuncs;
72 72
73 s16 ctl_reg; 73 u32 ctl_reg;
74 s16 io_reg; 74 u32 io_reg;
75 s16 intr_cfg_reg; 75 u32 intr_cfg_reg;
76 s16 intr_status_reg; 76 u32 intr_status_reg;
77 s16 intr_target_reg; 77 u32 intr_target_reg;
78 78
79 unsigned mux_bit:5; 79 unsigned mux_bit:5;
80 80
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8916.c b/drivers/pinctrl/qcom/pinctrl-msm8916.c
new file mode 100644
index 000000000000..20ebf244e80d
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-msm8916.c
@@ -0,0 +1,1005 @@
1/*
2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/platform_device.h>
17#include <linux/pinctrl/pinctrl.h>
18
19#include "pinctrl-msm.h"
20
21static const struct pinctrl_pin_desc msm8916_pins[] = {
22 PINCTRL_PIN(0, "GPIO_0"),
23 PINCTRL_PIN(1, "GPIO_1"),
24 PINCTRL_PIN(2, "GPIO_2"),
25 PINCTRL_PIN(3, "GPIO_3"),
26 PINCTRL_PIN(4, "GPIO_4"),
27 PINCTRL_PIN(5, "GPIO_5"),
28 PINCTRL_PIN(6, "GPIO_6"),
29 PINCTRL_PIN(7, "GPIO_7"),
30 PINCTRL_PIN(8, "GPIO_8"),
31 PINCTRL_PIN(9, "GPIO_9"),
32 PINCTRL_PIN(10, "GPIO_10"),
33 PINCTRL_PIN(11, "GPIO_11"),
34 PINCTRL_PIN(12, "GPIO_12"),
35 PINCTRL_PIN(13, "GPIO_13"),
36 PINCTRL_PIN(14, "GPIO_14"),
37 PINCTRL_PIN(15, "GPIO_15"),
38 PINCTRL_PIN(16, "GPIO_16"),
39 PINCTRL_PIN(17, "GPIO_17"),
40 PINCTRL_PIN(18, "GPIO_18"),
41 PINCTRL_PIN(19, "GPIO_19"),
42 PINCTRL_PIN(20, "GPIO_20"),
43 PINCTRL_PIN(21, "GPIO_21"),
44 PINCTRL_PIN(22, "GPIO_22"),
45 PINCTRL_PIN(23, "GPIO_23"),
46 PINCTRL_PIN(24, "GPIO_24"),
47 PINCTRL_PIN(25, "GPIO_25"),
48 PINCTRL_PIN(26, "GPIO_26"),
49 PINCTRL_PIN(27, "GPIO_27"),
50 PINCTRL_PIN(28, "GPIO_28"),
51 PINCTRL_PIN(29, "GPIO_29"),
52 PINCTRL_PIN(30, "GPIO_30"),
53 PINCTRL_PIN(31, "GPIO_31"),
54 PINCTRL_PIN(32, "GPIO_32"),
55 PINCTRL_PIN(33, "GPIO_33"),
56 PINCTRL_PIN(34, "GPIO_34"),
57 PINCTRL_PIN(35, "GPIO_35"),
58 PINCTRL_PIN(36, "GPIO_36"),
59 PINCTRL_PIN(37, "GPIO_37"),
60 PINCTRL_PIN(38, "GPIO_38"),
61 PINCTRL_PIN(39, "GPIO_39"),
62 PINCTRL_PIN(40, "GPIO_40"),
63 PINCTRL_PIN(41, "GPIO_41"),
64 PINCTRL_PIN(42, "GPIO_42"),
65 PINCTRL_PIN(43, "GPIO_43"),
66 PINCTRL_PIN(44, "GPIO_44"),
67 PINCTRL_PIN(45, "GPIO_45"),
68 PINCTRL_PIN(46, "GPIO_46"),
69 PINCTRL_PIN(47, "GPIO_47"),
70 PINCTRL_PIN(48, "GPIO_48"),
71 PINCTRL_PIN(49, "GPIO_49"),
72 PINCTRL_PIN(50, "GPIO_50"),
73 PINCTRL_PIN(51, "GPIO_51"),
74 PINCTRL_PIN(52, "GPIO_52"),
75 PINCTRL_PIN(53, "GPIO_53"),
76 PINCTRL_PIN(54, "GPIO_54"),
77 PINCTRL_PIN(55, "GPIO_55"),
78 PINCTRL_PIN(56, "GPIO_56"),
79 PINCTRL_PIN(57, "GPIO_57"),
80 PINCTRL_PIN(58, "GPIO_58"),
81 PINCTRL_PIN(59, "GPIO_59"),
82 PINCTRL_PIN(60, "GPIO_60"),
83 PINCTRL_PIN(61, "GPIO_61"),
84 PINCTRL_PIN(62, "GPIO_62"),
85 PINCTRL_PIN(63, "GPIO_63"),
86 PINCTRL_PIN(64, "GPIO_64"),
87 PINCTRL_PIN(65, "GPIO_65"),
88 PINCTRL_PIN(66, "GPIO_66"),
89 PINCTRL_PIN(67, "GPIO_67"),
90 PINCTRL_PIN(68, "GPIO_68"),
91 PINCTRL_PIN(69, "GPIO_69"),
92 PINCTRL_PIN(70, "GPIO_70"),
93 PINCTRL_PIN(71, "GPIO_71"),
94 PINCTRL_PIN(72, "GPIO_72"),
95 PINCTRL_PIN(73, "GPIO_73"),
96 PINCTRL_PIN(74, "GPIO_74"),
97 PINCTRL_PIN(75, "GPIO_75"),
98 PINCTRL_PIN(76, "GPIO_76"),
99 PINCTRL_PIN(77, "GPIO_77"),
100 PINCTRL_PIN(78, "GPIO_78"),
101 PINCTRL_PIN(79, "GPIO_79"),
102 PINCTRL_PIN(80, "GPIO_80"),
103 PINCTRL_PIN(81, "GPIO_81"),
104 PINCTRL_PIN(82, "GPIO_82"),
105 PINCTRL_PIN(83, "GPIO_83"),
106 PINCTRL_PIN(84, "GPIO_84"),
107 PINCTRL_PIN(85, "GPIO_85"),
108 PINCTRL_PIN(86, "GPIO_86"),
109 PINCTRL_PIN(87, "GPIO_87"),
110 PINCTRL_PIN(88, "GPIO_88"),
111 PINCTRL_PIN(89, "GPIO_89"),
112 PINCTRL_PIN(90, "GPIO_90"),
113 PINCTRL_PIN(91, "GPIO_91"),
114 PINCTRL_PIN(92, "GPIO_92"),
115 PINCTRL_PIN(93, "GPIO_93"),
116 PINCTRL_PIN(94, "GPIO_94"),
117 PINCTRL_PIN(95, "GPIO_95"),
118 PINCTRL_PIN(96, "GPIO_96"),
119 PINCTRL_PIN(97, "GPIO_97"),
120 PINCTRL_PIN(98, "GPIO_98"),
121 PINCTRL_PIN(99, "GPIO_99"),
122 PINCTRL_PIN(100, "GPIO_100"),
123 PINCTRL_PIN(101, "GPIO_101"),
124 PINCTRL_PIN(102, "GPIO_102"),
125 PINCTRL_PIN(103, "GPIO_103"),
126 PINCTRL_PIN(104, "GPIO_104"),
127 PINCTRL_PIN(105, "GPIO_105"),
128 PINCTRL_PIN(106, "GPIO_106"),
129 PINCTRL_PIN(107, "GPIO_107"),
130 PINCTRL_PIN(108, "GPIO_108"),
131 PINCTRL_PIN(109, "GPIO_109"),
132 PINCTRL_PIN(110, "GPIO_110"),
133 PINCTRL_PIN(111, "GPIO_111"),
134 PINCTRL_PIN(112, "GPIO_112"),
135 PINCTRL_PIN(113, "GPIO_113"),
136 PINCTRL_PIN(114, "GPIO_114"),
137 PINCTRL_PIN(115, "GPIO_115"),
138 PINCTRL_PIN(116, "GPIO_116"),
139 PINCTRL_PIN(117, "GPIO_117"),
140 PINCTRL_PIN(118, "GPIO_118"),
141 PINCTRL_PIN(119, "GPIO_119"),
142 PINCTRL_PIN(120, "GPIO_120"),
143 PINCTRL_PIN(121, "GPIO_121"),
144 PINCTRL_PIN(122, "SDC1_CLK"),
145 PINCTRL_PIN(123, "SDC1_CMD"),
146 PINCTRL_PIN(124, "SDC1_DATA"),
147 PINCTRL_PIN(125, "SDC2_CLK"),
148 PINCTRL_PIN(126, "SDC2_CMD"),
149 PINCTRL_PIN(127, "SDC2_DATA"),
150 PINCTRL_PIN(128, "QDSD_CLK"),
151 PINCTRL_PIN(129, "QDSD_CMD"),
152 PINCTRL_PIN(130, "QDSD_DATA0"),
153 PINCTRL_PIN(131, "QDSD_DATA1"),
154 PINCTRL_PIN(132, "QDSD_DATA2"),
155 PINCTRL_PIN(133, "QDSD_DATA3"),
156};
157
158#define DECLARE_MSM_GPIO_PINS(pin) \
159 static const unsigned int gpio##pin##_pins[] = { pin }
160
161DECLARE_MSM_GPIO_PINS(0);
162DECLARE_MSM_GPIO_PINS(1);
163DECLARE_MSM_GPIO_PINS(2);
164DECLARE_MSM_GPIO_PINS(3);
165DECLARE_MSM_GPIO_PINS(4);
166DECLARE_MSM_GPIO_PINS(5);
167DECLARE_MSM_GPIO_PINS(6);
168DECLARE_MSM_GPIO_PINS(7);
169DECLARE_MSM_GPIO_PINS(8);
170DECLARE_MSM_GPIO_PINS(9);
171DECLARE_MSM_GPIO_PINS(10);
172DECLARE_MSM_GPIO_PINS(11);
173DECLARE_MSM_GPIO_PINS(12);
174DECLARE_MSM_GPIO_PINS(13);
175DECLARE_MSM_GPIO_PINS(14);
176DECLARE_MSM_GPIO_PINS(15);
177DECLARE_MSM_GPIO_PINS(16);
178DECLARE_MSM_GPIO_PINS(17);
179DECLARE_MSM_GPIO_PINS(18);
180DECLARE_MSM_GPIO_PINS(19);
181DECLARE_MSM_GPIO_PINS(20);
182DECLARE_MSM_GPIO_PINS(21);
183DECLARE_MSM_GPIO_PINS(22);
184DECLARE_MSM_GPIO_PINS(23);
185DECLARE_MSM_GPIO_PINS(24);
186DECLARE_MSM_GPIO_PINS(25);
187DECLARE_MSM_GPIO_PINS(26);
188DECLARE_MSM_GPIO_PINS(27);
189DECLARE_MSM_GPIO_PINS(28);
190DECLARE_MSM_GPIO_PINS(29);
191DECLARE_MSM_GPIO_PINS(30);
192DECLARE_MSM_GPIO_PINS(31);
193DECLARE_MSM_GPIO_PINS(32);
194DECLARE_MSM_GPIO_PINS(33);
195DECLARE_MSM_GPIO_PINS(34);
196DECLARE_MSM_GPIO_PINS(35);
197DECLARE_MSM_GPIO_PINS(36);
198DECLARE_MSM_GPIO_PINS(37);
199DECLARE_MSM_GPIO_PINS(38);
200DECLARE_MSM_GPIO_PINS(39);
201DECLARE_MSM_GPIO_PINS(40);
202DECLARE_MSM_GPIO_PINS(41);
203DECLARE_MSM_GPIO_PINS(42);
204DECLARE_MSM_GPIO_PINS(43);
205DECLARE_MSM_GPIO_PINS(44);
206DECLARE_MSM_GPIO_PINS(45);
207DECLARE_MSM_GPIO_PINS(46);
208DECLARE_MSM_GPIO_PINS(47);
209DECLARE_MSM_GPIO_PINS(48);
210DECLARE_MSM_GPIO_PINS(49);
211DECLARE_MSM_GPIO_PINS(50);
212DECLARE_MSM_GPIO_PINS(51);
213DECLARE_MSM_GPIO_PINS(52);
214DECLARE_MSM_GPIO_PINS(53);
215DECLARE_MSM_GPIO_PINS(54);
216DECLARE_MSM_GPIO_PINS(55);
217DECLARE_MSM_GPIO_PINS(56);
218DECLARE_MSM_GPIO_PINS(57);
219DECLARE_MSM_GPIO_PINS(58);
220DECLARE_MSM_GPIO_PINS(59);
221DECLARE_MSM_GPIO_PINS(60);
222DECLARE_MSM_GPIO_PINS(61);
223DECLARE_MSM_GPIO_PINS(62);
224DECLARE_MSM_GPIO_PINS(63);
225DECLARE_MSM_GPIO_PINS(64);
226DECLARE_MSM_GPIO_PINS(65);
227DECLARE_MSM_GPIO_PINS(66);
228DECLARE_MSM_GPIO_PINS(67);
229DECLARE_MSM_GPIO_PINS(68);
230DECLARE_MSM_GPIO_PINS(69);
231DECLARE_MSM_GPIO_PINS(70);
232DECLARE_MSM_GPIO_PINS(71);
233DECLARE_MSM_GPIO_PINS(72);
234DECLARE_MSM_GPIO_PINS(73);
235DECLARE_MSM_GPIO_PINS(74);
236DECLARE_MSM_GPIO_PINS(75);
237DECLARE_MSM_GPIO_PINS(76);
238DECLARE_MSM_GPIO_PINS(77);
239DECLARE_MSM_GPIO_PINS(78);
240DECLARE_MSM_GPIO_PINS(79);
241DECLARE_MSM_GPIO_PINS(80);
242DECLARE_MSM_GPIO_PINS(81);
243DECLARE_MSM_GPIO_PINS(82);
244DECLARE_MSM_GPIO_PINS(83);
245DECLARE_MSM_GPIO_PINS(84);
246DECLARE_MSM_GPIO_PINS(85);
247DECLARE_MSM_GPIO_PINS(86);
248DECLARE_MSM_GPIO_PINS(87);
249DECLARE_MSM_GPIO_PINS(88);
250DECLARE_MSM_GPIO_PINS(89);
251DECLARE_MSM_GPIO_PINS(90);
252DECLARE_MSM_GPIO_PINS(91);
253DECLARE_MSM_GPIO_PINS(92);
254DECLARE_MSM_GPIO_PINS(93);
255DECLARE_MSM_GPIO_PINS(94);
256DECLARE_MSM_GPIO_PINS(95);
257DECLARE_MSM_GPIO_PINS(96);
258DECLARE_MSM_GPIO_PINS(97);
259DECLARE_MSM_GPIO_PINS(98);
260DECLARE_MSM_GPIO_PINS(99);
261DECLARE_MSM_GPIO_PINS(100);
262DECLARE_MSM_GPIO_PINS(101);
263DECLARE_MSM_GPIO_PINS(102);
264DECLARE_MSM_GPIO_PINS(103);
265DECLARE_MSM_GPIO_PINS(104);
266DECLARE_MSM_GPIO_PINS(105);
267DECLARE_MSM_GPIO_PINS(106);
268DECLARE_MSM_GPIO_PINS(107);
269DECLARE_MSM_GPIO_PINS(108);
270DECLARE_MSM_GPIO_PINS(109);
271DECLARE_MSM_GPIO_PINS(110);
272DECLARE_MSM_GPIO_PINS(111);
273DECLARE_MSM_GPIO_PINS(112);
274DECLARE_MSM_GPIO_PINS(113);
275DECLARE_MSM_GPIO_PINS(114);
276DECLARE_MSM_GPIO_PINS(115);
277DECLARE_MSM_GPIO_PINS(116);
278DECLARE_MSM_GPIO_PINS(117);
279DECLARE_MSM_GPIO_PINS(118);
280DECLARE_MSM_GPIO_PINS(119);
281DECLARE_MSM_GPIO_PINS(120);
282DECLARE_MSM_GPIO_PINS(121);
283
284static const unsigned int sdc1_clk_pins[] = { 122 };
285static const unsigned int sdc1_cmd_pins[] = { 123 };
286static const unsigned int sdc1_data_pins[] = { 124 };
287static const unsigned int sdc2_clk_pins[] = { 125 };
288static const unsigned int sdc2_cmd_pins[] = { 126 };
289static const unsigned int sdc2_data_pins[] = { 127 };
290static const unsigned int qdsd_clk_pins[] = { 128 };
291static const unsigned int qdsd_cmd_pins[] = { 129 };
292static const unsigned int qdsd_data0_pins[] = { 130 };
293static const unsigned int qdsd_data1_pins[] = { 131 };
294static const unsigned int qdsd_data2_pins[] = { 132 };
295static const unsigned int qdsd_data3_pins[] = { 133 };
296
297#define FUNCTION(fname) \
298 [MSM_MUX_##fname] = { \
299 .name = #fname, \
300 .groups = fname##_groups, \
301 .ngroups = ARRAY_SIZE(fname##_groups), \
302 }
303
304#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
305 { \
306 .name = "gpio" #id, \
307 .pins = gpio##id##_pins, \
308 .npins = ARRAY_SIZE(gpio##id##_pins), \
309 .funcs = (int[]){ \
310 MSM_MUX_gpio, \
311 MSM_MUX_##f1, \
312 MSM_MUX_##f2, \
313 MSM_MUX_##f3, \
314 MSM_MUX_##f4, \
315 MSM_MUX_##f5, \
316 MSM_MUX_##f6, \
317 MSM_MUX_##f7, \
318 MSM_MUX_##f8, \
319 MSM_MUX_##f9 \
320 }, \
321 .nfuncs = 10, \
322 .ctl_reg = 0x1000 * id, \
323 .io_reg = 0x4 + 0x1000 * id, \
324 .intr_cfg_reg = 0x8 + 0x1000 * id, \
325 .intr_status_reg = 0xc + 0x1000 * id, \
326 .intr_target_reg = 0x8 + 0x1000 * id, \
327 .mux_bit = 2, \
328 .pull_bit = 0, \
329 .drv_bit = 6, \
330 .oe_bit = 9, \
331 .in_bit = 0, \
332 .out_bit = 1, \
333 .intr_enable_bit = 0, \
334 .intr_status_bit = 0, \
335 .intr_target_bit = 5, \
336 .intr_target_kpss_val = 4, \
337 .intr_raw_status_bit = 4, \
338 .intr_polarity_bit = 1, \
339 .intr_detection_bit = 2, \
340 .intr_detection_width = 2, \
341 }
342
343#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
344 { \
345 .name = #pg_name, \
346 .pins = pg_name##_pins, \
347 .npins = ARRAY_SIZE(pg_name##_pins), \
348 .ctl_reg = ctl, \
349 .io_reg = 0, \
350 .intr_cfg_reg = 0, \
351 .intr_status_reg = 0, \
352 .intr_target_reg = 0, \
353 .mux_bit = -1, \
354 .pull_bit = pull, \
355 .drv_bit = drv, \
356 .oe_bit = -1, \
357 .in_bit = -1, \
358 .out_bit = -1, \
359 .intr_enable_bit = -1, \
360 .intr_status_bit = -1, \
361 .intr_target_bit = -1, \
362 .intr_target_kpss_val = -1, \
363 .intr_raw_status_bit = -1, \
364 .intr_polarity_bit = -1, \
365 .intr_detection_bit = -1, \
366 .intr_detection_width = -1, \
367 }
368
369enum msm8916_functions {
370 MSM_MUX_adsp_ext,
371 MSM_MUX_alsp_int,
372 MSM_MUX_atest_bbrx0,
373 MSM_MUX_atest_bbrx1,
374 MSM_MUX_atest_char,
375 MSM_MUX_atest_char0,
376 MSM_MUX_atest_char1,
377 MSM_MUX_atest_char2,
378 MSM_MUX_atest_char3,
379 MSM_MUX_atest_combodac,
380 MSM_MUX_atest_gpsadc0,
381 MSM_MUX_atest_gpsadc1,
382 MSM_MUX_atest_tsens,
383 MSM_MUX_atest_wlan0,
384 MSM_MUX_atest_wlan1,
385 MSM_MUX_backlight_en,
386 MSM_MUX_bimc_dte0,
387 MSM_MUX_bimc_dte1,
388 MSM_MUX_blsp_i2c1,
389 MSM_MUX_blsp_i2c2,
390 MSM_MUX_blsp_i2c3,
391 MSM_MUX_blsp_i2c4,
392 MSM_MUX_blsp_i2c5,
393 MSM_MUX_blsp_i2c6,
394 MSM_MUX_blsp_spi1,
395 MSM_MUX_blsp_spi1_cs1,
396 MSM_MUX_blsp_spi1_cs2,
397 MSM_MUX_blsp_spi1_cs3,
398 MSM_MUX_blsp_spi2,
399 MSM_MUX_blsp_spi2_cs1,
400 MSM_MUX_blsp_spi2_cs2,
401 MSM_MUX_blsp_spi2_cs3,
402 MSM_MUX_blsp_spi3,
403 MSM_MUX_blsp_spi3_cs1,
404 MSM_MUX_blsp_spi3_cs2,
405 MSM_MUX_blsp_spi3_cs3,
406 MSM_MUX_blsp_spi4,
407 MSM_MUX_blsp_spi5,
408 MSM_MUX_blsp_spi6,
409 MSM_MUX_blsp_uart1,
410 MSM_MUX_blsp_uart2,
411 MSM_MUX_blsp_uim1,
412 MSM_MUX_blsp_uim2,
413 MSM_MUX_cam1_rst,
414 MSM_MUX_cam1_standby,
415 MSM_MUX_cam_mclk0,
416 MSM_MUX_cam_mclk1,
417 MSM_MUX_cci_async,
418 MSM_MUX_cci_i2c,
419 MSM_MUX_cci_timer0,
420 MSM_MUX_cci_timer1,
421 MSM_MUX_cci_timer2,
422 MSM_MUX_cdc_pdm0,
423 MSM_MUX_codec_mad,
424 MSM_MUX_dbg_out,
425 MSM_MUX_display_5v,
426 MSM_MUX_dmic0_clk,
427 MSM_MUX_dmic0_data,
428 MSM_MUX_dsi_rst,
429 MSM_MUX_ebi0_wrcdc,
430 MSM_MUX_euro_us,
431 MSM_MUX_ext_lpass,
432 MSM_MUX_flash_strobe,
433 MSM_MUX_gcc_gp1_clk_a,
434 MSM_MUX_gcc_gp1_clk_b,
435 MSM_MUX_gcc_gp2_clk_a,
436 MSM_MUX_gcc_gp2_clk_b,
437 MSM_MUX_gcc_gp3_clk_a,
438 MSM_MUX_gcc_gp3_clk_b,
439 MSM_MUX_gpio,
440 MSM_MUX_gsm0_tx0,
441 MSM_MUX_gsm0_tx1,
442 MSM_MUX_gsm1_tx0,
443 MSM_MUX_gsm1_tx1,
444 MSM_MUX_gyro_accl,
445 MSM_MUX_kpsns0,
446 MSM_MUX_kpsns1,
447 MSM_MUX_kpsns2,
448 MSM_MUX_ldo_en,
449 MSM_MUX_ldo_update,
450 MSM_MUX_mag_int,
451 MSM_MUX_mdp_vsync,
452 MSM_MUX_modem_tsync,
453 MSM_MUX_m_voc,
454 MSM_MUX_nav_pps,
455 MSM_MUX_nav_tsync,
456 MSM_MUX_pa_indicator,
457 MSM_MUX_pbs0,
458 MSM_MUX_pbs1,
459 MSM_MUX_pbs2,
460 MSM_MUX_pri_mi2s,
461 MSM_MUX_pri_mi2s_ws,
462 MSM_MUX_prng_rosc,
463 MSM_MUX_pwr_crypto_enabled_a,
464 MSM_MUX_pwr_crypto_enabled_b,
465 MSM_MUX_pwr_modem_enabled_a,
466 MSM_MUX_pwr_modem_enabled_b,
467 MSM_MUX_pwr_nav_enabled_a,
468 MSM_MUX_pwr_nav_enabled_b,
469 MSM_MUX_qdss_ctitrig_in_a0,
470 MSM_MUX_qdss_ctitrig_in_a1,
471 MSM_MUX_qdss_ctitrig_in_b0,
472 MSM_MUX_qdss_ctitrig_in_b1,
473 MSM_MUX_qdss_ctitrig_out_a0,
474 MSM_MUX_qdss_ctitrig_out_a1,
475 MSM_MUX_qdss_ctitrig_out_b0,
476 MSM_MUX_qdss_ctitrig_out_b1,
477 MSM_MUX_qdss_traceclk_a,
478 MSM_MUX_qdss_traceclk_b,
479 MSM_MUX_qdss_tracectl_a,
480 MSM_MUX_qdss_tracectl_b,
481 MSM_MUX_qdss_tracedata_a,
482 MSM_MUX_qdss_tracedata_b,
483 MSM_MUX_reset_n,
484 MSM_MUX_sd_card,
485 MSM_MUX_sd_write,
486 MSM_MUX_sec_mi2s,
487 MSM_MUX_smb_int,
488 MSM_MUX_ssbi_wtr0,
489 MSM_MUX_ssbi_wtr1,
490 MSM_MUX_uim1,
491 MSM_MUX_uim2,
492 MSM_MUX_uim3,
493 MSM_MUX_uim_batt,
494 MSM_MUX_wcss_bt,
495 MSM_MUX_wcss_fm,
496 MSM_MUX_wcss_wlan,
497 MSM_MUX_webcam1_rst,
498 MSM_MUX_NA,
499};
500
501static const char * const gpio_groups[] = {
502 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
503 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
504 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
505 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
506 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
507 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
508 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
509 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
510 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
511 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
512 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
513 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
514 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
515 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
516 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
517 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
518 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
519 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121"
520};
521static const char * const adsp_ext_groups[] = { "gpio38" };
522static const char * const alsp_int_groups[] = { "gpio113" };
523static const char * const atest_bbrx0_groups[] = { "gpio17" };
524static const char * const atest_bbrx1_groups[] = { "gpio16" };
525static const char * const atest_char_groups[] = { "gpio62" };
526static const char * const atest_char0_groups[] = { "gpio60" };
527static const char * const atest_char1_groups[] = { "gpio59" };
528static const char * const atest_char2_groups[] = { "gpio58" };
529static const char * const atest_char3_groups[] = { "gpio57" };
530static const char * const atest_combodac_groups[] = {
531 "gpio4", "gpio12", "gpio13", "gpio20", "gpio21", "gpio28", "gpio29",
532 "gpio30", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", "gpio44",
533 "gpio45", "gpio46", "gpio47", "gpio48", "gpio69", "gpio107"
534};
535static const char * const atest_gpsadc0_groups[] = { "gpio7" };
536static const char * const atest_gpsadc1_groups[] = { "gpio18" };
537static const char * const atest_tsens_groups[] = { "gpio112" };
538static const char * const atest_wlan0_groups[] = { "gpio22" };
539static const char * const atest_wlan1_groups[] = { "gpio23" };
540static const char * const backlight_en_groups[] = { "gpio98" };
541static const char * const bimc_dte0_groups[] = { "gpio63", "gpio65" };
542static const char * const bimc_dte1_groups[] = { "gpio64", "gpio66" };
543static const char * const blsp_i2c1_groups[] = { "gpio2", "gpio3" };
544static const char * const blsp_i2c2_groups[] = { "gpio6", "gpio7" };
545static const char * const blsp_i2c3_groups[] = { "gpio10", "gpio11" };
546static const char * const blsp_i2c4_groups[] = { "gpio14", "gpio15" };
547static const char * const blsp_i2c5_groups[] = { "gpio18", "gpio19" };
548static const char * const blsp_i2c6_groups[] = { "gpio22", "gpio23" };
549static const char * const blsp_spi1_groups[] = {
550 "gpio0", "gpio1", "gpio2", "gpio3"
551};
552static const char * const blsp_spi1_cs1_groups[] = { "gpio110" };
553static const char * const blsp_spi1_cs2_groups[] = { "gpio16" };
554static const char * const blsp_spi1_cs3_groups[] = { "gpio4" };
555static const char * const blsp_spi2_groups[] = {
556 "gpio4", "gpio5", "gpio6", "gpio7"
557};
558static const char * const blsp_spi2_cs1_groups[] = { "gpio121" };
559static const char * const blsp_spi2_cs2_groups[] = { "gpio17" };
560static const char * const blsp_spi2_cs3_groups[] = { "gpio5" };
561static const char * const blsp_spi3_groups[] = {
562 "gpio8", "gpio9", "gpio10", "gpio11"
563};
564static const char * const blsp_spi3_cs1_groups[] = { "gpio120" };
565static const char * const blsp_spi3_cs2_groups[] = { "gpio37" };
566static const char * const blsp_spi3_cs3_groups[] = { "gpio69" };
567static const char * const blsp_spi4_groups[] = {
568 "gpio12", "gpio13", "gpio14", "gpio15"
569};
570static const char * const blsp_spi5_groups[] = {
571 "gpio16", "gpio17", "gpio18", "gpio19"
572};
573static const char * const blsp_spi6_groups[] = {
574 "gpio20", "gpio21", "gpio22", "gpio23"
575};
576static const char * const blsp_uart1_groups[] = {
577 "gpio0", "gpio1", "gpio2", "gpio3"
578};
579static const char * const blsp_uart2_groups[] = {
580 "gpio4", "gpio5", "gpio6", "gpio7"
581};
582static const char * const blsp_uim1_groups[] = { "gpio0", "gpio1" };
583static const char * const blsp_uim2_groups[] = { "gpio4", "gpio5" };
584static const char * const cam1_rst_groups[] = { "gpio35" };
585static const char * const cam1_standby_groups[] = { "gpio34" };
586static const char * const cam_mclk0_groups[] = { "gpio26" };
587static const char * const cam_mclk1_groups[] = { "gpio27" };
588static const char * const cci_async_groups[] = { "gpio33" };
589static const char * const cci_i2c_groups[] = { "gpio29", "gpio30" };
590static const char * const cci_timer0_groups[] = { "gpio31" };
591static const char * const cci_timer1_groups[] = { "gpio32" };
592static const char * const cci_timer2_groups[] = { "gpio38" };
593static const char * const cdc_pdm0_groups[] = {
594 "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"
595};
596static const char * const codec_mad_groups[] = { "gpio16" };
597static const char * const dbg_out_groups[] = { "gpio47" };
598static const char * const display_5v_groups[] = { "gpio97" };
599static const char * const dmic0_clk_groups[] = { "gpio0" };
600static const char * const dmic0_data_groups[] = { "gpio1" };
601static const char * const dsi_rst_groups[] = { "gpio25" };
602static const char * const ebi0_wrcdc_groups[] = { "gpio67" };
603static const char * const euro_us_groups[] = { "gpio120" };
604static const char * const ext_lpass_groups[] = { "gpio45" };
605static const char * const flash_strobe_groups[] = { "gpio31", "gpio32" };
606static const char * const gcc_gp1_clk_a_groups[] = { "gpio49" };
607static const char * const gcc_gp1_clk_b_groups[] = { "gpio97" };
608static const char * const gcc_gp2_clk_a_groups[] = { "gpio50" };
609static const char * const gcc_gp2_clk_b_groups[] = { "gpio12" };
610static const char * const gcc_gp3_clk_a_groups[] = { "gpio51" };
611static const char * const gcc_gp3_clk_b_groups[] = { "gpio13" };
612static const char * const gsm0_tx0_groups[] = { "gpio99" };
613static const char * const gsm0_tx1_groups[] = { "gpio100" };
614static const char * const gsm1_tx0_groups[] = { "gpio101" };
615static const char * const gsm1_tx1_groups[] = { "gpio102" };
616static const char * const gyro_accl_groups[] = {"gpio115" };
617static const char * const kpsns0_groups[] = { "gpio107" };
618static const char * const kpsns1_groups[] = { "gpio108" };
619static const char * const kpsns2_groups[] = { "gpio109" };
620static const char * const ldo_en_groups[] = { "gpio121" };
621static const char * const ldo_update_groups[] = { "gpio120" };
622static const char * const mag_int_groups[] = { "gpio69" };
623static const char * const mdp_vsync_groups[] = { "gpio24", "gpio25" };
624static const char * const modem_tsync_groups[] = { "gpio95" };
625static const char * const m_voc_groups[] = { "gpio8", "gpio119" };
626static const char * const nav_pps_groups[] = { "gpio95" };
627static const char * const nav_tsync_groups[] = { "gpio95" };
628static const char * const pa_indicator_groups[] = { "gpio86" };
629static const char * const pbs0_groups[] = { "gpio107" };
630static const char * const pbs1_groups[] = { "gpio108" };
631static const char * const pbs2_groups[] = { "gpio109" };
632static const char * const pri_mi2s_groups[] = {
633 "gpio113", "gpio114", "gpio115", "gpio116"
634};
635static const char * const pri_mi2s_ws_groups[] = { "gpio110" };
636static const char * const prng_rosc_groups[] = { "gpio43" };
637static const char * const pwr_crypto_enabled_a_groups[] = { "gpio35" };
638static const char * const pwr_crypto_enabled_b_groups[] = { "gpio115" };
639static const char * const pwr_modem_enabled_a_groups[] = { "gpio28" };
640static const char * const pwr_modem_enabled_b_groups[] = { "gpio113" };
641static const char * const pwr_nav_enabled_a_groups[] = { "gpio34" };
642static const char * const pwr_nav_enabled_b_groups[] = { "gpio114" };
643static const char * const qdss_ctitrig_in_a0_groups[] = { "gpio20" };
644static const char * const qdss_ctitrig_in_a1_groups[] = { "gpio49" };
645static const char * const qdss_ctitrig_in_b0_groups[] = { "gpio21" };
646static const char * const qdss_ctitrig_in_b1_groups[] = { "gpio50" };
647static const char * const qdss_ctitrig_out_a0_groups[] = { "gpio23" };
648static const char * const qdss_ctitrig_out_a1_groups[] = { "gpio52" };
649static const char * const qdss_ctitrig_out_b0_groups[] = { "gpio22" };
650static const char * const qdss_ctitrig_out_b1_groups[] = { "gpio51" };
651static const char * const qdss_traceclk_a_groups[] = { "gpio46" };
652static const char * const qdss_traceclk_b_groups[] = { "gpio5" };
653static const char * const qdss_tracectl_a_groups[] = { "gpio45" };
654static const char * const qdss_tracectl_b_groups[] = { "gpio4" };
655static const char * const qdss_tracedata_a_groups[] = {
656 "gpio8", "gpio9", "gpio10", "gpio39", "gpio40", "gpio41", "gpio42",
657 "gpio43", "gpio47", "gpio48", "gpio62", "gpio69", "gpio112", "gpio113",
658 "gpio114", "gpio115"
659};
660static const char * const qdss_tracedata_b_groups[] = {
661 "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
662 "gpio33", "gpio34", "gpio35", "gpio36", "gpio37", "gpio110", "gpio111",
663 "gpio120", "gpio121"
664};
665static const char * const reset_n_groups[] = { "gpio36" };
666static const char * const sd_card_groups[] = { "gpio38" };
667static const char * const sd_write_groups[] = { "gpio121" };
668static const char * const sec_mi2s_groups[] = {
669 "gpio112", "gpio117", "gpio118", "gpio119"
670};
671static const char * const smb_int_groups[] = { "gpio62" };
672static const char * const ssbi_wtr0_groups[] = { "gpio103", "gpio104" };
673static const char * const ssbi_wtr1_groups[] = { "gpio105", "gpio106" };
674static const char * const uim1_groups[] = {
675 "gpio57", "gpio58", "gpio59", "gpio60"
676};
677
678static const char * const uim2_groups[] = {
679 "gpio53", "gpio54", "gpio55", "gpio56"
680};
681static const char * const uim3_groups[] = {
682 "gpio49", "gpio50", "gpio51", "gpio52"
683};
684static const char * const uim_batt_groups[] = { "gpio61" };
685static const char * const wcss_bt_groups[] = { "gpio39", "gpio47", "gpio48" };
686static const char * const wcss_fm_groups[] = { "gpio45", "gpio46" };
687static const char * const wcss_wlan_groups[] = {
688 "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"
689};
690static const char * const webcam1_rst_groups[] = { "gpio28" };
691
692static const struct msm_function msm8916_functions[] = {
693 FUNCTION(adsp_ext),
694 FUNCTION(alsp_int),
695 FUNCTION(atest_bbrx0),
696 FUNCTION(atest_bbrx1),
697 FUNCTION(atest_char),
698 FUNCTION(atest_char0),
699 FUNCTION(atest_char1),
700 FUNCTION(atest_char2),
701 FUNCTION(atest_char3),
702 FUNCTION(atest_combodac),
703 FUNCTION(atest_gpsadc0),
704 FUNCTION(atest_gpsadc1),
705 FUNCTION(atest_tsens),
706 FUNCTION(atest_wlan0),
707 FUNCTION(atest_wlan1),
708 FUNCTION(backlight_en),
709 FUNCTION(bimc_dte0),
710 FUNCTION(bimc_dte1),
711 FUNCTION(blsp_i2c1),
712 FUNCTION(blsp_i2c2),
713 FUNCTION(blsp_i2c3),
714 FUNCTION(blsp_i2c4),
715 FUNCTION(blsp_i2c5),
716 FUNCTION(blsp_i2c6),
717 FUNCTION(blsp_spi1),
718 FUNCTION(blsp_spi1_cs1),
719 FUNCTION(blsp_spi1_cs2),
720 FUNCTION(blsp_spi1_cs3),
721 FUNCTION(blsp_spi2),
722 FUNCTION(blsp_spi2_cs1),
723 FUNCTION(blsp_spi2_cs2),
724 FUNCTION(blsp_spi2_cs3),
725 FUNCTION(blsp_spi3),
726 FUNCTION(blsp_spi3_cs1),
727 FUNCTION(blsp_spi3_cs2),
728 FUNCTION(blsp_spi3_cs3),
729 FUNCTION(blsp_spi4),
730 FUNCTION(blsp_spi5),
731 FUNCTION(blsp_spi6),
732 FUNCTION(blsp_uart1),
733 FUNCTION(blsp_uart2),
734 FUNCTION(blsp_uim1),
735 FUNCTION(blsp_uim2),
736 FUNCTION(cam1_rst),
737 FUNCTION(cam1_standby),
738 FUNCTION(cam_mclk0),
739 FUNCTION(cam_mclk1),
740 FUNCTION(cci_async),
741 FUNCTION(cci_i2c),
742 FUNCTION(cci_timer0),
743 FUNCTION(cci_timer1),
744 FUNCTION(cci_timer2),
745 FUNCTION(cdc_pdm0),
746 FUNCTION(codec_mad),
747 FUNCTION(dbg_out),
748 FUNCTION(display_5v),
749 FUNCTION(dmic0_clk),
750 FUNCTION(dmic0_data),
751 FUNCTION(dsi_rst),
752 FUNCTION(ebi0_wrcdc),
753 FUNCTION(euro_us),
754 FUNCTION(ext_lpass),
755 FUNCTION(flash_strobe),
756 FUNCTION(gcc_gp1_clk_a),
757 FUNCTION(gcc_gp1_clk_b),
758 FUNCTION(gcc_gp2_clk_a),
759 FUNCTION(gcc_gp2_clk_b),
760 FUNCTION(gcc_gp3_clk_a),
761 FUNCTION(gcc_gp3_clk_b),
762 FUNCTION(gpio),
763 FUNCTION(gsm0_tx0),
764 FUNCTION(gsm0_tx1),
765 FUNCTION(gsm1_tx0),
766 FUNCTION(gsm1_tx1),
767 FUNCTION(gyro_accl),
768 FUNCTION(kpsns0),
769 FUNCTION(kpsns1),
770 FUNCTION(kpsns2),
771 FUNCTION(ldo_en),
772 FUNCTION(ldo_update),
773 FUNCTION(mag_int),
774 FUNCTION(mdp_vsync),
775 FUNCTION(modem_tsync),
776 FUNCTION(m_voc),
777 FUNCTION(nav_pps),
778 FUNCTION(nav_tsync),
779 FUNCTION(pa_indicator),
780 FUNCTION(pbs0),
781 FUNCTION(pbs1),
782 FUNCTION(pbs2),
783 FUNCTION(pri_mi2s),
784 FUNCTION(pri_mi2s_ws),
785 FUNCTION(prng_rosc),
786 FUNCTION(pwr_crypto_enabled_a),
787 FUNCTION(pwr_crypto_enabled_b),
788 FUNCTION(pwr_modem_enabled_a),
789 FUNCTION(pwr_modem_enabled_b),
790 FUNCTION(pwr_nav_enabled_a),
791 FUNCTION(pwr_nav_enabled_b),
792 FUNCTION(qdss_ctitrig_in_a0),
793 FUNCTION(qdss_ctitrig_in_a1),
794 FUNCTION(qdss_ctitrig_in_b0),
795 FUNCTION(qdss_ctitrig_in_b1),
796 FUNCTION(qdss_ctitrig_out_a0),
797 FUNCTION(qdss_ctitrig_out_a1),
798 FUNCTION(qdss_ctitrig_out_b0),
799 FUNCTION(qdss_ctitrig_out_b1),
800 FUNCTION(qdss_traceclk_a),
801 FUNCTION(qdss_traceclk_b),
802 FUNCTION(qdss_tracectl_a),
803 FUNCTION(qdss_tracectl_b),
804 FUNCTION(qdss_tracedata_a),
805 FUNCTION(qdss_tracedata_b),
806 FUNCTION(reset_n),
807 FUNCTION(sd_card),
808 FUNCTION(sd_write),
809 FUNCTION(sec_mi2s),
810 FUNCTION(smb_int),
811 FUNCTION(ssbi_wtr0),
812 FUNCTION(ssbi_wtr1),
813 FUNCTION(uim1),
814 FUNCTION(uim2),
815 FUNCTION(uim3),
816 FUNCTION(uim_batt),
817 FUNCTION(wcss_bt),
818 FUNCTION(wcss_fm),
819 FUNCTION(wcss_wlan),
820 FUNCTION(webcam1_rst)
821};
822
823static const struct msm_pingroup msm8916_groups[] = {
824 PINGROUP(0, blsp_spi1, blsp_uart1, blsp_uim1, dmic0_clk, NA, NA, NA, NA, NA),
825 PINGROUP(1, blsp_spi1, blsp_uart1, blsp_uim1, dmic0_data, NA, NA, NA, NA, NA),
826 PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA, NA, NA),
827 PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA, NA, NA),
828 PINGROUP(4, blsp_spi2, blsp_uart2, blsp_uim2, blsp_spi1_cs3, qdss_tracectl_b, NA, atest_combodac, NA, NA),
829 PINGROUP(5, blsp_spi2, blsp_uart2, blsp_uim2, blsp_spi2_cs3, qdss_traceclk_b, NA, NA, NA, NA),
830 PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA, NA, NA),
831 PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA, NA, NA),
832 PINGROUP(8, blsp_spi3, m_voc, qdss_tracedata_a, NA, NA, NA, NA, NA, NA),
833 PINGROUP(9, blsp_spi3, qdss_tracedata_a, NA, NA, NA, NA, NA, NA, NA),
834 PINGROUP(10, blsp_spi3, blsp_i2c3, qdss_tracedata_a, NA, NA, NA, NA, NA, NA),
835 PINGROUP(11, blsp_spi3, blsp_i2c3, NA, NA, NA, NA, NA, NA, NA),
836 PINGROUP(12, blsp_spi4, gcc_gp2_clk_b, NA, atest_combodac, NA, NA, NA, NA, NA),
837 PINGROUP(13, blsp_spi4, gcc_gp3_clk_b, NA, atest_combodac, NA, NA, NA, NA, NA),
838 PINGROUP(14, blsp_spi4, blsp_i2c4, NA, NA, NA, NA, NA, NA, NA),
839 PINGROUP(15, blsp_spi4, blsp_i2c4, NA, NA, NA, NA, NA, NA, NA),
840 PINGROUP(16, blsp_spi5, blsp_spi1_cs2, NA, atest_bbrx1, NA, NA, NA, NA, NA),
841 PINGROUP(17, blsp_spi5, blsp_spi2_cs2, NA, atest_bbrx0, NA, NA, NA, NA, NA),
842 PINGROUP(18, blsp_spi5, blsp_i2c5, NA, atest_gpsadc1, NA, NA, NA, NA, NA),
843 PINGROUP(19, blsp_spi5, blsp_i2c5, NA, NA, NA, NA, NA, NA, NA),
844 PINGROUP(20, blsp_spi6, NA, NA, NA, NA, NA, NA, qdss_ctitrig_in_a0, NA),
845 PINGROUP(21, blsp_spi6, NA, NA, NA, NA, NA, NA, qdss_ctitrig_in_b0, NA),
846 PINGROUP(22, blsp_spi6, blsp_i2c6, NA, NA, NA, NA, NA, NA, NA),
847 PINGROUP(23, blsp_spi6, blsp_i2c6, NA, NA, NA, NA, NA, NA, NA),
848 PINGROUP(24, mdp_vsync, NA, NA, NA, NA, NA, NA, NA, NA),
849 PINGROUP(25, mdp_vsync, NA, NA, NA, NA, NA, NA, NA, NA),
850 PINGROUP(26, cam_mclk0, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, NA),
851 PINGROUP(27, cam_mclk1, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b),
852 PINGROUP(28, pwr_modem_enabled_a, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, atest_combodac),
853 PINGROUP(29, cci_i2c, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, atest_combodac),
854 PINGROUP(30, cci_i2c, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b),
855 PINGROUP(31, cci_timer0, NA, NA, NA, NA, NA, NA, NA, NA),
856 PINGROUP(32, cci_timer1, NA, NA, NA, NA, NA, NA, NA, NA),
857 PINGROUP(33, cci_async, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b),
858 PINGROUP(34, pwr_nav_enabled_a, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b),
859 PINGROUP(35, pwr_crypto_enabled_a, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b),
860 PINGROUP(36, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b, NA),
861 PINGROUP(37, blsp_spi3_cs2, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, NA),
862 PINGROUP(38, cci_timer2, adsp_ext, NA, NA, NA, NA, NA, NA, NA),
863 PINGROUP(39, wcss_bt, qdss_tracedata_a, NA, atest_combodac, NA, NA, NA, NA, NA),
864 PINGROUP(40, wcss_wlan, qdss_tracedata_a, NA, atest_combodac, NA, NA, NA, NA, NA),
865 PINGROUP(41, wcss_wlan, qdss_tracedata_a, NA, atest_combodac, NA, NA, NA, NA, NA),
866 PINGROUP(42, wcss_wlan, qdss_tracedata_a, NA, atest_combodac, NA, NA, NA, NA, NA),
867 PINGROUP(43, wcss_wlan, prng_rosc, qdss_tracedata_a, NA, atest_combodac, NA, NA, NA, NA),
868 PINGROUP(44, wcss_wlan, NA, atest_combodac, NA, NA, NA, NA, NA, NA),
869 PINGROUP(45, wcss_fm, ext_lpass, qdss_tracectl_a, NA, atest_combodac, NA, NA, NA, NA),
870 PINGROUP(46, wcss_fm, qdss_traceclk_a, NA, atest_combodac, NA, NA, NA, NA, NA),
871 PINGROUP(47, wcss_bt, dbg_out, qdss_tracedata_a, NA, atest_combodac, NA, NA, NA, NA),
872 PINGROUP(48, wcss_bt, qdss_tracedata_a, NA, atest_combodac, NA, NA, NA, NA, NA),
873 PINGROUP(49, uim3, gcc_gp1_clk_a, qdss_ctitrig_in_a1, NA, NA, NA, NA, NA, NA),
874 PINGROUP(50, uim3, gcc_gp2_clk_a, qdss_ctitrig_in_b1, NA, NA, NA, NA, NA, NA),
875 PINGROUP(51, uim3, gcc_gp3_clk_a, qdss_ctitrig_out_b1, NA, NA, NA, NA, NA, NA),
876 PINGROUP(52, uim3, NA, qdss_ctitrig_out_a1, NA, NA, NA, NA, NA, NA),
877 PINGROUP(53, uim2, NA, NA, NA, NA, NA, NA, NA, NA),
878 PINGROUP(54, uim2, NA, NA, NA, NA, NA, NA, NA, NA),
879 PINGROUP(55, uim2, NA, NA, NA, NA, NA, NA, NA, NA),
880 PINGROUP(56, uim2, NA, NA, NA, NA, NA, NA, NA, NA),
881 PINGROUP(57, uim1, atest_char3, NA, NA, NA, NA, NA, NA, NA),
882 PINGROUP(58, uim1, atest_char2, NA, NA, NA, NA, NA, NA, NA),
883 PINGROUP(59, uim1, atest_char1, NA, NA, NA, NA, NA, NA, NA),
884 PINGROUP(60, uim1, atest_char0, NA, NA, NA, NA, NA, NA, NA),
885 PINGROUP(61, uim_batt, NA, NA, NA, NA, NA, NA, NA, NA),
886 PINGROUP(62, atest_char, qdss_tracedata_a, NA, NA, NA, NA, NA, NA, NA),
887 PINGROUP(63, cdc_pdm0, bimc_dte0, NA, NA, NA, NA, NA, NA, NA),
888 PINGROUP(64, cdc_pdm0, bimc_dte1, NA, NA, NA, NA, NA, NA, NA),
889 PINGROUP(65, cdc_pdm0, bimc_dte0, NA, NA, NA, NA, NA, NA, NA),
890 PINGROUP(66, cdc_pdm0, bimc_dte1, NA, NA, NA, NA, NA, NA, NA),
891 PINGROUP(67, cdc_pdm0, ebi0_wrcdc, NA, NA, NA, NA, NA, NA, NA),
892 PINGROUP(68, cdc_pdm0, NA, NA, NA, NA, NA, NA, NA, NA),
893 PINGROUP(69, blsp_spi3_cs3, qdss_tracedata_a, NA, atest_combodac, NA, NA, NA, NA, NA),
894 PINGROUP(70, NA, NA, NA, NA, NA, NA, NA, NA, NA),
895 PINGROUP(71, NA, NA, NA, NA, NA, NA, NA, NA, NA),
896 PINGROUP(72, NA, NA, NA, NA, NA, NA, NA, NA, NA),
897 PINGROUP(73, NA, NA, NA, NA, NA, NA, NA, NA, NA),
898 PINGROUP(74, NA, NA, NA, NA, NA, NA, NA, NA, NA),
899 PINGROUP(75, NA, NA, NA, NA, NA, NA, NA, NA, NA),
900 PINGROUP(76, NA, NA, NA, NA, NA, NA, NA, NA, NA),
901 PINGROUP(77, NA, NA, NA, NA, NA, NA, NA, NA, NA),
902 PINGROUP(78, NA, NA, NA, NA, NA, NA, NA, NA, NA),
903 PINGROUP(79, NA, NA, NA, NA, NA, NA, NA, NA, NA),
904 PINGROUP(80, NA, NA, NA, NA, NA, NA, NA, NA, NA),
905 PINGROUP(81, NA, NA, NA, NA, NA, NA, NA, NA, NA),
906 PINGROUP(82, NA, NA, NA, NA, NA, NA, NA, NA, NA),
907 PINGROUP(83, NA, NA, NA, NA, NA, NA, NA, NA, NA),
908 PINGROUP(84, NA, NA, NA, NA, NA, NA, NA, NA, NA),
909 PINGROUP(85, NA, NA, NA, NA, NA, NA, NA, NA, NA),
910 PINGROUP(86, NA, pa_indicator, NA, NA, NA, NA, NA, NA, NA),
911 PINGROUP(87, NA, NA, NA, NA, NA, NA, NA, NA, NA),
912 PINGROUP(88, NA, NA, NA, NA, NA, NA, NA, NA, NA),
913 PINGROUP(89, NA, NA, NA, NA, NA, NA, NA, NA, NA),
914 PINGROUP(90, NA, NA, NA, NA, NA, NA, NA, NA, NA),
915 PINGROUP(91, NA, NA, NA, NA, NA, NA, NA, NA, NA),
916 PINGROUP(92, NA, NA, NA, NA, NA, NA, NA, NA, NA),
917 PINGROUP(93, NA, NA, NA, NA, NA, NA, NA, NA, NA),
918 PINGROUP(94, NA, NA, NA, NA, NA, NA, NA, NA, NA),
919 PINGROUP(95, NA, modem_tsync, nav_tsync, nav_pps, NA, NA, NA, NA, NA),
920 PINGROUP(96, NA, NA, NA, NA, NA, NA, NA, NA, NA),
921 PINGROUP(97, gcc_gp1_clk_b, NA, NA, NA, NA, NA, NA, NA, NA),
922 PINGROUP(98, NA, NA, NA, NA, NA, NA, NA, NA, NA),
923 PINGROUP(99, gsm0_tx0, NA, NA, NA, NA, NA, NA, NA, NA),
924 PINGROUP(100, gsm0_tx1, NA, NA, NA, NA, NA, NA, NA, NA),
925 PINGROUP(101, gsm1_tx0, NA, NA, NA, NA, NA, NA, NA, NA),
926 PINGROUP(102, gsm1_tx1, NA, NA, NA, NA, NA, NA, NA, NA),
927 PINGROUP(103, ssbi_wtr0, NA, NA, NA, NA, NA, NA, NA, NA),
928 PINGROUP(104, ssbi_wtr0, NA, NA, NA, NA, NA, NA, NA, NA),
929 PINGROUP(105, ssbi_wtr1, NA, NA, NA, NA, NA, NA, NA, NA),
930 PINGROUP(106, ssbi_wtr1, NA, NA, NA, NA, NA, NA, NA, NA),
931 PINGROUP(107, pbs0, NA, atest_combodac, NA, NA, NA, NA, NA, NA),
932 PINGROUP(108, pbs1, NA, NA, NA, NA, NA, NA, NA, NA),
933 PINGROUP(109, pbs2, NA, NA, NA, NA, NA, NA, NA, NA),
934 PINGROUP(110, blsp_spi1_cs1, pri_mi2s_ws, NA, qdss_tracedata_b, NA, NA, NA, NA, NA),
935 PINGROUP(111, qdss_tracedata_b, NA, NA, NA, NA, NA, NA, NA, NA),
936 PINGROUP(112, sec_mi2s, NA, NA, NA, qdss_tracedata_a, NA, atest_tsens, NA, NA),
937 PINGROUP(113, pri_mi2s, NA, pwr_modem_enabled_b, NA, NA, NA, NA, NA, qdss_tracedata_a),
938 PINGROUP(114, pri_mi2s, pwr_nav_enabled_b, NA, NA, NA, NA, NA, qdss_tracedata_a, NA),
939 PINGROUP(115, pri_mi2s, pwr_crypto_enabled_b, NA, NA, NA, NA, NA, qdss_tracedata_a, NA),
940 PINGROUP(116, pri_mi2s, NA, NA, NA, NA, NA, NA, NA, NA),
941 PINGROUP(117, sec_mi2s, NA, NA, NA, NA, NA, NA, NA, NA),
942 PINGROUP(118, sec_mi2s, NA, NA, NA, NA, NA, NA, NA, NA),
943 PINGROUP(119, sec_mi2s, m_voc, NA, NA, NA, NA, NA, NA, NA),
944 PINGROUP(120, blsp_spi3_cs1, ldo_update, NA, NA, NA, NA, NA, NA, NA),
945 PINGROUP(121, sd_write, blsp_spi2_cs1, ldo_en, NA, NA, NA, NA, NA, NA),
946 SDC_PINGROUP(sdc1_clk, 0x10a000, 13, 6),
947 SDC_PINGROUP(sdc1_cmd, 0x10a000, 11, 3),
948 SDC_PINGROUP(sdc1_data, 0x10a000, 9, 0),
949 SDC_PINGROUP(sdc2_clk, 0x109000, 14, 6),
950 SDC_PINGROUP(sdc2_cmd, 0x109000, 11, 3),
951 SDC_PINGROUP(sdc2_data, 0x109000, 9, 0),
952 SDC_PINGROUP(qdsd_clk, 0x19c000, 3, 0),
953 SDC_PINGROUP(qdsd_cmd, 0x19c000, 8, 5),
954 SDC_PINGROUP(qdsd_data0, 0x19c000, 13, 10),
955 SDC_PINGROUP(qdsd_data1, 0x19c000, 18, 15),
956 SDC_PINGROUP(qdsd_data2, 0x19c000, 23, 20),
957 SDC_PINGROUP(qdsd_data3, 0x19c000, 28, 25),
958};
959
960#define NUM_GPIO_PINGROUPS 122
961
962static const struct msm_pinctrl_soc_data msm8916_pinctrl = {
963 .pins = msm8916_pins,
964 .npins = ARRAY_SIZE(msm8916_pins),
965 .functions = msm8916_functions,
966 .nfunctions = ARRAY_SIZE(msm8916_functions),
967 .groups = msm8916_groups,
968 .ngroups = ARRAY_SIZE(msm8916_groups),
969 .ngpios = NUM_GPIO_PINGROUPS,
970};
971
972static int msm8916_pinctrl_probe(struct platform_device *pdev)
973{
974 return msm_pinctrl_probe(pdev, &msm8916_pinctrl);
975}
976
977static const struct of_device_id msm8916_pinctrl_of_match[] = {
978 { .compatible = "qcom,msm8916-pinctrl", },
979 { },
980};
981
982static struct platform_driver msm8916_pinctrl_driver = {
983 .driver = {
984 .name = "msm8916-pinctrl",
985 .of_match_table = msm8916_pinctrl_of_match,
986 },
987 .probe = msm8916_pinctrl_probe,
988 .remove = msm_pinctrl_remove,
989};
990
991static int __init msm8916_pinctrl_init(void)
992{
993 return platform_driver_register(&msm8916_pinctrl_driver);
994}
995arch_initcall(msm8916_pinctrl_init);
996
997static void __exit msm8916_pinctrl_exit(void)
998{
999 platform_driver_unregister(&msm8916_pinctrl_driver);
1000}
1001module_exit(msm8916_pinctrl_exit);
1002
1003MODULE_DESCRIPTION("Qualcomm msm8916 pinctrl driver");
1004MODULE_LICENSE("GPL v2");
1005MODULE_DEVICE_TABLE(of, msm8916_pinctrl_of_match);
diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
index b863b5080890..0f11a26d932b 100644
--- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
+++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
@@ -131,15 +131,17 @@ struct pmic_gpio_state {
131 struct gpio_chip chip; 131 struct gpio_chip chip;
132}; 132};
133 133
134struct pmic_gpio_bindings { 134static const struct pinconf_generic_params pmic_gpio_bindings[] = {
135 const char *property; 135 {"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0},
136 unsigned param; 136 {"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0},
137}; 137};
138 138
139static struct pmic_gpio_bindings pmic_gpio_bindings[] = { 139#ifdef CONFIG_DEBUG_FS
140 {"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP}, 140static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {
141 {"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH}, 141 PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true),
142 PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true),
142}; 143};
144#endif
143 145
144static const char *const pmic_gpio_groups[] = { 146static const char *const pmic_gpio_groups[] = {
145 "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", 147 "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
@@ -209,118 +211,11 @@ static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin,
209 return 0; 211 return 0;
210} 212}
211 213
212static int pmic_gpio_parse_dt_config(struct device_node *np,
213 struct pinctrl_dev *pctldev,
214 unsigned long **configs,
215 unsigned int *nconfs)
216{
217 struct pmic_gpio_bindings *par;
218 unsigned long cfg;
219 int ret, i;
220 u32 val;
221
222 for (i = 0; i < ARRAY_SIZE(pmic_gpio_bindings); i++) {
223 par = &pmic_gpio_bindings[i];
224 ret = of_property_read_u32(np, par->property, &val);
225
226 /* property not found */
227 if (ret == -EINVAL)
228 continue;
229
230 /* use zero as default value */
231 if (ret)
232 val = 0;
233
234 dev_dbg(pctldev->dev, "found %s with value %u\n",
235 par->property, val);
236
237 cfg = pinconf_to_config_packed(par->param, val);
238
239 ret = pinctrl_utils_add_config(pctldev, configs, nconfs, cfg);
240 if (ret)
241 return ret;
242 }
243
244 return 0;
245}
246
247static int pmic_gpio_dt_subnode_to_map(struct pinctrl_dev *pctldev,
248 struct device_node *np,
249 struct pinctrl_map **map,
250 unsigned *reserv, unsigned *nmaps,
251 enum pinctrl_map_type type)
252{
253 unsigned long *configs = NULL;
254 unsigned nconfs = 0;
255 struct property *prop;
256 const char *group;
257 int ret;
258
259 ret = pmic_gpio_parse_dt_config(np, pctldev, &configs, &nconfs);
260 if (ret < 0)
261 return ret;
262
263 if (!nconfs)
264 return 0;
265
266 ret = of_property_count_strings(np, "pins");
267 if (ret < 0)
268 goto exit;
269
270 ret = pinctrl_utils_reserve_map(pctldev, map, reserv, nmaps, ret);
271 if (ret < 0)
272 goto exit;
273
274 of_property_for_each_string(np, "pins", prop, group) {
275 ret = pinctrl_utils_add_map_configs(pctldev, map,
276 reserv, nmaps, group,
277 configs, nconfs, type);
278 if (ret < 0)
279 break;
280 }
281exit:
282 kfree(configs);
283 return ret;
284}
285
286static int pmic_gpio_dt_node_to_map(struct pinctrl_dev *pctldev,
287 struct device_node *np_config,
288 struct pinctrl_map **map, unsigned *nmaps)
289{
290 enum pinctrl_map_type type;
291 struct device_node *np;
292 unsigned reserv;
293 int ret;
294
295 ret = 0;
296 *map = NULL;
297 *nmaps = 0;
298 reserv = 0;
299 type = PIN_MAP_TYPE_CONFIGS_GROUP;
300
301 for_each_child_of_node(np_config, np) {
302 ret = pinconf_generic_dt_subnode_to_map(pctldev, np, map,
303 &reserv, nmaps, type);
304 if (ret)
305 break;
306
307 ret = pmic_gpio_dt_subnode_to_map(pctldev, np, map, &reserv,
308 nmaps, type);
309 if (ret)
310 break;
311 }
312
313 if (ret < 0)
314 pinctrl_utils_dt_free_map(pctldev, *map, *nmaps);
315
316 return ret;
317}
318
319static const struct pinctrl_ops pmic_gpio_pinctrl_ops = { 214static const struct pinctrl_ops pmic_gpio_pinctrl_ops = {
320 .get_groups_count = pmic_gpio_get_groups_count, 215 .get_groups_count = pmic_gpio_get_groups_count,
321 .get_group_name = pmic_gpio_get_group_name, 216 .get_group_name = pmic_gpio_get_group_name,
322 .get_group_pins = pmic_gpio_get_group_pins, 217 .get_group_pins = pmic_gpio_get_group_pins,
323 .dt_node_to_map = pmic_gpio_dt_node_to_map, 218 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
324 .dt_free_map = pinctrl_utils_dt_free_map, 219 .dt_free_map = pinctrl_utils_dt_free_map,
325}; 220};
326 221
@@ -590,6 +485,7 @@ static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
590} 485}
591 486
592static const struct pinconf_ops pmic_gpio_pinconf_ops = { 487static const struct pinconf_ops pmic_gpio_pinconf_ops = {
488 .is_generic = true,
593 .pin_config_group_get = pmic_gpio_config_get, 489 .pin_config_group_get = pmic_gpio_config_get,
594 .pin_config_group_set = pmic_gpio_config_set, 490 .pin_config_group_set = pmic_gpio_config_set,
595 .pin_config_group_dbg_show = pmic_gpio_config_dbg_show, 491 .pin_config_group_dbg_show = pmic_gpio_config_dbg_show,
@@ -848,6 +744,11 @@ static int pmic_gpio_probe(struct platform_device *pdev)
848 pctrldesc->name = dev_name(dev); 744 pctrldesc->name = dev_name(dev);
849 pctrldesc->pins = pindesc; 745 pctrldesc->pins = pindesc;
850 pctrldesc->npins = npins; 746 pctrldesc->npins = npins;
747 pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings);
748 pctrldesc->custom_params = pmic_gpio_bindings;
749#ifdef CONFIG_DEBUG_FS
750 pctrldesc->custom_conf_items = pmic_conf_items;
751#endif
851 752
852 for (i = 0; i < npins; i++, pindesc++) { 753 for (i = 0; i < npins; i++, pindesc++) {
853 pad = &pads[i]; 754 pad = &pads[i];
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index becb3792977b..c8f83f96546c 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -1300,6 +1300,25 @@ static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {
1300 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c), 1300 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
1301}; 1301};
1302 1302
1303/* pin banks of exynos7 pin-controller - BUS1 */
1304static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = {
1305 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00),
1306 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04),
1307 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08),
1308 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c),
1309 EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10),
1310 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14),
1311 EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18),
1312 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c),
1313 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20),
1314 EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24),
1315};
1316
1317static const struct samsung_pin_bank_data exynos7_pin_banks9[] __initconst = {
1318 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
1319 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
1320};
1321
1303const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = { 1322const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
1304 { 1323 {
1305 /* pin-controller instance 0 Alive data */ 1324 /* pin-controller instance 0 Alive data */
@@ -1342,5 +1361,15 @@ const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
1342 .pin_banks = exynos7_pin_banks7, 1361 .pin_banks = exynos7_pin_banks7,
1343 .nr_banks = ARRAY_SIZE(exynos7_pin_banks7), 1362 .nr_banks = ARRAY_SIZE(exynos7_pin_banks7),
1344 .eint_gpio_init = exynos_eint_gpio_init, 1363 .eint_gpio_init = exynos_eint_gpio_init,
1364 }, {
1365 /* pin-controller instance 8 BUS1 data */
1366 .pin_banks = exynos7_pin_banks8,
1367 .nr_banks = ARRAY_SIZE(exynos7_pin_banks8),
1368 .eint_gpio_init = exynos_eint_gpio_init,
1369 }, {
1370 /* pin-controller instance 9 AUD data */
1371 .pin_banks = exynos7_pin_banks9,
1372 .nr_banks = ARRAY_SIZE(exynos7_pin_banks9),
1373 .eint_gpio_init = exynos_eint_gpio_init,
1345 }, 1374 },
1346}; 1375};
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index 26187aa5cf5b..8c4b3d391823 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -20,6 +20,11 @@ config GPIO_SH_PFC
20 This enables support for GPIOs within the SoC's pin function 20 This enables support for GPIOs within the SoC's pin function
21 controller. 21 controller.
22 22
23config PINCTRL_PFC_EMEV2
24 def_bool y
25 depends on ARCH_EMEV2
26 select PINCTRL_SH_PFC
27
23config PINCTRL_PFC_R8A73A4 28config PINCTRL_PFC_R8A73A4
24 def_bool y 29 def_bool y
25 depends on ARCH_R8A73A4 30 depends on ARCH_R8A73A4
@@ -68,11 +73,6 @@ config PINCTRL_PFC_SH7269
68 depends on GPIOLIB 73 depends on GPIOLIB
69 select PINCTRL_SH_PFC 74 select PINCTRL_SH_PFC
70 75
71config PINCTRL_PFC_SH7372
72 def_bool y
73 depends on ARCH_SH7372
74 select PINCTRL_SH_PFC
75
76config PINCTRL_PFC_SH73A0 76config PINCTRL_PFC_SH73A0
77 def_bool y 77 def_bool y
78 depends on ARCH_SH73A0 78 depends on ARCH_SH73A0
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index ad8f4cf9faaa..f4074e166bcf 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -3,6 +3,7 @@ ifeq ($(CONFIG_GPIO_SH_PFC),y)
3sh-pfc-objs += gpio.o 3sh-pfc-objs += gpio.o
4endif 4endif
5obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc.o 5obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc.o
6obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-emev2.o
6obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o 7obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o
7obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o 8obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o
8obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o 9obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o
@@ -12,7 +13,6 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o
12obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o 13obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
13obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o 14obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o
14obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o 15obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o
15obj-$(CONFIG_PINCTRL_PFC_SH7372) += pfc-sh7372.o
16obj-$(CONFIG_PINCTRL_PFC_SH73A0) += pfc-sh73a0.o 16obj-$(CONFIG_PINCTRL_PFC_SH73A0) += pfc-sh73a0.o
17obj-$(CONFIG_PINCTRL_PFC_SH7720) += pfc-sh7720.o 17obj-$(CONFIG_PINCTRL_PFC_SH7720) += pfc-sh7720.o
18obj-$(CONFIG_PINCTRL_PFC_SH7722) += pfc-sh7722.o 18obj-$(CONFIG_PINCTRL_PFC_SH7722) += pfc-sh7722.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 66dc62d2156c..a56280814a3f 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -439,6 +439,12 @@ static int sh_pfc_init_ranges(struct sh_pfc *pfc)
439 439
440#ifdef CONFIG_OF 440#ifdef CONFIG_OF
441static const struct of_device_id sh_pfc_of_table[] = { 441static const struct of_device_id sh_pfc_of_table[] = {
442#ifdef CONFIG_PINCTRL_PFC_EMEV2
443 {
444 .compatible = "renesas,pfc-emev2",
445 .data = &emev2_pinmux_info,
446 },
447#endif
442#ifdef CONFIG_PINCTRL_PFC_R8A73A4 448#ifdef CONFIG_PINCTRL_PFC_R8A73A4
443 { 449 {
444 .compatible = "renesas,pfc-r8a73a4", 450 .compatible = "renesas,pfc-r8a73a4",
@@ -475,12 +481,6 @@ static const struct of_device_id sh_pfc_of_table[] = {
475 .data = &r8a7791_pinmux_info, 481 .data = &r8a7791_pinmux_info,
476 }, 482 },
477#endif 483#endif
478#ifdef CONFIG_PINCTRL_PFC_SH7372
479 {
480 .compatible = "renesas,pfc-sh7372",
481 .data = &sh7372_pinmux_info,
482 },
483#endif
484#ifdef CONFIG_PINCTRL_PFC_SH73A0 484#ifdef CONFIG_PINCTRL_PFC_SH73A0
485 { 485 {
486 .compatible = "renesas,pfc-sh73a0", 486 .compatible = "renesas,pfc-sh73a0",
@@ -579,6 +579,9 @@ static int sh_pfc_remove(struct platform_device *pdev)
579} 579}
580 580
581static const struct platform_device_id sh_pfc_id_table[] = { 581static const struct platform_device_id sh_pfc_id_table[] = {
582#ifdef CONFIG_PINCTRL_PFC_EMEV2
583 { "pfc-emev2", (kernel_ulong_t)&emev2_pinmux_info },
584#endif
582#ifdef CONFIG_PINCTRL_PFC_R8A73A4 585#ifdef CONFIG_PINCTRL_PFC_R8A73A4
583 { "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info }, 586 { "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info },
584#endif 587#endif
@@ -606,9 +609,6 @@ static const struct platform_device_id sh_pfc_id_table[] = {
606#ifdef CONFIG_PINCTRL_PFC_SH7269 609#ifdef CONFIG_PINCTRL_PFC_SH7269
607 { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info }, 610 { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
608#endif 611#endif
609#ifdef CONFIG_PINCTRL_PFC_SH7372
610 { "pfc-sh7372", (kernel_ulong_t)&sh7372_pinmux_info },
611#endif
612#ifdef CONFIG_PINCTRL_PFC_SH73A0 612#ifdef CONFIG_PINCTRL_PFC_SH73A0
613 { "pfc-sh73a0", (kernel_ulong_t)&sh73a0_pinmux_info }, 613 { "pfc-sh73a0", (kernel_ulong_t)&sh73a0_pinmux_info },
614#endif 614#endif
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index 3daaa5241c47..6b59d63b9c01 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -65,6 +65,7 @@ void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
65int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin); 65int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin);
66int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type); 66int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
67 67
68extern const struct sh_pfc_soc_info emev2_pinmux_info;
68extern const struct sh_pfc_soc_info r8a73a4_pinmux_info; 69extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
69extern const struct sh_pfc_soc_info r8a7740_pinmux_info; 70extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
70extern const struct sh_pfc_soc_info r8a7778_pinmux_info; 71extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
@@ -74,7 +75,6 @@ extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
74extern const struct sh_pfc_soc_info sh7203_pinmux_info; 75extern const struct sh_pfc_soc_info sh7203_pinmux_info;
75extern const struct sh_pfc_soc_info sh7264_pinmux_info; 76extern const struct sh_pfc_soc_info sh7264_pinmux_info;
76extern const struct sh_pfc_soc_info sh7269_pinmux_info; 77extern const struct sh_pfc_soc_info sh7269_pinmux_info;
77extern const struct sh_pfc_soc_info sh7372_pinmux_info;
78extern const struct sh_pfc_soc_info sh73a0_pinmux_info; 78extern const struct sh_pfc_soc_info sh73a0_pinmux_info;
79extern const struct sh_pfc_soc_info sh7720_pinmux_info; 79extern const struct sh_pfc_soc_info sh7720_pinmux_info;
80extern const struct sh_pfc_soc_info sh7722_pinmux_info; 80extern const struct sh_pfc_soc_info sh7722_pinmux_info;
diff --git a/drivers/pinctrl/sh-pfc/pfc-emev2.c b/drivers/pinctrl/sh-pfc/pfc-emev2.c
new file mode 100644
index 000000000000..849c6943ed30
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-emev2.c
@@ -0,0 +1,1711 @@
1/*
2 * Pin Function Controller Support
3 *
4 * Copyright (C) 2015 Niklas Söderlund
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/init.h>
11#include <linux/kernel.h>
12
13#include "sh_pfc.h"
14
15#define CPU_ALL_PORT(fn, pfx, sfx) \
16 PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \
17 PORT_10(100, fn, pfx##10, sfx), PORT_10(110, fn, pfx##11, sfx), \
18 PORT_10(120, fn, pfx##12, sfx), PORT_10(130, fn, pfx##13, sfx), \
19 PORT_10(140, fn, pfx##14, sfx), PORT_1(150, fn, pfx##150, sfx), \
20 PORT_1(151, fn, pfx##151, sfx), PORT_1(152, fn, pfx##152, sfx), \
21 PORT_1(153, fn, pfx##153, sfx), PORT_1(154, fn, pfx##154, sfx), \
22 PORT_1(155, fn, pfx##155, sfx), PORT_1(156, fn, pfx##156, sfx), \
23 PORT_1(157, fn, pfx##157, sfx), PORT_1(158, fn, pfx##158, sfx)
24
25enum {
26 PINMUX_RESERVED = 0,
27
28 PINMUX_DATA_BEGIN,
29 PORT_ALL(DATA),
30 PINMUX_DATA_END,
31
32 PINMUX_FUNCTION_BEGIN,
33 PORT_ALL(FN),
34
35 /* GPSR0 */
36 FN_LCD3_1_0_PORT18, FN_LCD3_1_0_PORT20, FN_LCD3_1_0_PORT21,
37 FN_LCD3_1_0_PORT22, FN_LCD3_1_0_PORT23,
38 FN_JT_SEL, FN_ERR_RST_REQB, FN_REF_CLKO, FN_EXT_CLKI, FN_LCD3_PXCLKB,
39
40 /* GPSR1 */
41 FN_LCD3_9_8_PORT38, FN_LCD3_9_8_PORT39, FN_LCD3_11_10_PORT40,
42 FN_LCD3_11_10_PORT41, FN_LCD3_11_10_PORT42, FN_LCD3_11_10_PORT43,
43 FN_IIC_1_0_PORT46, FN_IIC_1_0_PORT47,
44 FN_LCD3_R0, FN_LCD3_R1, FN_LCD3_R2, FN_LCD3_R3, FN_LCD3_R4, FN_LCD3_R5,
45 FN_IIC0_SCL, FN_IIC0_SDA, FN_SD_CKI, FN_SDI0_CKO, FN_SDI0_CKI,
46 FN_SDI0_CMD, FN_SDI0_DATA0, FN_SDI0_DATA1, FN_SDI0_DATA2,
47 FN_SDI0_DATA3, FN_SDI0_DATA4, FN_SDI0_DATA5, FN_SDI0_DATA6,
48 FN_SDI0_DATA7, FN_SDI1_CKO, FN_SDI1_CKI, FN_SDI1_CMD,
49
50 /* GPSR2 */
51 FN_AB_1_0_PORT71, FN_AB_1_0_PORT72, FN_AB_1_0_PORT73,
52 FN_AB_1_0_PORT74, FN_AB_1_0_PORT75, FN_AB_1_0_PORT76,
53 FN_AB_1_0_PORT77, FN_AB_1_0_PORT78, FN_AB_1_0_PORT79,
54 FN_AB_1_0_PORT80, FN_AB_1_0_PORT81, FN_AB_1_0_PORT82,
55 FN_AB_1_0_PORT83, FN_AB_1_0_PORT84, FN_AB_3_2_PORT85,
56 FN_AB_3_2_PORT86, FN_AB_3_2_PORT87, FN_AB_3_2_PORT88,
57 FN_AB_5_4_PORT89, FN_AB_5_4_PORT90, FN_AB_7_6_PORT91,
58 FN_AB_7_6_PORT92, FN_AB_1_0_PORT93, FN_AB_1_0_PORT94,
59 FN_AB_1_0_PORT95,
60 FN_SDI1_DATA0, FN_SDI1_DATA1, FN_SDI1_DATA2, FN_SDI1_DATA3,
61 FN_AB_CLK, FN_AB_CSB0, FN_AB_CSB1,
62
63 /* GPSR3 */
64 FN_AB_13_12_PORT104, FN_AB_13_12_PORT103, FN_AB_11_10_PORT102,
65 FN_AB_11_10_PORT101, FN_AB_11_10_PORT100, FN_AB_9_8_PORT99,
66 FN_AB_9_8_PORT98, FN_AB_9_8_PORT97,
67 FN_USI_1_0_PORT109, FN_USI_1_0_PORT110, FN_USI_1_0_PORT111,
68 FN_USI_1_0_PORT112, FN_USI_3_2_PORT113, FN_USI_3_2_PORT114,
69 FN_USI_5_4_PORT115, FN_USI_5_4_PORT116, FN_USI_5_4_PORT117,
70 FN_USI_5_4_PORT118, FN_USI_7_6_PORT119, FN_USI_9_8_PORT120,
71 FN_USI_9_8_PORT121,
72 FN_AB_A20, FN_USI0_CS1, FN_USI0_CS2, FN_USI1_DI,
73 FN_USI1_DO,
74 FN_NTSC_CLK, FN_NTSC_DATA0, FN_NTSC_DATA1, FN_NTSC_DATA2,
75 FN_NTSC_DATA3, FN_NTSC_DATA4,
76
77 /* GPRS4 */
78 FN_HSI_1_0_PORT143, FN_HSI_1_0_PORT144, FN_HSI_1_0_PORT145,
79 FN_HSI_1_0_PORT146, FN_HSI_1_0_PORT147, FN_HSI_1_0_PORT148,
80 FN_HSI_1_0_PORT149, FN_HSI_1_0_PORT150,
81 FN_UART_1_0_PORT157, FN_UART_1_0_PORT158,
82 FN_NTSC_DATA5, FN_NTSC_DATA6, FN_NTSC_DATA7, FN_CAM_CLKO,
83 FN_CAM_CLKI, FN_CAM_VS, FN_CAM_HS, FN_CAM_YUV0,
84 FN_CAM_YUV1, FN_CAM_YUV2, FN_CAM_YUV3, FN_CAM_YUV4,
85 FN_CAM_YUV5, FN_CAM_YUV6, FN_CAM_YUV7,
86 FN_JT_TDO, FN_JT_TDOEN, FN_LOWPWR, FN_USB_VBUS, FN_UART1_RX,
87 FN_UART1_TX,
88
89 /* CHG_PINSEL_LCD3 */
90 FN_SEL_LCD3_1_0_00, FN_SEL_LCD3_1_0_01,
91 FN_SEL_LCD3_9_8_00, FN_SEL_LCD3_9_8_10,
92 FN_SEL_LCD3_11_10_00, FN_SEL_LCD3_11_10_01, FN_SEL_LCD3_11_10_10,
93
94 /* CHG_PINSEL_IIC */
95 FN_SEL_IIC_1_0_00, FN_SEL_IIC_1_0_01,
96
97 /* CHG_PINSEL_AB */
98 FN_SEL_AB_1_0_00, FN_SEL_AB_1_0_10, FN_SEL_AB_3_2_00,
99 FN_SEL_AB_3_2_01, FN_SEL_AB_3_2_10, FN_SEL_AB_3_2_11,
100 FN_SEL_AB_5_4_00, FN_SEL_AB_5_4_01, FN_SEL_AB_5_4_10,
101 FN_SEL_AB_5_4_11, FN_SEL_AB_7_6_00, FN_SEL_AB_7_6_01,
102 FN_SEL_AB_7_6_10,
103 FN_SEL_AB_9_8_00, FN_SEL_AB_9_8_01, FN_SEL_AB_9_8_10,
104 FN_SEL_AB_11_10_00, FN_SEL_AB_11_10_10,
105 FN_SEL_AB_13_12_00, FN_SEL_AB_13_12_10,
106
107 /* CHG_PINSEL_USI */
108 FN_SEL_USI_1_0_00, FN_SEL_USI_1_0_01,
109 FN_SEL_USI_3_2_00, FN_SEL_USI_3_2_01,
110 FN_SEL_USI_5_4_00, FN_SEL_USI_5_4_01,
111 FN_SEL_USI_7_6_00, FN_SEL_USI_7_6_01,
112 FN_SEL_USI_9_8_00, FN_SEL_USI_9_8_01,
113
114 /* CHG_PINSEL_HSI */
115 FN_SEL_HSI_1_0_00, FN_SEL_HSI_1_0_01,
116
117 /* CHG_PINSEL_UART */
118 FN_SEL_UART_1_0_00, FN_SEL_UART_1_0_01,
119
120 PINMUX_FUNCTION_END,
121
122 PINMUX_MARK_BEGIN,
123
124 /* GPSR0 */
125 JT_SEL_MARK, ERR_RST_REQB_MARK, REF_CLKO_MARK, EXT_CLKI_MARK,
126 LCD3_PXCLKB_MARK, SD_CKI_MARK,
127
128 /* GPSR1 */
129 LCD3_R0_MARK, LCD3_R1_MARK, LCD3_R2_MARK, LCD3_R3_MARK, LCD3_R4_MARK,
130 LCD3_R5_MARK, IIC0_SCL_MARK, IIC0_SDA_MARK, SDI0_CKO_MARK,
131 SDI0_CKI_MARK, SDI0_CMD_MARK, SDI0_DATA0_MARK, SDI0_DATA1_MARK,
132 SDI0_DATA2_MARK, SDI0_DATA3_MARK, SDI0_DATA4_MARK, SDI0_DATA5_MARK,
133 SDI0_DATA6_MARK, SDI0_DATA7_MARK, SDI1_CKO_MARK, SDI1_CKI_MARK,
134 SDI1_CMD_MARK,
135
136 /* GPSR2 */
137 SDI1_DATA0_MARK, SDI1_DATA1_MARK, SDI1_DATA2_MARK, SDI1_DATA3_MARK,
138 AB_CLK_MARK, AB_CSB0_MARK, AB_CSB1_MARK,
139
140 /* GPSR3 */
141 AB_A20_MARK, USI0_CS1_MARK, USI0_CS2_MARK, USI1_DI_MARK,
142 USI1_DO_MARK,
143 NTSC_CLK_MARK, NTSC_DATA0_MARK, NTSC_DATA1_MARK, NTSC_DATA2_MARK,
144 NTSC_DATA3_MARK, NTSC_DATA4_MARK,
145
146 /* GPSR3 */
147 NTSC_DATA5_MARK, NTSC_DATA6_MARK, NTSC_DATA7_MARK, CAM_CLKO_MARK,
148 CAM_CLKI_MARK, CAM_VS_MARK, CAM_HS_MARK, CAM_YUV0_MARK,
149 CAM_YUV1_MARK, CAM_YUV2_MARK, CAM_YUV3_MARK, CAM_YUV4_MARK,
150 CAM_YUV5_MARK, CAM_YUV6_MARK, CAM_YUV7_MARK,
151 JT_TDO_MARK, JT_TDOEN_MARK, USB_VBUS_MARK, LOWPWR_MARK,
152 UART1_RX_MARK, UART1_TX_MARK,
153
154 /* CHG_PINSEL_LCD3 */
155 LCD3_PXCLK_MARK, LCD3_CLK_I_MARK, LCD3_HS_MARK, LCD3_VS_MARK,
156 LCD3_DE_MARK, LCD3_R6_MARK, LCD3_R7_MARK, LCD3_G0_MARK, LCD3_G1_MARK,
157 LCD3_G2_MARK, LCD3_G3_MARK, LCD3_G4_MARK, LCD3_G5_MARK, LCD3_G6_MARK,
158 LCD3_G7_MARK, LCD3_B0_MARK, LCD3_B1_MARK, LCD3_B2_MARK, LCD3_B3_MARK,
159 LCD3_B4_MARK, LCD3_B5_MARK, LCD3_B6_MARK, LCD3_B7_MARK,
160 YUV3_CLK_O_MARK, YUV3_CLK_I_MARK, YUV3_HS_MARK, YUV3_VS_MARK,
161 YUV3_DE_MARK, YUV3_D0_MARK, YUV3_D1_MARK, YUV3_D2_MARK, YUV3_D3_MARK,
162 YUV3_D4_MARK, YUV3_D5_MARK, YUV3_D6_MARK, YUV3_D7_MARK, YUV3_D8_MARK,
163 YUV3_D9_MARK, YUV3_D10_MARK, YUV3_D11_MARK, YUV3_D12_MARK,
164 YUV3_D13_MARK, YUV3_D14_MARK, YUV3_D15_MARK,
165 TP33_CLK_MARK, TP33_CTRL_MARK, TP33_DATA0_MARK, TP33_DATA1_MARK,
166 TP33_DATA2_MARK, TP33_DATA3_MARK, TP33_DATA4_MARK, TP33_DATA5_MARK,
167 TP33_DATA6_MARK, TP33_DATA7_MARK, TP33_DATA8_MARK, TP33_DATA9_MARK,
168 TP33_DATA10_MARK, TP33_DATA11_MARK, TP33_DATA12_MARK, TP33_DATA13_MARK,
169 TP33_DATA14_MARK, TP33_DATA15_MARK,
170
171 /* CHG_PINSEL_IIC */
172 IIC1_SCL_MARK, IIC1_SDA_MARK, UART3_RX_MARK, UART3_TX_MARK,
173
174 /* CHG_PINSEL_AB */
175 AB_CSB2_MARK, AB_CSB3_MARK, AB_RDB_MARK, AB_WRB_MARK,
176 AB_WAIT_MARK, AB_ADV_MARK, AB_AD0_MARK, AB_AD1_MARK,
177 AB_AD2_MARK, AB_AD3_MARK, AB_AD4_MARK, AB_AD5_MARK,
178 AB_AD6_MARK, AB_AD7_MARK, AB_AD8_MARK, AB_AD9_MARK,
179 AB_AD10_MARK, AB_AD11_MARK, AB_AD12_MARK, AB_AD13_MARK,
180 AB_AD14_MARK, AB_AD15_MARK, AB_A17_MARK, AB_A18_MARK,
181 AB_A19_MARK, AB_A21_MARK, AB_A22_MARK, AB_A23_MARK,
182 AB_A24_MARK, AB_A25_MARK, AB_A26_MARK, AB_A27_MARK,
183 AB_A28_MARK, AB_BEN0_MARK, AB_BEN1_MARK,
184 DTV_BCLK_A_MARK, DTV_PSYNC_A_MARK, DTV_VALID_A_MARK,
185 DTV_DATA_A_MARK,
186 SDI2_CKO_MARK, SDI2_CKI_MARK, SDI2_CMD_MARK,
187 SDI2_DATA0_MARK, SDI2_DATA1_MARK, SDI2_DATA2_MARK,
188 SDI2_DATA3_MARK,
189 CF_CSB0_MARK, CF_CSB1_MARK, CF_IORDB_MARK,
190 CF_IOWRB_MARK, CF_IORDY_MARK, CF_RESET_MARK,
191 CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK,
192 CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK,
193 CF_D08_MARK, CF_D09_MARK, CF_D10_MARK, CF_D11_MARK,
194 CF_D12_MARK, CF_D13_MARK, CF_D14_MARK, CF_D15_MARK,
195 CF_A00_MARK, CF_A01_MARK, CF_A02_MARK,
196 CF_INTRQ_MARK, CF_INPACKB_MARK, CF_CDB1_MARK, CF_CDB2_MARK,
197 USI5_CLK_A_MARK, USI5_DI_A_MARK, USI5_DO_A_MARK,
198 USI5_CS0_A_MARK, USI5_CS1_A_MARK, USI5_CS2_A_MARK,
199
200 /* CHG_PINSEL_USI */
201 USI0_CS3_MARK, USI0_CS4_MARK, USI0_CS5_MARK,
202 USI0_CS6_MARK,
203 USI2_CLK_MARK, USI2_DI_MARK, USI2_DO_MARK,
204 USI2_CS0_MARK, USI2_CS1_MARK, USI2_CS2_MARK,
205 USI3_CLK_MARK, USI3_DI_MARK, USI3_DO_MARK,
206 USI3_CS0_MARK,
207 USI4_CLK_MARK, USI4_DI_MARK, USI4_DO_MARK,
208 USI4_CS0_MARK, USI4_CS1_MARK,
209 PWM0_MARK, PWM1_MARK,
210 DTV_BCLK_B_MARK, DTV_PSYNC_B_MARK, DTV_VALID_B_MARK,
211 DTV_DATA_B_MARK,
212
213 /* CHG_PINSEL_HSI */
214 USI5_CLK_B_MARK, USI5_DO_B_MARK, USI5_CS0_B_MARK, USI5_CS1_B_MARK,
215 USI5_CS2_B_MARK, USI5_CS3_B_MARK, USI5_CS4_B_MARK, USI5_DI_B_MARK,
216
217 /* CHG_PINSEL_UART */
218 UART1_CTSB_MARK, UART1_RTSB_MARK,
219 UART2_RX_MARK, UART2_TX_MARK,
220
221 PINMUX_MARK_END,
222};
223
224/* Pin numbers for pins without a corresponding GPIO port number are computed
225 * from the row and column numbers with a 1000 offset to avoid collisions with
226 * GPIO port numbers. */
227#define PIN_NUMBER(row, col) (1000+((row)-1)*23+(col)-1)
228
229/* Expand to a list of sh_pfc_pin entries (named PORT#).
230 * NOTE: No config are recorded since the driver do not handle pinconf. */
231#define __PIN_CFG(pn, pfx, sfx) SH_PFC_PIN_CFG(pfx, 0)
232#define PINMUX_EMEV_GPIO_ALL() CPU_ALL_PORT(__PIN_CFG, , unused)
233
234static const struct sh_pfc_pin pinmux_pins[] = {
235 PINMUX_EMEV_GPIO_ALL(),
236
237 /* Pins not associated with a GPIO port */
238 SH_PFC_PIN_NAMED(2, 14, B14),
239 SH_PFC_PIN_NAMED(2, 15, B15),
240 SH_PFC_PIN_NAMED(2, 16, B16),
241 SH_PFC_PIN_NAMED(2, 17, B17),
242 SH_PFC_PIN_NAMED(3, 14, C14),
243 SH_PFC_PIN_NAMED(3, 15, C15),
244 SH_PFC_PIN_NAMED(3, 16, C16),
245 SH_PFC_PIN_NAMED(3, 17, C17),
246 SH_PFC_PIN_NAMED(4, 14, D14),
247 SH_PFC_PIN_NAMED(4, 15, D15),
248 SH_PFC_PIN_NAMED(4, 16, D16),
249 SH_PFC_PIN_NAMED(4, 17, D17),
250};
251
252/* Expand to a list of name_DATA, name_FN marks */
253#define __PORT_DATA(pn, pfx, sfx) PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN)
254#define PINMUX_EMEV_DATA_ALL() CPU_ALL_PORT(__PORT_DATA, , unused)
255
256static const u16 pinmux_data[] = {
257 PINMUX_EMEV_DATA_ALL(), /* PINMUX_DATA(PORTN_DATA, PORTN_FN), */
258
259 /* GPSR0 */
260 /* V9 */
261 PINMUX_DATA(JT_SEL_MARK, FN_JT_SEL),
262 /* U9 */
263 PINMUX_DATA(ERR_RST_REQB_MARK, FN_ERR_RST_REQB),
264 /* V8 */
265 PINMUX_DATA(REF_CLKO_MARK, FN_REF_CLKO),
266 /* U8 */
267 PINMUX_DATA(EXT_CLKI_MARK, FN_EXT_CLKI),
268 /* B22*/
269 PINMUX_IPSR_NOFN(LCD3_1_0_PORT18, LCD3_PXCLK, SEL_LCD3_1_0_00),
270 PINMUX_IPSR_NOFN(LCD3_1_0_PORT18, YUV3_CLK_O, SEL_LCD3_1_0_01),
271 /* C21 */
272 PINMUX_DATA(LCD3_PXCLKB_MARK, FN_LCD3_PXCLKB),
273 /* A21 */
274 PINMUX_IPSR_NOFN(LCD3_1_0_PORT20, LCD3_CLK_I, SEL_LCD3_1_0_00),
275 PINMUX_IPSR_NOFN(LCD3_1_0_PORT20, YUV3_CLK_I, SEL_LCD3_1_0_01),
276 /* B21 */
277 PINMUX_IPSR_NOFN(LCD3_1_0_PORT21, LCD3_HS, SEL_LCD3_1_0_00),
278 PINMUX_IPSR_NOFN(LCD3_1_0_PORT21, YUV3_HS, SEL_LCD3_1_0_01),
279 /* C20 */
280 PINMUX_IPSR_NOFN(LCD3_1_0_PORT22, LCD3_VS, SEL_LCD3_1_0_00),
281 PINMUX_IPSR_NOFN(LCD3_1_0_PORT22, YUV3_VS, SEL_LCD3_1_0_01),
282 /* D19 */
283 PINMUX_IPSR_NOFN(LCD3_1_0_PORT23, LCD3_DE, SEL_LCD3_1_0_00),
284 PINMUX_IPSR_NOFN(LCD3_1_0_PORT23, YUV3_DE, SEL_LCD3_1_0_01),
285
286 /* GPSR1 */
287 /* A20 */
288 PINMUX_DATA(LCD3_R0_MARK, FN_LCD3_R0),
289 /* B20 */
290 PINMUX_DATA(LCD3_R1_MARK, FN_LCD3_R1),
291 /* A19 */
292 PINMUX_DATA(LCD3_R2_MARK, FN_LCD3_R2),
293 /* B19 */
294 PINMUX_DATA(LCD3_R3_MARK, FN_LCD3_R3),
295 /* C19 */
296 PINMUX_DATA(LCD3_R4_MARK, FN_LCD3_R4),
297 /* B18 */
298 PINMUX_DATA(LCD3_R5_MARK, FN_LCD3_R5),
299 /* C18 */
300 PINMUX_IPSR_NOFN(LCD3_9_8_PORT38, LCD3_R6, SEL_LCD3_9_8_00),
301 PINMUX_IPSR_NOFN(LCD3_9_8_PORT38, TP33_CLK, SEL_LCD3_9_8_10),
302 /* D18 */
303 PINMUX_IPSR_NOFN(LCD3_9_8_PORT39, LCD3_R7, SEL_LCD3_9_8_00),
304 PINMUX_IPSR_NOFN(LCD3_9_8_PORT39, TP33_CTRL, SEL_LCD3_9_8_10),
305 /* A18 */
306 PINMUX_IPSR_NOFN(LCD3_11_10_PORT40, LCD3_G0, SEL_LCD3_11_10_00),
307 PINMUX_IPSR_NOFN(LCD3_11_10_PORT40, YUV3_D0, SEL_LCD3_11_10_01),
308 PINMUX_IPSR_NOFN(LCD3_11_10_PORT40, TP33_DATA0, SEL_LCD3_11_10_10),
309 /* A17 */
310 PINMUX_IPSR_NOFN(LCD3_11_10_PORT41, LCD3_G1, SEL_LCD3_11_10_00),
311 PINMUX_IPSR_NOFN(LCD3_11_10_PORT41, YUV3_D1, SEL_LCD3_11_10_01),
312 PINMUX_IPSR_NOFN(LCD3_11_10_PORT41, TP33_DATA1, SEL_LCD3_11_10_10),
313 /* B17 */
314 PINMUX_DATA(LCD3_G2_MARK, FN_SEL_LCD3_11_10_00),
315 PINMUX_DATA(YUV3_D2_MARK, FN_SEL_LCD3_11_10_01),
316 PINMUX_DATA(TP33_DATA2_MARK, FN_SEL_LCD3_11_10_10),
317 /* C17 */
318 PINMUX_DATA(LCD3_G3_MARK, FN_SEL_LCD3_11_10_00),
319 PINMUX_DATA(YUV3_D3_MARK, FN_SEL_LCD3_11_10_01),
320 PINMUX_DATA(TP33_DATA3_MARK, FN_SEL_LCD3_11_10_10),
321 /* D17 */
322 PINMUX_DATA(LCD3_G4_MARK, FN_SEL_LCD3_11_10_00),
323 PINMUX_DATA(YUV3_D4_MARK, FN_SEL_LCD3_11_10_01),
324 PINMUX_DATA(TP33_DATA4_MARK, FN_SEL_LCD3_11_10_10),
325 /* B16 */
326 PINMUX_DATA(LCD3_G5_MARK, FN_SEL_LCD3_11_10_00),
327 PINMUX_DATA(YUV3_D5_MARK, FN_SEL_LCD3_11_10_01),
328 PINMUX_DATA(TP33_DATA5_MARK, FN_SEL_LCD3_11_10_10),
329 /* C16 */
330 PINMUX_DATA(LCD3_G6_MARK, FN_SEL_LCD3_11_10_00),
331 PINMUX_DATA(YUV3_D6_MARK, FN_SEL_LCD3_11_10_01),
332 PINMUX_DATA(TP33_DATA6_MARK, FN_SEL_LCD3_11_10_10),
333 /* D16 */
334 PINMUX_DATA(LCD3_G7_MARK, FN_SEL_LCD3_11_10_00),
335 PINMUX_DATA(YUV3_D7_MARK, FN_SEL_LCD3_11_10_01),
336 PINMUX_DATA(TP33_DATA7_MARK, FN_SEL_LCD3_11_10_10),
337 /* A16 */
338 PINMUX_IPSR_NOFN(LCD3_11_10_PORT42, LCD3_B0, SEL_LCD3_11_10_00),
339 PINMUX_IPSR_NOFN(LCD3_11_10_PORT42, YUV3_D8, SEL_LCD3_11_10_01),
340 PINMUX_IPSR_NOFN(LCD3_11_10_PORT42, TP33_DATA8, SEL_LCD3_11_10_10),
341 /* A15 */
342 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B1, SEL_LCD3_11_10_00),
343 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D9, SEL_LCD3_11_10_01),
344 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA9, SEL_LCD3_11_10_10),
345 /* B15 */
346 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B2, SEL_LCD3_11_10_00),
347 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D10, SEL_LCD3_11_10_01),
348 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA10, SEL_LCD3_11_10_10),
349 /* C15 */
350 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B3, SEL_LCD3_11_10_00),
351 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D11, SEL_LCD3_11_10_01),
352 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA11, SEL_LCD3_11_10_10),
353 /* D15 */
354 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B4, SEL_LCD3_11_10_00),
355 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D12, SEL_LCD3_11_10_01),
356 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA12, SEL_LCD3_11_10_10),
357 /* B14 */
358 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B5, SEL_LCD3_11_10_00),
359 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D13, SEL_LCD3_11_10_01),
360 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA13, SEL_LCD3_11_10_10),
361 /* C14 */
362 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B6, SEL_LCD3_11_10_00),
363 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D14, SEL_LCD3_11_10_01),
364 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA14, SEL_LCD3_11_10_10),
365 /* D14 */
366 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B7, SEL_LCD3_11_10_00),
367 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D15, SEL_LCD3_11_10_01),
368 PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA15, SEL_LCD3_11_10_10),
369 /* AA9 */
370 PINMUX_DATA(IIC0_SCL_MARK, FN_IIC0_SCL),
371 /* AA8 */
372 PINMUX_DATA(IIC0_SDA_MARK, FN_IIC0_SDA),
373 /* Y9 */
374 PINMUX_IPSR_NOFN(IIC_1_0_PORT46, IIC1_SCL, SEL_IIC_1_0_00),
375 PINMUX_IPSR_NOFN(IIC_1_0_PORT46, UART3_RX, SEL_IIC_1_0_01),
376 /* Y8 */
377 PINMUX_IPSR_NOFN(IIC_1_0_PORT47, IIC1_SDA, SEL_IIC_1_0_00),
378 PINMUX_IPSR_NOFN(IIC_1_0_PORT47, UART3_TX, SEL_IIC_1_0_01),
379 /* AC19 */
380 PINMUX_DATA(SD_CKI_MARK, FN_SD_CKI),
381 /* AB18 */
382 PINMUX_DATA(SDI0_CKO_MARK, FN_SDI0_CKO),
383 /* AC18 */
384 PINMUX_DATA(SDI0_CKI_MARK, FN_SDI0_CKI),
385 /* Y12 */
386 PINMUX_DATA(SDI0_CMD_MARK, FN_SDI0_CMD),
387 /* AA13 */
388 PINMUX_DATA(SDI0_DATA0_MARK, FN_SDI0_DATA0),
389 /* Y13 */
390 PINMUX_DATA(SDI0_DATA1_MARK, FN_SDI0_DATA1),
391 /* AA14 */
392 PINMUX_DATA(SDI0_DATA2_MARK, FN_SDI0_DATA2),
393 /* Y14 */
394 PINMUX_DATA(SDI0_DATA3_MARK, FN_SDI0_DATA3),
395 /* AA15 */
396 PINMUX_DATA(SDI0_DATA4_MARK, FN_SDI0_DATA4),
397 /* Y15 */
398 PINMUX_DATA(SDI0_DATA5_MARK, FN_SDI0_DATA5),
399 /* AA16 */
400 PINMUX_DATA(SDI0_DATA6_MARK, FN_SDI0_DATA6),
401 /* Y16 */
402 PINMUX_DATA(SDI0_DATA7_MARK, FN_SDI0_DATA7),
403 /* AB22 */
404 PINMUX_DATA(SDI1_CKO_MARK, FN_SDI1_CKO),
405 /* AA23 */
406 PINMUX_DATA(SDI1_CKI_MARK, FN_SDI1_CKI),
407 /* AC21 */
408 PINMUX_DATA(SDI1_CMD_MARK, FN_SDI1_CMD),
409
410 /* GPSR2 */
411 /* AB21 */
412 PINMUX_DATA(SDI1_DATA0_MARK, FN_SDI1_DATA0),
413 /* AB20 */
414 PINMUX_DATA(SDI1_DATA1_MARK, FN_SDI1_DATA1),
415 /* AB19 */
416 PINMUX_DATA(SDI1_DATA2_MARK, FN_SDI1_DATA2),
417 /* AA19 */
418 PINMUX_DATA(SDI1_DATA3_MARK, FN_SDI1_DATA3),
419 /* J23 */
420 PINMUX_DATA(AB_CLK_MARK, FN_AB_CLK),
421 /* D21 */
422 PINMUX_DATA(AB_CSB0_MARK, FN_AB_CSB0),
423 /* E21 */
424 PINMUX_DATA(AB_CSB1_MARK, FN_AB_CSB1),
425 /* F20 */
426 PINMUX_IPSR_NOFN(AB_1_0_PORT71, AB_CSB2, SEL_AB_1_0_00),
427 PINMUX_IPSR_NOFN(AB_1_0_PORT71, CF_CSB0, SEL_AB_1_0_10),
428 /* G20 */
429 PINMUX_IPSR_NOFN(AB_1_0_PORT72, AB_CSB3, SEL_AB_1_0_00),
430 PINMUX_IPSR_NOFN(AB_1_0_PORT72, CF_CSB1, SEL_AB_1_0_10),
431 /* J20 */
432 PINMUX_IPSR_NOFN(AB_1_0_PORT73, AB_RDB, SEL_AB_1_0_00),
433 PINMUX_IPSR_NOFN(AB_1_0_PORT73, CF_IORDB, SEL_AB_1_0_10),
434 /* H20 */
435 PINMUX_IPSR_NOFN(AB_1_0_PORT74, AB_WRB, SEL_AB_1_0_00),
436 PINMUX_IPSR_NOFN(AB_1_0_PORT74, CF_IOWRB, SEL_AB_1_0_10),
437 /* L20 */
438 PINMUX_IPSR_NOFN(AB_1_0_PORT75, AB_WAIT, SEL_AB_1_0_00),
439 PINMUX_IPSR_NOFN(AB_1_0_PORT75, CF_IORDY, SEL_AB_1_0_10),
440 /* K20 */
441 PINMUX_IPSR_NOFN(AB_1_0_PORT76, AB_ADV, SEL_AB_1_0_00),
442 PINMUX_IPSR_NOFN(AB_1_0_PORT76, CF_RESET, SEL_AB_1_0_10),
443 /* C23 */
444 PINMUX_IPSR_NOFN(AB_1_0_PORT77, AB_AD0, SEL_AB_1_0_00),
445 PINMUX_IPSR_NOFN(AB_1_0_PORT77, CF_D00, SEL_AB_1_0_10),
446 /* C22 */
447 PINMUX_IPSR_NOFN(AB_1_0_PORT78, AB_AD1, SEL_AB_1_0_00),
448 PINMUX_IPSR_NOFN(AB_1_0_PORT78, CF_D01, SEL_AB_1_0_10),
449 /* D23 */
450 PINMUX_IPSR_NOFN(AB_1_0_PORT79, AB_AD2, SEL_AB_1_0_00),
451 PINMUX_IPSR_NOFN(AB_1_0_PORT79, CF_D02, SEL_AB_1_0_10),
452 /* D22 */
453 PINMUX_IPSR_NOFN(AB_1_0_PORT80, AB_AD3, SEL_AB_1_0_00),
454 PINMUX_IPSR_NOFN(AB_1_0_PORT80, CF_D03, SEL_AB_1_0_10),
455 /* E23 */
456 PINMUX_IPSR_NOFN(AB_1_0_PORT81, AB_AD4, SEL_AB_1_0_00),
457 PINMUX_IPSR_NOFN(AB_1_0_PORT81, CF_D04, SEL_AB_1_0_10),
458 /* E22 */
459 PINMUX_IPSR_NOFN(AB_1_0_PORT82, AB_AD5, SEL_AB_1_0_00),
460 PINMUX_IPSR_NOFN(AB_1_0_PORT82, CF_D05, SEL_AB_1_0_10),
461 /* F23 */
462 PINMUX_IPSR_NOFN(AB_1_0_PORT83, AB_AD6, SEL_AB_1_0_00),
463 PINMUX_IPSR_NOFN(AB_1_0_PORT83, CF_D06, SEL_AB_1_0_10),
464 /* F22 */
465 PINMUX_IPSR_NOFN(AB_1_0_PORT84, AB_AD7, SEL_AB_1_0_00),
466 PINMUX_IPSR_NOFN(AB_1_0_PORT84, CF_D07, SEL_AB_1_0_10),
467 /* F21 */
468 PINMUX_IPSR_NOFN(AB_3_2_PORT85, AB_AD8, SEL_AB_3_2_00),
469 PINMUX_IPSR_NOFN(AB_3_2_PORT85, DTV_BCLK_A, SEL_AB_3_2_01),
470 PINMUX_IPSR_NOFN(AB_3_2_PORT85, CF_D08, SEL_AB_3_2_10),
471 PINMUX_IPSR_NOFN(AB_3_2_PORT85, USI5_CLK_A, SEL_AB_3_2_11),
472 /* G23 */
473 PINMUX_IPSR_NOFN(AB_3_2_PORT86, AB_AD9, SEL_AB_3_2_00),
474 PINMUX_IPSR_NOFN(AB_3_2_PORT86, DTV_PSYNC_A, SEL_AB_3_2_01),
475 PINMUX_IPSR_NOFN(AB_3_2_PORT86, CF_D09, SEL_AB_3_2_10),
476 PINMUX_IPSR_NOFN(AB_3_2_PORT86, USI5_DI_A, SEL_AB_3_2_11),
477 /* G22 */
478 PINMUX_IPSR_NOFN(AB_3_2_PORT87, AB_AD10, SEL_AB_3_2_00),
479 PINMUX_IPSR_NOFN(AB_3_2_PORT87, DTV_VALID_A, SEL_AB_3_2_01),
480 PINMUX_IPSR_NOFN(AB_3_2_PORT87, CF_D10, SEL_AB_3_2_10),
481 PINMUX_IPSR_NOFN(AB_3_2_PORT87, USI5_DO_A, SEL_AB_3_2_11),
482 /* G21 */
483 PINMUX_IPSR_NOFN(AB_3_2_PORT88, AB_AD11, SEL_AB_3_2_00),
484 PINMUX_IPSR_NOFN(AB_3_2_PORT88, DTV_DATA_A, SEL_AB_3_2_01),
485 PINMUX_IPSR_NOFN(AB_3_2_PORT88, CF_D11, SEL_AB_3_2_10),
486 PINMUX_IPSR_NOFN(AB_3_2_PORT88, USI5_CS0_A, SEL_AB_3_2_11),
487 /* H23 */
488 PINMUX_IPSR_NOFN(AB_5_4_PORT89, AB_AD12, SEL_AB_5_4_00),
489 PINMUX_IPSR_NOFN(AB_5_4_PORT89, SDI2_DATA0, SEL_AB_5_4_01),
490 PINMUX_IPSR_NOFN(AB_5_4_PORT89, CF_D12, SEL_AB_5_4_10),
491 PINMUX_IPSR_NOFN(AB_5_4_PORT89, USI5_CS1_A, SEL_AB_5_4_11),
492 /* H22 */
493 PINMUX_IPSR_NOFN(AB_5_4_PORT90, AB_AD13, SEL_AB_5_4_00),
494 PINMUX_IPSR_NOFN(AB_5_4_PORT90, SDI2_DATA1, SEL_AB_5_4_01),
495 PINMUX_IPSR_NOFN(AB_5_4_PORT90, CF_D13, SEL_AB_5_4_10),
496 PINMUX_IPSR_NOFN(AB_5_4_PORT90, USI5_CS2_A, SEL_AB_5_4_11),
497 /* H21 */
498 PINMUX_IPSR_NOFN(AB_7_6_PORT91, AB_AD14, SEL_AB_7_6_00),
499 PINMUX_IPSR_NOFN(AB_7_6_PORT91, SDI2_DATA2, SEL_AB_7_6_01),
500 PINMUX_IPSR_NOFN(AB_7_6_PORT91, CF_D14, SEL_AB_7_6_10),
501 /* J22 */
502 PINMUX_IPSR_NOFN(AB_7_6_PORT92, AB_AD15, SEL_AB_7_6_00),
503 PINMUX_IPSR_NOFN(AB_7_6_PORT92, SDI2_DATA3, SEL_AB_7_6_01),
504 PINMUX_IPSR_NOFN(AB_7_6_PORT92, CF_D15, SEL_AB_7_6_10),
505 /* J21 */
506 PINMUX_IPSR_NOFN(AB_1_0_PORT93, AB_A17, SEL_AB_1_0_00),
507 PINMUX_IPSR_NOFN(AB_1_0_PORT93, CF_A00, SEL_AB_1_0_10),
508 /* K21 */
509 PINMUX_IPSR_NOFN(AB_1_0_PORT94, AB_A18, SEL_AB_1_0_00),
510 PINMUX_IPSR_NOFN(AB_1_0_PORT94, CF_A01, SEL_AB_1_0_10),
511 /* L21 */
512 PINMUX_IPSR_NOFN(AB_1_0_PORT95, AB_A19, SEL_AB_1_0_00),
513 PINMUX_IPSR_NOFN(AB_1_0_PORT95, CF_A02, SEL_AB_1_0_10),
514
515 /* GPSR3 */
516 /* M21 */
517 PINMUX_DATA(AB_A20_MARK, FN_AB_A20),
518 /* N21 */
519 PINMUX_IPSR_NOFN(AB_9_8_PORT97, AB_A21, SEL_AB_9_8_00),
520 PINMUX_IPSR_NOFN(AB_9_8_PORT97, SDI2_CKO, SEL_AB_9_8_01),
521 PINMUX_IPSR_NOFN(AB_9_8_PORT97, CF_INTRQ, SEL_AB_9_8_10),
522 /* M20 */
523 PINMUX_IPSR_NOFN(AB_9_8_PORT98, AB_A22, SEL_AB_9_8_00),
524 PINMUX_IPSR_NOFN(AB_9_8_PORT98, SDI2_CKI, SEL_AB_9_8_01),
525 /* N20 */
526 PINMUX_IPSR_NOFN(AB_9_8_PORT99, AB_A23, SEL_AB_9_8_00),
527 PINMUX_IPSR_NOFN(AB_9_8_PORT99, SDI2_CMD, SEL_AB_9_8_01),
528 /* L18 */
529 PINMUX_IPSR_NOFN(AB_11_10_PORT100, AB_A24, SEL_AB_11_10_00),
530 PINMUX_IPSR_NOFN(AB_11_10_PORT100, CF_INPACKB, SEL_AB_11_10_10),
531 /* M18 */
532 PINMUX_IPSR_NOFN(AB_11_10_PORT101, AB_A25, SEL_AB_11_10_00),
533 PINMUX_IPSR_NOFN(AB_11_10_PORT101, CF_CDB1, SEL_AB_11_10_10),
534 /* N18 */
535 PINMUX_IPSR_NOFN(AB_11_10_PORT102, AB_A26, SEL_AB_11_10_00),
536 PINMUX_IPSR_NOFN(AB_11_10_PORT102, CF_CDB2, SEL_AB_11_10_10),
537 /* L17 */
538 PINMUX_IPSR_NOFN(AB_13_12_PORT103, AB_A27, SEL_AB_13_12_00),
539 PINMUX_IPSR_NOFN(AB_13_12_PORT103, AB_BEN0, SEL_AB_13_12_10),
540 /* M17 */
541 PINMUX_IPSR_NOFN(AB_13_12_PORT104, AB_A28, SEL_AB_13_12_00),
542 PINMUX_IPSR_NOFN(AB_13_12_PORT104, AB_BEN1, SEL_AB_13_12_10),
543 /* B8 */
544 PINMUX_DATA(USI0_CS1_MARK, FN_USI0_CS1),
545 /* B9 */
546 PINMUX_DATA(USI0_CS2_MARK, FN_USI0_CS2),
547 /* C10 */
548 PINMUX_DATA(USI1_DI_MARK, FN_USI1_DI),
549 /* D10 */
550 PINMUX_DATA(USI1_DO_MARK, FN_USI1_DO),
551 /* AB5 */
552 PINMUX_IPSR_NOFN(USI_1_0_PORT109, USI2_CLK, SEL_USI_1_0_00),
553 PINMUX_IPSR_NOFN(USI_1_0_PORT109, DTV_BCLK_B, SEL_USI_1_0_01),
554 /* AA6 */
555 PINMUX_IPSR_NOFN(USI_1_0_PORT110, USI2_DI, SEL_USI_1_0_00),
556 PINMUX_IPSR_NOFN(USI_1_0_PORT110, DTV_PSYNC_B, SEL_USI_1_0_01),
557 /* AA5 */
558 PINMUX_IPSR_NOFN(USI_1_0_PORT111, USI2_DO, SEL_USI_1_0_00),
559 PINMUX_IPSR_NOFN(USI_1_0_PORT111, DTV_VALID_B, SEL_USI_1_0_01),
560 /* Y7 */
561 PINMUX_IPSR_NOFN(USI_1_0_PORT112, USI2_CS0, SEL_USI_1_0_00),
562 PINMUX_IPSR_NOFN(USI_1_0_PORT112, DTV_DATA_B, SEL_USI_1_0_01),
563 /* AA7 */
564 PINMUX_IPSR_NOFN(USI_3_2_PORT113, USI2_CS1, SEL_USI_3_2_00),
565 PINMUX_IPSR_NOFN(USI_3_2_PORT113, USI4_CS0, SEL_USI_3_2_01),
566 /* Y6 */
567 PINMUX_IPSR_NOFN(USI_3_2_PORT114, USI2_CS2, SEL_USI_3_2_00),
568 PINMUX_IPSR_NOFN(USI_3_2_PORT114, USI4_CS1, SEL_USI_3_2_01),
569 /* AC5 */
570 PINMUX_IPSR_NOFN(USI_5_4_PORT115, USI3_CLK, SEL_USI_5_4_00),
571 PINMUX_IPSR_NOFN(USI_5_4_PORT115, USI0_CS3, SEL_USI_5_4_01),
572 /* AC4 */
573 PINMUX_IPSR_NOFN(USI_5_4_PORT116, USI3_DI, SEL_USI_5_4_00),
574 PINMUX_IPSR_NOFN(USI_5_4_PORT116, USI0_CS4, SEL_USI_5_4_01),
575 /* AC3 */
576 PINMUX_IPSR_NOFN(USI_5_4_PORT117, USI3_DO, SEL_USI_5_4_00),
577 PINMUX_IPSR_NOFN(USI_5_4_PORT117, USI0_CS5, SEL_USI_5_4_01),
578 /* AB4 */
579 PINMUX_IPSR_NOFN(USI_5_4_PORT118, USI3_CS0, SEL_USI_5_4_00),
580 PINMUX_IPSR_NOFN(USI_5_4_PORT118, USI0_CS6, SEL_USI_5_4_01),
581 /* AB3 */
582 PINMUX_IPSR_NOFN(USI_7_6_PORT119, USI4_CLK, SEL_USI_7_6_01),
583 /* AA4 */
584 PINMUX_IPSR_NOFN(USI_9_8_PORT120, PWM0, SEL_USI_9_8_00),
585 PINMUX_IPSR_NOFN(USI_9_8_PORT120, USI4_DI, SEL_USI_9_8_01),
586 /* Y5 */
587 PINMUX_IPSR_NOFN(USI_9_8_PORT121, PWM1, SEL_USI_9_8_00),
588 PINMUX_IPSR_NOFN(USI_9_8_PORT121, USI4_DO, SEL_USI_9_8_01),
589 /* V20 */
590 PINMUX_DATA(NTSC_CLK_MARK, FN_NTSC_CLK),
591 /* P20 */
592 PINMUX_DATA(NTSC_DATA0_MARK, FN_NTSC_DATA0),
593 /* P18 */
594 PINMUX_DATA(NTSC_DATA1_MARK, FN_NTSC_DATA1),
595 /* R20 */
596 PINMUX_DATA(NTSC_DATA2_MARK, FN_NTSC_DATA2),
597 /* R18 */
598 PINMUX_DATA(NTSC_DATA3_MARK, FN_NTSC_DATA3),
599 /* T20 */
600 PINMUX_DATA(NTSC_DATA4_MARK, FN_NTSC_DATA4),
601
602 /* GPRS3 */
603 /* T18 */
604 PINMUX_DATA(NTSC_DATA5_MARK, FN_NTSC_DATA5),
605 /* U20 */
606 PINMUX_DATA(NTSC_DATA6_MARK, FN_NTSC_DATA6),
607 /* U18 */
608 PINMUX_DATA(NTSC_DATA7_MARK, FN_NTSC_DATA7),
609 /* W23 */
610 PINMUX_DATA(CAM_CLKO_MARK, FN_CAM_CLKO),
611 /* Y23 */
612 PINMUX_DATA(CAM_CLKI_MARK, FN_CAM_CLKI),
613 /* W22 */
614 PINMUX_DATA(CAM_VS_MARK, FN_CAM_VS),
615 /* V21 */
616 PINMUX_DATA(CAM_HS_MARK, FN_CAM_HS),
617 /* T21 */
618 PINMUX_DATA(CAM_YUV0_MARK, FN_CAM_YUV0),
619 /* T22 */
620 PINMUX_DATA(CAM_YUV1_MARK, FN_CAM_YUV1),
621 /* T23 */
622 PINMUX_DATA(CAM_YUV2_MARK, FN_CAM_YUV2),
623 /* U21 */
624 PINMUX_DATA(CAM_YUV3_MARK, FN_CAM_YUV3),
625 /* U22 */
626 PINMUX_DATA(CAM_YUV4_MARK, FN_CAM_YUV4),
627 /* U23 */
628 PINMUX_DATA(CAM_YUV5_MARK, FN_CAM_YUV5),
629 /* V22 */
630 PINMUX_DATA(CAM_YUV6_MARK, FN_CAM_YUV6),
631 /* V23 */
632 PINMUX_DATA(CAM_YUV7_MARK, FN_CAM_YUV7),
633 /* K22 */
634 PINMUX_IPSR_NOFN(HSI_1_0_PORT143, USI5_CLK_B, SEL_HSI_1_0_01),
635 /* K23 */
636 PINMUX_IPSR_NOFN(HSI_1_0_PORT144, USI5_DO_B, SEL_HSI_1_0_01),
637 /* L23 */
638 PINMUX_IPSR_NOFN(HSI_1_0_PORT145, USI5_CS0_B, SEL_HSI_1_0_01),
639 /* L22 */
640 PINMUX_IPSR_NOFN(HSI_1_0_PORT146, USI5_CS1_B, SEL_HSI_1_0_01),
641 /* N22 */
642 PINMUX_IPSR_NOFN(HSI_1_0_PORT147, USI5_CS2_B, SEL_HSI_1_0_01),
643 /* N23 */
644 PINMUX_IPSR_NOFN(HSI_1_0_PORT148, USI5_CS3_B, SEL_HSI_1_0_01),
645 /* M23 */
646 PINMUX_IPSR_NOFN(HSI_1_0_PORT149, USI5_CS4_B, SEL_HSI_1_0_01),
647 /* M22 */
648 PINMUX_IPSR_NOFN(HSI_1_0_PORT150, USI5_DI_B, SEL_HSI_1_0_01),
649 /* D13 */
650 PINMUX_DATA(JT_TDO_MARK, FN_JT_TDO),
651 /* F13 */
652 PINMUX_DATA(JT_TDOEN_MARK, FN_JT_TDOEN),
653 /* AA12 */
654 PINMUX_DATA(USB_VBUS_MARK, FN_USB_VBUS),
655 /* A12 */
656 PINMUX_DATA(LOWPWR_MARK, FN_LOWPWR),
657 /* Y11 */
658 PINMUX_DATA(UART1_RX_MARK, FN_UART1_RX),
659 /* Y10 */
660 PINMUX_DATA(UART1_TX_MARK, FN_UART1_TX),
661 /* AA10 */
662 PINMUX_IPSR_NOFN(UART_1_0_PORT157, UART1_CTSB, SEL_UART_1_0_00),
663 PINMUX_IPSR_NOFN(UART_1_0_PORT157, UART2_RX, SEL_UART_1_0_01),
664 /* AB10 */
665 PINMUX_IPSR_NOFN(UART_1_0_PORT158, UART1_RTSB, SEL_UART_1_0_00),
666 PINMUX_IPSR_NOFN(UART_1_0_PORT158, UART2_TX, SEL_UART_1_0_01),
667};
668
669
670#define EMEV_MUX_PIN(name, pin, mark) \
671 static const unsigned int name##_pins[] = { pin }; \
672 static const unsigned int name##_mux[] = { mark##_MARK }
673
674/* = [ System ] =========== */
675EMEV_MUX_PIN(err_rst_reqb, 3, ERR_RST_REQB);
676EMEV_MUX_PIN(ref_clko, 4, REF_CLKO);
677EMEV_MUX_PIN(ext_clki, 5, EXT_CLKI);
678EMEV_MUX_PIN(lowpwr, 154, LOWPWR);
679
680/* = [ External Memory] === */
681static const unsigned int ab_main_pins[] = {
682 /* AB_RDB, AB_WRB */
683 73, 74,
684 /* AB_AD[0:15] */
685 77, 78, 79, 80,
686 81, 82, 83, 84,
687 85, 86, 87, 88,
688 89, 90, 91, 92,
689};
690static const unsigned int ab_main_mux[] = {
691 AB_RDB_MARK, AB_WRB_MARK,
692 AB_AD0_MARK, AB_AD1_MARK, AB_AD2_MARK, AB_AD3_MARK,
693 AB_AD4_MARK, AB_AD5_MARK, AB_AD6_MARK, AB_AD7_MARK,
694 AB_AD8_MARK, AB_AD9_MARK, AB_AD10_MARK, AB_AD11_MARK,
695 AB_AD12_MARK, AB_AD13_MARK, AB_AD14_MARK, AB_AD15_MARK,
696};
697
698EMEV_MUX_PIN(ab_clk, 68, AB_CLK);
699EMEV_MUX_PIN(ab_csb0, 69, AB_CSB0);
700EMEV_MUX_PIN(ab_csb1, 70, AB_CSB1);
701EMEV_MUX_PIN(ab_csb2, 71, AB_CSB2);
702EMEV_MUX_PIN(ab_csb3, 72, AB_CSB3);
703EMEV_MUX_PIN(ab_wait, 75, AB_WAIT);
704EMEV_MUX_PIN(ab_adv, 76, AB_ADV);
705EMEV_MUX_PIN(ab_a17, 93, AB_A17);
706EMEV_MUX_PIN(ab_a18, 94, AB_A18);
707EMEV_MUX_PIN(ab_a19, 95, AB_A19);
708EMEV_MUX_PIN(ab_a20, 96, AB_A20);
709EMEV_MUX_PIN(ab_a21, 97, AB_A21);
710EMEV_MUX_PIN(ab_a22, 98, AB_A22);
711EMEV_MUX_PIN(ab_a23, 99, AB_A23);
712EMEV_MUX_PIN(ab_a24, 100, AB_A24);
713EMEV_MUX_PIN(ab_a25, 101, AB_A25);
714EMEV_MUX_PIN(ab_a26, 102, AB_A26);
715EMEV_MUX_PIN(ab_a27, 103, AB_A27);
716EMEV_MUX_PIN(ab_a28, 104, AB_A28);
717EMEV_MUX_PIN(ab_ben0, 103, AB_BEN0);
718EMEV_MUX_PIN(ab_ben1, 104, AB_BEN1);
719
720/* = [ CAM ] ============== */
721EMEV_MUX_PIN(cam_clko, 131, CAM_CLKO);
722static const unsigned int cam_pins[] = {
723 /* CLKI, VS, HS */
724 132, 133, 134,
725 /* CAM_YUV[0:7] */
726 135, 136, 137, 138,
727 139, 140, 141, 142,
728};
729static const unsigned int cam_mux[] = {
730 CAM_CLKI_MARK, CAM_VS_MARK, CAM_HS_MARK,
731 CAM_YUV0_MARK, CAM_YUV1_MARK, CAM_YUV2_MARK, CAM_YUV3_MARK,
732 CAM_YUV4_MARK, CAM_YUV5_MARK, CAM_YUV6_MARK, CAM_YUV7_MARK,
733};
734
735/* = [ CF ] -============== */
736static const unsigned int cf_ctrl_pins[] = {
737 /* CSB0, CSB1, IORDB, IOWRB, IORDY, RESET,
738 * A00, A01, A02, INTRQ, INPACKB, CDB1, CDB2 */
739 71, 72, 73, 74,
740 75, 76, 93, 94,
741 95, 97, 100, 101,
742 102,
743};
744static const unsigned int cf_ctrl_mux[] = {
745 CF_CSB0_MARK, CF_CSB1_MARK, CF_IORDB_MARK, CF_IOWRB_MARK,
746 CF_IORDY_MARK, CF_RESET_MARK, CF_A00_MARK, CF_A01_MARK,
747 CF_A02_MARK, CF_INTRQ_MARK, CF_INPACKB_MARK, CF_CDB1_MARK,
748 CF_CDB2_MARK,
749};
750
751static const unsigned int cf_data8_pins[] = {
752 /* CF_D[0:8] */
753 77, 78, 79, 80,
754 81, 82, 83, 84,
755};
756static const unsigned int cf_data8_mux[] = {
757 CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK,
758 CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK,
759};
760static const unsigned int cf_data16_pins[] = {
761 /* CF_D[0:15] */
762 77, 78, 79, 80,
763 81, 82, 83, 84,
764 85, 86, 87, 88,
765 89, 90, 91, 92,
766};
767static const unsigned int cf_data16_mux[] = {
768 CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK,
769 CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK,
770 CF_D08_MARK, CF_D09_MARK, CF_D10_MARK, CF_D11_MARK,
771 CF_D12_MARK, CF_D13_MARK, CF_D14_MARK, CF_D15_MARK,
772};
773
774/* = [ DTV ] ============== */
775static const unsigned int dtv_a_pins[] = {
776 /* BCLK, PSYNC, VALID, DATA */
777 85, 86, 87, 88,
778};
779static const unsigned int dtv_a_mux[] = {
780 DTV_BCLK_A_MARK, DTV_PSYNC_A_MARK, DTV_VALID_A_MARK, DTV_DATA_A_MARK,
781};
782
783static const unsigned int dtv_b_pins[] = {
784 /* BCLK, PSYNC, VALID, DATA */
785 109, 110, 111, 112,
786};
787static const unsigned int dtv_b_mux[] = {
788 DTV_BCLK_B_MARK, DTV_PSYNC_B_MARK, DTV_VALID_B_MARK, DTV_DATA_B_MARK,
789};
790
791/* = [ IIC0 ] ============= */
792static const unsigned int iic0_pins[] = {
793 /* SCL, SDA */
794 44, 45,
795};
796static const unsigned int iic0_mux[] = {
797 IIC0_SCL_MARK, IIC0_SDA_MARK,
798};
799
800/* = [ IIC1 ] ============= */
801static const unsigned int iic1_pins[] = {
802 /* SCL, SDA */
803 46, 47,
804};
805static const unsigned int iic1_mux[] = {
806 IIC1_SCL_MARK, IIC1_SDA_MARK,
807};
808
809/* = [ JTAG ] ============= */
810static const unsigned int jtag_pins[] = {
811 /* SEL, TDO, TDOEN */
812 2, 151, 152,
813};
814static const unsigned int jtag_mux[] = {
815 JT_SEL_MARK, JT_TDO_MARK, JT_TDOEN_MARK,
816};
817
818/* = [ LCD/YUV ] ========== */
819EMEV_MUX_PIN(lcd3_pxclk, 18, LCD3_PXCLK);
820EMEV_MUX_PIN(lcd3_pxclkb, 19, LCD3_PXCLKB);
821EMEV_MUX_PIN(lcd3_clk_i, 20, LCD3_CLK_I);
822
823static const unsigned int lcd3_sync_pins[] = {
824 /* HS, VS, DE */
825 21, 22, 23,
826};
827static const unsigned int lcd3_sync_mux[] = {
828 LCD3_HS_MARK, LCD3_VS_MARK, LCD3_DE_MARK,
829};
830
831static const unsigned int lcd3_rgb888_pins[] = {
832 /* R[0:7], G[0:7], B[0:7] */
833 32, 33, 34, 35,
834 36, 37, 38, 39,
835 40, 41, PIN_NUMBER(2, 17), PIN_NUMBER(3, 17),
836 PIN_NUMBER(4, 17), PIN_NUMBER(2, 16), PIN_NUMBER(3, 16),
837 PIN_NUMBER(4, 16),
838 42, 43, PIN_NUMBER(2, 15), PIN_NUMBER(3, 15),
839 PIN_NUMBER(4, 15), PIN_NUMBER(2, 14), PIN_NUMBER(3, 14),
840 PIN_NUMBER(4, 14)
841};
842static const unsigned int lcd3_rgb888_mux[] = {
843 LCD3_R0_MARK, LCD3_R1_MARK, LCD3_R2_MARK, LCD3_R3_MARK,
844 LCD3_R4_MARK, LCD3_R5_MARK, LCD3_R6_MARK, LCD3_R7_MARK,
845 LCD3_G0_MARK, LCD3_G1_MARK, LCD3_G2_MARK, LCD3_G3_MARK,
846 LCD3_G4_MARK, LCD3_G5_MARK, LCD3_G6_MARK, LCD3_G7_MARK,
847 LCD3_B0_MARK, LCD3_B1_MARK, LCD3_B2_MARK, LCD3_B3_MARK,
848 LCD3_B4_MARK, LCD3_B5_MARK, LCD3_B6_MARK, LCD3_B7_MARK,
849};
850
851EMEV_MUX_PIN(yuv3_clk_i, 20, YUV3_CLK_I);
852static const unsigned int yuv3_pins[] = {
853 /* CLK_O, HS, VS, DE */
854 18, 21, 22, 23,
855 /* YUV3_D[0:15] */
856 40, 41, PIN_NUMBER(2, 17), PIN_NUMBER(3, 17),
857 PIN_NUMBER(4, 17), PIN_NUMBER(2, 16), PIN_NUMBER(3, 16),
858 PIN_NUMBER(4, 16),
859 42, 43, PIN_NUMBER(2, 15), PIN_NUMBER(3, 15),
860 PIN_NUMBER(4, 15), PIN_NUMBER(2, 14), PIN_NUMBER(3, 14),
861 PIN_NUMBER(4, 14),
862};
863static const unsigned int yuv3_mux[] = {
864 YUV3_CLK_O_MARK, YUV3_HS_MARK, YUV3_VS_MARK, YUV3_DE_MARK,
865 YUV3_D0_MARK, YUV3_D1_MARK, YUV3_D2_MARK, YUV3_D3_MARK,
866 YUV3_D4_MARK, YUV3_D5_MARK, YUV3_D6_MARK, YUV3_D7_MARK,
867 YUV3_D8_MARK, YUV3_D9_MARK, YUV3_D10_MARK, YUV3_D11_MARK,
868 YUV3_D12_MARK, YUV3_D13_MARK, YUV3_D14_MARK, YUV3_D15_MARK,
869};
870
871/* = [ NTSC ] ============= */
872EMEV_MUX_PIN(ntsc_clk, 122, NTSC_CLK);
873static const unsigned int ntsc_data_pins[] = {
874 /* NTSC_DATA[0:7] */
875 123, 124, 125, 126,
876 127, 128, 129, 130,
877};
878static const unsigned int ntsc_data_mux[] = {
879 NTSC_DATA0_MARK, NTSC_DATA1_MARK, NTSC_DATA2_MARK, NTSC_DATA3_MARK,
880 NTSC_DATA4_MARK, NTSC_DATA5_MARK, NTSC_DATA6_MARK, NTSC_DATA7_MARK,
881};
882
883/* = [ PWM0 ] ============= */
884EMEV_MUX_PIN(pwm0, 120, PWM0);
885
886/* = [ PWM1 ] ============= */
887EMEV_MUX_PIN(pwm1, 121, PWM1);
888
889/* = [ SD ] =============== */
890EMEV_MUX_PIN(sd_cki, 48, SD_CKI);
891
892/* = [ SDIO0 ] ============ */
893static const unsigned int sdi0_ctrl_pins[] = {
894 /* CKO, CKI, CMD */
895 50, 51, 52,
896};
897static const unsigned int sdi0_ctrl_mux[] = {
898 SDI0_CKO_MARK, SDI0_CKI_MARK, SDI0_CMD_MARK,
899};
900
901static const unsigned int sdi0_data1_pins[] = {
902 /* SDI0_DATA[0] */
903 53,
904};
905static const unsigned int sdi0_data1_mux[] = {
906 SDI0_DATA0_MARK,
907};
908static const unsigned int sdi0_data4_pins[] = {
909 /* SDI0_DATA[0:3] */
910 53, 54, 55, 56,
911};
912static const unsigned int sdi0_data4_mux[] = {
913 SDI0_DATA0_MARK, SDI0_DATA1_MARK, SDI0_DATA2_MARK, SDI0_DATA3_MARK,
914};
915static const unsigned int sdi0_data8_pins[] = {
916 /* SDI0_DATA[0:7] */
917 53, 54, 55, 56,
918 57, 58, 59, 60
919};
920static const unsigned int sdi0_data8_mux[] = {
921 SDI0_DATA0_MARK, SDI0_DATA1_MARK, SDI0_DATA2_MARK, SDI0_DATA3_MARK,
922 SDI0_DATA4_MARK, SDI0_DATA5_MARK, SDI0_DATA6_MARK, SDI0_DATA7_MARK,
923};
924
925/* = [ SDIO1 ] ============ */
926static const unsigned int sdi1_ctrl_pins[] = {
927 /* CKO, CKI, CMD */
928 61, 62, 63,
929};
930static const unsigned int sdi1_ctrl_mux[] = {
931 SDI1_CKO_MARK, SDI1_CKI_MARK, SDI1_CMD_MARK,
932};
933
934static const unsigned int sdi1_data1_pins[] = {
935 /* SDI1_DATA[0] */
936 64,
937};
938static const unsigned int sdi1_data1_mux[] = {
939 SDI1_DATA0_MARK,
940};
941static const unsigned int sdi1_data4_pins[] = {
942 /* SDI1_DATA[0:3] */
943 64, 65, 66, 67,
944};
945static const unsigned int sdi1_data4_mux[] = {
946 SDI1_DATA0_MARK, SDI1_DATA1_MARK, SDI1_DATA2_MARK, SDI1_DATA3_MARK,
947};
948
949/* = [ SDIO2 ] ============ */
950static const unsigned int sdi2_ctrl_pins[] = {
951 /* CKO, CKI, CMD */
952 97, 98, 99,
953};
954static const unsigned int sdi2_ctrl_mux[] = {
955 SDI2_CKO_MARK, SDI2_CKI_MARK, SDI2_CMD_MARK,
956};
957
958static const unsigned int sdi2_data1_pins[] = {
959 /* SDI2_DATA[0] */
960 89,
961};
962static const unsigned int sdi2_data1_mux[] = {
963 SDI2_DATA0_MARK,
964};
965static const unsigned int sdi2_data4_pins[] = {
966 /* SDI2_DATA[0:3] */
967 89, 90, 91, 92,
968};
969static const unsigned int sdi2_data4_mux[] = {
970 SDI2_DATA0_MARK, SDI2_DATA1_MARK, SDI2_DATA2_MARK, SDI2_DATA3_MARK,
971};
972
973/* = [ TP33 ] ============= */
974static const unsigned int tp33_pins[] = {
975 /* CLK, CTRL */
976 38, 39,
977 /* TP33_DATA[0:15] */
978 40, 41, PIN_NUMBER(2, 17), PIN_NUMBER(3, 17),
979 PIN_NUMBER(4, 17), PIN_NUMBER(2, 16), PIN_NUMBER(3, 16),
980 PIN_NUMBER(4, 16),
981 42, 43, PIN_NUMBER(2, 15), PIN_NUMBER(3, 15),
982 PIN_NUMBER(4, 15), PIN_NUMBER(2, 14), PIN_NUMBER(3, 14),
983 PIN_NUMBER(4, 14),
984};
985static const unsigned int tp33_mux[] = {
986 TP33_CLK_MARK, TP33_CTRL_MARK,
987 TP33_DATA0_MARK, TP33_DATA1_MARK, TP33_DATA2_MARK, TP33_DATA3_MARK,
988 TP33_DATA4_MARK, TP33_DATA5_MARK, TP33_DATA6_MARK, TP33_DATA7_MARK,
989 TP33_DATA8_MARK, TP33_DATA9_MARK, TP33_DATA10_MARK, TP33_DATA11_MARK,
990 TP33_DATA12_MARK, TP33_DATA13_MARK, TP33_DATA14_MARK, TP33_DATA15_MARK,
991};
992
993/* = [ UART1 ] ============ */
994static const unsigned int uart1_data_pins[] = {
995 /* RX, TX */
996 155, 156,
997};
998static const unsigned int uart1_data_mux[] = {
999 UART1_RX_MARK, UART1_TX_MARK,
1000};
1001
1002static const unsigned int uart1_ctrl_pins[] = {
1003 /* CTSB, RTSB */
1004 157, 158,
1005};
1006static const unsigned int uart1_ctrl_mux[] = {
1007 UART1_CTSB_MARK, UART1_RTSB_MARK,
1008};
1009
1010/* = [ UART2 ] ============ */
1011static const unsigned int uart2_data_pins[] = {
1012 /* RX, TX */
1013 157, 158,
1014};
1015static const unsigned int uart2_data_mux[] = {
1016 UART2_RX_MARK, UART2_TX_MARK,
1017};
1018
1019/* = [ UART3 ] ============ */
1020static const unsigned int uart3_data_pins[] = {
1021 /* RX, TX */
1022 46, 47,
1023};
1024static const unsigned int uart3_data_mux[] = {
1025 UART3_RX_MARK, UART3_TX_MARK,
1026};
1027
1028/* = [ USB ] ============== */
1029EMEV_MUX_PIN(usb_vbus, 153, USB_VBUS);
1030
1031/* = [ USI0 ] ============== */
1032EMEV_MUX_PIN(usi0_cs1, 105, USI0_CS1);
1033EMEV_MUX_PIN(usi0_cs2, 106, USI0_CS2);
1034EMEV_MUX_PIN(usi0_cs3, 115, USI0_CS3);
1035EMEV_MUX_PIN(usi0_cs4, 116, USI0_CS4);
1036EMEV_MUX_PIN(usi0_cs5, 117, USI0_CS5);
1037EMEV_MUX_PIN(usi0_cs6, 118, USI0_CS6);
1038
1039/* = [ USI1 ] ============== */
1040static const unsigned int usi1_pins[] = {
1041 /* DI, DO*/
1042 107, 108,
1043};
1044static const unsigned int usi1_mux[] = {
1045 USI1_DI_MARK, USI1_DO_MARK,
1046};
1047
1048/* = [ USI2 ] ============== */
1049static const unsigned int usi2_pins[] = {
1050 /* CLK, DI, DO*/
1051 109, 110, 111,
1052};
1053static const unsigned int usi2_mux[] = {
1054 USI2_CLK_MARK, USI2_DI_MARK, USI2_DO_MARK,
1055};
1056EMEV_MUX_PIN(usi2_cs0, 112, USI2_CS0);
1057EMEV_MUX_PIN(usi2_cs1, 113, USI2_CS1);
1058EMEV_MUX_PIN(usi2_cs2, 114, USI2_CS2);
1059
1060/* = [ USI3 ] ============== */
1061static const unsigned int usi3_pins[] = {
1062 /* CLK, DI, DO*/
1063 115, 116, 117,
1064};
1065static const unsigned int usi3_mux[] = {
1066 USI3_CLK_MARK, USI3_DI_MARK, USI3_DO_MARK,
1067};
1068EMEV_MUX_PIN(usi3_cs0, 118, USI3_CS0);
1069
1070/* = [ USI4 ] ============== */
1071static const unsigned int usi4_pins[] = {
1072 /* CLK, DI, DO*/
1073 119, 120, 121,
1074};
1075static const unsigned int usi4_mux[] = {
1076 USI4_CLK_MARK, USI4_DI_MARK, USI4_DO_MARK,
1077};
1078EMEV_MUX_PIN(usi4_cs0, 113, USI4_CS0);
1079EMEV_MUX_PIN(usi4_cs1, 114, USI4_CS1);
1080
1081/* = [ USI5 ] ============== */
1082static const unsigned int usi5_a_pins[] = {
1083 /* CLK, DI, DO*/
1084 85, 86, 87,
1085};
1086static const unsigned int usi5_a_mux[] = {
1087 USI5_CLK_A_MARK, USI5_DI_A_MARK, USI5_DO_A_MARK,
1088};
1089EMEV_MUX_PIN(usi5_cs0_a, 88, USI5_CS0_A);
1090EMEV_MUX_PIN(usi5_cs1_a, 89, USI5_CS1_A);
1091EMEV_MUX_PIN(usi5_cs2_a, 90, USI5_CS2_A);
1092
1093static const unsigned int usi5_b_pins[] = {
1094 /* CLK, DI, DO*/
1095 143, 144, 150,
1096};
1097static const unsigned int usi5_b_mux[] = {
1098 USI5_CLK_B_MARK, USI5_DI_B_MARK, USI5_DO_B_MARK,
1099};
1100EMEV_MUX_PIN(usi5_cs0_b, 145, USI5_CS0_B);
1101EMEV_MUX_PIN(usi5_cs1_b, 146, USI5_CS1_B);
1102EMEV_MUX_PIN(usi5_cs2_b, 147, USI5_CS2_B);
1103EMEV_MUX_PIN(usi5_cs3_b, 148, USI5_CS3_B);
1104EMEV_MUX_PIN(usi5_cs4_b, 149, USI5_CS4_B);
1105
1106static const struct sh_pfc_pin_group pinmux_groups[] = {
1107 SH_PFC_PIN_GROUP(err_rst_reqb),
1108 SH_PFC_PIN_GROUP(ref_clko),
1109 SH_PFC_PIN_GROUP(ext_clki),
1110 SH_PFC_PIN_GROUP(lowpwr),
1111
1112 SH_PFC_PIN_GROUP(ab_main),
1113 SH_PFC_PIN_GROUP(ab_clk),
1114 SH_PFC_PIN_GROUP(ab_csb0),
1115 SH_PFC_PIN_GROUP(ab_csb1),
1116 SH_PFC_PIN_GROUP(ab_csb2),
1117 SH_PFC_PIN_GROUP(ab_csb3),
1118 SH_PFC_PIN_GROUP(ab_wait),
1119 SH_PFC_PIN_GROUP(ab_adv),
1120 SH_PFC_PIN_GROUP(ab_a17),
1121 SH_PFC_PIN_GROUP(ab_a18),
1122 SH_PFC_PIN_GROUP(ab_a19),
1123 SH_PFC_PIN_GROUP(ab_a20),
1124 SH_PFC_PIN_GROUP(ab_a21),
1125 SH_PFC_PIN_GROUP(ab_a22),
1126 SH_PFC_PIN_GROUP(ab_a23),
1127 SH_PFC_PIN_GROUP(ab_a24),
1128 SH_PFC_PIN_GROUP(ab_a25),
1129 SH_PFC_PIN_GROUP(ab_a26),
1130 SH_PFC_PIN_GROUP(ab_a27),
1131 SH_PFC_PIN_GROUP(ab_a28),
1132 SH_PFC_PIN_GROUP(ab_ben0),
1133 SH_PFC_PIN_GROUP(ab_ben1),
1134
1135 SH_PFC_PIN_GROUP(cam_clko),
1136 SH_PFC_PIN_GROUP(cam),
1137
1138 SH_PFC_PIN_GROUP(cf_ctrl),
1139 SH_PFC_PIN_GROUP(cf_data8),
1140 SH_PFC_PIN_GROUP(cf_data16),
1141
1142 SH_PFC_PIN_GROUP(dtv_a),
1143 SH_PFC_PIN_GROUP(dtv_b),
1144
1145 SH_PFC_PIN_GROUP(iic0),
1146
1147 SH_PFC_PIN_GROUP(iic1),
1148
1149 SH_PFC_PIN_GROUP(jtag),
1150
1151 SH_PFC_PIN_GROUP(lcd3_pxclk),
1152 SH_PFC_PIN_GROUP(lcd3_pxclkb),
1153 SH_PFC_PIN_GROUP(lcd3_clk_i),
1154 SH_PFC_PIN_GROUP(lcd3_sync),
1155 SH_PFC_PIN_GROUP(lcd3_rgb888),
1156 SH_PFC_PIN_GROUP(yuv3_clk_i),
1157 SH_PFC_PIN_GROUP(yuv3),
1158
1159 SH_PFC_PIN_GROUP(ntsc_clk),
1160 SH_PFC_PIN_GROUP(ntsc_data),
1161
1162 SH_PFC_PIN_GROUP(pwm0),
1163
1164 SH_PFC_PIN_GROUP(pwm1),
1165
1166 SH_PFC_PIN_GROUP(sd_cki),
1167
1168 SH_PFC_PIN_GROUP(sdi0_ctrl),
1169 SH_PFC_PIN_GROUP(sdi0_data1),
1170 SH_PFC_PIN_GROUP(sdi0_data4),
1171 SH_PFC_PIN_GROUP(sdi0_data8),
1172
1173 SH_PFC_PIN_GROUP(sdi1_ctrl),
1174 SH_PFC_PIN_GROUP(sdi1_data1),
1175 SH_PFC_PIN_GROUP(sdi1_data4),
1176
1177 SH_PFC_PIN_GROUP(sdi2_ctrl),
1178 SH_PFC_PIN_GROUP(sdi2_data1),
1179 SH_PFC_PIN_GROUP(sdi2_data4),
1180
1181 SH_PFC_PIN_GROUP(tp33),
1182
1183 SH_PFC_PIN_GROUP(uart1_data),
1184 SH_PFC_PIN_GROUP(uart1_ctrl),
1185
1186 SH_PFC_PIN_GROUP(uart2_data),
1187
1188 SH_PFC_PIN_GROUP(uart3_data),
1189
1190 SH_PFC_PIN_GROUP(usb_vbus),
1191
1192 SH_PFC_PIN_GROUP(usi0_cs1),
1193 SH_PFC_PIN_GROUP(usi0_cs2),
1194 SH_PFC_PIN_GROUP(usi0_cs3),
1195 SH_PFC_PIN_GROUP(usi0_cs4),
1196 SH_PFC_PIN_GROUP(usi0_cs5),
1197 SH_PFC_PIN_GROUP(usi0_cs6),
1198
1199 SH_PFC_PIN_GROUP(usi1),
1200
1201 SH_PFC_PIN_GROUP(usi2),
1202 SH_PFC_PIN_GROUP(usi2_cs0),
1203 SH_PFC_PIN_GROUP(usi2_cs1),
1204 SH_PFC_PIN_GROUP(usi2_cs2),
1205
1206 SH_PFC_PIN_GROUP(usi3),
1207 SH_PFC_PIN_GROUP(usi3_cs0),
1208
1209 SH_PFC_PIN_GROUP(usi4),
1210 SH_PFC_PIN_GROUP(usi4_cs0),
1211 SH_PFC_PIN_GROUP(usi4_cs1),
1212
1213 SH_PFC_PIN_GROUP(usi5_a),
1214 SH_PFC_PIN_GROUP(usi5_cs0_a),
1215 SH_PFC_PIN_GROUP(usi5_cs1_a),
1216 SH_PFC_PIN_GROUP(usi5_cs2_a),
1217 SH_PFC_PIN_GROUP(usi5_b),
1218 SH_PFC_PIN_GROUP(usi5_cs0_b),
1219 SH_PFC_PIN_GROUP(usi5_cs1_b),
1220 SH_PFC_PIN_GROUP(usi5_cs2_b),
1221 SH_PFC_PIN_GROUP(usi5_cs3_b),
1222 SH_PFC_PIN_GROUP(usi5_cs4_b),
1223};
1224
1225static const char * const ab_groups[] = {
1226 "ab_main",
1227 "ab_clk",
1228 "ab_csb0",
1229 "ab_csb1",
1230 "ab_csb2",
1231 "ab_csb3",
1232 "ab_wait",
1233 "ab_adv",
1234 "ab_a17",
1235 "ab_a18",
1236 "ab_a19",
1237 "ab_a20",
1238 "ab_a21",
1239 "ab_a22",
1240 "ab_a23",
1241 "ab_a24",
1242 "ab_a25",
1243 "ab_a26",
1244 "ab_a27",
1245 "ab_a28",
1246 "ab_ben0",
1247 "ab_ben1",
1248};
1249
1250static const char * const cam_groups[] = {
1251 "cam_clko",
1252 "cam",
1253};
1254
1255static const char * const cf_groups[] = {
1256 "cf_ctrl",
1257 "cf_data8",
1258 "cf_data16",
1259};
1260
1261static const char * const dtv_groups[] = {
1262 "dtv_a",
1263 "dtv_b",
1264};
1265
1266static const char * const iic0_groups[] = {
1267 "iic0",
1268};
1269
1270static const char * const iic1_groups[] = {
1271 "iic1",
1272};
1273
1274static const char * const jtag_groups[] = {
1275 "jtag",
1276};
1277
1278static const char * const lcd_groups[] = {
1279 "lcd3_pxclk",
1280 "lcd3_pxclkb",
1281 "lcd3_clk_i",
1282 "lcd3_sync",
1283 "lcd3_rgb888",
1284 "yuv3_clk_i",
1285 "yuv3",
1286};
1287
1288static const char * const ntsc_groups[] = {
1289 "ntsc_clk",
1290 "ntsc_data",
1291};
1292
1293static const char * const pwm0_groups[] = {
1294 "pwm0",
1295};
1296
1297static const char * const pwm1_groups[] = {
1298 "pwm1",
1299};
1300
1301static const char * const sd_groups[] = {
1302 "sd_cki",
1303};
1304
1305static const char * const sdi0_groups[] = {
1306 "sdi0_ctrl",
1307 "sdi0_data1",
1308 "sdi0_data4",
1309 "sdi0_data8",
1310};
1311
1312static const char * const sdi1_groups[] = {
1313 "sdi1_ctrl",
1314 "sdi1_data1",
1315 "sdi1_data4",
1316};
1317
1318static const char * const sdi2_groups[] = {
1319 "sdi2_ctrl",
1320 "sdi2_data1",
1321 "sdi2_data4",
1322};
1323
1324static const char * const tp33_groups[] = {
1325 "tp33",
1326};
1327
1328static const char * const uart1_groups[] = {
1329 "uart1_data",
1330 "uart1_ctrl",
1331};
1332
1333static const char * const uart2_groups[] = {
1334 "uart2_data",
1335};
1336
1337static const char * const uart3_groups[] = {
1338 "uart3_data",
1339};
1340
1341static const char * const usb_groups[] = {
1342 "usb_vbus",
1343};
1344
1345static const char * const usi0_groups[] = {
1346 "usi0_cs1",
1347 "usi0_cs2",
1348 "usi0_cs3",
1349 "usi0_cs4",
1350 "usi0_cs5",
1351 "usi0_cs6",
1352};
1353
1354static const char * const usi1_groups[] = {
1355 "usi1",
1356};
1357
1358static const char * const usi2_groups[] = {
1359 "usi2",
1360 "usi2_cs0",
1361 "usi2_cs1",
1362 "usi2_cs2",
1363};
1364
1365static const char * const usi3_groups[] = {
1366 "usi3",
1367 "usi3_cs0",
1368};
1369
1370static const char * const usi4_groups[] = {
1371 "usi4",
1372 "usi4_cs0",
1373 "usi4_cs1",
1374};
1375
1376static const char * const usi5_groups[] = {
1377 "usi5_a",
1378 "usi5_cs0_a",
1379 "usi5_cs1_a",
1380 "usi5_cs2_a",
1381 "usi5_b",
1382 "usi5_cs0_b",
1383 "usi5_cs1_b",
1384 "usi5_cs2_b",
1385 "usi5_cs3_b",
1386 "usi5_cs4_b",
1387};
1388
1389static const struct sh_pfc_function pinmux_functions[] = {
1390 SH_PFC_FUNCTION(ab),
1391 SH_PFC_FUNCTION(cam),
1392 SH_PFC_FUNCTION(cf),
1393 SH_PFC_FUNCTION(dtv),
1394 SH_PFC_FUNCTION(iic0),
1395 SH_PFC_FUNCTION(iic1),
1396 SH_PFC_FUNCTION(jtag),
1397 SH_PFC_FUNCTION(lcd),
1398 SH_PFC_FUNCTION(ntsc),
1399 SH_PFC_FUNCTION(pwm0),
1400 SH_PFC_FUNCTION(pwm1),
1401 SH_PFC_FUNCTION(sd),
1402 SH_PFC_FUNCTION(sdi0),
1403 SH_PFC_FUNCTION(sdi1),
1404 SH_PFC_FUNCTION(sdi2),
1405 SH_PFC_FUNCTION(tp33),
1406 SH_PFC_FUNCTION(uart1),
1407 SH_PFC_FUNCTION(uart2),
1408 SH_PFC_FUNCTION(uart3),
1409 SH_PFC_FUNCTION(usb),
1410 SH_PFC_FUNCTION(usi0),
1411 SH_PFC_FUNCTION(usi1),
1412 SH_PFC_FUNCTION(usi2),
1413 SH_PFC_FUNCTION(usi3),
1414 SH_PFC_FUNCTION(usi4),
1415 SH_PFC_FUNCTION(usi5),
1416};
1417
1418static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1419 { PINMUX_CFG_REG("GPSR0", 0xe0140200, 32, 1) {
1420 0, PORT31_FN, /* PIN: J18 */
1421 0, PORT30_FN, /* PIN: H18 */
1422 0, PORT29_FN, /* PIN: G18 */
1423 0, PORT28_FN, /* PIN: F18 */
1424 0, PORT27_FN, /* PIN: F17 */
1425 0, PORT26_FN, /* PIN: F16 */
1426 0, PORT25_FN, /* PIN: E20 */
1427 0, PORT24_FN, /* PIN: D20 */
1428 FN_LCD3_1_0_PORT23, PORT23_FN, /* PIN: D19 */
1429 FN_LCD3_1_0_PORT22, PORT22_FN, /* PIN: C20 */
1430 FN_LCD3_1_0_PORT21, PORT21_FN, /* PIN: B21 */
1431 FN_LCD3_1_0_PORT20, PORT20_FN, /* PIN: A21 */
1432 FN_LCD3_PXCLKB, PORT19_FN, /* PIN: C21 */
1433 FN_LCD3_1_0_PORT18, PORT18_FN, /* PIN: B22 */
1434 0, PORT17_FN, /* PIN: W20 */
1435 0, PORT16_FN, /* PIN: W21 */
1436 0, PORT15_FN, /* PIN: Y19 */
1437 0, PORT14_FN, /* PIN: Y20 */
1438 0, PORT13_FN, /* PIN: Y21 */
1439 0, PORT12_FN, /* PIN: AA20 */
1440 0, PORT11_FN, /* PIN: AA21 */
1441 0, PORT10_FN, /* PIN: AA22 */
1442 0, PORT9_FN, /* PIN: V15 */
1443 0, PORT8_FN, /* PIN: V16 */
1444 0, PORT7_FN, /* PIN: V17 */
1445 0, PORT6_FN, /* PIN: V18 */
1446 FN_EXT_CLKI, PORT5_FN, /* PIN: U8 */
1447 FN_REF_CLKO, PORT4_FN, /* PIN: V8 */
1448 FN_ERR_RST_REQB, PORT3_FN, /* PIN: U9 */
1449 FN_JT_SEL, PORT2_FN, /* PIN: V9 */
1450 0, PORT1_FN, /* PIN: U10 */
1451 0, PORT0_FN, /* PIN: V10 */
1452 }
1453 },
1454 { PINMUX_CFG_REG("GPSR1", 0xe0140204, 32, 1) {
1455 FN_SDI1_CMD, PORT63_FN, /* PIN: AC21 */
1456 FN_SDI1_CKI, PORT62_FN, /* PIN: AA23 */
1457 FN_SDI1_CKO, PORT61_FN, /* PIN: AB22 */
1458 FN_SDI0_DATA7, PORT60_FN, /* PIN: Y16 */
1459 FN_SDI0_DATA6, PORT59_FN, /* PIN: AA16 */
1460 FN_SDI0_DATA5, PORT58_FN, /* PIN: Y15 */
1461 FN_SDI0_DATA4, PORT57_FN, /* PIN: AA15 */
1462 FN_SDI0_DATA3, PORT56_FN, /* PIN: Y14 */
1463 FN_SDI0_DATA2, PORT55_FN, /* PIN: AA14 */
1464 FN_SDI0_DATA1, PORT54_FN, /* PIN: Y13 */
1465 FN_SDI0_DATA0, PORT53_FN, /* PIN: AA13 */
1466 FN_SDI0_CMD, PORT52_FN, /* PIN: Y12 */
1467 FN_SDI0_CKI, PORT51_FN, /* PIN: AC18 */
1468 FN_SDI0_CKO, PORT50_FN, /* PIN: AB18 */
1469 0, PORT49_FN, /* PIN: AB16 */
1470 FN_SD_CKI, PORT48_FN, /* PIN: AC19 */
1471 FN_IIC_1_0_PORT47, PORT47_FN, /* PIN: Y8 */
1472 FN_IIC_1_0_PORT46, PORT46_FN, /* PIN: Y9 */
1473 FN_IIC0_SDA, PORT45_FN, /* PIN: AA8 */
1474 FN_IIC0_SCL, PORT44_FN, /* PIN: AA9 */
1475 FN_LCD3_11_10_PORT43, PORT43_FN, /* PIN: A15 */
1476 FN_LCD3_11_10_PORT42, PORT42_FN, /* PIN: A16 */
1477 FN_LCD3_11_10_PORT41, PORT41_FN, /* PIN: A17 */
1478 FN_LCD3_11_10_PORT40, PORT40_FN, /* PIN: A18 */
1479 FN_LCD3_9_8_PORT39, PORT39_FN, /* PIN: D18 */
1480 FN_LCD3_9_8_PORT38, PORT38_FN, /* PIN: C18 */
1481 FN_LCD3_R5, PORT37_FN, /* PIN: B18 */
1482 FN_LCD3_R4, PORT36_FN, /* PIN: C19 */
1483 FN_LCD3_R3, PORT35_FN, /* PIN: B19 */
1484 FN_LCD3_R2, PORT34_FN, /* PIN: A19 */
1485 FN_LCD3_R1, PORT33_FN, /* PIN: B20 */
1486 FN_LCD3_R0, PORT32_FN, /* PIN: A20 */
1487 }
1488 },
1489 { PINMUX_CFG_REG("GPSR2", 0xe0140208, 32, 1) {
1490 FN_AB_1_0_PORT95, PORT95_FN, /* PIN: L21 */
1491 FN_AB_1_0_PORT94, PORT94_FN, /* PIN: K21 */
1492 FN_AB_1_0_PORT93, PORT93_FN, /* PIN: J21 */
1493 FN_AB_7_6_PORT92, PORT92_FN, /* PIN: J22 */
1494 FN_AB_7_6_PORT91, PORT91_FN, /* PIN: H21 */
1495 FN_AB_5_4_PORT90, PORT90_FN, /* PIN: H22 */
1496 FN_AB_5_4_PORT89, PORT89_FN, /* PIN: H23 */
1497 FN_AB_3_2_PORT88, PORT88_FN, /* PIN: G21 */
1498 FN_AB_3_2_PORT87, PORT87_FN, /* PIN: G22 */
1499 FN_AB_3_2_PORT86, PORT86_FN, /* PIN: G23 */
1500 FN_AB_3_2_PORT85, PORT85_FN, /* PIN: F21 */
1501 FN_AB_1_0_PORT84, PORT84_FN, /* PIN: F22 */
1502 FN_AB_1_0_PORT83, PORT83_FN, /* PIN: F23 */
1503 FN_AB_1_0_PORT82, PORT82_FN, /* PIN: E22 */
1504 FN_AB_1_0_PORT81, PORT81_FN, /* PIN: E23 */
1505 FN_AB_1_0_PORT80, PORT80_FN, /* PIN: D22 */
1506 FN_AB_1_0_PORT79, PORT79_FN, /* PIN: D23 */
1507 FN_AB_1_0_PORT78, PORT78_FN, /* PIN: C22 */
1508 FN_AB_1_0_PORT77, PORT77_FN, /* PIN: C23 */
1509 FN_AB_1_0_PORT76, PORT76_FN, /* PIN: K20 */
1510 FN_AB_1_0_PORT75, PORT75_FN, /* PIN: L20 */
1511 FN_AB_1_0_PORT74, PORT74_FN, /* PIN: H20 */
1512 FN_AB_1_0_PORT73, PORT73_FN, /* PIN: J20 */
1513 FN_AB_1_0_PORT72, PORT72_FN, /* PIN: G20 */
1514 FN_AB_1_0_PORT71, PORT71_FN, /* PIN: F20 */
1515 FN_AB_CSB1, PORT70_FN, /* PIN: E21 */
1516 FN_AB_CSB0, PORT69_FN, /* PIN: D21 */
1517 FN_AB_CLK, PORT68_FN, /* PIN: J23 */
1518 FN_SDI1_DATA3, PORT67_FN, /* PIN: AA19 */
1519 FN_SDI1_DATA2, PORT66_FN, /* PIN: AB19 */
1520 FN_SDI1_DATA1, PORT65_FN, /* PIN: AB20 */
1521 FN_SDI1_DATA0, PORT64_FN, /* PIN: AB21 */
1522 }
1523 },
1524 { PINMUX_CFG_REG("GPSR3", 0xe014020c, 32, 1) {
1525 FN_NTSC_DATA4, PORT127_FN, /* PIN: T20 */
1526 FN_NTSC_DATA3, PORT126_FN, /* PIN: R18 */
1527 FN_NTSC_DATA2, PORT125_FN, /* PIN: R20 */
1528 FN_NTSC_DATA1, PORT124_FN, /* PIN: P18 */
1529 FN_NTSC_DATA0, PORT123_FN, /* PIN: P20 */
1530 FN_NTSC_CLK, PORT122_FN, /* PIN: V20 */
1531 FN_USI_9_8_PORT121, PORT121_FN, /* PIN: Y5 */
1532 FN_USI_9_8_PORT120, PORT120_FN, /* PIN: AA4 */
1533 FN_USI_7_6_PORT119, PORT119_FN, /* PIN: AB3 */
1534 FN_USI_5_4_PORT118, PORT118_FN, /* PIN: AB4 */
1535 FN_USI_5_4_PORT117, PORT117_FN, /* PIN: AC3 */
1536 FN_USI_5_4_PORT116, PORT116_FN, /* PIN: AC4 */
1537 FN_USI_5_4_PORT115, PORT115_FN, /* PIN: AC5 */
1538 FN_USI_3_2_PORT114, PORT114_FN, /* PIN: Y6 */
1539 FN_USI_3_2_PORT113, PORT113_FN, /* PIN: AA7 */
1540 FN_USI_1_0_PORT112, PORT112_FN, /* PIN: Y7 */
1541 FN_USI_1_0_PORT111, PORT111_FN, /* PIN: AA5 */
1542 FN_USI_1_0_PORT110, PORT110_FN, /* PIN: AA6 */
1543 FN_USI_1_0_PORT109, PORT109_FN, /* PIN: AB5 */
1544 FN_USI1_DO, PORT108_FN, /* PIN: D10 */
1545 FN_USI1_DI, PORT107_FN, /* PIN: C10 */
1546 FN_USI0_CS2, PORT106_FN, /* PIN: B9 */
1547 FN_USI0_CS1, PORT105_FN, /* PIN: B8 */
1548 FN_AB_13_12_PORT104, PORT104_FN, /* PIN: M17 */
1549 FN_AB_13_12_PORT103, PORT103_FN, /* PIN: L17 */
1550 FN_AB_11_10_PORT102, PORT102_FN, /* PIN: N18 */
1551 FN_AB_11_10_PORT101, PORT101_FN, /* PIN: M18 */
1552 FN_AB_11_10_PORT100, PORT100_FN, /* PIN: L18 */
1553 FN_AB_9_8_PORT99, PORT99_FN, /* PIN: N20 */
1554 FN_AB_9_8_PORT98, PORT98_FN, /* PIN: M20 */
1555 FN_AB_9_8_PORT97, PORT97_FN, /* PIN: N21 */
1556 FN_AB_A20, PORT96_FN, /* PIN: M21 */
1557 }
1558 },
1559 { PINMUX_CFG_REG("GPSR4", 0xe0140210, 32, 1) {
1560 0, 0,
1561 FN_UART_1_0_PORT158, PORT158_FN, /* PIN: AB10 */
1562 FN_UART_1_0_PORT157, PORT157_FN, /* PIN: AA10 */
1563 FN_UART1_TX, PORT156_FN, /* PIN: Y10 */
1564 FN_UART1_RX, PORT155_FN, /* PIN: Y11 */
1565 FN_LOWPWR, PORT154_FN, /* PIN: A12 */
1566 FN_USB_VBUS, PORT153_FN, /* PIN: AA12 */
1567 FN_JT_TDOEN, PORT152_FN, /* PIN: F13 */
1568 FN_JT_TDO, PORT151_FN, /* PIN: D13 */
1569 FN_HSI_1_0_PORT150, PORT150_FN, /* PIN: M22 */
1570 FN_HSI_1_0_PORT149, PORT149_FN, /* PIN: M23 */
1571 FN_HSI_1_0_PORT148, PORT148_FN, /* PIN: N23 */
1572 FN_HSI_1_0_PORT147, PORT147_FN, /* PIN: N22 */
1573 FN_HSI_1_0_PORT146, PORT146_FN, /* PIN: L22 */
1574 FN_HSI_1_0_PORT145, PORT145_FN, /* PIN: L23 */
1575 FN_HSI_1_0_PORT144, PORT144_FN, /* PIN: K23 */
1576 FN_HSI_1_0_PORT143, PORT143_FN, /* PIN: K22 */
1577 FN_CAM_YUV7, PORT142_FN, /* PIN: V23 */
1578 FN_CAM_YUV6, PORT141_FN, /* PIN: V22 */
1579 FN_CAM_YUV5, PORT140_FN, /* PIN: U23 */
1580 FN_CAM_YUV4, PORT139_FN, /* PIN: U22 */
1581 FN_CAM_YUV3, PORT138_FN, /* PIN: U21 */
1582 FN_CAM_YUV2, PORT137_FN, /* PIN: T23 */
1583 FN_CAM_YUV1, PORT136_FN, /* PIN: T22 */
1584 FN_CAM_YUV0, PORT135_FN, /* PIN: T21 */
1585 FN_CAM_HS, PORT134_FN, /* PIN: V21 */
1586 FN_CAM_VS, PORT133_FN, /* PIN: W22 */
1587 FN_CAM_CLKI, PORT132_FN, /* PIN: Y23 */
1588 FN_CAM_CLKO, PORT131_FN, /* PIN: W23 */
1589 FN_NTSC_DATA7, PORT130_FN, /* PIN: U18 */
1590 FN_NTSC_DATA6, PORT129_FN, /* PIN: U20 */
1591 FN_NTSC_DATA5, PORT128_FN, /* PIN: T18 */
1592 }
1593 },
1594 { PINMUX_CFG_REG_VAR("CHG_PINSEL_LCD3", 0xe0140284, 32,
1595 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1596 1, 1, 1, 1, 2, 2, 2, 2, 2, 2) {
1597 /* 31 - 12 */
1598 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1599 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1600 0, 0, 0, 0, 0, 0, 0, 0,
1601 /* 11 - 10 */
1602 FN_SEL_LCD3_11_10_00, FN_SEL_LCD3_11_10_01,
1603 FN_SEL_LCD3_11_10_10, 0,
1604 /* 9 - 8 */
1605 FN_SEL_LCD3_9_8_00, 0, FN_SEL_LCD3_9_8_10, 0,
1606 /* 7 - 2 */
1607 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1608 /* 1 - 0 */
1609 FN_SEL_LCD3_1_0_00, FN_SEL_LCD3_1_0_01, 0, 0,
1610 }
1611 },
1612 { PINMUX_CFG_REG_VAR("CHG_PINSEL_UART", 0xe0140288, 32,
1613 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1614 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2) {
1615 /* 31 - 2 */
1616 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1617 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1618 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1619 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1620 /* 1 - 0 */
1621 FN_SEL_UART_1_0_00, FN_SEL_UART_1_0_01, 0, 0,
1622 }
1623 },
1624 { PINMUX_CFG_REG_VAR("CHG_PINSEL_IIC", 0xe014028c, 32,
1625 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1626 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2) {
1627 /* 31 - 2 */
1628 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1629 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1630 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1631 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1632 /* 1 - 0 */
1633 FN_SEL_IIC_1_0_00, FN_SEL_IIC_1_0_01, 0, 0,
1634 }
1635 },
1636 { PINMUX_CFG_REG_VAR("CHG_PINSEL_AB", 0xe0140294, 32,
1637 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1638 2, 2, 2, 2, 2, 2, 2, 2) {
1639 /* 31 - 14 */
1640 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1641 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1642 0, 0, 0, 0,
1643 /* 13 - 12 */
1644 FN_SEL_AB_13_12_00, 0, FN_SEL_AB_13_12_10, 0,
1645 /* 11 - 10 */
1646 FN_SEL_AB_11_10_00, 0, FN_SEL_AB_11_10_10, 0,
1647 /* 9 - 8 */
1648 FN_SEL_AB_9_8_00, FN_SEL_AB_9_8_01, FN_SEL_AB_9_8_10, 0,
1649 /* 7 - 6 */
1650 FN_SEL_AB_7_6_00, FN_SEL_AB_7_6_01, FN_SEL_AB_7_6_10, 0,
1651 /* 5 - 4 */
1652 FN_SEL_AB_5_4_00, FN_SEL_AB_5_4_01,
1653 FN_SEL_AB_5_4_10, FN_SEL_AB_5_4_11,
1654 /* 3 - 2 */
1655 FN_SEL_AB_3_2_00, FN_SEL_AB_3_2_01,
1656 FN_SEL_AB_3_2_10, FN_SEL_AB_3_2_11,
1657 /* 1 - 0 */
1658 FN_SEL_AB_1_0_00, 0, FN_SEL_AB_1_0_10, 0,
1659 }
1660 },
1661 { PINMUX_CFG_REG_VAR("CHG_PINSEL_USI", 0xe0140298, 32,
1662 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1663 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2) {
1664 /* 31 - 10 */
1665 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1666 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1667 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1668 /* 9 - 8 */
1669 FN_SEL_USI_9_8_00, FN_SEL_USI_9_8_01, 0, 0,
1670 /* 7 - 6 */
1671 FN_SEL_USI_7_6_00, FN_SEL_USI_7_6_01, 0, 0,
1672 /* 5 - 4 */
1673 FN_SEL_USI_5_4_00, FN_SEL_USI_5_4_01, 0, 0,
1674 /* 3 - 2 */
1675 FN_SEL_USI_3_2_00, FN_SEL_USI_3_2_01, 0, 0,
1676 /* 1 - 0 */
1677 FN_SEL_USI_1_0_00, FN_SEL_USI_1_0_01, 0, 0,
1678 }
1679 },
1680 { PINMUX_CFG_REG_VAR("CHG_PINSEL_HSI", 0xe01402a8, 32,
1681 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1682 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2) {
1683 /* 31 - 2 */
1684 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1685 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1686 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1687 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1688 /* 1 - 0 */
1689 FN_SEL_HSI_1_0_00, FN_SEL_HSI_1_0_01, 0, 0,
1690 }
1691 },
1692 { },
1693};
1694
1695const struct sh_pfc_soc_info emev2_pinmux_info = {
1696 .name = "emev2_pfc",
1697
1698 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1699
1700 .pins = pinmux_pins,
1701 .nr_pins = ARRAY_SIZE(pinmux_pins),
1702 .groups = pinmux_groups,
1703 .nr_groups = ARRAY_SIZE(pinmux_groups),
1704 .functions = pinmux_functions,
1705 .nr_functions = ARRAY_SIZE(pinmux_functions),
1706
1707 .cfg_regs = pinmux_config_regs,
1708
1709 .gpio_data = pinmux_data,
1710 .gpio_data_size = ARRAY_SIZE(pinmux_data),
1711};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index 9a179c94b4dc..80c1843bb6ad 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -2241,6 +2241,13 @@ static const unsigned int intc_irq3_pins[] = {
2241static const unsigned int intc_irq3_mux[] = { 2241static const unsigned int intc_irq3_mux[] = {
2242 IRQ3_MARK, 2242 IRQ3_MARK,
2243}; 2243};
2244/* - MLB+ ------------------------------------------------------------------- */
2245static const unsigned int mlb_3pin_pins[] = {
2246 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2247};
2248static const unsigned int mlb_3pin_mux[] = {
2249 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2250};
2244/* - MMCIF0 ----------------------------------------------------------------- */ 2251/* - MMCIF0 ----------------------------------------------------------------- */
2245static const unsigned int mmc0_data1_pins[] = { 2252static const unsigned int mmc0_data1_pins[] = {
2246 /* D[0] */ 2253 /* D[0] */
@@ -3873,6 +3880,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
3873 SH_PFC_PIN_GROUP(intc_irq1), 3880 SH_PFC_PIN_GROUP(intc_irq1),
3874 SH_PFC_PIN_GROUP(intc_irq2), 3881 SH_PFC_PIN_GROUP(intc_irq2),
3875 SH_PFC_PIN_GROUP(intc_irq3), 3882 SH_PFC_PIN_GROUP(intc_irq3),
3883 SH_PFC_PIN_GROUP(mlb_3pin),
3876 SH_PFC_PIN_GROUP(mmc0_data1), 3884 SH_PFC_PIN_GROUP(mmc0_data1),
3877 SH_PFC_PIN_GROUP(mmc0_data4), 3885 SH_PFC_PIN_GROUP(mmc0_data4),
3878 SH_PFC_PIN_GROUP(mmc0_data8), 3886 SH_PFC_PIN_GROUP(mmc0_data8),
@@ -4198,6 +4206,10 @@ static const char * const intc_groups[] = {
4198 "intc_irq3", 4206 "intc_irq3",
4199}; 4207};
4200 4208
4209static const char * const mlb_groups[] = {
4210 "mlb_3pin",
4211};
4212
4201static const char * const mmc0_groups[] = { 4213static const char * const mmc0_groups[] = {
4202 "mmc0_data1", 4214 "mmc0_data1",
4203 "mmc0_data4", 4215 "mmc0_data4",
@@ -4511,6 +4523,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
4511 SH_PFC_FUNCTION(iic2), 4523 SH_PFC_FUNCTION(iic2),
4512 SH_PFC_FUNCTION(iic3), 4524 SH_PFC_FUNCTION(iic3),
4513 SH_PFC_FUNCTION(intc), 4525 SH_PFC_FUNCTION(intc),
4526 SH_PFC_FUNCTION(mlb),
4514 SH_PFC_FUNCTION(mmc0), 4527 SH_PFC_FUNCTION(mmc0),
4515 SH_PFC_FUNCTION(mmc1), 4528 SH_PFC_FUNCTION(mmc1),
4516 SH_PFC_FUNCTION(msiof0), 4529 SH_PFC_FUNCTION(msiof0),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
index c6e5deba238e..fdd2c8729791 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
@@ -378,7 +378,7 @@ enum {
378 /* IPSR16 */ 378 /* IPSR16 */
379 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C, 379 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C,
380 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C, 380 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C,
381 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C, 381 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
382 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B, 382 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
383 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B, 383 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
384 384
@@ -764,7 +764,7 @@ enum {
764 GLO_SDATA_C_MARK, VI1_DATA6_C_MARK, 764 GLO_SDATA_C_MARK, VI1_DATA6_C_MARK,
765 HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK, 765 HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK,
766 GLO_SS_C_MARK, VI1_DATA7_C_MARK, 766 GLO_SS_C_MARK, VI1_DATA7_C_MARK,
767 HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CK_MARK, GLO_RFON_C_MARK, 767 HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CLK_MARK, GLO_RFON_C_MARK,
768 HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK, 768 HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK,
769 HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK, 769 HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK,
770 PINMUX_MARK_END, 770 PINMUX_MARK_END,
@@ -1664,7 +1664,7 @@ static const u16 pinmux_data[] = {
1664 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, VI1_DATA7_C, SEL_VI1_2), 1664 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
1665 PINMUX_IPSR_MODSEL_DATA(IP16_7_6, HSCK1, SEL_HSCIF1_0), 1665 PINMUX_IPSR_MODSEL_DATA(IP16_7_6, HSCK1, SEL_HSCIF1_0),
1666 PINMUX_IPSR_MODSEL_DATA(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0), 1666 PINMUX_IPSR_MODSEL_DATA(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
1667 PINMUX_IPSR_DATA(IP16_7_6, MLB_CK), 1667 PINMUX_IPSR_DATA(IP16_7_6, MLB_CLK),
1668 PINMUX_IPSR_MODSEL_DATA(IP16_7_6, GLO_RFON_C, SEL_GPS_2), 1668 PINMUX_IPSR_MODSEL_DATA(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
1669 PINMUX_IPSR_MODSEL_DATA(IP16_9_8, HCTS1_N, SEL_HSCIF1_0), 1669 PINMUX_IPSR_MODSEL_DATA(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
1670 PINMUX_IPSR_DATA(IP16_9_8, SCIFB1_CTS_N), 1670 PINMUX_IPSR_DATA(IP16_9_8, SCIFB1_CTS_N),
@@ -2391,6 +2391,13 @@ static const unsigned int intc_irq3_pins[] = {
2391static const unsigned int intc_irq3_mux[] = { 2391static const unsigned int intc_irq3_mux[] = {
2392 IRQ3_MARK, 2392 IRQ3_MARK,
2393}; 2393};
2394/* - MLB+ ------------------------------------------------------------------- */
2395static const unsigned int mlb_3pin_pins[] = {
2396 RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
2397};
2398static const unsigned int mlb_3pin_mux[] = {
2399 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2400};
2394/* - MMCIF ------------------------------------------------------------------ */ 2401/* - MMCIF ------------------------------------------------------------------ */
2395static const unsigned int mmc_data1_pins[] = { 2402static const unsigned int mmc_data1_pins[] = {
2396 /* D[0] */ 2403 /* D[0] */
@@ -4267,6 +4274,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
4267 SH_PFC_PIN_GROUP(intc_irq1), 4274 SH_PFC_PIN_GROUP(intc_irq1),
4268 SH_PFC_PIN_GROUP(intc_irq2), 4275 SH_PFC_PIN_GROUP(intc_irq2),
4269 SH_PFC_PIN_GROUP(intc_irq3), 4276 SH_PFC_PIN_GROUP(intc_irq3),
4277 SH_PFC_PIN_GROUP(mlb_3pin),
4270 SH_PFC_PIN_GROUP(mmc_data1), 4278 SH_PFC_PIN_GROUP(mmc_data1),
4271 SH_PFC_PIN_GROUP(mmc_data4), 4279 SH_PFC_PIN_GROUP(mmc_data4),
4272 SH_PFC_PIN_GROUP(mmc_data8), 4280 SH_PFC_PIN_GROUP(mmc_data8),
@@ -4648,6 +4656,10 @@ static const char * const intc_groups[] = {
4648 "intc_irq3", 4656 "intc_irq3",
4649}; 4657};
4650 4658
4659static const char * const mlb_groups[] = {
4660 "mlb_3pin",
4661};
4662
4651static const char * const mmc_groups[] = { 4663static const char * const mmc_groups[] = {
4652 "mmc_data1", 4664 "mmc_data1",
4653 "mmc_data4", 4665 "mmc_data4",
@@ -4972,6 +4984,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
4972 SH_PFC_FUNCTION(i2c7), 4984 SH_PFC_FUNCTION(i2c7),
4973 SH_PFC_FUNCTION(i2c8), 4985 SH_PFC_FUNCTION(i2c8),
4974 SH_PFC_FUNCTION(intc), 4986 SH_PFC_FUNCTION(intc),
4987 SH_PFC_FUNCTION(mlb),
4975 SH_PFC_FUNCTION(mmc), 4988 SH_PFC_FUNCTION(mmc),
4976 SH_PFC_FUNCTION(msiof0), 4989 SH_PFC_FUNCTION(msiof0),
4977 SH_PFC_FUNCTION(msiof1), 4990 SH_PFC_FUNCTION(msiof1),
@@ -5974,7 +5987,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5974 /* IP16_9_8 [2] */ 5987 /* IP16_9_8 [2] */
5975 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B, 5988 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
5976 /* IP16_7_6 [2] */ 5989 /* IP16_7_6 [2] */
5977 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C, 5990 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
5978 /* IP16_5_3 [3] */ 5991 /* IP16_5_3 [3] */
5979 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, 5992 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B,
5980 FN_GLO_SS_C, FN_VI1_DATA7_C, 5993 FN_GLO_SS_C, FN_VI1_DATA7_C,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
deleted file mode 100644
index 8211f66a2f68..000000000000
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ /dev/null
@@ -1,2645 +0,0 @@
1/*
2 * sh7372 processor support - PFC hardware block
3 *
4 * Copyright (C) 2010 Kuninori Morimoto <morimoto.kuninori@renesas.com>
5 *
6 * Based on
7 * sh7367 processor support - PFC hardware block
8 * Copyright (C) 2010 Magnus Damm
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23#include <linux/io.h>
24#include <linux/kernel.h>
25#include <linux/pinctrl/pinconf-generic.h>
26#include <linux/sh_intc.h>
27
28#include "core.h"
29#include "sh_pfc.h"
30
31#define CPU_ALL_PORT(fn, pfx, sfx) \
32 PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \
33 PORT_10(100, fn, pfx##10, sfx), PORT_10(110, fn, pfx##11, sfx), \
34 PORT_10(120, fn, pfx##12, sfx), PORT_10(130, fn, pfx##13, sfx), \
35 PORT_10(140, fn, pfx##14, sfx), PORT_10(150, fn, pfx##15, sfx), \
36 PORT_10(160, fn, pfx##16, sfx), PORT_10(170, fn, pfx##17, sfx), \
37 PORT_10(180, fn, pfx##18, sfx), PORT_1(190, fn, pfx##190, sfx)
38
39#define IRQC_PIN_MUX(irq, pin) \
40static const unsigned int intc_irq##irq##_pins[] = { \
41 pin, \
42}; \
43static const unsigned int intc_irq##irq##_mux[] = { \
44 IRQ##irq##_MARK, \
45}
46
47#define IRQC_PINS_MUX(irq, pin0, pin1) \
48static const unsigned int intc_irq##irq##_0_pins[] = { \
49 pin0, \
50}; \
51static const unsigned int intc_irq##irq##_0_mux[] = { \
52 IRQ##irq##_##pin0##_MARK, \
53}; \
54static const unsigned int intc_irq##irq##_1_pins[] = { \
55 pin1, \
56}; \
57static const unsigned int intc_irq##irq##_1_mux[] = { \
58 IRQ##irq##_##pin1##_MARK, \
59}
60
61enum {
62 PINMUX_RESERVED = 0,
63
64 /* PORT0_DATA -> PORT190_DATA */
65 PINMUX_DATA_BEGIN,
66 PORT_ALL(DATA),
67 PINMUX_DATA_END,
68
69 /* PORT0_IN -> PORT190_IN */
70 PINMUX_INPUT_BEGIN,
71 PORT_ALL(IN),
72 PINMUX_INPUT_END,
73
74 /* PORT0_OUT -> PORT190_OUT */
75 PINMUX_OUTPUT_BEGIN,
76 PORT_ALL(OUT),
77 PINMUX_OUTPUT_END,
78
79 PINMUX_FUNCTION_BEGIN,
80 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT190_FN_IN */
81 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT190_FN_OUT */
82 PORT_ALL(FN0), /* PORT0_FN0 -> PORT190_FN0 */
83 PORT_ALL(FN1), /* PORT0_FN1 -> PORT190_FN1 */
84 PORT_ALL(FN2), /* PORT0_FN2 -> PORT190_FN2 */
85 PORT_ALL(FN3), /* PORT0_FN3 -> PORT190_FN3 */
86 PORT_ALL(FN4), /* PORT0_FN4 -> PORT190_FN4 */
87 PORT_ALL(FN5), /* PORT0_FN5 -> PORT190_FN5 */
88 PORT_ALL(FN6), /* PORT0_FN6 -> PORT190_FN6 */
89 PORT_ALL(FN7), /* PORT0_FN7 -> PORT190_FN7 */
90
91 MSEL1CR_31_0, MSEL1CR_31_1,
92 MSEL1CR_30_0, MSEL1CR_30_1,
93 MSEL1CR_29_0, MSEL1CR_29_1,
94 MSEL1CR_28_0, MSEL1CR_28_1,
95 MSEL1CR_27_0, MSEL1CR_27_1,
96 MSEL1CR_26_0, MSEL1CR_26_1,
97 MSEL1CR_16_0, MSEL1CR_16_1,
98 MSEL1CR_15_0, MSEL1CR_15_1,
99 MSEL1CR_14_0, MSEL1CR_14_1,
100 MSEL1CR_13_0, MSEL1CR_13_1,
101 MSEL1CR_12_0, MSEL1CR_12_1,
102 MSEL1CR_9_0, MSEL1CR_9_1,
103 MSEL1CR_8_0, MSEL1CR_8_1,
104 MSEL1CR_7_0, MSEL1CR_7_1,
105 MSEL1CR_6_0, MSEL1CR_6_1,
106 MSEL1CR_4_0, MSEL1CR_4_1,
107 MSEL1CR_3_0, MSEL1CR_3_1,
108 MSEL1CR_2_0, MSEL1CR_2_1,
109 MSEL1CR_0_0, MSEL1CR_0_1,
110
111 MSEL3CR_27_0, MSEL3CR_27_1,
112 MSEL3CR_26_0, MSEL3CR_26_1,
113 MSEL3CR_21_0, MSEL3CR_21_1,
114 MSEL3CR_20_0, MSEL3CR_20_1,
115 MSEL3CR_15_0, MSEL3CR_15_1,
116 MSEL3CR_9_0, MSEL3CR_9_1,
117 MSEL3CR_6_0, MSEL3CR_6_1,
118
119 MSEL4CR_19_0, MSEL4CR_19_1,
120 MSEL4CR_18_0, MSEL4CR_18_1,
121 MSEL4CR_17_0, MSEL4CR_17_1,
122 MSEL4CR_16_0, MSEL4CR_16_1,
123 MSEL4CR_15_0, MSEL4CR_15_1,
124 MSEL4CR_14_0, MSEL4CR_14_1,
125 MSEL4CR_10_0, MSEL4CR_10_1,
126 MSEL4CR_6_0, MSEL4CR_6_1,
127 MSEL4CR_4_0, MSEL4CR_4_1,
128 MSEL4CR_1_0, MSEL4CR_1_1,
129 PINMUX_FUNCTION_END,
130
131 PINMUX_MARK_BEGIN,
132
133 /* IRQ */
134 IRQ0_6_MARK, IRQ0_162_MARK, IRQ1_MARK, IRQ2_4_MARK,
135 IRQ2_5_MARK, IRQ3_8_MARK, IRQ3_16_MARK, IRQ4_17_MARK,
136 IRQ4_163_MARK, IRQ5_MARK, IRQ6_39_MARK, IRQ6_164_MARK,
137 IRQ7_40_MARK, IRQ7_167_MARK, IRQ8_41_MARK, IRQ8_168_MARK,
138 IRQ9_42_MARK, IRQ9_169_MARK, IRQ10_MARK, IRQ11_MARK,
139 IRQ12_80_MARK, IRQ12_137_MARK, IRQ13_81_MARK, IRQ13_145_MARK,
140 IRQ14_82_MARK, IRQ14_146_MARK, IRQ15_83_MARK, IRQ15_147_MARK,
141 IRQ16_84_MARK, IRQ16_170_MARK, IRQ17_MARK, IRQ18_MARK,
142 IRQ19_MARK, IRQ20_MARK, IRQ21_MARK, IRQ22_MARK,
143 IRQ23_MARK, IRQ24_MARK, IRQ25_MARK, IRQ26_121_MARK,
144 IRQ26_172_MARK, IRQ27_122_MARK, IRQ27_180_MARK, IRQ28_123_MARK,
145 IRQ28_181_MARK, IRQ29_129_MARK, IRQ29_182_MARK, IRQ30_130_MARK,
146 IRQ30_183_MARK, IRQ31_138_MARK, IRQ31_184_MARK,
147
148 /* MSIOF0 */
149 MSIOF0_TSYNC_MARK, MSIOF0_TSCK_MARK, MSIOF0_RXD_MARK,
150 MSIOF0_RSCK_MARK, MSIOF0_RSYNC_MARK, MSIOF0_MCK0_MARK,
151 MSIOF0_MCK1_MARK, MSIOF0_SS1_MARK, MSIOF0_SS2_MARK,
152 MSIOF0_TXD_MARK,
153
154 /* MSIOF1 */
155 MSIOF1_TSCK_39_MARK, MSIOF1_TSYNC_40_MARK,
156 MSIOF1_TSCK_88_MARK, MSIOF1_TSYNC_89_MARK,
157 MSIOF1_TXD_41_MARK, MSIOF1_RXD_42_MARK,
158 MSIOF1_TXD_90_MARK, MSIOF1_RXD_91_MARK,
159 MSIOF1_SS1_43_MARK, MSIOF1_SS2_44_MARK,
160 MSIOF1_SS1_92_MARK, MSIOF1_SS2_93_MARK,
161 MSIOF1_RSCK_MARK, MSIOF1_RSYNC_MARK,
162 MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK,
163
164 /* MSIOF2 */
165 MSIOF2_RSCK_MARK, MSIOF2_RSYNC_MARK, MSIOF2_MCK0_MARK,
166 MSIOF2_MCK1_MARK, MSIOF2_SS1_MARK, MSIOF2_SS2_MARK,
167 MSIOF2_TSYNC_MARK, MSIOF2_TSCK_MARK, MSIOF2_RXD_MARK,
168 MSIOF2_TXD_MARK,
169
170 /* BBIF1 */
171 BBIF1_RXD_MARK, BBIF1_TSYNC_MARK, BBIF1_TSCK_MARK,
172 BBIF1_TXD_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK,
173 BBIF1_FLOW_MARK, BB_RX_FLOW_N_MARK,
174
175 /* BBIF2 */
176 BBIF2_TSCK1_MARK, BBIF2_TSYNC1_MARK,
177 BBIF2_TXD1_MARK, BBIF2_RXD_MARK,
178
179 /* FSI */
180 FSIACK_MARK, FSIBCK_MARK, FSIAILR_MARK, FSIAIBT_MARK,
181 FSIAISLD_MARK, FSIAOMC_MARK, FSIAOLR_MARK, FSIAOBT_MARK,
182 FSIAOSLD_MARK, FSIASPDIF_11_MARK, FSIASPDIF_15_MARK,
183
184 /* FMSI */
185 FMSOCK_MARK, FMSOOLR_MARK, FMSIOLR_MARK, FMSOOBT_MARK,
186 FMSIOBT_MARK, FMSOSLD_MARK, FMSOILR_MARK, FMSIILR_MARK,
187 FMSOIBT_MARK, FMSIIBT_MARK, FMSISLD_MARK, FMSICK_MARK,
188
189 /* SCIFA0 */
190 SCIFA0_TXD_MARK, SCIFA0_RXD_MARK, SCIFA0_SCK_MARK,
191 SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
192
193 /* SCIFA1 */
194 SCIFA1_TXD_MARK, SCIFA1_RXD_MARK, SCIFA1_SCK_MARK,
195 SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
196
197 /* SCIFA2 */
198 SCIFA2_CTS1_MARK, SCIFA2_RTS1_MARK, SCIFA2_TXD1_MARK,
199 SCIFA2_RXD1_MARK, SCIFA2_SCK1_MARK,
200
201 /* SCIFA3 */
202 SCIFA3_CTS_43_MARK, SCIFA3_CTS_140_MARK, SCIFA3_RTS_44_MARK,
203 SCIFA3_RTS_141_MARK, SCIFA3_SCK_MARK, SCIFA3_TXD_MARK,
204 SCIFA3_RXD_MARK,
205
206 /* SCIFA4 */
207 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
208
209 /* SCIFA5 */
210 SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
211
212 /* SCIFB */
213 SCIFB_SCK_MARK, SCIFB_RTS_MARK, SCIFB_CTS_MARK,
214 SCIFB_TXD_MARK, SCIFB_RXD_MARK,
215
216 /* CEU */
217 VIO_HD_MARK, VIO_CKO1_MARK, VIO_CKO2_MARK, VIO_VD_MARK,
218 VIO_CLK_MARK, VIO_FIELD_MARK, VIO_CKO_MARK,
219 VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK, VIO_D3_MARK,
220 VIO_D4_MARK, VIO_D5_MARK, VIO_D6_MARK, VIO_D7_MARK,
221 VIO_D8_MARK, VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK,
222 VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK, VIO_D15_MARK,
223
224 /* USB0 */
225 IDIN_0_MARK, EXTLP_0_MARK, OVCN2_0_MARK, PWEN_0_MARK,
226 OVCN_0_MARK, VBUS0_0_MARK,
227
228 /* USB1 */
229 IDIN_1_18_MARK, IDIN_1_113_MARK,
230 PWEN_1_115_MARK, PWEN_1_138_MARK,
231 OVCN_1_114_MARK, OVCN_1_162_MARK,
232 EXTLP_1_MARK, OVCN2_1_MARK,
233 VBUS0_1_MARK,
234
235 /* GPIO */
236 GPI0_MARK, GPI1_MARK, GPO0_MARK, GPO1_MARK,
237
238 /* BSC */
239 BS_MARK, WE1_MARK,
240 CKO_MARK, WAIT_MARK, RDWR_MARK,
241
242 A0_MARK, A1_MARK, A2_MARK, A3_MARK,
243 A6_MARK, A7_MARK, A8_MARK, A9_MARK,
244 A10_MARK, A11_MARK, A12_MARK, A13_MARK,
245 A14_MARK, A15_MARK, A16_MARK, A17_MARK,
246 A18_MARK, A19_MARK, A20_MARK, A21_MARK,
247 A22_MARK, A23_MARK, A24_MARK, A25_MARK,
248 A26_MARK,
249
250 CS0_MARK, CS2_MARK, CS4_MARK,
251 CS5A_MARK, CS5B_MARK, CS6A_MARK,
252
253 /* BSC/FLCTL */
254 RD_FSC_MARK, WE0_FWE_MARK, A4_FOE_MARK, A5_FCDE_MARK,
255 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
256 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
257 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
258 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
259
260 /* MMCIF(1) */
261 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
262 MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
263 MMCCMD0_MARK, MMCCLK0_MARK,
264
265 /* MMCIF(2) */
266 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
267 MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
268 MMCCLK1_MARK, MMCCMD1_MARK,
269
270 /* SPU2 */
271 VINT_I_MARK,
272
273 /* FLCTL */
274 FCE1_MARK, FCE0_MARK, FRB_MARK,
275
276 /* HSI */
277 GP_RX_FLAG_MARK, GP_RX_DATA_MARK, GP_TX_READY_MARK,
278 GP_RX_WAKE_MARK, MP_TX_FLAG_MARK, MP_TX_DATA_MARK,
279 MP_RX_READY_MARK, MP_TX_WAKE_MARK,
280
281 /* MFI */
282 MFIv6_MARK,
283 MFIv4_MARK,
284
285 MEMC_CS0_MARK, MEMC_BUSCLK_MEMC_A0_MARK,
286 MEMC_CS1_MEMC_A1_MARK, MEMC_ADV_MEMC_DREQ0_MARK,
287 MEMC_WAIT_MEMC_DREQ1_MARK, MEMC_NOE_MARK,
288 MEMC_NWE_MARK, MEMC_INT_MARK,
289
290 MEMC_AD0_MARK, MEMC_AD1_MARK, MEMC_AD2_MARK,
291 MEMC_AD3_MARK, MEMC_AD4_MARK, MEMC_AD5_MARK,
292 MEMC_AD6_MARK, MEMC_AD7_MARK, MEMC_AD8_MARK,
293 MEMC_AD9_MARK, MEMC_AD10_MARK, MEMC_AD11_MARK,
294 MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK,
295 MEMC_AD15_MARK,
296
297 /* SIM */
298 SIM_RST_MARK, SIM_CLK_MARK, SIM_D_MARK,
299
300 /* TPU */
301 TPU0TO0_MARK, TPU0TO1_MARK,
302 TPU0TO2_93_MARK, TPU0TO2_99_MARK,
303 TPU0TO3_MARK,
304
305 /* I2C2 */
306 I2C_SCL2_MARK, I2C_SDA2_MARK,
307
308 /* I2C3(1) */
309 I2C_SCL3_MARK, I2C_SDA3_MARK,
310
311 /* I2C3(2) */
312 I2C_SCL3S_MARK, I2C_SDA3S_MARK,
313
314 /* I2C4(2) */
315 I2C_SCL4_MARK, I2C_SDA4_MARK,
316
317 /* I2C4(2) */
318 I2C_SCL4S_MARK, I2C_SDA4S_MARK,
319
320 /* KEYSC */
321 KEYOUT0_MARK, KEYIN0_121_MARK, KEYIN0_136_MARK,
322 KEYOUT1_MARK, KEYIN1_122_MARK, KEYIN1_135_MARK,
323 KEYOUT2_MARK, KEYIN2_123_MARK, KEYIN2_134_MARK,
324 KEYOUT3_MARK, KEYIN3_124_MARK, KEYIN3_133_MARK,
325 KEYOUT4_MARK, KEYIN4_MARK,
326 KEYOUT5_MARK, KEYIN5_MARK,
327 KEYOUT6_MARK, KEYIN6_MARK,
328 KEYOUT7_MARK, KEYIN7_MARK,
329
330 /* LCDC */
331 LCDC0_SELECT_MARK,
332 LCDC1_SELECT_MARK,
333 LCDHSYN_MARK, LCDCS_MARK, LCDVSYN_MARK, LCDDCK_MARK,
334 LCDWR_MARK, LCDRD_MARK, LCDDISP_MARK, LCDRS_MARK,
335 LCDLCLK_MARK, LCDDON_MARK,
336
337 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
338 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
339 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
340 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
341 LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
342 LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
343
344 /* IRDA */
345 IRDA_OUT_MARK, IRDA_IN_MARK, IRDA_FIRSEL_MARK,
346 IROUT_139_MARK, IROUT_140_MARK,
347
348 /* TSIF1 */
349 TS0_1SELECT_MARK,
350 TS0_2SELECT_MARK,
351 TS1_1SELECT_MARK,
352 TS1_2SELECT_MARK,
353
354 TS_SPSYNC1_MARK, TS_SDAT1_MARK,
355 TS_SDEN1_MARK, TS_SCK1_MARK,
356
357 /* TSIF2 */
358 TS_SPSYNC2_MARK, TS_SDAT2_MARK,
359 TS_SDEN2_MARK, TS_SCK2_MARK,
360
361 /* HDMI */
362 HDMI_HPD_MARK, HDMI_CEC_MARK,
363
364 /* SDHI0 */
365 SDHICLK0_MARK, SDHICD0_MARK,
366 SDHICMD0_MARK, SDHIWP0_MARK,
367 SDHID0_0_MARK, SDHID0_1_MARK,
368 SDHID0_2_MARK, SDHID0_3_MARK,
369
370 /* SDHI1 */
371 SDHICLK1_MARK, SDHICMD1_MARK, SDHID1_0_MARK,
372 SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
373
374 /* SDHI2 */
375 SDHICLK2_MARK, SDHICMD2_MARK, SDHID2_0_MARK,
376 SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
377
378 /* SDENC */
379 SDENC_CPG_MARK,
380 SDENC_DV_CLKI_MARK,
381
382 PINMUX_MARK_END,
383};
384
385static const u16 pinmux_data[] = {
386 PINMUX_DATA_ALL(),
387
388 /* IRQ */
389 PINMUX_DATA(IRQ0_6_MARK, PORT6_FN0, MSEL1CR_0_0),
390 PINMUX_DATA(IRQ0_162_MARK, PORT162_FN0, MSEL1CR_0_1),
391 PINMUX_DATA(IRQ1_MARK, PORT12_FN0),
392 PINMUX_DATA(IRQ2_4_MARK, PORT4_FN0, MSEL1CR_2_0),
393 PINMUX_DATA(IRQ2_5_MARK, PORT5_FN0, MSEL1CR_2_1),
394 PINMUX_DATA(IRQ3_8_MARK, PORT8_FN0, MSEL1CR_3_0),
395 PINMUX_DATA(IRQ3_16_MARK, PORT16_FN0, MSEL1CR_3_1),
396 PINMUX_DATA(IRQ4_17_MARK, PORT17_FN0, MSEL1CR_4_0),
397 PINMUX_DATA(IRQ4_163_MARK, PORT163_FN0, MSEL1CR_4_1),
398 PINMUX_DATA(IRQ5_MARK, PORT18_FN0),
399 PINMUX_DATA(IRQ6_39_MARK, PORT39_FN0, MSEL1CR_6_0),
400 PINMUX_DATA(IRQ6_164_MARK, PORT164_FN0, MSEL1CR_6_1),
401 PINMUX_DATA(IRQ7_40_MARK, PORT40_FN0, MSEL1CR_7_1),
402 PINMUX_DATA(IRQ7_167_MARK, PORT167_FN0, MSEL1CR_7_0),
403 PINMUX_DATA(IRQ8_41_MARK, PORT41_FN0, MSEL1CR_8_1),
404 PINMUX_DATA(IRQ8_168_MARK, PORT168_FN0, MSEL1CR_8_0),
405 PINMUX_DATA(IRQ9_42_MARK, PORT42_FN0, MSEL1CR_9_0),
406 PINMUX_DATA(IRQ9_169_MARK, PORT169_FN0, MSEL1CR_9_1),
407 PINMUX_DATA(IRQ10_MARK, PORT65_FN0, MSEL1CR_9_1),
408 PINMUX_DATA(IRQ11_MARK, PORT67_FN0),
409 PINMUX_DATA(IRQ12_80_MARK, PORT80_FN0, MSEL1CR_12_0),
410 PINMUX_DATA(IRQ12_137_MARK, PORT137_FN0, MSEL1CR_12_1),
411 PINMUX_DATA(IRQ13_81_MARK, PORT81_FN0, MSEL1CR_13_0),
412 PINMUX_DATA(IRQ13_145_MARK, PORT145_FN0, MSEL1CR_13_1),
413 PINMUX_DATA(IRQ14_82_MARK, PORT82_FN0, MSEL1CR_14_0),
414 PINMUX_DATA(IRQ14_146_MARK, PORT146_FN0, MSEL1CR_14_1),
415 PINMUX_DATA(IRQ15_83_MARK, PORT83_FN0, MSEL1CR_15_0),
416 PINMUX_DATA(IRQ15_147_MARK, PORT147_FN0, MSEL1CR_15_1),
417 PINMUX_DATA(IRQ16_84_MARK, PORT84_FN0, MSEL1CR_16_0),
418 PINMUX_DATA(IRQ16_170_MARK, PORT170_FN0, MSEL1CR_16_1),
419 PINMUX_DATA(IRQ17_MARK, PORT85_FN0),
420 PINMUX_DATA(IRQ18_MARK, PORT86_FN0),
421 PINMUX_DATA(IRQ19_MARK, PORT87_FN0),
422 PINMUX_DATA(IRQ20_MARK, PORT92_FN0),
423 PINMUX_DATA(IRQ21_MARK, PORT93_FN0),
424 PINMUX_DATA(IRQ22_MARK, PORT94_FN0),
425 PINMUX_DATA(IRQ23_MARK, PORT95_FN0),
426 PINMUX_DATA(IRQ24_MARK, PORT112_FN0),
427 PINMUX_DATA(IRQ25_MARK, PORT119_FN0),
428 PINMUX_DATA(IRQ26_121_MARK, PORT121_FN0, MSEL1CR_26_1),
429 PINMUX_DATA(IRQ26_172_MARK, PORT172_FN0, MSEL1CR_26_0),
430 PINMUX_DATA(IRQ27_122_MARK, PORT122_FN0, MSEL1CR_27_1),
431 PINMUX_DATA(IRQ27_180_MARK, PORT180_FN0, MSEL1CR_27_0),
432 PINMUX_DATA(IRQ28_123_MARK, PORT123_FN0, MSEL1CR_28_1),
433 PINMUX_DATA(IRQ28_181_MARK, PORT181_FN0, MSEL1CR_28_0),
434 PINMUX_DATA(IRQ29_129_MARK, PORT129_FN0, MSEL1CR_29_1),
435 PINMUX_DATA(IRQ29_182_MARK, PORT182_FN0, MSEL1CR_29_0),
436 PINMUX_DATA(IRQ30_130_MARK, PORT130_FN0, MSEL1CR_30_1),
437 PINMUX_DATA(IRQ30_183_MARK, PORT183_FN0, MSEL1CR_30_0),
438 PINMUX_DATA(IRQ31_138_MARK, PORT138_FN0, MSEL1CR_31_1),
439 PINMUX_DATA(IRQ31_184_MARK, PORT184_FN0, MSEL1CR_31_0),
440
441 /* Function 1 */
442 PINMUX_DATA(BBIF2_TSCK1_MARK, PORT0_FN1),
443 PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT1_FN1),
444 PINMUX_DATA(BBIF2_TXD1_MARK, PORT2_FN1),
445 PINMUX_DATA(BBIF2_RXD_MARK, PORT3_FN1),
446 PINMUX_DATA(FSIACK_MARK, PORT4_FN1),
447 PINMUX_DATA(FSIAILR_MARK, PORT5_FN1),
448 PINMUX_DATA(FSIAIBT_MARK, PORT6_FN1),
449 PINMUX_DATA(FSIAISLD_MARK, PORT7_FN1),
450 PINMUX_DATA(FSIAOMC_MARK, PORT8_FN1),
451 PINMUX_DATA(FSIAOLR_MARK, PORT9_FN1),
452 PINMUX_DATA(FSIAOBT_MARK, PORT10_FN1),
453 PINMUX_DATA(FSIAOSLD_MARK, PORT11_FN1),
454 PINMUX_DATA(FMSOCK_MARK, PORT12_FN1),
455 PINMUX_DATA(FMSOOLR_MARK, PORT13_FN1),
456 PINMUX_DATA(FMSOOBT_MARK, PORT14_FN1),
457 PINMUX_DATA(FMSOSLD_MARK, PORT15_FN1),
458 PINMUX_DATA(FMSOILR_MARK, PORT16_FN1),
459 PINMUX_DATA(FMSOIBT_MARK, PORT17_FN1),
460 PINMUX_DATA(FMSISLD_MARK, PORT18_FN1),
461 PINMUX_DATA(A0_MARK, PORT19_FN1),
462 PINMUX_DATA(A1_MARK, PORT20_FN1),
463 PINMUX_DATA(A2_MARK, PORT21_FN1),
464 PINMUX_DATA(A3_MARK, PORT22_FN1),
465 PINMUX_DATA(A4_FOE_MARK, PORT23_FN1),
466 PINMUX_DATA(A5_FCDE_MARK, PORT24_FN1),
467 PINMUX_DATA(A6_MARK, PORT25_FN1),
468 PINMUX_DATA(A7_MARK, PORT26_FN1),
469 PINMUX_DATA(A8_MARK, PORT27_FN1),
470 PINMUX_DATA(A9_MARK, PORT28_FN1),
471 PINMUX_DATA(A10_MARK, PORT29_FN1),
472 PINMUX_DATA(A11_MARK, PORT30_FN1),
473 PINMUX_DATA(A12_MARK, PORT31_FN1),
474 PINMUX_DATA(A13_MARK, PORT32_FN1),
475 PINMUX_DATA(A14_MARK, PORT33_FN1),
476 PINMUX_DATA(A15_MARK, PORT34_FN1),
477 PINMUX_DATA(A16_MARK, PORT35_FN1),
478 PINMUX_DATA(A17_MARK, PORT36_FN1),
479 PINMUX_DATA(A18_MARK, PORT37_FN1),
480 PINMUX_DATA(A19_MARK, PORT38_FN1),
481 PINMUX_DATA(A20_MARK, PORT39_FN1),
482 PINMUX_DATA(A21_MARK, PORT40_FN1),
483 PINMUX_DATA(A22_MARK, PORT41_FN1),
484 PINMUX_DATA(A23_MARK, PORT42_FN1),
485 PINMUX_DATA(A24_MARK, PORT43_FN1),
486 PINMUX_DATA(A25_MARK, PORT44_FN1),
487 PINMUX_DATA(A26_MARK, PORT45_FN1),
488 PINMUX_DATA(D0_NAF0_MARK, PORT46_FN1),
489 PINMUX_DATA(D1_NAF1_MARK, PORT47_FN1),
490 PINMUX_DATA(D2_NAF2_MARK, PORT48_FN1),
491 PINMUX_DATA(D3_NAF3_MARK, PORT49_FN1),
492 PINMUX_DATA(D4_NAF4_MARK, PORT50_FN1),
493 PINMUX_DATA(D5_NAF5_MARK, PORT51_FN1),
494 PINMUX_DATA(D6_NAF6_MARK, PORT52_FN1),
495 PINMUX_DATA(D7_NAF7_MARK, PORT53_FN1),
496 PINMUX_DATA(D8_NAF8_MARK, PORT54_FN1),
497 PINMUX_DATA(D9_NAF9_MARK, PORT55_FN1),
498 PINMUX_DATA(D10_NAF10_MARK, PORT56_FN1),
499 PINMUX_DATA(D11_NAF11_MARK, PORT57_FN1),
500 PINMUX_DATA(D12_NAF12_MARK, PORT58_FN1),
501 PINMUX_DATA(D13_NAF13_MARK, PORT59_FN1),
502 PINMUX_DATA(D14_NAF14_MARK, PORT60_FN1),
503 PINMUX_DATA(D15_NAF15_MARK, PORT61_FN1),
504 PINMUX_DATA(CS0_MARK, PORT62_FN1),
505 PINMUX_DATA(CS2_MARK, PORT63_FN1),
506 PINMUX_DATA(CS4_MARK, PORT64_FN1),
507 PINMUX_DATA(CS5A_MARK, PORT65_FN1),
508 PINMUX_DATA(CS5B_MARK, PORT66_FN1),
509 PINMUX_DATA(CS6A_MARK, PORT67_FN1),
510 PINMUX_DATA(FCE0_MARK, PORT68_FN1),
511 PINMUX_DATA(RD_FSC_MARK, PORT69_FN1),
512 PINMUX_DATA(WE0_FWE_MARK, PORT70_FN1),
513 PINMUX_DATA(WE1_MARK, PORT71_FN1),
514 PINMUX_DATA(CKO_MARK, PORT72_FN1),
515 PINMUX_DATA(FRB_MARK, PORT73_FN1),
516 PINMUX_DATA(WAIT_MARK, PORT74_FN1),
517 PINMUX_DATA(RDWR_MARK, PORT75_FN1),
518 PINMUX_DATA(MEMC_AD0_MARK, PORT76_FN1),
519 PINMUX_DATA(MEMC_AD1_MARK, PORT77_FN1),
520 PINMUX_DATA(MEMC_AD2_MARK, PORT78_FN1),
521 PINMUX_DATA(MEMC_AD3_MARK, PORT79_FN1),
522 PINMUX_DATA(MEMC_AD4_MARK, PORT80_FN1),
523 PINMUX_DATA(MEMC_AD5_MARK, PORT81_FN1),
524 PINMUX_DATA(MEMC_AD6_MARK, PORT82_FN1),
525 PINMUX_DATA(MEMC_AD7_MARK, PORT83_FN1),
526 PINMUX_DATA(MEMC_AD8_MARK, PORT84_FN1),
527 PINMUX_DATA(MEMC_AD9_MARK, PORT85_FN1),
528 PINMUX_DATA(MEMC_AD10_MARK, PORT86_FN1),
529 PINMUX_DATA(MEMC_AD11_MARK, PORT87_FN1),
530 PINMUX_DATA(MEMC_AD12_MARK, PORT88_FN1),
531 PINMUX_DATA(MEMC_AD13_MARK, PORT89_FN1),
532 PINMUX_DATA(MEMC_AD14_MARK, PORT90_FN1),
533 PINMUX_DATA(MEMC_AD15_MARK, PORT91_FN1),
534 PINMUX_DATA(MEMC_CS0_MARK, PORT92_FN1),
535 PINMUX_DATA(MEMC_BUSCLK_MEMC_A0_MARK, PORT93_FN1),
536 PINMUX_DATA(MEMC_CS1_MEMC_A1_MARK, PORT94_FN1),
537 PINMUX_DATA(MEMC_ADV_MEMC_DREQ0_MARK, PORT95_FN1),
538 PINMUX_DATA(MEMC_WAIT_MEMC_DREQ1_MARK, PORT96_FN1),
539 PINMUX_DATA(MEMC_NOE_MARK, PORT97_FN1),
540 PINMUX_DATA(MEMC_NWE_MARK, PORT98_FN1),
541 PINMUX_DATA(MEMC_INT_MARK, PORT99_FN1),
542 PINMUX_DATA(VIO_VD_MARK, PORT100_FN1),
543 PINMUX_DATA(VIO_HD_MARK, PORT101_FN1),
544 PINMUX_DATA(VIO_D0_MARK, PORT102_FN1),
545 PINMUX_DATA(VIO_D1_MARK, PORT103_FN1),
546 PINMUX_DATA(VIO_D2_MARK, PORT104_FN1),
547 PINMUX_DATA(VIO_D3_MARK, PORT105_FN1),
548 PINMUX_DATA(VIO_D4_MARK, PORT106_FN1),
549 PINMUX_DATA(VIO_D5_MARK, PORT107_FN1),
550 PINMUX_DATA(VIO_D6_MARK, PORT108_FN1),
551 PINMUX_DATA(VIO_D7_MARK, PORT109_FN1),
552 PINMUX_DATA(VIO_D8_MARK, PORT110_FN1),
553 PINMUX_DATA(VIO_D9_MARK, PORT111_FN1),
554 PINMUX_DATA(VIO_D10_MARK, PORT112_FN1),
555 PINMUX_DATA(VIO_D11_MARK, PORT113_FN1),
556 PINMUX_DATA(VIO_D12_MARK, PORT114_FN1),
557 PINMUX_DATA(VIO_D13_MARK, PORT115_FN1),
558 PINMUX_DATA(VIO_D14_MARK, PORT116_FN1),
559 PINMUX_DATA(VIO_D15_MARK, PORT117_FN1),
560 PINMUX_DATA(VIO_CLK_MARK, PORT118_FN1),
561 PINMUX_DATA(VIO_FIELD_MARK, PORT119_FN1),
562 PINMUX_DATA(VIO_CKO_MARK, PORT120_FN1),
563 PINMUX_DATA(LCDD0_MARK, PORT121_FN1),
564 PINMUX_DATA(LCDD1_MARK, PORT122_FN1),
565 PINMUX_DATA(LCDD2_MARK, PORT123_FN1),
566 PINMUX_DATA(LCDD3_MARK, PORT124_FN1),
567 PINMUX_DATA(LCDD4_MARK, PORT125_FN1),
568 PINMUX_DATA(LCDD5_MARK, PORT126_FN1),
569 PINMUX_DATA(LCDD6_MARK, PORT127_FN1),
570 PINMUX_DATA(LCDD7_MARK, PORT128_FN1),
571 PINMUX_DATA(LCDD8_MARK, PORT129_FN1),
572 PINMUX_DATA(LCDD9_MARK, PORT130_FN1),
573 PINMUX_DATA(LCDD10_MARK, PORT131_FN1),
574 PINMUX_DATA(LCDD11_MARK, PORT132_FN1),
575 PINMUX_DATA(LCDD12_MARK, PORT133_FN1),
576 PINMUX_DATA(LCDD13_MARK, PORT134_FN1),
577 PINMUX_DATA(LCDD14_MARK, PORT135_FN1),
578 PINMUX_DATA(LCDD15_MARK, PORT136_FN1),
579 PINMUX_DATA(LCDD16_MARK, PORT137_FN1),
580 PINMUX_DATA(LCDD17_MARK, PORT138_FN1),
581 PINMUX_DATA(LCDD18_MARK, PORT139_FN1),
582 PINMUX_DATA(LCDD19_MARK, PORT140_FN1),
583 PINMUX_DATA(LCDD20_MARK, PORT141_FN1),
584 PINMUX_DATA(LCDD21_MARK, PORT142_FN1),
585 PINMUX_DATA(LCDD22_MARK, PORT143_FN1),
586 PINMUX_DATA(LCDD23_MARK, PORT144_FN1),
587 PINMUX_DATA(LCDHSYN_MARK, PORT145_FN1),
588 PINMUX_DATA(LCDVSYN_MARK, PORT146_FN1),
589 PINMUX_DATA(LCDDCK_MARK, PORT147_FN1),
590 PINMUX_DATA(LCDRD_MARK, PORT148_FN1),
591 PINMUX_DATA(LCDDISP_MARK, PORT149_FN1),
592 PINMUX_DATA(LCDLCLK_MARK, PORT150_FN1),
593 PINMUX_DATA(LCDDON_MARK, PORT151_FN1),
594 PINMUX_DATA(SCIFA0_TXD_MARK, PORT152_FN1),
595 PINMUX_DATA(SCIFA0_RXD_MARK, PORT153_FN1),
596 PINMUX_DATA(SCIFA1_TXD_MARK, PORT154_FN1),
597 PINMUX_DATA(SCIFA1_RXD_MARK, PORT155_FN1),
598 PINMUX_DATA(TS_SPSYNC1_MARK, PORT156_FN1),
599 PINMUX_DATA(TS_SDAT1_MARK, PORT157_FN1),
600 PINMUX_DATA(TS_SDEN1_MARK, PORT158_FN1),
601 PINMUX_DATA(TS_SCK1_MARK, PORT159_FN1),
602 PINMUX_DATA(TPU0TO0_MARK, PORT160_FN1),
603 PINMUX_DATA(TPU0TO1_MARK, PORT161_FN1),
604 PINMUX_DATA(SCIFB_SCK_MARK, PORT162_FN1),
605 PINMUX_DATA(SCIFB_RTS_MARK, PORT163_FN1),
606 PINMUX_DATA(SCIFB_CTS_MARK, PORT164_FN1),
607 PINMUX_DATA(SCIFB_TXD_MARK, PORT165_FN1),
608 PINMUX_DATA(SCIFB_RXD_MARK, PORT166_FN1),
609 PINMUX_DATA(VBUS0_0_MARK, PORT167_FN1),
610 PINMUX_DATA(VBUS0_1_MARK, PORT168_FN1),
611 PINMUX_DATA(HDMI_HPD_MARK, PORT169_FN1),
612 PINMUX_DATA(HDMI_CEC_MARK, PORT170_FN1),
613 PINMUX_DATA(SDHICLK0_MARK, PORT171_FN1),
614 PINMUX_DATA(SDHICD0_MARK, PORT172_FN1),
615 PINMUX_DATA(SDHID0_0_MARK, PORT173_FN1),
616 PINMUX_DATA(SDHID0_1_MARK, PORT174_FN1),
617 PINMUX_DATA(SDHID0_2_MARK, PORT175_FN1),
618 PINMUX_DATA(SDHID0_3_MARK, PORT176_FN1),
619 PINMUX_DATA(SDHICMD0_MARK, PORT177_FN1),
620 PINMUX_DATA(SDHIWP0_MARK, PORT178_FN1),
621 PINMUX_DATA(SDHICLK1_MARK, PORT179_FN1),
622 PINMUX_DATA(SDHID1_0_MARK, PORT180_FN1),
623 PINMUX_DATA(SDHID1_1_MARK, PORT181_FN1),
624 PINMUX_DATA(SDHID1_2_MARK, PORT182_FN1),
625 PINMUX_DATA(SDHID1_3_MARK, PORT183_FN1),
626 PINMUX_DATA(SDHICMD1_MARK, PORT184_FN1),
627 PINMUX_DATA(SDHICLK2_MARK, PORT185_FN1),
628 PINMUX_DATA(SDHID2_0_MARK, PORT186_FN1),
629 PINMUX_DATA(SDHID2_1_MARK, PORT187_FN1),
630 PINMUX_DATA(SDHID2_2_MARK, PORT188_FN1),
631 PINMUX_DATA(SDHID2_3_MARK, PORT189_FN1),
632 PINMUX_DATA(SDHICMD2_MARK, PORT190_FN1),
633
634 /* Function 2 */
635 PINMUX_DATA(FSIBCK_MARK, PORT4_FN2),
636 PINMUX_DATA(SCIFA4_RXD_MARK, PORT5_FN2),
637 PINMUX_DATA(SCIFA4_TXD_MARK, PORT6_FN2),
638 PINMUX_DATA(SCIFA5_RXD_MARK, PORT8_FN2),
639 PINMUX_DATA(FSIASPDIF_11_MARK, PORT11_FN2),
640 PINMUX_DATA(SCIFA5_TXD_MARK, PORT12_FN2),
641 PINMUX_DATA(FMSIOLR_MARK, PORT13_FN2),
642 PINMUX_DATA(FMSIOBT_MARK, PORT14_FN2),
643 PINMUX_DATA(FSIASPDIF_15_MARK, PORT15_FN2),
644 PINMUX_DATA(FMSIILR_MARK, PORT16_FN2),
645 PINMUX_DATA(FMSIIBT_MARK, PORT17_FN2),
646 PINMUX_DATA(BS_MARK, PORT19_FN2),
647 PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT36_FN2),
648 PINMUX_DATA(MSIOF0_TSCK_MARK, PORT37_FN2),
649 PINMUX_DATA(MSIOF0_RXD_MARK, PORT38_FN2),
650 PINMUX_DATA(MSIOF0_RSCK_MARK, PORT39_FN2),
651 PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT40_FN2),
652 PINMUX_DATA(MSIOF0_MCK0_MARK, PORT41_FN2),
653 PINMUX_DATA(MSIOF0_MCK1_MARK, PORT42_FN2),
654 PINMUX_DATA(MSIOF0_SS1_MARK, PORT43_FN2),
655 PINMUX_DATA(MSIOF0_SS2_MARK, PORT44_FN2),
656 PINMUX_DATA(MSIOF0_TXD_MARK, PORT45_FN2),
657 PINMUX_DATA(FMSICK_MARK, PORT65_FN2),
658 PINMUX_DATA(FCE1_MARK, PORT66_FN2),
659 PINMUX_DATA(BBIF1_RXD_MARK, PORT76_FN2),
660 PINMUX_DATA(BBIF1_TSYNC_MARK, PORT77_FN2),
661 PINMUX_DATA(BBIF1_TSCK_MARK, PORT78_FN2),
662 PINMUX_DATA(BBIF1_TXD_MARK, PORT79_FN2),
663 PINMUX_DATA(BBIF1_RSCK_MARK, PORT80_FN2),
664 PINMUX_DATA(BBIF1_RSYNC_MARK, PORT81_FN2),
665 PINMUX_DATA(BBIF1_FLOW_MARK, PORT82_FN2),
666 PINMUX_DATA(BB_RX_FLOW_N_MARK, PORT83_FN2),
667 PINMUX_DATA(MSIOF1_RSCK_MARK, PORT84_FN2),
668 PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT85_FN2),
669 PINMUX_DATA(MSIOF1_MCK0_MARK, PORT86_FN2),
670 PINMUX_DATA(MSIOF1_MCK1_MARK, PORT87_FN2),
671 PINMUX_DATA(MSIOF1_TSCK_88_MARK, PORT88_FN2, MSEL4CR_10_1),
672 PINMUX_DATA(MSIOF1_TSYNC_89_MARK, PORT89_FN2, MSEL4CR_10_1),
673 PINMUX_DATA(MSIOF1_TXD_90_MARK, PORT90_FN2, MSEL4CR_10_1),
674 PINMUX_DATA(MSIOF1_RXD_91_MARK, PORT91_FN2, MSEL4CR_10_1),
675 PINMUX_DATA(MSIOF1_SS1_92_MARK, PORT92_FN2, MSEL4CR_10_1),
676 PINMUX_DATA(MSIOF1_SS2_93_MARK, PORT93_FN2, MSEL4CR_10_1),
677 PINMUX_DATA(SCIFA2_CTS1_MARK, PORT94_FN2),
678 PINMUX_DATA(SCIFA2_RTS1_MARK, PORT95_FN2),
679 PINMUX_DATA(SCIFA2_TXD1_MARK, PORT96_FN2),
680 PINMUX_DATA(SCIFA2_RXD1_MARK, PORT97_FN2),
681 PINMUX_DATA(SCIFA2_SCK1_MARK, PORT98_FN2),
682 PINMUX_DATA(I2C_SCL2_MARK, PORT110_FN2),
683 PINMUX_DATA(I2C_SDA2_MARK, PORT111_FN2),
684 PINMUX_DATA(I2C_SCL3_MARK, PORT114_FN2, MSEL4CR_16_1),
685 PINMUX_DATA(I2C_SDA3_MARK, PORT115_FN2, MSEL4CR_16_1),
686 PINMUX_DATA(I2C_SCL4_MARK, PORT116_FN2, MSEL4CR_17_1),
687 PINMUX_DATA(I2C_SDA4_MARK, PORT117_FN2, MSEL4CR_17_1),
688 PINMUX_DATA(MSIOF2_RSCK_MARK, PORT134_FN2),
689 PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT135_FN2),
690 PINMUX_DATA(MSIOF2_MCK0_MARK, PORT136_FN2),
691 PINMUX_DATA(MSIOF2_MCK1_MARK, PORT137_FN2),
692 PINMUX_DATA(MSIOF2_SS1_MARK, PORT138_FN2),
693 PINMUX_DATA(MSIOF2_SS2_MARK, PORT139_FN2),
694 PINMUX_DATA(SCIFA3_CTS_140_MARK, PORT140_FN2, MSEL3CR_9_1),
695 PINMUX_DATA(SCIFA3_RTS_141_MARK, PORT141_FN2),
696 PINMUX_DATA(SCIFA3_SCK_MARK, PORT142_FN2),
697 PINMUX_DATA(SCIFA3_TXD_MARK, PORT143_FN2),
698 PINMUX_DATA(SCIFA3_RXD_MARK, PORT144_FN2),
699 PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT148_FN2),
700 PINMUX_DATA(MSIOF2_TSCK_MARK, PORT149_FN2),
701 PINMUX_DATA(MSIOF2_RXD_MARK, PORT150_FN2),
702 PINMUX_DATA(MSIOF2_TXD_MARK, PORT151_FN2),
703 PINMUX_DATA(SCIFA0_SCK_MARK, PORT156_FN2),
704 PINMUX_DATA(SCIFA0_RTS_MARK, PORT157_FN2),
705 PINMUX_DATA(SCIFA0_CTS_MARK, PORT158_FN2),
706 PINMUX_DATA(SCIFA1_SCK_MARK, PORT159_FN2),
707 PINMUX_DATA(SCIFA1_RTS_MARK, PORT160_FN2),
708 PINMUX_DATA(SCIFA1_CTS_MARK, PORT161_FN2),
709
710 /* Function 3 */
711 PINMUX_DATA(VIO_CKO1_MARK, PORT16_FN3),
712 PINMUX_DATA(VIO_CKO2_MARK, PORT17_FN3),
713 PINMUX_DATA(IDIN_1_18_MARK, PORT18_FN3, MSEL4CR_14_1),
714 PINMUX_DATA(MSIOF1_TSCK_39_MARK, PORT39_FN3, MSEL4CR_10_0),
715 PINMUX_DATA(MSIOF1_TSYNC_40_MARK, PORT40_FN3, MSEL4CR_10_0),
716 PINMUX_DATA(MSIOF1_TXD_41_MARK, PORT41_FN3, MSEL4CR_10_0),
717 PINMUX_DATA(MSIOF1_RXD_42_MARK, PORT42_FN3, MSEL4CR_10_0),
718 PINMUX_DATA(MSIOF1_SS1_43_MARK, PORT43_FN3, MSEL4CR_10_0),
719 PINMUX_DATA(MSIOF1_SS2_44_MARK, PORT44_FN3, MSEL4CR_10_0),
720 PINMUX_DATA(MMCD1_0_MARK, PORT54_FN3, MSEL4CR_15_1),
721 PINMUX_DATA(MMCD1_1_MARK, PORT55_FN3, MSEL4CR_15_1),
722 PINMUX_DATA(MMCD1_2_MARK, PORT56_FN3, MSEL4CR_15_1),
723 PINMUX_DATA(MMCD1_3_MARK, PORT57_FN3, MSEL4CR_15_1),
724 PINMUX_DATA(MMCD1_4_MARK, PORT58_FN3, MSEL4CR_15_1),
725 PINMUX_DATA(MMCD1_5_MARK, PORT59_FN3, MSEL4CR_15_1),
726 PINMUX_DATA(MMCD1_6_MARK, PORT60_FN3, MSEL4CR_15_1),
727 PINMUX_DATA(MMCD1_7_MARK, PORT61_FN3, MSEL4CR_15_1),
728 PINMUX_DATA(VINT_I_MARK, PORT65_FN3),
729 PINMUX_DATA(MMCCLK1_MARK, PORT66_FN3, MSEL4CR_15_1),
730 PINMUX_DATA(MMCCMD1_MARK, PORT67_FN3, MSEL4CR_15_1),
731 PINMUX_DATA(TPU0TO2_93_MARK, PORT93_FN3),
732 PINMUX_DATA(TPU0TO2_99_MARK, PORT99_FN3),
733 PINMUX_DATA(TPU0TO3_MARK, PORT112_FN3),
734 PINMUX_DATA(IDIN_0_MARK, PORT113_FN3),
735 PINMUX_DATA(EXTLP_0_MARK, PORT114_FN3),
736 PINMUX_DATA(OVCN2_0_MARK, PORT115_FN3),
737 PINMUX_DATA(PWEN_0_MARK, PORT116_FN3),
738 PINMUX_DATA(OVCN_0_MARK, PORT117_FN3),
739 PINMUX_DATA(KEYOUT7_MARK, PORT121_FN3),
740 PINMUX_DATA(KEYOUT6_MARK, PORT122_FN3),
741 PINMUX_DATA(KEYOUT5_MARK, PORT123_FN3),
742 PINMUX_DATA(KEYOUT4_MARK, PORT124_FN3),
743 PINMUX_DATA(KEYOUT3_MARK, PORT125_FN3),
744 PINMUX_DATA(KEYOUT2_MARK, PORT126_FN3),
745 PINMUX_DATA(KEYOUT1_MARK, PORT127_FN3),
746 PINMUX_DATA(KEYOUT0_MARK, PORT128_FN3),
747 PINMUX_DATA(KEYIN7_MARK, PORT129_FN3),
748 PINMUX_DATA(KEYIN6_MARK, PORT130_FN3),
749 PINMUX_DATA(KEYIN5_MARK, PORT131_FN3),
750 PINMUX_DATA(KEYIN4_MARK, PORT132_FN3),
751 PINMUX_DATA(KEYIN3_133_MARK, PORT133_FN3, MSEL4CR_18_0),
752 PINMUX_DATA(KEYIN2_134_MARK, PORT134_FN3, MSEL4CR_18_0),
753 PINMUX_DATA(KEYIN1_135_MARK, PORT135_FN3, MSEL4CR_18_0),
754 PINMUX_DATA(KEYIN0_136_MARK, PORT136_FN3, MSEL4CR_18_0),
755 PINMUX_DATA(TS_SPSYNC2_MARK, PORT137_FN3),
756 PINMUX_DATA(IROUT_139_MARK, PORT139_FN3),
757 PINMUX_DATA(IRDA_OUT_MARK, PORT140_FN3),
758 PINMUX_DATA(IRDA_IN_MARK, PORT141_FN3),
759 PINMUX_DATA(IRDA_FIRSEL_MARK, PORT142_FN3),
760 PINMUX_DATA(TS_SDAT2_MARK, PORT145_FN3),
761 PINMUX_DATA(TS_SDEN2_MARK, PORT146_FN3),
762 PINMUX_DATA(TS_SCK2_MARK, PORT147_FN3),
763
764 /* Function 4 */
765 PINMUX_DATA(SCIFA3_CTS_43_MARK, PORT43_FN4, MSEL3CR_9_0),
766 PINMUX_DATA(SCIFA3_RTS_44_MARK, PORT44_FN4),
767 PINMUX_DATA(GP_RX_FLAG_MARK, PORT76_FN4),
768 PINMUX_DATA(GP_RX_DATA_MARK, PORT77_FN4),
769 PINMUX_DATA(GP_TX_READY_MARK, PORT78_FN4),
770 PINMUX_DATA(GP_RX_WAKE_MARK, PORT79_FN4),
771 PINMUX_DATA(MP_TX_FLAG_MARK, PORT80_FN4),
772 PINMUX_DATA(MP_TX_DATA_MARK, PORT81_FN4),
773 PINMUX_DATA(MP_RX_READY_MARK, PORT82_FN4),
774 PINMUX_DATA(MP_TX_WAKE_MARK, PORT83_FN4),
775 PINMUX_DATA(MMCD0_0_MARK, PORT84_FN4, MSEL4CR_15_0),
776 PINMUX_DATA(MMCD0_1_MARK, PORT85_FN4, MSEL4CR_15_0),
777 PINMUX_DATA(MMCD0_2_MARK, PORT86_FN4, MSEL4CR_15_0),
778 PINMUX_DATA(MMCD0_3_MARK, PORT87_FN4, MSEL4CR_15_0),
779 PINMUX_DATA(MMCD0_4_MARK, PORT88_FN4, MSEL4CR_15_0),
780 PINMUX_DATA(MMCD0_5_MARK, PORT89_FN4, MSEL4CR_15_0),
781 PINMUX_DATA(MMCD0_6_MARK, PORT90_FN4, MSEL4CR_15_0),
782 PINMUX_DATA(MMCD0_7_MARK, PORT91_FN4, MSEL4CR_15_0),
783 PINMUX_DATA(MMCCMD0_MARK, PORT92_FN4, MSEL4CR_15_0),
784 PINMUX_DATA(SIM_RST_MARK, PORT94_FN4),
785 PINMUX_DATA(SIM_CLK_MARK, PORT95_FN4),
786 PINMUX_DATA(SIM_D_MARK, PORT98_FN4),
787 PINMUX_DATA(MMCCLK0_MARK, PORT99_FN4, MSEL4CR_15_0),
788 PINMUX_DATA(IDIN_1_113_MARK, PORT113_FN4, MSEL4CR_14_0),
789 PINMUX_DATA(OVCN_1_114_MARK, PORT114_FN4, MSEL4CR_14_0),
790 PINMUX_DATA(PWEN_1_115_MARK, PORT115_FN4),
791 PINMUX_DATA(EXTLP_1_MARK, PORT116_FN4),
792 PINMUX_DATA(OVCN2_1_MARK, PORT117_FN4),
793 PINMUX_DATA(KEYIN0_121_MARK, PORT121_FN4, MSEL4CR_18_1),
794 PINMUX_DATA(KEYIN1_122_MARK, PORT122_FN4, MSEL4CR_18_1),
795 PINMUX_DATA(KEYIN2_123_MARK, PORT123_FN4, MSEL4CR_18_1),
796 PINMUX_DATA(KEYIN3_124_MARK, PORT124_FN4, MSEL4CR_18_1),
797 PINMUX_DATA(PWEN_1_138_MARK, PORT138_FN4),
798 PINMUX_DATA(IROUT_140_MARK, PORT140_FN4),
799 PINMUX_DATA(LCDCS_MARK, PORT145_FN4),
800 PINMUX_DATA(LCDWR_MARK, PORT147_FN4),
801 PINMUX_DATA(LCDRS_MARK, PORT149_FN4),
802 PINMUX_DATA(OVCN_1_162_MARK, PORT162_FN4, MSEL4CR_14_1),
803
804 /* Function 5 */
805 PINMUX_DATA(GPI0_MARK, PORT41_FN5),
806 PINMUX_DATA(GPI1_MARK, PORT42_FN5),
807 PINMUX_DATA(GPO0_MARK, PORT43_FN5),
808 PINMUX_DATA(GPO1_MARK, PORT44_FN5),
809 PINMUX_DATA(I2C_SCL3S_MARK, PORT137_FN5, MSEL4CR_16_0),
810 PINMUX_DATA(I2C_SDA3S_MARK, PORT145_FN5, MSEL4CR_16_0),
811 PINMUX_DATA(I2C_SCL4S_MARK, PORT146_FN5, MSEL4CR_17_0),
812 PINMUX_DATA(I2C_SDA4S_MARK, PORT147_FN5, MSEL4CR_17_0),
813
814 /* Function select */
815 PINMUX_DATA(LCDC0_SELECT_MARK, MSEL3CR_6_0),
816 PINMUX_DATA(LCDC1_SELECT_MARK, MSEL3CR_6_1),
817
818 PINMUX_DATA(TS0_1SELECT_MARK, MSEL3CR_21_0, MSEL3CR_20_0),
819 PINMUX_DATA(TS0_2SELECT_MARK, MSEL3CR_21_0, MSEL3CR_20_1),
820 PINMUX_DATA(TS1_1SELECT_MARK, MSEL3CR_27_0, MSEL3CR_26_0),
821 PINMUX_DATA(TS1_2SELECT_MARK, MSEL3CR_27_0, MSEL3CR_26_1),
822
823 PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0),
824 PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1),
825
826 PINMUX_DATA(MFIv6_MARK, MSEL4CR_6_0),
827 PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1),
828};
829
830#define __I (SH_PFC_PIN_CFG_INPUT)
831#define __O (SH_PFC_PIN_CFG_OUTPUT)
832#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
833#define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
834#define __PU (SH_PFC_PIN_CFG_PULL_UP)
835#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
836
837#define SH7372_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD)
838#define SH7372_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU)
839#define SH7372_PIN_I_PU_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PUD)
840#define SH7372_PIN_IO(pin) SH_PFC_PIN_CFG(pin, __IO)
841#define SH7372_PIN_IO_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PD)
842#define SH7372_PIN_IO_PU(pin) SH_PFC_PIN_CFG(pin, __IO | __PU)
843#define SH7372_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
844#define SH7372_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
845#define SH7372_PIN_O_PU_PD(pin) SH_PFC_PIN_CFG(pin, __O | __PUD)
846
847static const struct sh_pfc_pin pinmux_pins[] = {
848 /* Table 57-1 (I/O and Pull U/D) */
849 SH7372_PIN_IO_PD(0), SH7372_PIN_IO_PD(1),
850 SH7372_PIN_O(2), SH7372_PIN_I_PD(3),
851 SH7372_PIN_I_PD(4), SH7372_PIN_I_PD(5),
852 SH7372_PIN_IO_PU_PD(6), SH7372_PIN_I_PD(7),
853 SH7372_PIN_IO_PD(8), SH7372_PIN_O(9),
854 SH7372_PIN_O(10), SH7372_PIN_O(11),
855 SH7372_PIN_IO_PU_PD(12), SH7372_PIN_IO_PD(13),
856 SH7372_PIN_IO_PD(14), SH7372_PIN_O(15),
857 SH7372_PIN_IO_PD(16), SH7372_PIN_IO_PD(17),
858 SH7372_PIN_I_PD(18), SH7372_PIN_IO(19),
859 SH7372_PIN_IO(20), SH7372_PIN_IO(21),
860 SH7372_PIN_IO(22), SH7372_PIN_IO(23),
861 SH7372_PIN_IO(24), SH7372_PIN_IO(25),
862 SH7372_PIN_IO(26), SH7372_PIN_IO(27),
863 SH7372_PIN_IO(28), SH7372_PIN_IO(29),
864 SH7372_PIN_IO(30), SH7372_PIN_IO(31),
865 SH7372_PIN_IO(32), SH7372_PIN_IO(33),
866 SH7372_PIN_IO(34), SH7372_PIN_IO(35),
867 SH7372_PIN_IO(36), SH7372_PIN_IO(37),
868 SH7372_PIN_IO(38), SH7372_PIN_IO(39),
869 SH7372_PIN_IO(40), SH7372_PIN_IO(41),
870 SH7372_PIN_IO(42), SH7372_PIN_IO(43),
871 SH7372_PIN_IO(44), SH7372_PIN_IO(45),
872 SH7372_PIN_IO_PU(46), SH7372_PIN_IO_PU(47),
873 SH7372_PIN_IO_PU(48), SH7372_PIN_IO_PU(49),
874 SH7372_PIN_IO_PU(50), SH7372_PIN_IO_PU(51),
875 SH7372_PIN_IO_PU(52), SH7372_PIN_IO_PU(53),
876 SH7372_PIN_IO_PU(54), SH7372_PIN_IO_PU(55),
877 SH7372_PIN_IO_PU(56), SH7372_PIN_IO_PU(57),
878 SH7372_PIN_IO_PU(58), SH7372_PIN_IO_PU(59),
879 SH7372_PIN_IO_PU(60), SH7372_PIN_IO_PU(61),
880 SH7372_PIN_IO(62), SH7372_PIN_O(63),
881 SH7372_PIN_O(64), SH7372_PIN_IO_PU(65),
882 SH7372_PIN_O_PU_PD(66), SH7372_PIN_IO_PU(67),
883 SH7372_PIN_O(68), SH7372_PIN_IO(69),
884 SH7372_PIN_IO(70), SH7372_PIN_IO(71),
885 SH7372_PIN_O(72), SH7372_PIN_I_PU(73),
886 SH7372_PIN_I_PU_PD(74), SH7372_PIN_IO_PU_PD(75),
887 SH7372_PIN_IO_PU_PD(76), SH7372_PIN_IO_PU_PD(77),
888 SH7372_PIN_IO_PU_PD(78), SH7372_PIN_IO_PU_PD(79),
889 SH7372_PIN_IO_PU_PD(80), SH7372_PIN_IO_PU_PD(81),
890 SH7372_PIN_IO_PU_PD(82), SH7372_PIN_IO_PU_PD(83),
891 SH7372_PIN_IO_PU_PD(84), SH7372_PIN_IO_PU_PD(85),
892 SH7372_PIN_IO_PU_PD(86), SH7372_PIN_IO_PU_PD(87),
893 SH7372_PIN_IO_PU_PD(88), SH7372_PIN_IO_PU_PD(89),
894 SH7372_PIN_IO_PU_PD(90), SH7372_PIN_IO_PU_PD(91),
895 SH7372_PIN_IO_PU_PD(92), SH7372_PIN_IO_PU_PD(93),
896 SH7372_PIN_IO_PU_PD(94), SH7372_PIN_IO_PU_PD(95),
897 SH7372_PIN_IO_PU(96), SH7372_PIN_IO_PU_PD(97),
898 SH7372_PIN_IO_PU_PD(98), SH7372_PIN_O_PU_PD(99),
899 SH7372_PIN_IO_PD(100), SH7372_PIN_IO_PD(101),
900 SH7372_PIN_IO_PD(102), SH7372_PIN_IO_PD(103),
901 SH7372_PIN_IO_PD(104), SH7372_PIN_IO_PD(105),
902 SH7372_PIN_IO_PU(106), SH7372_PIN_IO_PU(107),
903 SH7372_PIN_IO_PU(108), SH7372_PIN_IO_PU(109),
904 SH7372_PIN_IO_PU(110), SH7372_PIN_IO_PU(111),
905 SH7372_PIN_IO_PD(112), SH7372_PIN_IO_PD(113),
906 SH7372_PIN_IO_PU(114), SH7372_PIN_IO_PU(115),
907 SH7372_PIN_IO_PU(116), SH7372_PIN_IO_PU(117),
908 SH7372_PIN_IO_PU(118), SH7372_PIN_IO_PU(119),
909 SH7372_PIN_IO_PU(120), SH7372_PIN_IO_PD(121),
910 SH7372_PIN_IO_PD(122), SH7372_PIN_IO_PD(123),
911 SH7372_PIN_IO_PD(124), SH7372_PIN_IO_PD(125),
912 SH7372_PIN_IO_PD(126), SH7372_PIN_IO_PD(127),
913 SH7372_PIN_IO_PD(128), SH7372_PIN_IO_PU_PD(129),
914 SH7372_PIN_IO_PU_PD(130), SH7372_PIN_IO_PU_PD(131),
915 SH7372_PIN_IO_PU_PD(132), SH7372_PIN_IO_PU_PD(133),
916 SH7372_PIN_IO_PU_PD(134), SH7372_PIN_IO_PU_PD(135),
917 SH7372_PIN_IO_PD(136), SH7372_PIN_IO_PD(137),
918 SH7372_PIN_IO_PD(138), SH7372_PIN_IO_PD(139),
919 SH7372_PIN_IO_PD(140), SH7372_PIN_IO_PD(141),
920 SH7372_PIN_IO_PD(142), SH7372_PIN_IO_PU_PD(143),
921 SH7372_PIN_IO_PD(144), SH7372_PIN_IO_PD(145),
922 SH7372_PIN_IO_PD(146), SH7372_PIN_IO_PD(147),
923 SH7372_PIN_IO_PD(148), SH7372_PIN_IO_PD(149),
924 SH7372_PIN_IO_PD(150), SH7372_PIN_IO_PD(151),
925 SH7372_PIN_IO_PU_PD(152), SH7372_PIN_I_PD(153),
926 SH7372_PIN_IO_PU_PD(154), SH7372_PIN_I_PD(155),
927 SH7372_PIN_IO_PD(156), SH7372_PIN_IO_PD(157),
928 SH7372_PIN_I_PD(158), SH7372_PIN_IO_PD(159),
929 SH7372_PIN_O(160), SH7372_PIN_IO_PD(161),
930 SH7372_PIN_IO_PD(162), SH7372_PIN_IO_PD(163),
931 SH7372_PIN_I_PD(164), SH7372_PIN_IO_PD(165),
932 SH7372_PIN_I_PD(166), SH7372_PIN_I_PD(167),
933 SH7372_PIN_I_PD(168), SH7372_PIN_I_PD(169),
934 SH7372_PIN_I_PD(170), SH7372_PIN_O(171),
935 SH7372_PIN_IO_PU_PD(172), SH7372_PIN_IO_PU_PD(173),
936 SH7372_PIN_IO_PU_PD(174), SH7372_PIN_IO_PU_PD(175),
937 SH7372_PIN_IO_PU_PD(176), SH7372_PIN_IO_PU_PD(177),
938 SH7372_PIN_IO_PU_PD(178), SH7372_PIN_O(179),
939 SH7372_PIN_IO_PU_PD(180), SH7372_PIN_IO_PU_PD(181),
940 SH7372_PIN_IO_PU_PD(182), SH7372_PIN_IO_PU_PD(183),
941 SH7372_PIN_IO_PU_PD(184), SH7372_PIN_O(185),
942 SH7372_PIN_IO_PU_PD(186), SH7372_PIN_IO_PU_PD(187),
943 SH7372_PIN_IO_PU_PD(188), SH7372_PIN_IO_PU_PD(189),
944 SH7372_PIN_IO_PU_PD(190),
945};
946
947/* - BSC -------------------------------------------------------------------- */
948static const unsigned int bsc_data8_pins[] = {
949 /* D[0:7] */
950 46, 47, 48, 49, 50, 51, 52, 53,
951};
952static const unsigned int bsc_data8_mux[] = {
953 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
954 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
955};
956static const unsigned int bsc_data16_pins[] = {
957 /* D[0:15] */
958 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
959};
960static const unsigned int bsc_data16_mux[] = {
961 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
962 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
963 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
964 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
965};
966static const unsigned int bsc_cs0_pins[] = {
967 /* CS */
968 62,
969};
970static const unsigned int bsc_cs0_mux[] = {
971 CS0_MARK,
972};
973static const unsigned int bsc_cs2_pins[] = {
974 /* CS */
975 63,
976};
977static const unsigned int bsc_cs2_mux[] = {
978 CS2_MARK,
979};
980static const unsigned int bsc_cs4_pins[] = {
981 /* CS */
982 64,
983};
984static const unsigned int bsc_cs4_mux[] = {
985 CS4_MARK,
986};
987static const unsigned int bsc_cs5a_pins[] = {
988 /* CS */
989 65,
990};
991static const unsigned int bsc_cs5a_mux[] = {
992 CS5A_MARK,
993};
994static const unsigned int bsc_cs5b_pins[] = {
995 /* CS */
996 66,
997};
998static const unsigned int bsc_cs5b_mux[] = {
999 CS5B_MARK,
1000};
1001static const unsigned int bsc_cs6a_pins[] = {
1002 /* CS */
1003 67,
1004};
1005static const unsigned int bsc_cs6a_mux[] = {
1006 CS6A_MARK,
1007};
1008static const unsigned int bsc_rd_we8_pins[] = {
1009 /* RD, WE[0] */
1010 69, 70,
1011};
1012static const unsigned int bsc_rd_we8_mux[] = {
1013 RD_FSC_MARK, WE0_FWE_MARK,
1014};
1015static const unsigned int bsc_rd_we16_pins[] = {
1016 /* RD, WE[0:1] */
1017 69, 70, 71,
1018};
1019static const unsigned int bsc_rd_we16_mux[] = {
1020 RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
1021};
1022static const unsigned int bsc_bs_pins[] = {
1023 /* BS */
1024 19,
1025};
1026static const unsigned int bsc_bs_mux[] = {
1027 BS_MARK,
1028};
1029static const unsigned int bsc_rdwr_pins[] = {
1030 /* RDWR */
1031 75,
1032};
1033static const unsigned int bsc_rdwr_mux[] = {
1034 RDWR_MARK,
1035};
1036static const unsigned int bsc_wait_pins[] = {
1037 /* WAIT */
1038 74,
1039};
1040static const unsigned int bsc_wait_mux[] = {
1041 WAIT_MARK,
1042};
1043/* - CEU -------------------------------------------------------------------- */
1044static const unsigned int ceu_data_0_7_pins[] = {
1045 /* D[0:7] */
1046 102, 103, 104, 105, 106, 107, 108, 109,
1047};
1048static const unsigned int ceu_data_0_7_mux[] = {
1049 VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK, VIO_D3_MARK,
1050 VIO_D4_MARK, VIO_D5_MARK, VIO_D6_MARK, VIO_D7_MARK,
1051};
1052static const unsigned int ceu_data_8_15_pins[] = {
1053 /* D[8:15] */
1054 110, 111, 112, 113, 114, 115, 116, 117,
1055};
1056static const unsigned int ceu_data_8_15_mux[] = {
1057 VIO_D8_MARK, VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK,
1058 VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK, VIO_D15_MARK,
1059};
1060static const unsigned int ceu_clk_0_pins[] = {
1061 /* CKO */
1062 120,
1063};
1064static const unsigned int ceu_clk_0_mux[] = {
1065 VIO_CKO_MARK,
1066};
1067static const unsigned int ceu_clk_1_pins[] = {
1068 /* CKO */
1069 16,
1070};
1071static const unsigned int ceu_clk_1_mux[] = {
1072 VIO_CKO1_MARK,
1073};
1074static const unsigned int ceu_clk_2_pins[] = {
1075 /* CKO */
1076 17,
1077};
1078static const unsigned int ceu_clk_2_mux[] = {
1079 VIO_CKO2_MARK,
1080};
1081static const unsigned int ceu_sync_pins[] = {
1082 /* CLK, VD, HD */
1083 118, 100, 101,
1084};
1085static const unsigned int ceu_sync_mux[] = {
1086 VIO_CLK_MARK, VIO_VD_MARK, VIO_HD_MARK,
1087};
1088static const unsigned int ceu_field_pins[] = {
1089 /* FIELD */
1090 119,
1091};
1092static const unsigned int ceu_field_mux[] = {
1093 VIO_FIELD_MARK,
1094};
1095/* - FLCTL ------------------------------------------------------------------ */
1096static const unsigned int flctl_data_pins[] = {
1097 /* NAF[0:15] */
1098 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
1099};
1100static const unsigned int flctl_data_mux[] = {
1101 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1102 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1103 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1104 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1105};
1106static const unsigned int flctl_ce0_pins[] = {
1107 /* CE */
1108 68,
1109};
1110static const unsigned int flctl_ce0_mux[] = {
1111 FCE0_MARK,
1112};
1113static const unsigned int flctl_ce1_pins[] = {
1114 /* CE */
1115 66,
1116};
1117static const unsigned int flctl_ce1_mux[] = {
1118 FCE1_MARK,
1119};
1120static const unsigned int flctl_ctrl_pins[] = {
1121 /* FCDE, FOE, FSC, FWE, FRB */
1122 24, 23, 69, 70, 73,
1123};
1124static const unsigned int flctl_ctrl_mux[] = {
1125 A5_FCDE_MARK, A4_FOE_MARK, RD_FSC_MARK, WE0_FWE_MARK, FRB_MARK,
1126};
1127/* - FSIA ------------------------------------------------------------------- */
1128static const unsigned int fsia_mclk_in_pins[] = {
1129 /* CK */
1130 4,
1131};
1132static const unsigned int fsia_mclk_in_mux[] = {
1133 FSIACK_MARK,
1134};
1135static const unsigned int fsia_mclk_out_pins[] = {
1136 /* OMC */
1137 8,
1138};
1139static const unsigned int fsia_mclk_out_mux[] = {
1140 FSIAOMC_MARK,
1141};
1142static const unsigned int fsia_sclk_in_pins[] = {
1143 /* ILR, IBT */
1144 5, 6,
1145};
1146static const unsigned int fsia_sclk_in_mux[] = {
1147 FSIAILR_MARK, FSIAIBT_MARK,
1148};
1149static const unsigned int fsia_sclk_out_pins[] = {
1150 /* OLR, OBT */
1151 9, 10,
1152};
1153static const unsigned int fsia_sclk_out_mux[] = {
1154 FSIAOLR_MARK, FSIAOBT_MARK,
1155};
1156static const unsigned int fsia_data_in_pins[] = {
1157 /* ISLD */
1158 7,
1159};
1160static const unsigned int fsia_data_in_mux[] = {
1161 FSIAISLD_MARK,
1162};
1163static const unsigned int fsia_data_out_pins[] = {
1164 /* OSLD */
1165 11,
1166};
1167static const unsigned int fsia_data_out_mux[] = {
1168 FSIAOSLD_MARK,
1169};
1170static const unsigned int fsia_spdif_0_pins[] = {
1171 /* SPDIF */
1172 11,
1173};
1174static const unsigned int fsia_spdif_0_mux[] = {
1175 FSIASPDIF_11_MARK,
1176};
1177static const unsigned int fsia_spdif_1_pins[] = {
1178 /* SPDIF */
1179 15,
1180};
1181static const unsigned int fsia_spdif_1_mux[] = {
1182 FSIASPDIF_15_MARK,
1183};
1184/* - FSIB ------------------------------------------------------------------- */
1185static const unsigned int fsib_mclk_in_pins[] = {
1186 /* CK */
1187 4,
1188};
1189static const unsigned int fsib_mclk_in_mux[] = {
1190 FSIBCK_MARK,
1191};
1192/* - HDMI ------------------------------------------------------------------- */
1193static const unsigned int hdmi_pins[] = {
1194 /* HPD, CEC */
1195 169, 170,
1196};
1197static const unsigned int hdmi_mux[] = {
1198 HDMI_HPD_MARK, HDMI_CEC_MARK,
1199};
1200/* - INTC ------------------------------------------------------------------- */
1201IRQC_PINS_MUX(0, 6, 162);
1202IRQC_PIN_MUX(1, 12);
1203IRQC_PINS_MUX(2, 4, 5);
1204IRQC_PINS_MUX(3, 8, 16);
1205IRQC_PINS_MUX(4, 17, 163);
1206IRQC_PIN_MUX(5, 18);
1207IRQC_PINS_MUX(6, 39, 164);
1208IRQC_PINS_MUX(7, 40, 167);
1209IRQC_PINS_MUX(8, 41, 168);
1210IRQC_PINS_MUX(9, 42, 169);
1211IRQC_PIN_MUX(10, 65);
1212IRQC_PIN_MUX(11, 67);
1213IRQC_PINS_MUX(12, 80, 137);
1214IRQC_PINS_MUX(13, 81, 145);
1215IRQC_PINS_MUX(14, 82, 146);
1216IRQC_PINS_MUX(15, 83, 147);
1217IRQC_PINS_MUX(16, 84, 170);
1218IRQC_PIN_MUX(17, 85);
1219IRQC_PIN_MUX(18, 86);
1220IRQC_PIN_MUX(19, 87);
1221IRQC_PIN_MUX(20, 92);
1222IRQC_PIN_MUX(21, 93);
1223IRQC_PIN_MUX(22, 94);
1224IRQC_PIN_MUX(23, 95);
1225IRQC_PIN_MUX(24, 112);
1226IRQC_PIN_MUX(25, 119);
1227IRQC_PINS_MUX(26, 121, 172);
1228IRQC_PINS_MUX(27, 122, 180);
1229IRQC_PINS_MUX(28, 123, 181);
1230IRQC_PINS_MUX(29, 129, 182);
1231IRQC_PINS_MUX(30, 130, 183);
1232IRQC_PINS_MUX(31, 138, 184);
1233/* - KEYSC ------------------------------------------------------------------ */
1234static const unsigned int keysc_in04_0_pins[] = {
1235 /* KEYIN[0:4] */
1236 136, 135, 134, 133, 132,
1237};
1238static const unsigned int keysc_in04_0_mux[] = {
1239 KEYIN0_136_MARK, KEYIN1_135_MARK, KEYIN2_134_MARK, KEYIN3_133_MARK,
1240 KEYIN4_MARK,
1241};
1242static const unsigned int keysc_in04_1_pins[] = {
1243 /* KEYIN[0:4] */
1244 121, 122, 123, 124, 132,
1245};
1246static const unsigned int keysc_in04_1_mux[] = {
1247 KEYIN0_121_MARK, KEYIN1_122_MARK, KEYIN2_123_MARK, KEYIN3_124_MARK,
1248 KEYIN4_MARK,
1249};
1250static const unsigned int keysc_in5_pins[] = {
1251 /* KEYIN5 */
1252 131,
1253};
1254static const unsigned int keysc_in5_mux[] = {
1255 KEYIN5_MARK,
1256};
1257static const unsigned int keysc_in6_pins[] = {
1258 /* KEYIN6 */
1259 130,
1260};
1261static const unsigned int keysc_in6_mux[] = {
1262 KEYIN6_MARK,
1263};
1264static const unsigned int keysc_in7_pins[] = {
1265 /* KEYIN7 */
1266 129,
1267};
1268static const unsigned int keysc_in7_mux[] = {
1269 KEYIN7_MARK,
1270};
1271static const unsigned int keysc_out4_pins[] = {
1272 /* KEYOUT[0:3] */
1273 128, 127, 126, 125,
1274};
1275static const unsigned int keysc_out4_mux[] = {
1276 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
1277};
1278static const unsigned int keysc_out5_pins[] = {
1279 /* KEYOUT[0:4] */
1280 128, 127, 126, 125, 124,
1281};
1282static const unsigned int keysc_out5_mux[] = {
1283 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
1284 KEYOUT4_MARK,
1285};
1286static const unsigned int keysc_out6_pins[] = {
1287 /* KEYOUT[0:5] */
1288 128, 127, 126, 125, 124, 123,
1289};
1290static const unsigned int keysc_out6_mux[] = {
1291 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
1292 KEYOUT4_MARK, KEYOUT5_MARK,
1293};
1294static const unsigned int keysc_out8_pins[] = {
1295 /* KEYOUT[0:7] */
1296 128, 127, 126, 125, 124, 123, 122, 121,
1297};
1298static const unsigned int keysc_out8_mux[] = {
1299 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
1300 KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
1301};
1302/* - LCD -------------------------------------------------------------------- */
1303static const unsigned int lcd_data8_pins[] = {
1304 /* D[0:7] */
1305 121, 122, 123, 124, 125, 126, 127, 128,
1306};
1307static const unsigned int lcd_data8_mux[] = {
1308 /* LCDC */
1309 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1310 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1311};
1312static const unsigned int lcd_data9_pins[] = {
1313 /* D[0:8] */
1314 121, 122, 123, 124, 125, 126, 127, 128,
1315 129,
1316 137, 138, 139, 140, 141, 142, 143, 144,
1317};
1318static const unsigned int lcd_data9_mux[] = {
1319 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1320 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1321 LCDD8_MARK,
1322};
1323static const unsigned int lcd_data12_pins[] = {
1324 /* D[0:11] */
1325 121, 122, 123, 124, 125, 126, 127, 128,
1326 129, 130, 131, 132,
1327};
1328static const unsigned int lcd_data12_mux[] = {
1329 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1330 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1331 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1332};
1333static const unsigned int lcd_data16_pins[] = {
1334 /* D[0:15] */
1335 121, 122, 123, 124, 125, 126, 127, 128,
1336 129, 130, 131, 132, 133, 134, 135, 136,
1337};
1338static const unsigned int lcd_data16_mux[] = {
1339 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1340 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1341 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1342 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1343};
1344static const unsigned int lcd_data18_pins[] = {
1345 /* D[0:17] */
1346 121, 122, 123, 124, 125, 126, 127, 128,
1347 129, 130, 131, 132, 133, 134, 135, 136,
1348 137, 138,
1349};
1350static const unsigned int lcd_data18_mux[] = {
1351 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1352 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1353 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1354 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1355 LCDD16_MARK, LCDD17_MARK,
1356};
1357static const unsigned int lcd_data24_pins[] = {
1358 /* D[0:23] */
1359 121, 122, 123, 124, 125, 126, 127, 128,
1360 129, 130, 131, 132, 133, 134, 135, 136,
1361 137, 138, 139, 140, 141, 142, 143, 144,
1362};
1363static const unsigned int lcd_data24_mux[] = {
1364 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1365 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1366 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1367 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1368 LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
1369 LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
1370};
1371static const unsigned int lcd_display_pins[] = {
1372 /* DON */
1373 151,
1374};
1375static const unsigned int lcd_display_mux[] = {
1376 LCDDON_MARK,
1377};
1378static const unsigned int lcd_lclk_pins[] = {
1379 /* LCLK */
1380 150,
1381};
1382static const unsigned int lcd_lclk_mux[] = {
1383 LCDLCLK_MARK,
1384};
1385static const unsigned int lcd_sync_pins[] = {
1386 /* VSYN, HSYN, DCK, DISP */
1387 146, 145, 147, 149,
1388};
1389static const unsigned int lcd_sync_mux[] = {
1390 LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK,
1391};
1392static const unsigned int lcd_sys_pins[] = {
1393 /* CS, WR, RD, RS */
1394 145, 147, 148, 149,
1395};
1396static const unsigned int lcd_sys_mux[] = {
1397 LCDCS_MARK, LCDWR_MARK, LCDRD_MARK, LCDRS_MARK,
1398};
1399/* - MMCIF ------------------------------------------------------------------ */
1400static const unsigned int mmc0_data1_0_pins[] = {
1401 /* D[0] */
1402 84,
1403};
1404static const unsigned int mmc0_data1_0_mux[] = {
1405 MMCD0_0_MARK,
1406};
1407static const unsigned int mmc0_data4_0_pins[] = {
1408 /* D[0:3] */
1409 84, 85, 86, 87,
1410};
1411static const unsigned int mmc0_data4_0_mux[] = {
1412 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
1413};
1414static const unsigned int mmc0_data8_0_pins[] = {
1415 /* D[0:7] */
1416 84, 85, 86, 87, 88, 89, 90, 91,
1417};
1418static const unsigned int mmc0_data8_0_mux[] = {
1419 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
1420 MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
1421};
1422static const unsigned int mmc0_ctrl_0_pins[] = {
1423 /* CMD, CLK */
1424 92, 99,
1425};
1426static const unsigned int mmc0_ctrl_0_mux[] = {
1427 MMCCMD0_MARK, MMCCLK0_MARK,
1428};
1429
1430static const unsigned int mmc0_data1_1_pins[] = {
1431 /* D[0] */
1432 54,
1433};
1434static const unsigned int mmc0_data1_1_mux[] = {
1435 MMCD1_0_MARK,
1436};
1437static const unsigned int mmc0_data4_1_pins[] = {
1438 /* D[0:3] */
1439 54, 55, 56, 57,
1440};
1441static const unsigned int mmc0_data4_1_mux[] = {
1442 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
1443};
1444static const unsigned int mmc0_data8_1_pins[] = {
1445 /* D[0:7] */
1446 54, 55, 56, 57, 58, 59, 60, 61,
1447};
1448static const unsigned int mmc0_data8_1_mux[] = {
1449 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
1450 MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
1451};
1452static const unsigned int mmc0_ctrl_1_pins[] = {
1453 /* CMD, CLK */
1454 67, 66,
1455};
1456static const unsigned int mmc0_ctrl_1_mux[] = {
1457 MMCCMD1_MARK, MMCCLK1_MARK,
1458};
1459/* - SCIFA0 ----------------------------------------------------------------- */
1460static const unsigned int scifa0_data_pins[] = {
1461 /* RXD, TXD */
1462 153, 152,
1463};
1464static const unsigned int scifa0_data_mux[] = {
1465 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
1466};
1467static const unsigned int scifa0_clk_pins[] = {
1468 /* SCK */
1469 156,
1470};
1471static const unsigned int scifa0_clk_mux[] = {
1472 SCIFA0_SCK_MARK,
1473};
1474static const unsigned int scifa0_ctrl_pins[] = {
1475 /* RTS, CTS */
1476 157, 158,
1477};
1478static const unsigned int scifa0_ctrl_mux[] = {
1479 SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
1480};
1481/* - SCIFA1 ----------------------------------------------------------------- */
1482static const unsigned int scifa1_data_pins[] = {
1483 /* RXD, TXD */
1484 155, 154,
1485};
1486static const unsigned int scifa1_data_mux[] = {
1487 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
1488};
1489static const unsigned int scifa1_clk_pins[] = {
1490 /* SCK */
1491 159,
1492};
1493static const unsigned int scifa1_clk_mux[] = {
1494 SCIFA1_SCK_MARK,
1495};
1496static const unsigned int scifa1_ctrl_pins[] = {
1497 /* RTS, CTS */
1498 160, 161,
1499};
1500static const unsigned int scifa1_ctrl_mux[] = {
1501 SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
1502};
1503/* - SCIFA2 ----------------------------------------------------------------- */
1504static const unsigned int scifa2_data_pins[] = {
1505 /* RXD, TXD */
1506 97, 96,
1507};
1508static const unsigned int scifa2_data_mux[] = {
1509 SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK,
1510};
1511static const unsigned int scifa2_clk_pins[] = {
1512 /* SCK */
1513 98,
1514};
1515static const unsigned int scifa2_clk_mux[] = {
1516 SCIFA2_SCK1_MARK,
1517};
1518static const unsigned int scifa2_ctrl_pins[] = {
1519 /* RTS, CTS */
1520 95, 94,
1521};
1522static const unsigned int scifa2_ctrl_mux[] = {
1523 SCIFA2_RTS1_MARK, SCIFA2_CTS1_MARK,
1524};
1525/* - SCIFA3 ----------------------------------------------------------------- */
1526static const unsigned int scifa3_data_pins[] = {
1527 /* RXD, TXD */
1528 144, 143,
1529};
1530static const unsigned int scifa3_data_mux[] = {
1531 SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
1532};
1533static const unsigned int scifa3_clk_pins[] = {
1534 /* SCK */
1535 142,
1536};
1537static const unsigned int scifa3_clk_mux[] = {
1538 SCIFA3_SCK_MARK,
1539};
1540static const unsigned int scifa3_ctrl_0_pins[] = {
1541 /* RTS, CTS */
1542 44, 43,
1543};
1544static const unsigned int scifa3_ctrl_0_mux[] = {
1545 SCIFA3_RTS_44_MARK, SCIFA3_CTS_43_MARK,
1546};
1547static const unsigned int scifa3_ctrl_1_pins[] = {
1548 /* RTS, CTS */
1549 141, 140,
1550};
1551static const unsigned int scifa3_ctrl_1_mux[] = {
1552 SCIFA3_RTS_141_MARK, SCIFA3_CTS_140_MARK,
1553};
1554/* - SCIFA4 ----------------------------------------------------------------- */
1555static const unsigned int scifa4_data_pins[] = {
1556 /* RXD, TXD */
1557 5, 6,
1558};
1559static const unsigned int scifa4_data_mux[] = {
1560 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
1561};
1562/* - SCIFA5 ----------------------------------------------------------------- */
1563static const unsigned int scifa5_data_pins[] = {
1564 /* RXD, TXD */
1565 8, 12,
1566};
1567static const unsigned int scifa5_data_mux[] = {
1568 SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
1569};
1570/* - SCIFB ------------------------------------------------------------------ */
1571static const unsigned int scifb_data_pins[] = {
1572 /* RXD, TXD */
1573 166, 165,
1574};
1575static const unsigned int scifb_data_mux[] = {
1576 SCIFB_RXD_MARK, SCIFB_TXD_MARK,
1577};
1578static const unsigned int scifb_clk_pins[] = {
1579 /* SCK */
1580 162,
1581};
1582static const unsigned int scifb_clk_mux[] = {
1583 SCIFB_SCK_MARK,
1584};
1585static const unsigned int scifb_ctrl_pins[] = {
1586 /* RTS, CTS */
1587 163, 164,
1588};
1589static const unsigned int scifb_ctrl_mux[] = {
1590 SCIFB_RTS_MARK, SCIFB_CTS_MARK,
1591};
1592/* - SDHI0 ------------------------------------------------------------------ */
1593static const unsigned int sdhi0_data1_pins[] = {
1594 /* D0 */
1595 173,
1596};
1597static const unsigned int sdhi0_data1_mux[] = {
1598 SDHID0_0_MARK,
1599};
1600static const unsigned int sdhi0_data4_pins[] = {
1601 /* D[0:3] */
1602 173, 174, 175, 176,
1603};
1604static const unsigned int sdhi0_data4_mux[] = {
1605 SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
1606};
1607static const unsigned int sdhi0_ctrl_pins[] = {
1608 /* CMD, CLK */
1609 177, 171,
1610};
1611static const unsigned int sdhi0_ctrl_mux[] = {
1612 SDHICMD0_MARK, SDHICLK0_MARK,
1613};
1614static const unsigned int sdhi0_cd_pins[] = {
1615 /* CD */
1616 172,
1617};
1618static const unsigned int sdhi0_cd_mux[] = {
1619 SDHICD0_MARK,
1620};
1621static const unsigned int sdhi0_wp_pins[] = {
1622 /* WP */
1623 178,
1624};
1625static const unsigned int sdhi0_wp_mux[] = {
1626 SDHIWP0_MARK,
1627};
1628/* - SDHI1 ------------------------------------------------------------------ */
1629static const unsigned int sdhi1_data1_pins[] = {
1630 /* D0 */
1631 180,
1632};
1633static const unsigned int sdhi1_data1_mux[] = {
1634 SDHID1_0_MARK,
1635};
1636static const unsigned int sdhi1_data4_pins[] = {
1637 /* D[0:3] */
1638 180, 181, 182, 183,
1639};
1640static const unsigned int sdhi1_data4_mux[] = {
1641 SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
1642};
1643static const unsigned int sdhi1_ctrl_pins[] = {
1644 /* CMD, CLK */
1645 184, 179,
1646};
1647static const unsigned int sdhi1_ctrl_mux[] = {
1648 SDHICMD1_MARK, SDHICLK1_MARK,
1649};
1650
1651static const unsigned int sdhi2_data1_pins[] = {
1652 /* D0 */
1653 186,
1654};
1655static const unsigned int sdhi2_data1_mux[] = {
1656 SDHID2_0_MARK,
1657};
1658static const unsigned int sdhi2_data4_pins[] = {
1659 /* D[0:3] */
1660 186, 187, 188, 189,
1661};
1662static const unsigned int sdhi2_data4_mux[] = {
1663 SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
1664};
1665static const unsigned int sdhi2_ctrl_pins[] = {
1666 /* CMD, CLK */
1667 190, 185,
1668};
1669static const unsigned int sdhi2_ctrl_mux[] = {
1670 SDHICMD2_MARK, SDHICLK2_MARK,
1671};
1672/* - USB0 ------------------------------------------------------------------- */
1673static const unsigned int usb0_vbus_pins[] = {
1674 /* VBUS */
1675 167,
1676};
1677static const unsigned int usb0_vbus_mux[] = {
1678 VBUS0_0_MARK,
1679};
1680static const unsigned int usb0_otg_id_pins[] = {
1681 /* IDIN */
1682 113,
1683};
1684static const unsigned int usb0_otg_id_mux[] = {
1685 IDIN_0_MARK,
1686};
1687static const unsigned int usb0_otg_ctrl_pins[] = {
1688 /* PWEN, EXTLP, OVCN, OVCN2 */
1689 116, 114, 117, 115,
1690};
1691static const unsigned int usb0_otg_ctrl_mux[] = {
1692 PWEN_0_MARK, EXTLP_0_MARK, OVCN_0_MARK, OVCN2_0_MARK,
1693};
1694/* - USB1 ------------------------------------------------------------------- */
1695static const unsigned int usb1_vbus_pins[] = {
1696 /* VBUS */
1697 168,
1698};
1699static const unsigned int usb1_vbus_mux[] = {
1700 VBUS0_1_MARK,
1701};
1702static const unsigned int usb1_otg_id_0_pins[] = {
1703 /* IDIN */
1704 113,
1705};
1706static const unsigned int usb1_otg_id_0_mux[] = {
1707 IDIN_1_113_MARK,
1708};
1709static const unsigned int usb1_otg_id_1_pins[] = {
1710 /* IDIN */
1711 18,
1712};
1713static const unsigned int usb1_otg_id_1_mux[] = {
1714 IDIN_1_18_MARK,
1715};
1716static const unsigned int usb1_otg_ctrl_0_pins[] = {
1717 /* PWEN, EXTLP, OVCN, OVCN2 */
1718 115, 116, 114, 117, 113,
1719};
1720static const unsigned int usb1_otg_ctrl_0_mux[] = {
1721 PWEN_1_115_MARK, EXTLP_1_MARK, OVCN_1_114_MARK, OVCN2_1_MARK,
1722};
1723static const unsigned int usb1_otg_ctrl_1_pins[] = {
1724 /* PWEN, EXTLP, OVCN, OVCN2 */
1725 138, 116, 162, 117, 18,
1726};
1727static const unsigned int usb1_otg_ctrl_1_mux[] = {
1728 PWEN_1_138_MARK, EXTLP_1_MARK, OVCN_1_162_MARK, OVCN2_1_MARK,
1729};
1730
1731static const struct sh_pfc_pin_group pinmux_groups[] = {
1732 SH_PFC_PIN_GROUP(bsc_data8),
1733 SH_PFC_PIN_GROUP(bsc_data16),
1734 SH_PFC_PIN_GROUP(bsc_cs0),
1735 SH_PFC_PIN_GROUP(bsc_cs2),
1736 SH_PFC_PIN_GROUP(bsc_cs4),
1737 SH_PFC_PIN_GROUP(bsc_cs5a),
1738 SH_PFC_PIN_GROUP(bsc_cs5b),
1739 SH_PFC_PIN_GROUP(bsc_cs6a),
1740 SH_PFC_PIN_GROUP(bsc_rd_we8),
1741 SH_PFC_PIN_GROUP(bsc_rd_we16),
1742 SH_PFC_PIN_GROUP(bsc_bs),
1743 SH_PFC_PIN_GROUP(bsc_rdwr),
1744 SH_PFC_PIN_GROUP(ceu_data_0_7),
1745 SH_PFC_PIN_GROUP(ceu_data_8_15),
1746 SH_PFC_PIN_GROUP(ceu_clk_0),
1747 SH_PFC_PIN_GROUP(ceu_clk_1),
1748 SH_PFC_PIN_GROUP(ceu_clk_2),
1749 SH_PFC_PIN_GROUP(ceu_sync),
1750 SH_PFC_PIN_GROUP(ceu_field),
1751 SH_PFC_PIN_GROUP(flctl_data),
1752 SH_PFC_PIN_GROUP(flctl_ce0),
1753 SH_PFC_PIN_GROUP(flctl_ce1),
1754 SH_PFC_PIN_GROUP(flctl_ctrl),
1755 SH_PFC_PIN_GROUP(fsia_mclk_in),
1756 SH_PFC_PIN_GROUP(fsia_mclk_out),
1757 SH_PFC_PIN_GROUP(fsia_sclk_in),
1758 SH_PFC_PIN_GROUP(fsia_sclk_out),
1759 SH_PFC_PIN_GROUP(fsia_data_in),
1760 SH_PFC_PIN_GROUP(fsia_data_out),
1761 SH_PFC_PIN_GROUP(fsia_spdif_0),
1762 SH_PFC_PIN_GROUP(fsia_spdif_1),
1763 SH_PFC_PIN_GROUP(fsib_mclk_in),
1764 SH_PFC_PIN_GROUP(hdmi),
1765 SH_PFC_PIN_GROUP(intc_irq0_0),
1766 SH_PFC_PIN_GROUP(intc_irq0_1),
1767 SH_PFC_PIN_GROUP(intc_irq1),
1768 SH_PFC_PIN_GROUP(intc_irq2_0),
1769 SH_PFC_PIN_GROUP(intc_irq2_1),
1770 SH_PFC_PIN_GROUP(intc_irq3_0),
1771 SH_PFC_PIN_GROUP(intc_irq3_1),
1772 SH_PFC_PIN_GROUP(intc_irq4_0),
1773 SH_PFC_PIN_GROUP(intc_irq4_1),
1774 SH_PFC_PIN_GROUP(intc_irq5),
1775 SH_PFC_PIN_GROUP(intc_irq6_0),
1776 SH_PFC_PIN_GROUP(intc_irq6_1),
1777 SH_PFC_PIN_GROUP(intc_irq7_0),
1778 SH_PFC_PIN_GROUP(intc_irq7_1),
1779 SH_PFC_PIN_GROUP(intc_irq8_0),
1780 SH_PFC_PIN_GROUP(intc_irq8_1),
1781 SH_PFC_PIN_GROUP(intc_irq9_0),
1782 SH_PFC_PIN_GROUP(intc_irq9_1),
1783 SH_PFC_PIN_GROUP(intc_irq10),
1784 SH_PFC_PIN_GROUP(intc_irq11),
1785 SH_PFC_PIN_GROUP(intc_irq12_0),
1786 SH_PFC_PIN_GROUP(intc_irq12_1),
1787 SH_PFC_PIN_GROUP(intc_irq13_0),
1788 SH_PFC_PIN_GROUP(intc_irq13_1),
1789 SH_PFC_PIN_GROUP(intc_irq14_0),
1790 SH_PFC_PIN_GROUP(intc_irq14_1),
1791 SH_PFC_PIN_GROUP(intc_irq15_0),
1792 SH_PFC_PIN_GROUP(intc_irq15_1),
1793 SH_PFC_PIN_GROUP(intc_irq16_0),
1794 SH_PFC_PIN_GROUP(intc_irq16_1),
1795 SH_PFC_PIN_GROUP(intc_irq17),
1796 SH_PFC_PIN_GROUP(intc_irq18),
1797 SH_PFC_PIN_GROUP(intc_irq19),
1798 SH_PFC_PIN_GROUP(intc_irq20),
1799 SH_PFC_PIN_GROUP(intc_irq21),
1800 SH_PFC_PIN_GROUP(intc_irq22),
1801 SH_PFC_PIN_GROUP(intc_irq23),
1802 SH_PFC_PIN_GROUP(intc_irq24),
1803 SH_PFC_PIN_GROUP(intc_irq25),
1804 SH_PFC_PIN_GROUP(intc_irq26_0),
1805 SH_PFC_PIN_GROUP(intc_irq26_1),
1806 SH_PFC_PIN_GROUP(intc_irq27_0),
1807 SH_PFC_PIN_GROUP(intc_irq27_1),
1808 SH_PFC_PIN_GROUP(intc_irq28_0),
1809 SH_PFC_PIN_GROUP(intc_irq28_1),
1810 SH_PFC_PIN_GROUP(intc_irq29_0),
1811 SH_PFC_PIN_GROUP(intc_irq29_1),
1812 SH_PFC_PIN_GROUP(intc_irq30_0),
1813 SH_PFC_PIN_GROUP(intc_irq30_1),
1814 SH_PFC_PIN_GROUP(intc_irq31_0),
1815 SH_PFC_PIN_GROUP(intc_irq31_1),
1816 SH_PFC_PIN_GROUP(keysc_in04_0),
1817 SH_PFC_PIN_GROUP(keysc_in04_1),
1818 SH_PFC_PIN_GROUP(keysc_in5),
1819 SH_PFC_PIN_GROUP(keysc_in6),
1820 SH_PFC_PIN_GROUP(keysc_in7),
1821 SH_PFC_PIN_GROUP(keysc_out4),
1822 SH_PFC_PIN_GROUP(keysc_out5),
1823 SH_PFC_PIN_GROUP(keysc_out6),
1824 SH_PFC_PIN_GROUP(keysc_out8),
1825 SH_PFC_PIN_GROUP(lcd_data8),
1826 SH_PFC_PIN_GROUP(lcd_data9),
1827 SH_PFC_PIN_GROUP(lcd_data12),
1828 SH_PFC_PIN_GROUP(lcd_data16),
1829 SH_PFC_PIN_GROUP(lcd_data18),
1830 SH_PFC_PIN_GROUP(lcd_data24),
1831 SH_PFC_PIN_GROUP(lcd_display),
1832 SH_PFC_PIN_GROUP(lcd_lclk),
1833 SH_PFC_PIN_GROUP(lcd_sync),
1834 SH_PFC_PIN_GROUP(lcd_sys),
1835 SH_PFC_PIN_GROUP(mmc0_data1_0),
1836 SH_PFC_PIN_GROUP(mmc0_data4_0),
1837 SH_PFC_PIN_GROUP(mmc0_data8_0),
1838 SH_PFC_PIN_GROUP(mmc0_ctrl_0),
1839 SH_PFC_PIN_GROUP(mmc0_data1_1),
1840 SH_PFC_PIN_GROUP(mmc0_data4_1),
1841 SH_PFC_PIN_GROUP(mmc0_data8_1),
1842 SH_PFC_PIN_GROUP(mmc0_ctrl_1),
1843 SH_PFC_PIN_GROUP(scifa0_data),
1844 SH_PFC_PIN_GROUP(scifa0_clk),
1845 SH_PFC_PIN_GROUP(scifa0_ctrl),
1846 SH_PFC_PIN_GROUP(scifa1_data),
1847 SH_PFC_PIN_GROUP(scifa1_clk),
1848 SH_PFC_PIN_GROUP(scifa1_ctrl),
1849 SH_PFC_PIN_GROUP(scifa2_data),
1850 SH_PFC_PIN_GROUP(scifa2_clk),
1851 SH_PFC_PIN_GROUP(scifa2_ctrl),
1852 SH_PFC_PIN_GROUP(scifa3_data),
1853 SH_PFC_PIN_GROUP(scifa3_clk),
1854 SH_PFC_PIN_GROUP(scifa3_ctrl_0),
1855 SH_PFC_PIN_GROUP(scifa3_ctrl_1),
1856 SH_PFC_PIN_GROUP(scifa4_data),
1857 SH_PFC_PIN_GROUP(scifa5_data),
1858 SH_PFC_PIN_GROUP(scifb_data),
1859 SH_PFC_PIN_GROUP(scifb_clk),
1860 SH_PFC_PIN_GROUP(scifb_ctrl),
1861 SH_PFC_PIN_GROUP(sdhi0_data1),
1862 SH_PFC_PIN_GROUP(sdhi0_data4),
1863 SH_PFC_PIN_GROUP(sdhi0_ctrl),
1864 SH_PFC_PIN_GROUP(sdhi0_cd),
1865 SH_PFC_PIN_GROUP(sdhi0_wp),
1866 SH_PFC_PIN_GROUP(sdhi1_data1),
1867 SH_PFC_PIN_GROUP(sdhi1_data4),
1868 SH_PFC_PIN_GROUP(sdhi1_ctrl),
1869 SH_PFC_PIN_GROUP(sdhi2_data1),
1870 SH_PFC_PIN_GROUP(sdhi2_data4),
1871 SH_PFC_PIN_GROUP(sdhi2_ctrl),
1872 SH_PFC_PIN_GROUP(usb0_vbus),
1873 SH_PFC_PIN_GROUP(usb0_otg_id),
1874 SH_PFC_PIN_GROUP(usb0_otg_ctrl),
1875 SH_PFC_PIN_GROUP(usb1_vbus),
1876 SH_PFC_PIN_GROUP(usb1_otg_id_0),
1877 SH_PFC_PIN_GROUP(usb1_otg_id_1),
1878 SH_PFC_PIN_GROUP(usb1_otg_ctrl_0),
1879 SH_PFC_PIN_GROUP(usb1_otg_ctrl_1),
1880};
1881
1882static const char * const bsc_groups[] = {
1883 "bsc_data8",
1884 "bsc_data16",
1885 "bsc_cs0",
1886 "bsc_cs2",
1887 "bsc_cs4",
1888 "bsc_cs5a",
1889 "bsc_cs5b",
1890 "bsc_cs6a",
1891 "bsc_rd_we8",
1892 "bsc_rd_we16",
1893 "bsc_bs",
1894 "bsc_rdwr",
1895};
1896
1897static const char * const ceu_groups[] = {
1898 "ceu_data_0_7",
1899 "ceu_data_8_15",
1900 "ceu_clk_0",
1901 "ceu_clk_1",
1902 "ceu_clk_2",
1903 "ceu_sync",
1904 "ceu_field",
1905};
1906
1907static const char * const flctl_groups[] = {
1908 "flctl_data",
1909 "flctl_ce0",
1910 "flctl_ce1",
1911 "flctl_ctrl",
1912};
1913
1914static const char * const fsia_groups[] = {
1915 "fsia_mclk_in",
1916 "fsia_mclk_out",
1917 "fsia_sclk_in",
1918 "fsia_sclk_out",
1919 "fsia_data_in",
1920 "fsia_data_out",
1921 "fsia_spdif_0",
1922 "fsia_spdif_1",
1923};
1924
1925static const char * const fsib_groups[] = {
1926 "fsib_mclk_in",
1927};
1928
1929static const char * const hdmi_groups[] = {
1930 "hdmi",
1931};
1932
1933static const char * const intc_groups[] = {
1934 "intc_irq0_0",
1935 "intc_irq0_1",
1936 "intc_irq1",
1937 "intc_irq2_0",
1938 "intc_irq2_1",
1939 "intc_irq3_0",
1940 "intc_irq3_1",
1941 "intc_irq4_0",
1942 "intc_irq4_1",
1943 "intc_irq5",
1944 "intc_irq6_0",
1945 "intc_irq6_1",
1946 "intc_irq7_0",
1947 "intc_irq7_1",
1948 "intc_irq8_0",
1949 "intc_irq8_1",
1950 "intc_irq9_0",
1951 "intc_irq9_1",
1952 "intc_irq10",
1953 "intc_irq11",
1954 "intc_irq12_0",
1955 "intc_irq12_1",
1956 "intc_irq13_0",
1957 "intc_irq13_1",
1958 "intc_irq14_0",
1959 "intc_irq14_1",
1960 "intc_irq15_0",
1961 "intc_irq15_1",
1962 "intc_irq16_0",
1963 "intc_irq16_1",
1964 "intc_irq17",
1965 "intc_irq18",
1966 "intc_irq19",
1967 "intc_irq20",
1968 "intc_irq21",
1969 "intc_irq22",
1970 "intc_irq23",
1971 "intc_irq24",
1972 "intc_irq25",
1973 "intc_irq26_0",
1974 "intc_irq26_1",
1975 "intc_irq27_0",
1976 "intc_irq27_1",
1977 "intc_irq28_0",
1978 "intc_irq28_1",
1979 "intc_irq29_0",
1980 "intc_irq29_1",
1981 "intc_irq30_0",
1982 "intc_irq30_1",
1983 "intc_irq31_0",
1984 "intc_irq31_1",
1985};
1986
1987static const char * const keysc_groups[] = {
1988 "keysc_in04_0",
1989 "keysc_in04_1",
1990 "keysc_in5",
1991 "keysc_in6",
1992 "keysc_in7",
1993 "keysc_out4",
1994 "keysc_out5",
1995 "keysc_out6",
1996 "keysc_out8",
1997};
1998
1999static const char * const lcd_groups[] = {
2000 "lcd_data8",
2001 "lcd_data9",
2002 "lcd_data12",
2003 "lcd_data16",
2004 "lcd_data18",
2005 "lcd_data24",
2006 "lcd_display",
2007 "lcd_lclk",
2008 "lcd_sync",
2009 "lcd_sys",
2010};
2011
2012static const char * const mmc0_groups[] = {
2013 "mmc0_data1_0",
2014 "mmc0_data4_0",
2015 "mmc0_data8_0",
2016 "mmc0_ctrl_0",
2017 "mmc0_data1_1",
2018 "mmc0_data4_1",
2019 "mmc0_data8_1",
2020 "mmc0_ctrl_1",
2021};
2022
2023static const char * const scifa0_groups[] = {
2024 "scifa0_data",
2025 "scifa0_clk",
2026 "scifa0_ctrl",
2027};
2028
2029static const char * const scifa1_groups[] = {
2030 "scifa1_data",
2031 "scifa1_clk",
2032 "scifa1_ctrl",
2033};
2034
2035static const char * const scifa2_groups[] = {
2036 "scifa2_data",
2037 "scifa2_clk",
2038 "scifa2_ctrl",
2039};
2040
2041static const char * const scifa3_groups[] = {
2042 "scifa3_data",
2043 "scifa3_clk",
2044 "scifa3_ctrl_0",
2045 "scifa3_ctrl_1",
2046};
2047
2048static const char * const scifa4_groups[] = {
2049 "scifa4_data",
2050};
2051
2052static const char * const scifa5_groups[] = {
2053 "scifa5_data",
2054};
2055
2056static const char * const scifb_groups[] = {
2057 "scifb_data",
2058 "scifb_clk",
2059 "scifb_ctrl",
2060};
2061
2062static const char * const sdhi0_groups[] = {
2063 "sdhi0_data1",
2064 "sdhi0_data4",
2065 "sdhi0_ctrl",
2066 "sdhi0_cd",
2067 "sdhi0_wp",
2068};
2069
2070static const char * const sdhi1_groups[] = {
2071 "sdhi1_data1",
2072 "sdhi1_data4",
2073 "sdhi1_ctrl",
2074};
2075
2076static const char * const sdhi2_groups[] = {
2077 "sdhi2_data1",
2078 "sdhi2_data4",
2079 "sdhi2_ctrl",
2080};
2081
2082static const char * const usb0_groups[] = {
2083 "usb0_vbus",
2084 "usb0_otg_id",
2085 "usb0_otg_ctrl",
2086};
2087
2088static const char * const usb1_groups[] = {
2089 "usb1_vbus",
2090 "usb1_otg_id_0",
2091 "usb1_otg_id_1",
2092 "usb1_otg_ctrl_0",
2093 "usb1_otg_ctrl_1",
2094};
2095
2096static const struct sh_pfc_function pinmux_functions[] = {
2097 SH_PFC_FUNCTION(bsc),
2098 SH_PFC_FUNCTION(ceu),
2099 SH_PFC_FUNCTION(flctl),
2100 SH_PFC_FUNCTION(fsia),
2101 SH_PFC_FUNCTION(fsib),
2102 SH_PFC_FUNCTION(hdmi),
2103 SH_PFC_FUNCTION(intc),
2104 SH_PFC_FUNCTION(keysc),
2105 SH_PFC_FUNCTION(lcd),
2106 SH_PFC_FUNCTION(mmc0),
2107 SH_PFC_FUNCTION(scifa0),
2108 SH_PFC_FUNCTION(scifa1),
2109 SH_PFC_FUNCTION(scifa2),
2110 SH_PFC_FUNCTION(scifa3),
2111 SH_PFC_FUNCTION(scifa4),
2112 SH_PFC_FUNCTION(scifa5),
2113 SH_PFC_FUNCTION(scifb),
2114 SH_PFC_FUNCTION(sdhi0),
2115 SH_PFC_FUNCTION(sdhi1),
2116 SH_PFC_FUNCTION(sdhi2),
2117 SH_PFC_FUNCTION(usb0),
2118 SH_PFC_FUNCTION(usb1),
2119};
2120
2121static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2122 PORTCR(0, 0xE6051000), /* PORT0CR */
2123 PORTCR(1, 0xE6051001), /* PORT1CR */
2124 PORTCR(2, 0xE6051002), /* PORT2CR */
2125 PORTCR(3, 0xE6051003), /* PORT3CR */
2126 PORTCR(4, 0xE6051004), /* PORT4CR */
2127 PORTCR(5, 0xE6051005), /* PORT5CR */
2128 PORTCR(6, 0xE6051006), /* PORT6CR */
2129 PORTCR(7, 0xE6051007), /* PORT7CR */
2130 PORTCR(8, 0xE6051008), /* PORT8CR */
2131 PORTCR(9, 0xE6051009), /* PORT9CR */
2132 PORTCR(10, 0xE605100A), /* PORT10CR */
2133 PORTCR(11, 0xE605100B), /* PORT11CR */
2134 PORTCR(12, 0xE605100C), /* PORT12CR */
2135 PORTCR(13, 0xE605100D), /* PORT13CR */
2136 PORTCR(14, 0xE605100E), /* PORT14CR */
2137 PORTCR(15, 0xE605100F), /* PORT15CR */
2138 PORTCR(16, 0xE6051010), /* PORT16CR */
2139 PORTCR(17, 0xE6051011), /* PORT17CR */
2140 PORTCR(18, 0xE6051012), /* PORT18CR */
2141 PORTCR(19, 0xE6051013), /* PORT19CR */
2142 PORTCR(20, 0xE6051014), /* PORT20CR */
2143 PORTCR(21, 0xE6051015), /* PORT21CR */
2144 PORTCR(22, 0xE6051016), /* PORT22CR */
2145 PORTCR(23, 0xE6051017), /* PORT23CR */
2146 PORTCR(24, 0xE6051018), /* PORT24CR */
2147 PORTCR(25, 0xE6051019), /* PORT25CR */
2148 PORTCR(26, 0xE605101A), /* PORT26CR */
2149 PORTCR(27, 0xE605101B), /* PORT27CR */
2150 PORTCR(28, 0xE605101C), /* PORT28CR */
2151 PORTCR(29, 0xE605101D), /* PORT29CR */
2152 PORTCR(30, 0xE605101E), /* PORT30CR */
2153 PORTCR(31, 0xE605101F), /* PORT31CR */
2154 PORTCR(32, 0xE6051020), /* PORT32CR */
2155 PORTCR(33, 0xE6051021), /* PORT33CR */
2156 PORTCR(34, 0xE6051022), /* PORT34CR */
2157 PORTCR(35, 0xE6051023), /* PORT35CR */
2158 PORTCR(36, 0xE6051024), /* PORT36CR */
2159 PORTCR(37, 0xE6051025), /* PORT37CR */
2160 PORTCR(38, 0xE6051026), /* PORT38CR */
2161 PORTCR(39, 0xE6051027), /* PORT39CR */
2162 PORTCR(40, 0xE6051028), /* PORT40CR */
2163 PORTCR(41, 0xE6051029), /* PORT41CR */
2164 PORTCR(42, 0xE605102A), /* PORT42CR */
2165 PORTCR(43, 0xE605102B), /* PORT43CR */
2166 PORTCR(44, 0xE605102C), /* PORT44CR */
2167 PORTCR(45, 0xE605102D), /* PORT45CR */
2168 PORTCR(46, 0xE605202E), /* PORT46CR */
2169 PORTCR(47, 0xE605202F), /* PORT47CR */
2170 PORTCR(48, 0xE6052030), /* PORT48CR */
2171 PORTCR(49, 0xE6052031), /* PORT49CR */
2172 PORTCR(50, 0xE6052032), /* PORT50CR */
2173 PORTCR(51, 0xE6052033), /* PORT51CR */
2174 PORTCR(52, 0xE6052034), /* PORT52CR */
2175 PORTCR(53, 0xE6052035), /* PORT53CR */
2176 PORTCR(54, 0xE6052036), /* PORT54CR */
2177 PORTCR(55, 0xE6052037), /* PORT55CR */
2178 PORTCR(56, 0xE6052038), /* PORT56CR */
2179 PORTCR(57, 0xE6052039), /* PORT57CR */
2180 PORTCR(58, 0xE605203A), /* PORT58CR */
2181 PORTCR(59, 0xE605203B), /* PORT59CR */
2182 PORTCR(60, 0xE605203C), /* PORT60CR */
2183 PORTCR(61, 0xE605203D), /* PORT61CR */
2184 PORTCR(62, 0xE605203E), /* PORT62CR */
2185 PORTCR(63, 0xE605203F), /* PORT63CR */
2186 PORTCR(64, 0xE6052040), /* PORT64CR */
2187 PORTCR(65, 0xE6052041), /* PORT65CR */
2188 PORTCR(66, 0xE6052042), /* PORT66CR */
2189 PORTCR(67, 0xE6052043), /* PORT67CR */
2190 PORTCR(68, 0xE6052044), /* PORT68CR */
2191 PORTCR(69, 0xE6052045), /* PORT69CR */
2192 PORTCR(70, 0xE6052046), /* PORT70CR */
2193 PORTCR(71, 0xE6052047), /* PORT71CR */
2194 PORTCR(72, 0xE6052048), /* PORT72CR */
2195 PORTCR(73, 0xE6052049), /* PORT73CR */
2196 PORTCR(74, 0xE605204A), /* PORT74CR */
2197 PORTCR(75, 0xE605204B), /* PORT75CR */
2198 PORTCR(76, 0xE605004C), /* PORT76CR */
2199 PORTCR(77, 0xE605004D), /* PORT77CR */
2200 PORTCR(78, 0xE605004E), /* PORT78CR */
2201 PORTCR(79, 0xE605004F), /* PORT79CR */
2202 PORTCR(80, 0xE6050050), /* PORT80CR */
2203 PORTCR(81, 0xE6050051), /* PORT81CR */
2204 PORTCR(82, 0xE6050052), /* PORT82CR */
2205 PORTCR(83, 0xE6050053), /* PORT83CR */
2206 PORTCR(84, 0xE6050054), /* PORT84CR */
2207 PORTCR(85, 0xE6050055), /* PORT85CR */
2208 PORTCR(86, 0xE6050056), /* PORT86CR */
2209 PORTCR(87, 0xE6050057), /* PORT87CR */
2210 PORTCR(88, 0xE6050058), /* PORT88CR */
2211 PORTCR(89, 0xE6050059), /* PORT89CR */
2212 PORTCR(90, 0xE605005A), /* PORT90CR */
2213 PORTCR(91, 0xE605005B), /* PORT91CR */
2214 PORTCR(92, 0xE605005C), /* PORT92CR */
2215 PORTCR(93, 0xE605005D), /* PORT93CR */
2216 PORTCR(94, 0xE605005E), /* PORT94CR */
2217 PORTCR(95, 0xE605005F), /* PORT95CR */
2218 PORTCR(96, 0xE6050060), /* PORT96CR */
2219 PORTCR(97, 0xE6050061), /* PORT97CR */
2220 PORTCR(98, 0xE6050062), /* PORT98CR */
2221 PORTCR(99, 0xE6050063), /* PORT99CR */
2222 PORTCR(100, 0xE6053064), /* PORT100CR */
2223 PORTCR(101, 0xE6053065), /* PORT101CR */
2224 PORTCR(102, 0xE6053066), /* PORT102CR */
2225 PORTCR(103, 0xE6053067), /* PORT103CR */
2226 PORTCR(104, 0xE6053068), /* PORT104CR */
2227 PORTCR(105, 0xE6053069), /* PORT105CR */
2228 PORTCR(106, 0xE605306A), /* PORT106CR */
2229 PORTCR(107, 0xE605306B), /* PORT107CR */
2230 PORTCR(108, 0xE605306C), /* PORT108CR */
2231 PORTCR(109, 0xE605306D), /* PORT109CR */
2232 PORTCR(110, 0xE605306E), /* PORT110CR */
2233 PORTCR(111, 0xE605306F), /* PORT111CR */
2234 PORTCR(112, 0xE6053070), /* PORT112CR */
2235 PORTCR(113, 0xE6053071), /* PORT113CR */
2236 PORTCR(114, 0xE6053072), /* PORT114CR */
2237 PORTCR(115, 0xE6053073), /* PORT115CR */
2238 PORTCR(116, 0xE6053074), /* PORT116CR */
2239 PORTCR(117, 0xE6053075), /* PORT117CR */
2240 PORTCR(118, 0xE6053076), /* PORT118CR */
2241 PORTCR(119, 0xE6053077), /* PORT119CR */
2242 PORTCR(120, 0xE6053078), /* PORT120CR */
2243 PORTCR(121, 0xE6050079), /* PORT121CR */
2244 PORTCR(122, 0xE605007A), /* PORT122CR */
2245 PORTCR(123, 0xE605007B), /* PORT123CR */
2246 PORTCR(124, 0xE605007C), /* PORT124CR */
2247 PORTCR(125, 0xE605007D), /* PORT125CR */
2248 PORTCR(126, 0xE605007E), /* PORT126CR */
2249 PORTCR(127, 0xE605007F), /* PORT127CR */
2250 PORTCR(128, 0xE6050080), /* PORT128CR */
2251 PORTCR(129, 0xE6050081), /* PORT129CR */
2252 PORTCR(130, 0xE6050082), /* PORT130CR */
2253 PORTCR(131, 0xE6050083), /* PORT131CR */
2254 PORTCR(132, 0xE6050084), /* PORT132CR */
2255 PORTCR(133, 0xE6050085), /* PORT133CR */
2256 PORTCR(134, 0xE6050086), /* PORT134CR */
2257 PORTCR(135, 0xE6050087), /* PORT135CR */
2258 PORTCR(136, 0xE6050088), /* PORT136CR */
2259 PORTCR(137, 0xE6050089), /* PORT137CR */
2260 PORTCR(138, 0xE605008A), /* PORT138CR */
2261 PORTCR(139, 0xE605008B), /* PORT139CR */
2262 PORTCR(140, 0xE605008C), /* PORT140CR */
2263 PORTCR(141, 0xE605008D), /* PORT141CR */
2264 PORTCR(142, 0xE605008E), /* PORT142CR */
2265 PORTCR(143, 0xE605008F), /* PORT143CR */
2266 PORTCR(144, 0xE6050090), /* PORT144CR */
2267 PORTCR(145, 0xE6050091), /* PORT145CR */
2268 PORTCR(146, 0xE6050092), /* PORT146CR */
2269 PORTCR(147, 0xE6050093), /* PORT147CR */
2270 PORTCR(148, 0xE6050094), /* PORT148CR */
2271 PORTCR(149, 0xE6050095), /* PORT149CR */
2272 PORTCR(150, 0xE6050096), /* PORT150CR */
2273 PORTCR(151, 0xE6050097), /* PORT151CR */
2274 PORTCR(152, 0xE6053098), /* PORT152CR */
2275 PORTCR(153, 0xE6053099), /* PORT153CR */
2276 PORTCR(154, 0xE605309A), /* PORT154CR */
2277 PORTCR(155, 0xE605309B), /* PORT155CR */
2278 PORTCR(156, 0xE605009C), /* PORT156CR */
2279 PORTCR(157, 0xE605009D), /* PORT157CR */
2280 PORTCR(158, 0xE605009E), /* PORT158CR */
2281 PORTCR(159, 0xE605009F), /* PORT159CR */
2282 PORTCR(160, 0xE60500A0), /* PORT160CR */
2283 PORTCR(161, 0xE60500A1), /* PORT161CR */
2284 PORTCR(162, 0xE60500A2), /* PORT162CR */
2285 PORTCR(163, 0xE60500A3), /* PORT163CR */
2286 PORTCR(164, 0xE60500A4), /* PORT164CR */
2287 PORTCR(165, 0xE60500A5), /* PORT165CR */
2288 PORTCR(166, 0xE60500A6), /* PORT166CR */
2289 PORTCR(167, 0xE60520A7), /* PORT167CR */
2290 PORTCR(168, 0xE60520A8), /* PORT168CR */
2291 PORTCR(169, 0xE60520A9), /* PORT169CR */
2292 PORTCR(170, 0xE60520AA), /* PORT170CR */
2293 PORTCR(171, 0xE60520AB), /* PORT171CR */
2294 PORTCR(172, 0xE60520AC), /* PORT172CR */
2295 PORTCR(173, 0xE60520AD), /* PORT173CR */
2296 PORTCR(174, 0xE60520AE), /* PORT174CR */
2297 PORTCR(175, 0xE60520AF), /* PORT175CR */
2298 PORTCR(176, 0xE60520B0), /* PORT176CR */
2299 PORTCR(177, 0xE60520B1), /* PORT177CR */
2300 PORTCR(178, 0xE60520B2), /* PORT178CR */
2301 PORTCR(179, 0xE60520B3), /* PORT179CR */
2302 PORTCR(180, 0xE60520B4), /* PORT180CR */
2303 PORTCR(181, 0xE60520B5), /* PORT181CR */
2304 PORTCR(182, 0xE60520B6), /* PORT182CR */
2305 PORTCR(183, 0xE60520B7), /* PORT183CR */
2306 PORTCR(184, 0xE60520B8), /* PORT184CR */
2307 PORTCR(185, 0xE60520B9), /* PORT185CR */
2308 PORTCR(186, 0xE60520BA), /* PORT186CR */
2309 PORTCR(187, 0xE60520BB), /* PORT187CR */
2310 PORTCR(188, 0xE60520BC), /* PORT188CR */
2311 PORTCR(189, 0xE60520BD), /* PORT189CR */
2312 PORTCR(190, 0xE60520BE), /* PORT190CR */
2313
2314 { PINMUX_CFG_REG("MSEL1CR", 0xE605800C, 32, 1) {
2315 MSEL1CR_31_0, MSEL1CR_31_1,
2316 MSEL1CR_30_0, MSEL1CR_30_1,
2317 MSEL1CR_29_0, MSEL1CR_29_1,
2318 MSEL1CR_28_0, MSEL1CR_28_1,
2319 MSEL1CR_27_0, MSEL1CR_27_1,
2320 MSEL1CR_26_0, MSEL1CR_26_1,
2321 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2322 0, 0, 0, 0, 0, 0, 0, 0,
2323 MSEL1CR_16_0, MSEL1CR_16_1,
2324 MSEL1CR_15_0, MSEL1CR_15_1,
2325 MSEL1CR_14_0, MSEL1CR_14_1,
2326 MSEL1CR_13_0, MSEL1CR_13_1,
2327 MSEL1CR_12_0, MSEL1CR_12_1,
2328 0, 0, 0, 0,
2329 MSEL1CR_9_0, MSEL1CR_9_1,
2330 MSEL1CR_8_0, MSEL1CR_8_1,
2331 MSEL1CR_7_0, MSEL1CR_7_1,
2332 MSEL1CR_6_0, MSEL1CR_6_1,
2333 0, 0,
2334 MSEL1CR_4_0, MSEL1CR_4_1,
2335 MSEL1CR_3_0, MSEL1CR_3_1,
2336 MSEL1CR_2_0, MSEL1CR_2_1,
2337 0, 0,
2338 MSEL1CR_0_0, MSEL1CR_0_1,
2339 }
2340 },
2341 { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
2342 0, 0, 0, 0,
2343 0, 0, 0, 0,
2344 MSEL3CR_27_0, MSEL3CR_27_1,
2345 MSEL3CR_26_0, MSEL3CR_26_1,
2346 0, 0, 0, 0,
2347 0, 0, 0, 0,
2348 MSEL3CR_21_0, MSEL3CR_21_1,
2349 MSEL3CR_20_0, MSEL3CR_20_1,
2350 0, 0, 0, 0,
2351 0, 0, 0, 0,
2352 MSEL3CR_15_0, MSEL3CR_15_1,
2353 0, 0, 0, 0,
2354 0, 0, 0, 0,
2355 0, 0,
2356 MSEL3CR_9_0, MSEL3CR_9_1,
2357 0, 0, 0, 0,
2358 MSEL3CR_6_0, MSEL3CR_6_1,
2359 0, 0, 0, 0,
2360 0, 0, 0, 0,
2361 0, 0, 0, 0,
2362 }
2363 },
2364 { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
2365 0, 0, 0, 0,
2366 0, 0, 0, 0,
2367 0, 0, 0, 0,
2368 0, 0, 0, 0,
2369 0, 0, 0, 0,
2370 0, 0, 0, 0,
2371 MSEL4CR_19_0, MSEL4CR_19_1,
2372 MSEL4CR_18_0, MSEL4CR_18_1,
2373 MSEL4CR_17_0, MSEL4CR_17_1,
2374 MSEL4CR_16_0, MSEL4CR_16_1,
2375 MSEL4CR_15_0, MSEL4CR_15_1,
2376 MSEL4CR_14_0, MSEL4CR_14_1,
2377 0, 0, 0, 0,
2378 0, 0,
2379 MSEL4CR_10_0, MSEL4CR_10_1,
2380 0, 0, 0, 0,
2381 0, 0,
2382 MSEL4CR_6_0, MSEL4CR_6_1,
2383 0, 0,
2384 MSEL4CR_4_0, MSEL4CR_4_1,
2385 0, 0, 0, 0,
2386 MSEL4CR_1_0, MSEL4CR_1_1,
2387 0, 0,
2388 }
2389 },
2390 { },
2391};
2392
2393static const struct pinmux_data_reg pinmux_data_regs[] = {
2394 { PINMUX_DATA_REG("PORTL095_064DR", 0xE6054008, 32) {
2395 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
2396 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
2397 PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
2398 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
2399 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
2400 0, 0, 0, 0,
2401 0, 0, 0, 0,
2402 0, 0, 0, 0,
2403 }
2404 },
2405 { PINMUX_DATA_REG("PORTL127_096DR", 0xE605400C, 32) {
2406 PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
2407 PORT123_DATA, PORT122_DATA, PORT121_DATA, 0,
2408 0, 0, 0, 0,
2409 0, 0, 0, 0,
2410 0, 0, 0, 0,
2411 0, 0, 0, 0,
2412 0, 0, 0, 0,
2413 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA,
2414 }
2415 },
2416 { PINMUX_DATA_REG("PORTL159_128DR", 0xE6054010, 32) {
2417 PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
2418 0, 0, 0, 0,
2419 PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
2420 PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
2421 PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
2422 PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
2423 PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
2424 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA,
2425 }
2426 },
2427 { PINMUX_DATA_REG("PORTL191_160DR", 0xE6054014, 32) {
2428 0, 0, 0, 0,
2429 0, 0, 0, 0,
2430 0, 0, 0, 0,
2431 0, 0, 0, 0,
2432 0, 0, 0, 0,
2433 0, 0, 0, 0,
2434 0, PORT166_DATA, PORT165_DATA, PORT164_DATA,
2435 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA,
2436 }
2437 },
2438 { PINMUX_DATA_REG("PORTD031_000DR", 0xE6055000, 32) {
2439 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
2440 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
2441 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
2442 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
2443 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
2444 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
2445 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
2446 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA,
2447 }
2448 },
2449 { PINMUX_DATA_REG("PORTD063_032DR", 0xE6055004, 32) {
2450 0, 0, 0, 0, 0, 0, 0, 0,
2451 0, 0, 0, 0, 0, 0, 0, 0,
2452 0, 0, PORT45_DATA, PORT44_DATA,
2453 PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
2454 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
2455 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA,
2456 }
2457 },
2458 { PINMUX_DATA_REG("PORTR063_032DR", 0xE6056004, 32) {
2459 PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
2460 PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
2461 PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
2462 PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
2463 PORT47_DATA, PORT46_DATA, 0, 0,
2464 0, 0, 0, 0,
2465 0, 0, 0, 0,
2466 0, 0, 0, 0,
2467 }
2468 },
2469 { PINMUX_DATA_REG("PORTR095_064DR", 0xE6056008, 32) {
2470 0, 0, 0, 0,
2471 0, 0, 0, 0,
2472 0, 0, 0, 0,
2473 0, 0, 0, 0,
2474 0, 0, 0, 0,
2475 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
2476 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
2477 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA,
2478 }
2479 },
2480 { PINMUX_DATA_REG("PORTR191_160DR", 0xE6056014, 32) {
2481 0, PORT190_DATA, PORT189_DATA, PORT188_DATA,
2482 PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
2483 PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
2484 PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
2485 PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
2486 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
2487 PORT167_DATA, 0, 0, 0,
2488 0, 0, 0, 0,
2489 }
2490 },
2491 { PINMUX_DATA_REG("PORTU127_096DR", 0xE605700C, 32) {
2492 0, 0, 0, 0,
2493 0, 0, 0, PORT120_DATA,
2494 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
2495 PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
2496 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
2497 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
2498 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
2499 0, 0, 0, 0,
2500 }
2501 },
2502 { PINMUX_DATA_REG("PORTU159_128DR", 0xE6057010, 32) {
2503 0, 0, 0, 0,
2504 PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
2505 0, 0, 0, 0,
2506 0, 0, 0, 0,
2507 0, 0, 0, 0,
2508 0, 0, 0, 0,
2509 0, 0, 0, 0,
2510 0, 0, 0, 0,
2511 }
2512 },
2513 { },
2514};
2515
2516#define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5))
2517#define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5))
2518static const struct pinmux_irq pinmux_irqs[] = {
2519 PINMUX_IRQ(EXT_IRQ16L(0), 6, 162),
2520 PINMUX_IRQ(EXT_IRQ16L(1), 12),
2521 PINMUX_IRQ(EXT_IRQ16L(2), 4, 5),
2522 PINMUX_IRQ(EXT_IRQ16L(3), 8, 16),
2523 PINMUX_IRQ(EXT_IRQ16L(4), 17, 163),
2524 PINMUX_IRQ(EXT_IRQ16L(5), 18),
2525 PINMUX_IRQ(EXT_IRQ16L(6), 39, 164),
2526 PINMUX_IRQ(EXT_IRQ16L(7), 40, 167),
2527 PINMUX_IRQ(EXT_IRQ16L(8), 41, 168),
2528 PINMUX_IRQ(EXT_IRQ16L(9), 42, 169),
2529 PINMUX_IRQ(EXT_IRQ16L(10), 65),
2530 PINMUX_IRQ(EXT_IRQ16L(11), 67),
2531 PINMUX_IRQ(EXT_IRQ16L(12), 80, 137),
2532 PINMUX_IRQ(EXT_IRQ16L(13), 81, 145),
2533 PINMUX_IRQ(EXT_IRQ16L(14), 82, 146),
2534 PINMUX_IRQ(EXT_IRQ16L(15), 83, 147),
2535 PINMUX_IRQ(EXT_IRQ16H(16), 84, 170),
2536 PINMUX_IRQ(EXT_IRQ16H(17), 85),
2537 PINMUX_IRQ(EXT_IRQ16H(18), 86),
2538 PINMUX_IRQ(EXT_IRQ16H(19), 87),
2539 PINMUX_IRQ(EXT_IRQ16H(20), 92),
2540 PINMUX_IRQ(EXT_IRQ16H(21), 93),
2541 PINMUX_IRQ(EXT_IRQ16H(22), 94),
2542 PINMUX_IRQ(EXT_IRQ16H(23), 95),
2543 PINMUX_IRQ(EXT_IRQ16H(24), 112),
2544 PINMUX_IRQ(EXT_IRQ16H(25), 119),
2545 PINMUX_IRQ(EXT_IRQ16H(26), 121, 172),
2546 PINMUX_IRQ(EXT_IRQ16H(27), 122, 180),
2547 PINMUX_IRQ(EXT_IRQ16H(28), 123, 181),
2548 PINMUX_IRQ(EXT_IRQ16H(29), 129, 182),
2549 PINMUX_IRQ(EXT_IRQ16H(30), 130, 183),
2550 PINMUX_IRQ(EXT_IRQ16H(31), 138, 184),
2551};
2552
2553#define PORTnCR_PULMD_OFF (0 << 6)
2554#define PORTnCR_PULMD_DOWN (2 << 6)
2555#define PORTnCR_PULMD_UP (3 << 6)
2556#define PORTnCR_PULMD_MASK (3 << 6)
2557
2558struct sh7372_portcr_group {
2559 unsigned int end_pin;
2560 unsigned int offset;
2561};
2562
2563static const struct sh7372_portcr_group sh7372_portcr_offsets[] = {
2564 { 45, 0x1000 }, { 75, 0x2000 }, { 99, 0x0000 }, { 120, 0x3000 },
2565 { 151, 0x0000 }, { 155, 0x3000 }, { 166, 0x0000 }, { 190, 0x2000 },
2566};
2567
2568static void __iomem *sh7372_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
2569{
2570 unsigned int i;
2571
2572 for (i = 0; i < ARRAY_SIZE(sh7372_portcr_offsets); ++i) {
2573 const struct sh7372_portcr_group *group =
2574 &sh7372_portcr_offsets[i];
2575
2576 if (pin <= group->end_pin)
2577 return pfc->windows->virt + group->offset + pin;
2578 }
2579
2580 return NULL;
2581}
2582
2583static unsigned int sh7372_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
2584{
2585 void __iomem *addr = sh7372_pinmux_portcr(pfc, pin);
2586 u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
2587
2588 switch (value) {
2589 case PORTnCR_PULMD_UP:
2590 return PIN_CONFIG_BIAS_PULL_UP;
2591 case PORTnCR_PULMD_DOWN:
2592 return PIN_CONFIG_BIAS_PULL_DOWN;
2593 case PORTnCR_PULMD_OFF:
2594 default:
2595 return PIN_CONFIG_BIAS_DISABLE;
2596 }
2597}
2598
2599static void sh7372_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
2600 unsigned int bias)
2601{
2602 void __iomem *addr = sh7372_pinmux_portcr(pfc, pin);
2603 u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
2604
2605 switch (bias) {
2606 case PIN_CONFIG_BIAS_PULL_UP:
2607 value |= PORTnCR_PULMD_UP;
2608 break;
2609 case PIN_CONFIG_BIAS_PULL_DOWN:
2610 value |= PORTnCR_PULMD_DOWN;
2611 break;
2612 }
2613
2614 iowrite8(value, addr);
2615}
2616
2617static const struct sh_pfc_soc_operations sh7372_pfc_ops = {
2618 .get_bias = sh7372_pinmux_get_bias,
2619 .set_bias = sh7372_pinmux_set_bias,
2620};
2621
2622const struct sh_pfc_soc_info sh7372_pinmux_info = {
2623 .name = "sh7372_pfc",
2624 .ops = &sh7372_pfc_ops,
2625
2626 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2627 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2628 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2629
2630 .pins = pinmux_pins,
2631 .nr_pins = ARRAY_SIZE(pinmux_pins),
2632 .groups = pinmux_groups,
2633 .nr_groups = ARRAY_SIZE(pinmux_groups),
2634 .functions = pinmux_functions,
2635 .nr_functions = ARRAY_SIZE(pinmux_functions),
2636
2637 .cfg_regs = pinmux_config_regs,
2638 .data_regs = pinmux_data_regs,
2639
2640 .gpio_data = pinmux_data,
2641 .gpio_data_size = ARRAY_SIZE(pinmux_data),
2642
2643 .gpio_irq = pinmux_irqs,
2644 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
2645};
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index 910deaefa0ac..072e7c62cab7 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -122,7 +122,7 @@ static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np,
122 return ret; 122 return ret;
123 } 123 }
124 124
125 ret = pinconf_generic_parse_dt_config(np, &configs, &num_configs); 125 ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs);
126 if (ret < 0) 126 if (ret < 0)
127 return ret; 127 return ret;
128 128
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 5b7283182c1e..c83728626906 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -167,6 +167,8 @@ struct sh_pfc_soc_info {
167 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr) 167 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
168#define PINMUX_IPSR_NOGM(ispr, fn, ms) \ 168#define PINMUX_IPSR_NOGM(ispr, fn, ms) \
169 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ms) 169 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ms)
170#define PINMUX_IPSR_NOFN(ipsr, fn, ms) \
171 PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##ms)
170#define PINMUX_IPSR_MSEL(ipsr, fn, ms) \ 172#define PINMUX_IPSR_MSEL(ipsr, fn, ms) \
171 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr, FN_##ms) 173 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr, FN_##ms)
172#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) \ 174#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) \
diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c
index 4871647c7f85..2a1f07249b2f 100644
--- a/drivers/pinctrl/sirf/pinctrl-sirf.c
+++ b/drivers/pinctrl/sirf/pinctrl-sirf.c
@@ -38,7 +38,6 @@ struct sirfsoc_gpio_bank {
38 38
39struct sirfsoc_gpio_chip { 39struct sirfsoc_gpio_chip {
40 struct of_mm_gpio_chip chip; 40 struct of_mm_gpio_chip chip;
41 bool is_marco; /* for marco, some registers are different with prima2 */
42 struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS]; 41 struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
43}; 42};
44 43
@@ -149,23 +148,14 @@ static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx,
149 148
150 for (i = 0; i < mux->muxmask_counts; i++) { 149 for (i = 0; i < mux->muxmask_counts; i++) {
151 u32 muxval; 150 u32 muxval;
152 if (!spmx->is_marco) { 151 muxval = readl(spmx->gpio_virtbase +
153 muxval = readl(spmx->gpio_virtbase + 152 SIRFSOC_GPIO_PAD_EN(mask[i].group));
154 SIRFSOC_GPIO_PAD_EN(mask[i].group)); 153 if (enable)
155 if (enable) 154 muxval = muxval & ~mask[i].mask;
156 muxval = muxval & ~mask[i].mask; 155 else
157 else 156 muxval = muxval | mask[i].mask;
158 muxval = muxval | mask[i].mask; 157 writel(muxval, spmx->gpio_virtbase +
159 writel(muxval, spmx->gpio_virtbase + 158 SIRFSOC_GPIO_PAD_EN(mask[i].group));
160 SIRFSOC_GPIO_PAD_EN(mask[i].group));
161 } else {
162 if (enable)
163 writel(mask[i].mask, spmx->gpio_virtbase +
164 SIRFSOC_GPIO_PAD_EN_CLR(mask[i].group));
165 else
166 writel(mask[i].mask, spmx->gpio_virtbase +
167 SIRFSOC_GPIO_PAD_EN(mask[i].group));
168 }
169 } 159 }
170 160
171 if (mux->funcmask && enable) { 161 if (mux->funcmask && enable) {
@@ -223,16 +213,11 @@ static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
223 213
224 spmx = pinctrl_dev_get_drvdata(pmxdev); 214 spmx = pinctrl_dev_get_drvdata(pmxdev);
225 215
226 if (!spmx->is_marco) { 216 muxval = readl(spmx->gpio_virtbase +
227 muxval = readl(spmx->gpio_virtbase + 217 SIRFSOC_GPIO_PAD_EN(group));
228 SIRFSOC_GPIO_PAD_EN(group)); 218 muxval = muxval | (1 << (offset - range->pin_base));
229 muxval = muxval | (1 << (offset - range->pin_base)); 219 writel(muxval, spmx->gpio_virtbase +
230 writel(muxval, spmx->gpio_virtbase + 220 SIRFSOC_GPIO_PAD_EN(group));
231 SIRFSOC_GPIO_PAD_EN(group));
232 } else {
233 writel(1 << (offset - range->pin_base), spmx->gpio_virtbase +
234 SIRFSOC_GPIO_PAD_EN(group));
235 }
236 221
237 return 0; 222 return 0;
238} 223}
@@ -256,7 +241,6 @@ static void __iomem *sirfsoc_rsc_of_iomap(void)
256{ 241{
257 const struct of_device_id rsc_ids[] = { 242 const struct of_device_id rsc_ids[] = {
258 { .compatible = "sirf,prima2-rsc" }, 243 { .compatible = "sirf,prima2-rsc" },
259 { .compatible = "sirf,marco-rsc" },
260 {} 244 {}
261 }; 245 };
262 struct device_node *np; 246 struct device_node *np;
@@ -284,7 +268,6 @@ static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc,
284static const struct of_device_id pinmux_ids[] = { 268static const struct of_device_id pinmux_ids[] = {
285 { .compatible = "sirf,prima2-pinctrl", .data = &prima2_pinctrl_data, }, 269 { .compatible = "sirf,prima2-pinctrl", .data = &prima2_pinctrl_data, },
286 { .compatible = "sirf,atlas6-pinctrl", .data = &atlas6_pinctrl_data, }, 270 { .compatible = "sirf,atlas6-pinctrl", .data = &atlas6_pinctrl_data, },
287 { .compatible = "sirf,marco-pinctrl", .data = &prima2_pinctrl_data, },
288 {} 271 {}
289}; 272};
290 273
@@ -317,9 +300,6 @@ static int sirfsoc_pinmux_probe(struct platform_device *pdev)
317 goto out_no_rsc_remap; 300 goto out_no_rsc_remap;
318 } 301 }
319 302
320 if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
321 spmx->is_marco = 1;
322
323 pdata = of_match_node(pinmux_ids, np)->data; 303 pdata = of_match_node(pinmux_ids, np)->data;
324 sirfsoc_pin_groups = pdata->grps; 304 sirfsoc_pin_groups = pdata->grps;
325 sirfsoc_pingrp_cnt = pdata->grps_cnt; 305 sirfsoc_pingrp_cnt = pdata->grps_cnt;
@@ -803,7 +783,6 @@ static int sirfsoc_gpio_probe(struct device_node *np)
803 struct sirfsoc_gpio_bank *bank; 783 struct sirfsoc_gpio_bank *bank;
804 void __iomem *regs; 784 void __iomem *regs;
805 struct platform_device *pdev; 785 struct platform_device *pdev;
806 bool is_marco = false;
807 786
808 u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS]; 787 u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS];
809 788
@@ -819,9 +798,6 @@ static int sirfsoc_gpio_probe(struct device_node *np)
819 if (!regs) 798 if (!regs)
820 return -ENOMEM; 799 return -ENOMEM;
821 800
822 if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
823 is_marco = 1;
824
825 sgpio->chip.gc.request = sirfsoc_gpio_request; 801 sgpio->chip.gc.request = sirfsoc_gpio_request;
826 sgpio->chip.gc.free = sirfsoc_gpio_free; 802 sgpio->chip.gc.free = sirfsoc_gpio_free;
827 sgpio->chip.gc.direction_input = sirfsoc_gpio_direction_input; 803 sgpio->chip.gc.direction_input = sirfsoc_gpio_direction_input;
@@ -836,7 +812,6 @@ static int sirfsoc_gpio_probe(struct device_node *np)
836 sgpio->chip.gc.of_gpio_n_cells = 2; 812 sgpio->chip.gc.of_gpio_n_cells = 2;
837 sgpio->chip.gc.dev = &pdev->dev; 813 sgpio->chip.gc.dev = &pdev->dev;
838 sgpio->chip.regs = regs; 814 sgpio->chip.regs = regs;
839 sgpio->is_marco = is_marco;
840 815
841 err = gpiochip_add(&sgpio->chip.gc); 816 err = gpiochip_add(&sgpio->chip.gc);
842 if (err) { 817 if (err) {
diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.h b/drivers/pinctrl/sirf/pinctrl-sirf.h
index d7f16b499ad9..9550335fe57a 100644
--- a/drivers/pinctrl/sirf/pinctrl-sirf.h
+++ b/drivers/pinctrl/sirf/pinctrl-sirf.h
@@ -49,7 +49,6 @@ struct sirfsoc_pmx {
49 u32 paden_regs[SIRFSOC_GPIO_NO_OF_BANKS]; 49 u32 paden_regs[SIRFSOC_GPIO_NO_OF_BANKS];
50 u32 dspen_regs; 50 u32 dspen_regs;
51 u32 rsc_regs[3]; 51 u32 rsc_regs[3];
52 bool is_marco;
53}; 52};
54 53
55/* SIRFSOC_GPIO_PAD_EN set */ 54/* SIRFSOC_GPIO_PAD_EN set */
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 230a952608cb..2eb893e0ea1e 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -21,6 +21,10 @@ config PINCTRL_SUN6I_A31
21 def_bool MACH_SUN6I 21 def_bool MACH_SUN6I
22 select PINCTRL_SUNXI_COMMON 22 select PINCTRL_SUNXI_COMMON
23 23
24config PINCTRL_SUN6I_A31S
25 def_bool MACH_SUN6I
26 select PINCTRL_SUNXI_COMMON
27
24config PINCTRL_SUN6I_A31_R 28config PINCTRL_SUN6I_A31_R
25 def_bool MACH_SUN6I 29 def_bool MACH_SUN6I
26 depends on RESET_CONTROLLER 30 depends on RESET_CONTROLLER
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index c7d92e4673b5..b796d579dce6 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o
6obj-$(CONFIG_PINCTRL_SUN5I_A10S) += pinctrl-sun5i-a10s.o 6obj-$(CONFIG_PINCTRL_SUN5I_A10S) += pinctrl-sun5i-a10s.o
7obj-$(CONFIG_PINCTRL_SUN5I_A13) += pinctrl-sun5i-a13.o 7obj-$(CONFIG_PINCTRL_SUN5I_A13) += pinctrl-sun5i-a13.o
8obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o 8obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o
9obj-$(CONFIG_PINCTRL_SUN6I_A31S) += pinctrl-sun6i-a31s.o
9obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o 10obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o
10obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o 11obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o
11obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o 12obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
index f42858eaca28..18038f0d6b52 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
@@ -134,24 +134,28 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
134 SUNXI_FUNCTION(0x1, "gpio_out"), 134 SUNXI_FUNCTION(0x1, "gpio_out"),
135 SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */ 135 SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
136 SUNXI_FUNCTION(0x3, "lcd1"), /* D15 */ 136 SUNXI_FUNCTION(0x3, "lcd1"), /* D15 */
137 SUNXI_FUNCTION(0x4, "clk_out_a"),
137 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */ 138 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
138 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16), 139 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
139 SUNXI_FUNCTION(0x0, "gpio_in"), 140 SUNXI_FUNCTION(0x0, "gpio_in"),
140 SUNXI_FUNCTION(0x1, "gpio_out"), 141 SUNXI_FUNCTION(0x1, "gpio_out"),
141 SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */ 142 SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
142 SUNXI_FUNCTION(0x3, "lcd1"), /* D16 */ 143 SUNXI_FUNCTION(0x3, "lcd1"), /* D16 */
144 SUNXI_FUNCTION(0x4, "dmic"), /* CLK */
143 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */ 145 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
144 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17), 146 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
145 SUNXI_FUNCTION(0x0, "gpio_in"), 147 SUNXI_FUNCTION(0x0, "gpio_in"),
146 SUNXI_FUNCTION(0x1, "gpio_out"), 148 SUNXI_FUNCTION(0x1, "gpio_out"),
147 SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */ 149 SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
148 SUNXI_FUNCTION(0x3, "lcd1"), /* D17 */ 150 SUNXI_FUNCTION(0x3, "lcd1"), /* D17 */
151 SUNXI_FUNCTION(0x4, "dmic"), /* DIN */
149 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */ 152 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
150 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18), 153 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
151 SUNXI_FUNCTION(0x0, "gpio_in"), 154 SUNXI_FUNCTION(0x0, "gpio_in"),
152 SUNXI_FUNCTION(0x1, "gpio_out"), 155 SUNXI_FUNCTION(0x1, "gpio_out"),
153 SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */ 156 SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
154 SUNXI_FUNCTION(0x3, "lcd1"), /* D18 */ 157 SUNXI_FUNCTION(0x3, "lcd1"), /* D18 */
158 SUNXI_FUNCTION(0x4, "clk_out_b"),
155 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */ 159 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
156 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19), 160 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
157 SUNXI_FUNCTION(0x0, "gpio_in"), 161 SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -207,6 +211,7 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
207 SUNXI_FUNCTION(0x1, "gpio_out"), 211 SUNXI_FUNCTION(0x1, "gpio_out"),
208 SUNXI_FUNCTION(0x2, "gmac"), /* MDC */ 212 SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
209 SUNXI_FUNCTION(0x3, "lcd1"), /* HSYNC */ 213 SUNXI_FUNCTION(0x3, "lcd1"), /* HSYNC */
214 SUNXI_FUNCTION(0x4, "clk_out_c"),
210 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */ 215 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */
211 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27), 216 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
212 SUNXI_FUNCTION(0x0, "gpio_in"), 217 SUNXI_FUNCTION(0x0, "gpio_in"),
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
new file mode 100644
index 000000000000..9b5a91f610c7
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
@@ -0,0 +1,815 @@
1/*
2 * Allwinner A31s SoCs pinctrl driver.
3 *
4 * Copyright (C) 2014 Hans de Goede <hdegoede@redhat.com>
5 *
6 * Based on pinctrl-sun6i-a31.c, which is:
7 * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/of.h>
17#include <linux/of_device.h>
18#include <linux/pinctrl/pinctrl.h>
19
20#include "pinctrl-sunxi.h"
21
22static const struct sunxi_desc_pin sun6i_a31s_pins[] = {
23 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
24 SUNXI_FUNCTION(0x0, "gpio_in"),
25 SUNXI_FUNCTION(0x1, "gpio_out"),
26 SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */
27 SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
28 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
29 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
30 SUNXI_FUNCTION(0x0, "gpio_in"),
31 SUNXI_FUNCTION(0x1, "gpio_out"),
32 SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */
33 SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
34 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */
35 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
36 SUNXI_FUNCTION(0x0, "gpio_in"),
37 SUNXI_FUNCTION(0x1, "gpio_out"),
38 SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
39 SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
40 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */
41 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
42 SUNXI_FUNCTION(0x0, "gpio_in"),
43 SUNXI_FUNCTION(0x1, "gpio_out"),
44 SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
45 SUNXI_FUNCTION(0x4, "uart1"), /* RING */
46 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */
47 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
48 SUNXI_FUNCTION(0x0, "gpio_in"),
49 SUNXI_FUNCTION(0x1, "gpio_out"),
50 SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */
51 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
52 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */
53 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
54 SUNXI_FUNCTION(0x0, "gpio_in"),
55 SUNXI_FUNCTION(0x1, "gpio_out"),
56 SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */
57 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
58 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */
59 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
60 SUNXI_FUNCTION(0x0, "gpio_in"),
61 SUNXI_FUNCTION(0x1, "gpio_out"),
62 SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */
63 SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
64 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */
65 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
66 SUNXI_FUNCTION(0x0, "gpio_in"),
67 SUNXI_FUNCTION(0x1, "gpio_out"),
68 SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */
69 SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
70 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */
71 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
72 SUNXI_FUNCTION(0x0, "gpio_in"),
73 SUNXI_FUNCTION(0x1, "gpio_out"),
74 SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */
75 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */
76 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
77 SUNXI_FUNCTION(0x0, "gpio_in"),
78 SUNXI_FUNCTION(0x1, "gpio_out"),
79 SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
80 SUNXI_FUNCTION(0x4, "mmc3"), /* CMD */
81 SUNXI_FUNCTION(0x5, "mmc2"), /* CMD */
82 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */
83 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
84 SUNXI_FUNCTION(0x0, "gpio_in"),
85 SUNXI_FUNCTION(0x1, "gpio_out"),
86 SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */
87 SUNXI_FUNCTION(0x4, "mmc3"), /* CLK */
88 SUNXI_FUNCTION(0x5, "mmc2"), /* CLK */
89 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */
90 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
91 SUNXI_FUNCTION(0x0, "gpio_in"),
92 SUNXI_FUNCTION(0x1, "gpio_out"),
93 SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */
94 SUNXI_FUNCTION(0x4, "mmc3"), /* D0 */
95 SUNXI_FUNCTION(0x5, "mmc2"), /* D0 */
96 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */
97 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
98 SUNXI_FUNCTION(0x0, "gpio_in"),
99 SUNXI_FUNCTION(0x1, "gpio_out"),
100 SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */
101 SUNXI_FUNCTION(0x4, "mmc3"), /* D1 */
102 SUNXI_FUNCTION(0x5, "mmc2"), /* D1 */
103 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */
104 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
105 SUNXI_FUNCTION(0x0, "gpio_in"),
106 SUNXI_FUNCTION(0x1, "gpio_out"),
107 SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */
108 SUNXI_FUNCTION(0x4, "mmc3"), /* D2 */
109 SUNXI_FUNCTION(0x5, "mmc2"), /* D2 */
110 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */
111 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
112 SUNXI_FUNCTION(0x0, "gpio_in"),
113 SUNXI_FUNCTION(0x1, "gpio_out"),
114 SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */
115 SUNXI_FUNCTION(0x4, "mmc3"), /* D3 */
116 SUNXI_FUNCTION(0x5, "mmc2"), /* D3 */
117 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */
118 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
119 SUNXI_FUNCTION(0x0, "gpio_in"),
120 SUNXI_FUNCTION(0x1, "gpio_out"),
121 SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
122 SUNXI_FUNCTION(0x4, "clk_out_a"),
123 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
124 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
125 SUNXI_FUNCTION(0x0, "gpio_in"),
126 SUNXI_FUNCTION(0x1, "gpio_out"),
127 SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
128 SUNXI_FUNCTION(0x4, "dmic"), /* CLK */
129 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
130 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
131 SUNXI_FUNCTION(0x0, "gpio_in"),
132 SUNXI_FUNCTION(0x1, "gpio_out"),
133 SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
134 SUNXI_FUNCTION(0x4, "dmic"), /* DIN */
135 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
136 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
137 SUNXI_FUNCTION(0x0, "gpio_in"),
138 SUNXI_FUNCTION(0x1, "gpio_out"),
139 SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
140 SUNXI_FUNCTION(0x4, "clk_out_b"),
141 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
142 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
143 SUNXI_FUNCTION(0x0, "gpio_in"),
144 SUNXI_FUNCTION(0x1, "gpio_out"),
145 SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */
146 SUNXI_FUNCTION(0x4, "pwm3"), /* Positive */
147 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */
148 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),
149 SUNXI_FUNCTION(0x0, "gpio_in"),
150 SUNXI_FUNCTION(0x1, "gpio_out"),
151 SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */
152 SUNXI_FUNCTION(0x4, "pwm3"), /* Negative */
153 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */
154 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),
155 SUNXI_FUNCTION(0x0, "gpio_in"),
156 SUNXI_FUNCTION(0x1, "gpio_out"),
157 SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */
158 SUNXI_FUNCTION(0x4, "spi3"), /* CS0 */
159 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */
160 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 22),
161 SUNXI_FUNCTION(0x0, "gpio_in"),
162 SUNXI_FUNCTION(0x1, "gpio_out"),
163 SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */
164 SUNXI_FUNCTION(0x4, "spi3"), /* CLK */
165 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 22)), /* PA_EINT22 */
166 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 23),
167 SUNXI_FUNCTION(0x0, "gpio_in"),
168 SUNXI_FUNCTION(0x1, "gpio_out"),
169 SUNXI_FUNCTION(0x2, "gmac"), /* COL */
170 SUNXI_FUNCTION(0x4, "spi3"), /* MOSI */
171 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 23)), /* PA_EINT23 */
172 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 24),
173 SUNXI_FUNCTION(0x0, "gpio_in"),
174 SUNXI_FUNCTION(0x1, "gpio_out"),
175 SUNXI_FUNCTION(0x2, "gmac"), /* CRS */
176 SUNXI_FUNCTION(0x4, "spi3"), /* MISO */
177 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 24)), /* PA_EINT24 */
178 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 25),
179 SUNXI_FUNCTION(0x0, "gpio_in"),
180 SUNXI_FUNCTION(0x1, "gpio_out"),
181 SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */
182 SUNXI_FUNCTION(0x4, "spi3"), /* CS1 */
183 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 25)), /* PA_EINT25 */
184 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 26),
185 SUNXI_FUNCTION(0x0, "gpio_in"),
186 SUNXI_FUNCTION(0x1, "gpio_out"),
187 SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
188 SUNXI_FUNCTION(0x4, "clk_out_c"),
189 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 26)), /* PA_EINT26 */
190 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
191 SUNXI_FUNCTION(0x0, "gpio_in"),
192 SUNXI_FUNCTION(0x1, "gpio_out"),
193 SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */
194 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 27)), /* PA_EINT27 */
195 /* Hole */
196 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
197 SUNXI_FUNCTION(0x0, "gpio_in"),
198 SUNXI_FUNCTION(0x1, "gpio_out"),
199 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
200 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
201 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PB_EINT0 */
202 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
203 SUNXI_FUNCTION(0x0, "gpio_in"),
204 SUNXI_FUNCTION(0x1, "gpio_out"),
205 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
206 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PB_EINT1 */
207 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
208 SUNXI_FUNCTION(0x0, "gpio_in"),
209 SUNXI_FUNCTION(0x1, "gpio_out"),
210 SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
211 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PB_EINT2 */
212 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
213 SUNXI_FUNCTION(0x0, "gpio_in"),
214 SUNXI_FUNCTION(0x1, "gpio_out"),
215 SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */
216 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PB_EINT3 */
217 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
218 SUNXI_FUNCTION(0x0, "gpio_in"),
219 SUNXI_FUNCTION(0x1, "gpio_out"),
220 SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
221 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
222 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PB_EINT4 */
223 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
224 SUNXI_FUNCTION(0x0, "gpio_in"),
225 SUNXI_FUNCTION(0x1, "gpio_out"),
226 SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
227 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
228 SUNXI_FUNCTION(0x4, "i2c3"), /* SCK */
229 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PB_EINT5 */
230 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
231 SUNXI_FUNCTION(0x0, "gpio_in"),
232 SUNXI_FUNCTION(0x1, "gpio_out"),
233 SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
234 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
235 SUNXI_FUNCTION(0x4, "i2c3"), /* SDA */
236 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PB_EINT6 */
237 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
238 SUNXI_FUNCTION(0x0, "gpio_in"),
239 SUNXI_FUNCTION(0x1, "gpio_out"),
240 SUNXI_FUNCTION(0x3, "i2s0"), /* DI */
241 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PB_EINT7 */
242 /* Hole */
243 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
244 SUNXI_FUNCTION(0x0, "gpio_in"),
245 SUNXI_FUNCTION(0x1, "gpio_out"),
246 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
247 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
248 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
249 SUNXI_FUNCTION(0x0, "gpio_in"),
250 SUNXI_FUNCTION(0x1, "gpio_out"),
251 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
252 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
253 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
254 SUNXI_FUNCTION(0x0, "gpio_in"),
255 SUNXI_FUNCTION(0x1, "gpio_out"),
256 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
257 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
258 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
259 SUNXI_FUNCTION(0x0, "gpio_in"),
260 SUNXI_FUNCTION(0x1, "gpio_out"),
261 SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */
262 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
263 SUNXI_FUNCTION(0x0, "gpio_in"),
264 SUNXI_FUNCTION(0x1, "gpio_out"),
265 SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
266 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
267 SUNXI_FUNCTION(0x0, "gpio_in"),
268 SUNXI_FUNCTION(0x1, "gpio_out"),
269 SUNXI_FUNCTION(0x2, "nand0")), /* RE */
270 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
271 SUNXI_FUNCTION(0x0, "gpio_in"),
272 SUNXI_FUNCTION(0x1, "gpio_out"),
273 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
274 SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */
275 SUNXI_FUNCTION(0x4, "mmc3")), /* CMD */
276 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
277 SUNXI_FUNCTION(0x0, "gpio_in"),
278 SUNXI_FUNCTION(0x1, "gpio_out"),
279 SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
280 SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */
281 SUNXI_FUNCTION(0x4, "mmc3")), /* CLK */
282 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
283 SUNXI_FUNCTION(0x0, "gpio_in"),
284 SUNXI_FUNCTION(0x1, "gpio_out"),
285 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
286 SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
287 SUNXI_FUNCTION(0x4, "mmc3")), /* D0 */
288 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
289 SUNXI_FUNCTION(0x0, "gpio_in"),
290 SUNXI_FUNCTION(0x1, "gpio_out"),
291 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
292 SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
293 SUNXI_FUNCTION(0x4, "mmc3")), /* D1 */
294 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
295 SUNXI_FUNCTION(0x0, "gpio_in"),
296 SUNXI_FUNCTION(0x1, "gpio_out"),
297 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
298 SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */
299 SUNXI_FUNCTION(0x4, "mmc3")), /* D2 */
300 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
301 SUNXI_FUNCTION(0x0, "gpio_in"),
302 SUNXI_FUNCTION(0x1, "gpio_out"),
303 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
304 SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */
305 SUNXI_FUNCTION(0x4, "mmc3")), /* D3 */
306 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
307 SUNXI_FUNCTION(0x0, "gpio_in"),
308 SUNXI_FUNCTION(0x1, "gpio_out"),
309 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
310 SUNXI_FUNCTION(0x3, "mmc2"), /* D4 */
311 SUNXI_FUNCTION(0x4, "mmc3")), /* D4 */
312 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
313 SUNXI_FUNCTION(0x0, "gpio_in"),
314 SUNXI_FUNCTION(0x1, "gpio_out"),
315 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
316 SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */
317 SUNXI_FUNCTION(0x4, "mmc3")), /* D5 */
318 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
319 SUNXI_FUNCTION(0x0, "gpio_in"),
320 SUNXI_FUNCTION(0x1, "gpio_out"),
321 SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
322 SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */
323 SUNXI_FUNCTION(0x4, "mmc3")), /* D6 */
324 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
325 SUNXI_FUNCTION(0x0, "gpio_in"),
326 SUNXI_FUNCTION(0x1, "gpio_out"),
327 SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
328 SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */
329 SUNXI_FUNCTION(0x4, "mmc3")), /* D7 */
330 /* Hole in pin numbering ! */
331 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24),
332 SUNXI_FUNCTION(0x0, "gpio_in"),
333 SUNXI_FUNCTION(0x1, "gpio_out"),
334 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
335 SUNXI_FUNCTION(0x3, "mmc2"), /* RST */
336 SUNXI_FUNCTION(0x4, "mmc3")), /* RST */
337 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 25),
338 SUNXI_FUNCTION(0x0, "gpio_in"),
339 SUNXI_FUNCTION(0x1, "gpio_out"),
340 SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */
341 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 26),
342 SUNXI_FUNCTION(0x0, "gpio_in"),
343 SUNXI_FUNCTION(0x1, "gpio_out"),
344 SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */
345 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 27),
346 SUNXI_FUNCTION(0x0, "gpio_in"),
347 SUNXI_FUNCTION(0x1, "gpio_out"),
348 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
349 /* Hole */
350 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
351 SUNXI_FUNCTION(0x0, "gpio_in"),
352 SUNXI_FUNCTION(0x1, "gpio_out"),
353 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
354 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
355 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
356 SUNXI_FUNCTION(0x0, "gpio_in"),
357 SUNXI_FUNCTION(0x1, "gpio_out"),
358 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
359 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
360 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
361 SUNXI_FUNCTION(0x0, "gpio_in"),
362 SUNXI_FUNCTION(0x1, "gpio_out"),
363 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
364 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
365 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
366 SUNXI_FUNCTION(0x0, "gpio_in"),
367 SUNXI_FUNCTION(0x1, "gpio_out"),
368 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
369 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
370 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
371 SUNXI_FUNCTION(0x0, "gpio_in"),
372 SUNXI_FUNCTION(0x1, "gpio_out"),
373 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
374 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
375 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
376 SUNXI_FUNCTION(0x0, "gpio_in"),
377 SUNXI_FUNCTION(0x1, "gpio_out"),
378 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
379 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
380 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
381 SUNXI_FUNCTION(0x0, "gpio_in"),
382 SUNXI_FUNCTION(0x1, "gpio_out"),
383 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
384 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
385 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
386 SUNXI_FUNCTION(0x0, "gpio_in"),
387 SUNXI_FUNCTION(0x1, "gpio_out"),
388 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
389 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
390 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
391 SUNXI_FUNCTION(0x0, "gpio_in"),
392 SUNXI_FUNCTION(0x1, "gpio_out"),
393 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
394 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
395 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
396 SUNXI_FUNCTION(0x0, "gpio_in"),
397 SUNXI_FUNCTION(0x1, "gpio_out"),
398 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
399 SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
400 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
401 SUNXI_FUNCTION(0x0, "gpio_in"),
402 SUNXI_FUNCTION(0x1, "gpio_out"),
403 SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */
404 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
405 SUNXI_FUNCTION(0x0, "gpio_in"),
406 SUNXI_FUNCTION(0x1, "gpio_out"),
407 SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */
408 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
409 SUNXI_FUNCTION(0x0, "gpio_in"),
410 SUNXI_FUNCTION(0x1, "gpio_out"),
411 SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */
412 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
413 SUNXI_FUNCTION(0x0, "gpio_in"),
414 SUNXI_FUNCTION(0x1, "gpio_out"),
415 SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */
416 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
417 SUNXI_FUNCTION(0x0, "gpio_in"),
418 SUNXI_FUNCTION(0x1, "gpio_out"),
419 SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
420 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
421 SUNXI_FUNCTION(0x0, "gpio_in"),
422 SUNXI_FUNCTION(0x1, "gpio_out"),
423 SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
424 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
425 SUNXI_FUNCTION(0x0, "gpio_in"),
426 SUNXI_FUNCTION(0x1, "gpio_out"),
427 SUNXI_FUNCTION(0x2, "lcd0")), /* D16 */
428 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
429 SUNXI_FUNCTION(0x0, "gpio_in"),
430 SUNXI_FUNCTION(0x1, "gpio_out"),
431 SUNXI_FUNCTION(0x2, "lcd0")), /* D17 */
432 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
433 SUNXI_FUNCTION(0x0, "gpio_in"),
434 SUNXI_FUNCTION(0x1, "gpio_out"),
435 SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */
436 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
437 SUNXI_FUNCTION(0x0, "gpio_in"),
438 SUNXI_FUNCTION(0x1, "gpio_out"),
439 SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */
440 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
441 SUNXI_FUNCTION(0x0, "gpio_in"),
442 SUNXI_FUNCTION(0x1, "gpio_out"),
443 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
444 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
445 SUNXI_FUNCTION(0x0, "gpio_in"),
446 SUNXI_FUNCTION(0x1, "gpio_out"),
447 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
448 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
449 SUNXI_FUNCTION(0x0, "gpio_in"),
450 SUNXI_FUNCTION(0x1, "gpio_out"),
451 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
452 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
453 SUNXI_FUNCTION(0x0, "gpio_in"),
454 SUNXI_FUNCTION(0x1, "gpio_out"),
455 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
456 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
457 SUNXI_FUNCTION(0x0, "gpio_in"),
458 SUNXI_FUNCTION(0x1, "gpio_out"),
459 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
460 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
461 SUNXI_FUNCTION(0x0, "gpio_in"),
462 SUNXI_FUNCTION(0x1, "gpio_out"),
463 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
464 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
465 SUNXI_FUNCTION(0x0, "gpio_in"),
466 SUNXI_FUNCTION(0x1, "gpio_out"),
467 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
468 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
469 SUNXI_FUNCTION(0x0, "gpio_in"),
470 SUNXI_FUNCTION(0x1, "gpio_out"),
471 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
472 /* Hole */
473 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
474 SUNXI_FUNCTION(0x0, "gpio_in"),
475 SUNXI_FUNCTION(0x1, "gpio_out"),
476 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
477 SUNXI_FUNCTION(0x3, "ts"), /* CLK */
478 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PE_EINT0 */
479 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
480 SUNXI_FUNCTION(0x0, "gpio_in"),
481 SUNXI_FUNCTION(0x1, "gpio_out"),
482 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
483 SUNXI_FUNCTION(0x3, "ts"), /* ERR */
484 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PE_EINT1 */
485 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
486 SUNXI_FUNCTION(0x0, "gpio_in"),
487 SUNXI_FUNCTION(0x1, "gpio_out"),
488 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
489 SUNXI_FUNCTION(0x3, "ts"), /* SYNC */
490 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PE_EINT2 */
491 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
492 SUNXI_FUNCTION(0x0, "gpio_in"),
493 SUNXI_FUNCTION(0x1, "gpio_out"),
494 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
495 SUNXI_FUNCTION(0x3, "ts"), /* DVLD */
496 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PE_EINT3 */
497 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
498 SUNXI_FUNCTION(0x0, "gpio_in"),
499 SUNXI_FUNCTION(0x1, "gpio_out"),
500 SUNXI_FUNCTION(0x2, "csi"), /* D0 */
501 SUNXI_FUNCTION(0x3, "uart5"), /* TX */
502 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PE_EINT4 */
503 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
504 SUNXI_FUNCTION(0x0, "gpio_in"),
505 SUNXI_FUNCTION(0x1, "gpio_out"),
506 SUNXI_FUNCTION(0x2, "csi"), /* D1 */
507 SUNXI_FUNCTION(0x3, "uart5"), /* RX */
508 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PE_EINT5 */
509 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
510 SUNXI_FUNCTION(0x0, "gpio_in"),
511 SUNXI_FUNCTION(0x1, "gpio_out"),
512 SUNXI_FUNCTION(0x2, "csi"), /* D2 */
513 SUNXI_FUNCTION(0x3, "uart5"), /* RTS */
514 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PE_EINT6 */
515 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
516 SUNXI_FUNCTION(0x0, "gpio_in"),
517 SUNXI_FUNCTION(0x1, "gpio_out"),
518 SUNXI_FUNCTION(0x2, "csi"), /* D3 */
519 SUNXI_FUNCTION(0x3, "uart5"), /* CTS */
520 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PE_EINT7 */
521 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
522 SUNXI_FUNCTION(0x0, "gpio_in"),
523 SUNXI_FUNCTION(0x1, "gpio_out"),
524 SUNXI_FUNCTION(0x2, "csi"), /* D4 */
525 SUNXI_FUNCTION(0x3, "ts"), /* D0 */
526 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PE_EINT8 */
527 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
528 SUNXI_FUNCTION(0x0, "gpio_in"),
529 SUNXI_FUNCTION(0x1, "gpio_out"),
530 SUNXI_FUNCTION(0x2, "csi"), /* D5 */
531 SUNXI_FUNCTION(0x3, "ts"), /* D1 */
532 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PE_EINT9 */
533 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
534 SUNXI_FUNCTION(0x0, "gpio_in"),
535 SUNXI_FUNCTION(0x1, "gpio_out"),
536 SUNXI_FUNCTION(0x2, "csi"), /* D6 */
537 SUNXI_FUNCTION(0x3, "ts"), /* D2 */
538 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PE_EINT10 */
539 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
540 SUNXI_FUNCTION(0x0, "gpio_in"),
541 SUNXI_FUNCTION(0x1, "gpio_out"),
542 SUNXI_FUNCTION(0x2, "csi"), /* D7 */
543 SUNXI_FUNCTION(0x3, "ts"), /* D3 */
544 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PE_EINT11 */
545 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
546 SUNXI_FUNCTION(0x0, "gpio_in"),
547 SUNXI_FUNCTION(0x1, "gpio_out"),
548 SUNXI_FUNCTION(0x2, "csi"), /* D8 */
549 SUNXI_FUNCTION(0x3, "ts"), /* D4 */
550 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PE_EINT12 */
551 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
552 SUNXI_FUNCTION(0x0, "gpio_in"),
553 SUNXI_FUNCTION(0x1, "gpio_out"),
554 SUNXI_FUNCTION(0x2, "csi"), /* D9 */
555 SUNXI_FUNCTION(0x3, "ts"), /* D5 */
556 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PE_EINT13 */
557 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
558 SUNXI_FUNCTION(0x0, "gpio_in"),
559 SUNXI_FUNCTION(0x1, "gpio_out"),
560 SUNXI_FUNCTION(0x2, "csi"), /* D10 */
561 SUNXI_FUNCTION(0x3, "ts"), /* D6 */
562 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PE_EINT14 */
563 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
564 SUNXI_FUNCTION(0x0, "gpio_in"),
565 SUNXI_FUNCTION(0x1, "gpio_out"),
566 SUNXI_FUNCTION(0x2, "csi"), /* D11 */
567 SUNXI_FUNCTION(0x3, "ts"), /* D7 */
568 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), /* PE_EINT15 */
569 /* Hole */
570 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
571 SUNXI_FUNCTION(0x0, "gpio_in"),
572 SUNXI_FUNCTION(0x1, "gpio_out"),
573 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
574 SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
575 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
576 SUNXI_FUNCTION(0x0, "gpio_in"),
577 SUNXI_FUNCTION(0x1, "gpio_out"),
578 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
579 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
580 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
581 SUNXI_FUNCTION(0x0, "gpio_in"),
582 SUNXI_FUNCTION(0x1, "gpio_out"),
583 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
584 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
585 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
586 SUNXI_FUNCTION(0x0, "gpio_in"),
587 SUNXI_FUNCTION(0x1, "gpio_out"),
588 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
589 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
590 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
591 SUNXI_FUNCTION(0x0, "gpio_in"),
592 SUNXI_FUNCTION(0x1, "gpio_out"),
593 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
594 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
595 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
596 SUNXI_FUNCTION(0x0, "gpio_in"),
597 SUNXI_FUNCTION(0x1, "gpio_out"),
598 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
599 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
600 /* Hole */
601 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
602 SUNXI_FUNCTION(0x0, "gpio_in"),
603 SUNXI_FUNCTION(0x1, "gpio_out"),
604 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
605 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PG_EINT0 */
606 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
607 SUNXI_FUNCTION(0x0, "gpio_in"),
608 SUNXI_FUNCTION(0x1, "gpio_out"),
609 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
610 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PG_EINT1 */
611 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
612 SUNXI_FUNCTION(0x0, "gpio_in"),
613 SUNXI_FUNCTION(0x1, "gpio_out"),
614 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
615 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PG_EINT2 */
616 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
617 SUNXI_FUNCTION(0x0, "gpio_in"),
618 SUNXI_FUNCTION(0x1, "gpio_out"),
619 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
620 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PG_EINT3 */
621 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
622 SUNXI_FUNCTION(0x0, "gpio_in"),
623 SUNXI_FUNCTION(0x1, "gpio_out"),
624 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
625 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PG_EINT4 */
626 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
627 SUNXI_FUNCTION(0x0, "gpio_in"),
628 SUNXI_FUNCTION(0x1, "gpio_out"),
629 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
630 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PG_EINT5 */
631 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
632 SUNXI_FUNCTION(0x0, "gpio_in"),
633 SUNXI_FUNCTION(0x1, "gpio_out"),
634 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
635 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PG_EINT6 */
636 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
637 SUNXI_FUNCTION(0x0, "gpio_in"),
638 SUNXI_FUNCTION(0x1, "gpio_out"),
639 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
640 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PG_EINT7 */
641 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
642 SUNXI_FUNCTION(0x0, "gpio_in"),
643 SUNXI_FUNCTION(0x1, "gpio_out"),
644 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
645 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PG_EINT8 */
646 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
647 SUNXI_FUNCTION(0x0, "gpio_in"),
648 SUNXI_FUNCTION(0x1, "gpio_out"),
649 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
650 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PG_EINT9 */
651 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
652 SUNXI_FUNCTION(0x0, "gpio_in"),
653 SUNXI_FUNCTION(0x1, "gpio_out"),
654 SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
655 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PG_EINT10 */
656 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
657 SUNXI_FUNCTION(0x0, "gpio_in"),
658 SUNXI_FUNCTION(0x1, "gpio_out"),
659 SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
660 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), /* PG_EINT11 */
661 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
662 SUNXI_FUNCTION(0x0, "gpio_in"),
663 SUNXI_FUNCTION(0x1, "gpio_out"),
664 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
665 SUNXI_FUNCTION(0x3, "i2s1"), /* MCLK */
666 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)), /* PG_EINT12 */
667 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
668 SUNXI_FUNCTION(0x0, "gpio_in"),
669 SUNXI_FUNCTION(0x1, "gpio_out"),
670 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
671 SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */
672 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)), /* PG_EINT13 */
673 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
674 SUNXI_FUNCTION(0x0, "gpio_in"),
675 SUNXI_FUNCTION(0x1, "gpio_out"),
676 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
677 SUNXI_FUNCTION(0x3, "i2s1"), /* LRCK */
678 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)), /* PG_EINT14 */
679 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
680 SUNXI_FUNCTION(0x0, "gpio_in"),
681 SUNXI_FUNCTION(0x1, "gpio_out"),
682 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
683 SUNXI_FUNCTION(0x3, "i2s1"), /* DIN */
684 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)), /* PG_EINT15 */
685 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16),
686 SUNXI_FUNCTION(0x0, "gpio_in"),
687 SUNXI_FUNCTION(0x1, "gpio_out"),
688 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
689 SUNXI_FUNCTION(0x3, "i2s1"), /* DOUT */
690 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 16)), /* PG_EINT16 */
691 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17),
692 SUNXI_FUNCTION(0x0, "gpio_in"),
693 SUNXI_FUNCTION(0x1, "gpio_out"),
694 SUNXI_FUNCTION(0x2, "uart4"), /* TX */
695 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 17)), /* PG_EINT17 */
696 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18),
697 SUNXI_FUNCTION(0x0, "gpio_in"),
698 SUNXI_FUNCTION(0x1, "gpio_out"),
699 SUNXI_FUNCTION(0x2, "uart4"), /* RX */
700 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 18)), /* PG_EINT18 */
701 /* Hole, note H starts at pin 9 */
702 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
703 SUNXI_FUNCTION(0x0, "gpio_in"),
704 SUNXI_FUNCTION(0x1, "gpio_out"),
705 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
706 SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
707 SUNXI_FUNCTION(0x4, "pwm1")), /* Positive */
708 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
709 SUNXI_FUNCTION(0x0, "gpio_in"),
710 SUNXI_FUNCTION(0x1, "gpio_out"),
711 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
712 SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
713 SUNXI_FUNCTION(0x4, "pwm1")), /* Negative */
714 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
715 SUNXI_FUNCTION(0x0, "gpio_in"),
716 SUNXI_FUNCTION(0x1, "gpio_out"),
717 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
718 SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
719 SUNXI_FUNCTION(0x4, "pwm2")), /* Positive */
720 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
721 SUNXI_FUNCTION(0x0, "gpio_in"),
722 SUNXI_FUNCTION(0x1, "gpio_out"),
723 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
724 SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
725 SUNXI_FUNCTION(0x4, "pwm2")), /* Negative */
726 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
727 SUNXI_FUNCTION(0x0, "gpio_in"),
728 SUNXI_FUNCTION(0x1, "gpio_out"),
729 SUNXI_FUNCTION(0x2, "pwm0")),
730 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
731 SUNXI_FUNCTION(0x0, "gpio_in"),
732 SUNXI_FUNCTION(0x1, "gpio_out"),
733 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
734 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
735 SUNXI_FUNCTION(0x0, "gpio_in"),
736 SUNXI_FUNCTION(0x1, "gpio_out"),
737 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
738 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
739 SUNXI_FUNCTION(0x0, "gpio_in"),
740 SUNXI_FUNCTION(0x1, "gpio_out"),
741 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
742 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
743 SUNXI_FUNCTION(0x0, "gpio_in"),
744 SUNXI_FUNCTION(0x1, "gpio_out"),
745 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
746 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
747 SUNXI_FUNCTION(0x0, "gpio_in"),
748 SUNXI_FUNCTION(0x1, "gpio_out"),
749 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
750 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
751 SUNXI_FUNCTION(0x0, "gpio_in"),
752 SUNXI_FUNCTION(0x1, "gpio_out"),
753 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
754 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
755 SUNXI_FUNCTION(0x0, "gpio_in"),
756 SUNXI_FUNCTION(0x1, "gpio_out"),
757 SUNXI_FUNCTION(0x2, "uart0")), /* TX */
758 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
759 SUNXI_FUNCTION(0x0, "gpio_in"),
760 SUNXI_FUNCTION(0x1, "gpio_out"),
761 SUNXI_FUNCTION(0x2, "uart0")), /* RX */
762 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22),
763 SUNXI_FUNCTION(0x0, "gpio_in"),
764 SUNXI_FUNCTION(0x1, "gpio_out")),
765 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23),
766 SUNXI_FUNCTION(0x0, "gpio_in"),
767 SUNXI_FUNCTION(0x1, "gpio_out")),
768 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24),
769 SUNXI_FUNCTION(0x0, "gpio_in"),
770 SUNXI_FUNCTION(0x1, "gpio_out")),
771 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25),
772 SUNXI_FUNCTION(0x0, "gpio_in"),
773 SUNXI_FUNCTION(0x1, "gpio_out")),
774 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26),
775 SUNXI_FUNCTION(0x0, "gpio_in"),
776 SUNXI_FUNCTION(0x1, "gpio_out")),
777 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27),
778 SUNXI_FUNCTION(0x0, "gpio_in"),
779 SUNXI_FUNCTION(0x1, "gpio_out")),
780 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 28),
781 SUNXI_FUNCTION(0x0, "gpio_in"),
782 SUNXI_FUNCTION(0x1, "gpio_out")),
783};
784
785static const struct sunxi_pinctrl_desc sun6i_a31s_pinctrl_data = {
786 .pins = sun6i_a31s_pins,
787 .npins = ARRAY_SIZE(sun6i_a31s_pins),
788 .irq_banks = 4,
789};
790
791static int sun6i_a31s_pinctrl_probe(struct platform_device *pdev)
792{
793 return sunxi_pinctrl_init(pdev,
794 &sun6i_a31s_pinctrl_data);
795}
796
797static struct of_device_id sun6i_a31s_pinctrl_match[] = {
798 { .compatible = "allwinner,sun6i-a31s-pinctrl", },
799 {}
800};
801MODULE_DEVICE_TABLE(of, sun6i_a31s_pinctrl_match);
802
803static struct platform_driver sun6i_a31s_pinctrl_driver = {
804 .probe = sun6i_a31s_pinctrl_probe,
805 .driver = {
806 .name = "sun6i-a31s-pinctrl",
807 .owner = THIS_MODULE,
808 .of_match_table = sun6i_a31s_pinctrl_match,
809 },
810};
811module_platform_driver(sun6i_a31s_pinctrl_driver);
812
813MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
814MODULE_DESCRIPTION("Allwinner A31s pinctrl driver");
815MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-26 06:32:16 -0500