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authorLinus Walleij <linus.walleij@linaro.org>2014-05-09 02:47:16 -0400
committerLinus Walleij <linus.walleij@linaro.org>2014-05-09 02:47:16 -0400
commit9dffe1d4a7c2ee53b982ecb12c277040743d6ca2 (patch)
tree3f8a0ade83fc79423b5a3e034bc6debcdc00df8f /drivers/pinctrl
parent2aa02733fb869e217b3c5c0860273f7feb4f04d6 (diff)
parentdc9691066fa7de51178de5ac3e06b3681557a7b4 (diff)
Merge tag 'sunxi-pinctrl-for-3.16' of https://github.com/mripard/linux into devel
Pinctrl cleanup and reworks for 3.16 This serie of patch: - Moves the Allwinner pinctrl driver to a folder of its own - removes the sunxi-pinctrl-pins header, and split the driver into a core one, with all the logic, and smaller drivers, one for each SoC, that declare the pins, and will provide to the core the set of pins. - And does a few cleanups here and there.
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/Kconfig6
-rw-r--r--drivers/pinctrl/Makefile2
-rw-r--r--drivers/pinctrl/pinctrl-sunxi-pins.h3937
-rw-r--r--drivers/pinctrl/pinctrl-sunxi.h617
-rw-r--r--drivers/pinctrl/sunxi/Kconfig32
-rw-r--r--drivers/pinctrl/sunxi/Makefile10
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c1039
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c690
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c411
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c141
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c865
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c1065
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sunxi.c (renamed from drivers/pinctrl/pinctrl-sunxi.c)62
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sunxi.h258
14 files changed, 4524 insertions, 4611 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 934fd89978d3..4508f6abee48 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -291,11 +291,6 @@ config PINCTRL_SIRF
291 select PINMUX 291 select PINMUX
292 select GPIOLIB_IRQCHIP 292 select GPIOLIB_IRQCHIP
293 293
294config PINCTRL_SUNXI
295 bool
296 select PINMUX
297 select GENERIC_PINCONF
298
299config PINCTRL_ST 294config PINCTRL_ST
300 bool 295 bool
301 depends on OF 296 depends on OF
@@ -392,6 +387,7 @@ config PINCTRL_S3C64XX
392source "drivers/pinctrl/mvebu/Kconfig" 387source "drivers/pinctrl/mvebu/Kconfig"
393source "drivers/pinctrl/sh-pfc/Kconfig" 388source "drivers/pinctrl/sh-pfc/Kconfig"
394source "drivers/pinctrl/spear/Kconfig" 389source "drivers/pinctrl/spear/Kconfig"
390source "drivers/pinctrl/sunxi/Kconfig"
395source "drivers/pinctrl/vt8500/Kconfig" 391source "drivers/pinctrl/vt8500/Kconfig"
396 392
397config PINCTRL_XWAY 393config PINCTRL_XWAY
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 68bb399fc577..c2621438785e 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -49,7 +49,6 @@ obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
49obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o 49obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
50obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o 50obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
51obj-$(CONFIG_PINCTRL_SIRF) += sirf/ 51obj-$(CONFIG_PINCTRL_SIRF) += sirf/
52obj-$(CONFIG_PINCTRL_SUNXI) += pinctrl-sunxi.o
53obj-$(CONFIG_PINCTRL_TEGRA) += pinctrl-tegra.o 52obj-$(CONFIG_PINCTRL_TEGRA) += pinctrl-tegra.o
54obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o 53obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o
55obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o 54obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
@@ -75,3 +74,4 @@ obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/
75obj-$(CONFIG_SUPERH) += sh-pfc/ 74obj-$(CONFIG_SUPERH) += sh-pfc/
76obj-$(CONFIG_PLAT_SPEAR) += spear/ 75obj-$(CONFIG_PLAT_SPEAR) += spear/
77obj-$(CONFIG_ARCH_VT8500) += vt8500/ 76obj-$(CONFIG_ARCH_VT8500) += vt8500/
77obj-$(CONFIG_ARCH_SUNXI) += sunxi/
diff --git a/drivers/pinctrl/pinctrl-sunxi-pins.h b/drivers/pinctrl/pinctrl-sunxi-pins.h
deleted file mode 100644
index 51100caf05f9..000000000000
--- a/drivers/pinctrl/pinctrl-sunxi-pins.h
+++ /dev/null
@@ -1,3937 +0,0 @@
1/*
2 * Allwinner A1X SoCs pinctrl driver.
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#ifndef __PINCTRL_SUNXI_PINS_H
14#define __PINCTRL_SUNXI_PINS_H
15
16#include "pinctrl-sunxi.h"
17
18static const struct sunxi_desc_pin sun4i_a10_pins[] = {
19 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
20 SUNXI_FUNCTION(0x0, "gpio_in"),
21 SUNXI_FUNCTION(0x1, "gpio_out"),
22 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
23 SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
24 SUNXI_FUNCTION(0x4, "uart2")), /* RTS */
25 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
26 SUNXI_FUNCTION(0x0, "gpio_in"),
27 SUNXI_FUNCTION(0x1, "gpio_out"),
28 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
29 SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
30 SUNXI_FUNCTION(0x4, "uart2")), /* CTS */
31 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
32 SUNXI_FUNCTION(0x0, "gpio_in"),
33 SUNXI_FUNCTION(0x1, "gpio_out"),
34 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
35 SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
36 SUNXI_FUNCTION(0x4, "uart2")), /* TX */
37 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
38 SUNXI_FUNCTION(0x0, "gpio_in"),
39 SUNXI_FUNCTION(0x1, "gpio_out"),
40 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
41 SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
42 SUNXI_FUNCTION(0x4, "uart2")), /* RX */
43 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
44 SUNXI_FUNCTION(0x0, "gpio_in"),
45 SUNXI_FUNCTION(0x1, "gpio_out"),
46 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
47 SUNXI_FUNCTION(0x3, "spi1")), /* CS1 */
48 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
49 SUNXI_FUNCTION(0x0, "gpio_in"),
50 SUNXI_FUNCTION(0x1, "gpio_out"),
51 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
52 SUNXI_FUNCTION(0x3, "spi3")), /* CS0 */
53 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
54 SUNXI_FUNCTION(0x0, "gpio_in"),
55 SUNXI_FUNCTION(0x1, "gpio_out"),
56 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
57 SUNXI_FUNCTION(0x3, "spi3")), /* CLK */
58 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
59 SUNXI_FUNCTION(0x0, "gpio_in"),
60 SUNXI_FUNCTION(0x1, "gpio_out"),
61 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
62 SUNXI_FUNCTION(0x3, "spi3")), /* MOSI */
63 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
64 SUNXI_FUNCTION(0x0, "gpio_in"),
65 SUNXI_FUNCTION(0x1, "gpio_out"),
66 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
67 SUNXI_FUNCTION(0x3, "spi3")), /* MISO */
68 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
69 SUNXI_FUNCTION(0x0, "gpio_in"),
70 SUNXI_FUNCTION(0x1, "gpio_out"),
71 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
72 SUNXI_FUNCTION(0x3, "spi3")), /* CS1 */
73 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
74 SUNXI_FUNCTION(0x0, "gpio_in"),
75 SUNXI_FUNCTION(0x1, "gpio_out"),
76 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
77 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
78 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
79 SUNXI_FUNCTION(0x0, "gpio_in"),
80 SUNXI_FUNCTION(0x1, "gpio_out"),
81 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
82 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
83 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
84 SUNXI_FUNCTION(0x0, "gpio_in"),
85 SUNXI_FUNCTION(0x1, "gpio_out"),
86 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
87 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
88 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */
89 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
90 SUNXI_FUNCTION(0x0, "gpio_in"),
91 SUNXI_FUNCTION(0x1, "gpio_out"),
92 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
93 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
94 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */
95 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
96 SUNXI_FUNCTION(0x0, "gpio_in"),
97 SUNXI_FUNCTION(0x1, "gpio_out"),
98 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
99 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
100 SUNXI_FUNCTION(0x4, "uart1")), /* DTR */
101 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
102 SUNXI_FUNCTION(0x0, "gpio_in"),
103 SUNXI_FUNCTION(0x1, "gpio_out"),
104 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
105 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
106 SUNXI_FUNCTION(0x4, "uart1")), /* DSR */
107 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
108 SUNXI_FUNCTION(0x0, "gpio_in"),
109 SUNXI_FUNCTION(0x1, "gpio_out"),
110 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
111 SUNXI_FUNCTION(0x3, "can"), /* TX */
112 SUNXI_FUNCTION(0x4, "uart1")), /* DCD */
113 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
114 SUNXI_FUNCTION(0x0, "gpio_in"),
115 SUNXI_FUNCTION(0x1, "gpio_out"),
116 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
117 SUNXI_FUNCTION(0x3, "can"), /* RX */
118 SUNXI_FUNCTION(0x4, "uart1")), /* RING */
119 /* Hole */
120 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
121 SUNXI_FUNCTION(0x0, "gpio_in"),
122 SUNXI_FUNCTION(0x1, "gpio_out"),
123 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
124 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
125 SUNXI_FUNCTION(0x0, "gpio_in"),
126 SUNXI_FUNCTION(0x1, "gpio_out"),
127 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
128 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
129 SUNXI_FUNCTION(0x0, "gpio_in"),
130 SUNXI_FUNCTION(0x1, "gpio_out"),
131 SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */
132 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
133 SUNXI_FUNCTION(0x0, "gpio_in"),
134 SUNXI_FUNCTION(0x1, "gpio_out"),
135 SUNXI_FUNCTION(0x2, "ir0")), /* TX */
136 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
137 SUNXI_FUNCTION(0x0, "gpio_in"),
138 SUNXI_FUNCTION(0x1, "gpio_out"),
139 SUNXI_FUNCTION(0x2, "ir0")), /* RX */
140 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
141 SUNXI_FUNCTION(0x0, "gpio_in"),
142 SUNXI_FUNCTION(0x1, "gpio_out"),
143 SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
144 SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */
145 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
146 SUNXI_FUNCTION(0x0, "gpio_in"),
147 SUNXI_FUNCTION(0x1, "gpio_out"),
148 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
149 SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */
150 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
151 SUNXI_FUNCTION(0x0, "gpio_in"),
152 SUNXI_FUNCTION(0x1, "gpio_out"),
153 SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */
154 SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */
155 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8,
156 SUNXI_FUNCTION(0x0, "gpio_in"),
157 SUNXI_FUNCTION(0x1, "gpio_out"),
158 SUNXI_FUNCTION(0x2, "i2s"), /* DO0 */
159 SUNXI_FUNCTION(0x3, "ac97")), /* DO */
160 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9,
161 SUNXI_FUNCTION(0x0, "gpio_in"),
162 SUNXI_FUNCTION(0x1, "gpio_out"),
163 SUNXI_FUNCTION(0x2, "i2s")), /* DO1 */
164 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
165 SUNXI_FUNCTION(0x0, "gpio_in"),
166 SUNXI_FUNCTION(0x1, "gpio_out"),
167 SUNXI_FUNCTION(0x2, "i2s")), /* DO2 */
168 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11,
169 SUNXI_FUNCTION(0x0, "gpio_in"),
170 SUNXI_FUNCTION(0x1, "gpio_out"),
171 SUNXI_FUNCTION(0x2, "i2s")), /* DO3 */
172 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12,
173 SUNXI_FUNCTION(0x0, "gpio_in"),
174 SUNXI_FUNCTION(0x1, "gpio_out"),
175 SUNXI_FUNCTION(0x2, "i2s"), /* DI */
176 SUNXI_FUNCTION(0x3, "ac97")), /* DI */
177 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13,
178 SUNXI_FUNCTION(0x0, "gpio_in"),
179 SUNXI_FUNCTION(0x1, "gpio_out"),
180 SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */
181 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14,
182 SUNXI_FUNCTION(0x0, "gpio_in"),
183 SUNXI_FUNCTION(0x1, "gpio_out"),
184 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
185 SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */
186 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
187 SUNXI_FUNCTION(0x0, "gpio_in"),
188 SUNXI_FUNCTION(0x1, "gpio_out"),
189 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
190 SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */
191 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
192 SUNXI_FUNCTION(0x0, "gpio_in"),
193 SUNXI_FUNCTION(0x1, "gpio_out"),
194 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
195 SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */
196 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
197 SUNXI_FUNCTION(0x0, "gpio_in"),
198 SUNXI_FUNCTION(0x1, "gpio_out"),
199 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
200 SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */
201 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
202 SUNXI_FUNCTION(0x0, "gpio_in"),
203 SUNXI_FUNCTION(0x1, "gpio_out"),
204 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
205 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19,
206 SUNXI_FUNCTION(0x0, "gpio_in"),
207 SUNXI_FUNCTION(0x1, "gpio_out"),
208 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
209 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20,
210 SUNXI_FUNCTION(0x0, "gpio_in"),
211 SUNXI_FUNCTION(0x1, "gpio_out"),
212 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
213 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21,
214 SUNXI_FUNCTION(0x0, "gpio_in"),
215 SUNXI_FUNCTION(0x1, "gpio_out"),
216 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
217 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22,
218 SUNXI_FUNCTION(0x0, "gpio_in"),
219 SUNXI_FUNCTION(0x1, "gpio_out"),
220 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
221 SUNXI_FUNCTION(0x3, "ir1")), /* TX */
222 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23,
223 SUNXI_FUNCTION(0x0, "gpio_in"),
224 SUNXI_FUNCTION(0x1, "gpio_out"),
225 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
226 SUNXI_FUNCTION(0x3, "ir1")), /* RX */
227 /* Hole */
228 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
229 SUNXI_FUNCTION(0x0, "gpio_in"),
230 SUNXI_FUNCTION(0x1, "gpio_out"),
231 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
232 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
233 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
234 SUNXI_FUNCTION(0x0, "gpio_in"),
235 SUNXI_FUNCTION(0x1, "gpio_out"),
236 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
237 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
238 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
239 SUNXI_FUNCTION(0x0, "gpio_in"),
240 SUNXI_FUNCTION(0x1, "gpio_out"),
241 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
242 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
243 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
244 SUNXI_FUNCTION(0x0, "gpio_in"),
245 SUNXI_FUNCTION(0x1, "gpio_out"),
246 SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */
247 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
248 SUNXI_FUNCTION(0x0, "gpio_in"),
249 SUNXI_FUNCTION(0x1, "gpio_out"),
250 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
251 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
252 SUNXI_FUNCTION(0x0, "gpio_in"),
253 SUNXI_FUNCTION(0x1, "gpio_out"),
254 SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */
255 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
256 SUNXI_FUNCTION(0x0, "gpio_in"),
257 SUNXI_FUNCTION(0x1, "gpio_out"),
258 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
259 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
260 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
261 SUNXI_FUNCTION(0x0, "gpio_in"),
262 SUNXI_FUNCTION(0x1, "gpio_out"),
263 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
264 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
265 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
266 SUNXI_FUNCTION(0x0, "gpio_in"),
267 SUNXI_FUNCTION(0x1, "gpio_out"),
268 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
269 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
270 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
271 SUNXI_FUNCTION(0x0, "gpio_in"),
272 SUNXI_FUNCTION(0x1, "gpio_out"),
273 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
274 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
275 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
276 SUNXI_FUNCTION(0x0, "gpio_in"),
277 SUNXI_FUNCTION(0x1, "gpio_out"),
278 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
279 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
280 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
281 SUNXI_FUNCTION(0x0, "gpio_in"),
282 SUNXI_FUNCTION(0x1, "gpio_out"),
283 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
284 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
285 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
286 SUNXI_FUNCTION(0x0, "gpio_in"),
287 SUNXI_FUNCTION(0x1, "gpio_out"),
288 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */
289 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
290 SUNXI_FUNCTION(0x0, "gpio_in"),
291 SUNXI_FUNCTION(0x1, "gpio_out"),
292 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */
293 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
294 SUNXI_FUNCTION(0x0, "gpio_in"),
295 SUNXI_FUNCTION(0x1, "gpio_out"),
296 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */
297 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
298 SUNXI_FUNCTION(0x0, "gpio_in"),
299 SUNXI_FUNCTION(0x1, "gpio_out"),
300 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */
301 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
302 SUNXI_FUNCTION(0x0, "gpio_in"),
303 SUNXI_FUNCTION(0x1, "gpio_out"),
304 SUNXI_FUNCTION(0x2, "nand0")), /* NWP */
305 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
306 SUNXI_FUNCTION(0x0, "gpio_in"),
307 SUNXI_FUNCTION(0x1, "gpio_out"),
308 SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */
309 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
310 SUNXI_FUNCTION(0x0, "gpio_in"),
311 SUNXI_FUNCTION(0x1, "gpio_out"),
312 SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */
313 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
314 SUNXI_FUNCTION(0x0, "gpio_in"),
315 SUNXI_FUNCTION(0x1, "gpio_out"),
316 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
317 SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */
318 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20,
319 SUNXI_FUNCTION(0x0, "gpio_in"),
320 SUNXI_FUNCTION(0x1, "gpio_out"),
321 SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
322 SUNXI_FUNCTION(0x3, "spi2")), /* CLK */
323 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21,
324 SUNXI_FUNCTION(0x0, "gpio_in"),
325 SUNXI_FUNCTION(0x1, "gpio_out"),
326 SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
327 SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */
328 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22,
329 SUNXI_FUNCTION(0x0, "gpio_in"),
330 SUNXI_FUNCTION(0x1, "gpio_out"),
331 SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
332 SUNXI_FUNCTION(0x3, "spi2")), /* MISO */
333 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23,
334 SUNXI_FUNCTION(0x0, "gpio_in"),
335 SUNXI_FUNCTION(0x1, "gpio_out"),
336 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
337 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24,
338 SUNXI_FUNCTION(0x0, "gpio_in"),
339 SUNXI_FUNCTION(0x1, "gpio_out"),
340 SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */
341 /* Hole */
342 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
343 SUNXI_FUNCTION(0x0, "gpio_in"),
344 SUNXI_FUNCTION(0x1, "gpio_out"),
345 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
346 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
347 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
348 SUNXI_FUNCTION(0x0, "gpio_in"),
349 SUNXI_FUNCTION(0x1, "gpio_out"),
350 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
351 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
352 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
353 SUNXI_FUNCTION(0x0, "gpio_in"),
354 SUNXI_FUNCTION(0x1, "gpio_out"),
355 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
356 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
357 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
358 SUNXI_FUNCTION(0x0, "gpio_in"),
359 SUNXI_FUNCTION(0x1, "gpio_out"),
360 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
361 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
362 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
363 SUNXI_FUNCTION(0x0, "gpio_in"),
364 SUNXI_FUNCTION(0x1, "gpio_out"),
365 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
366 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
367 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
368 SUNXI_FUNCTION(0x0, "gpio_in"),
369 SUNXI_FUNCTION(0x1, "gpio_out"),
370 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
371 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
372 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
373 SUNXI_FUNCTION(0x0, "gpio_in"),
374 SUNXI_FUNCTION(0x1, "gpio_out"),
375 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
376 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
377 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
378 SUNXI_FUNCTION(0x0, "gpio_in"),
379 SUNXI_FUNCTION(0x1, "gpio_out"),
380 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
381 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
382 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
383 SUNXI_FUNCTION(0x0, "gpio_in"),
384 SUNXI_FUNCTION(0x1, "gpio_out"),
385 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
386 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
387 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
388 SUNXI_FUNCTION(0x0, "gpio_in"),
389 SUNXI_FUNCTION(0x1, "gpio_out"),
390 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
391 SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */
392 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
393 SUNXI_FUNCTION(0x0, "gpio_in"),
394 SUNXI_FUNCTION(0x1, "gpio_out"),
395 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
396 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
397 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
398 SUNXI_FUNCTION(0x0, "gpio_in"),
399 SUNXI_FUNCTION(0x1, "gpio_out"),
400 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
401 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
402 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
403 SUNXI_FUNCTION(0x0, "gpio_in"),
404 SUNXI_FUNCTION(0x1, "gpio_out"),
405 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
406 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
407 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
408 SUNXI_FUNCTION(0x0, "gpio_in"),
409 SUNXI_FUNCTION(0x1, "gpio_out"),
410 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
411 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
412 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
413 SUNXI_FUNCTION(0x0, "gpio_in"),
414 SUNXI_FUNCTION(0x1, "gpio_out"),
415 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
416 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
417 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
418 SUNXI_FUNCTION(0x0, "gpio_in"),
419 SUNXI_FUNCTION(0x1, "gpio_out"),
420 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
421 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
422 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
423 SUNXI_FUNCTION(0x0, "gpio_in"),
424 SUNXI_FUNCTION(0x1, "gpio_out"),
425 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
426 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
427 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
428 SUNXI_FUNCTION(0x0, "gpio_in"),
429 SUNXI_FUNCTION(0x1, "gpio_out"),
430 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
431 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
432 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
433 SUNXI_FUNCTION(0x0, "gpio_in"),
434 SUNXI_FUNCTION(0x1, "gpio_out"),
435 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
436 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
437 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
438 SUNXI_FUNCTION(0x0, "gpio_in"),
439 SUNXI_FUNCTION(0x1, "gpio_out"),
440 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
441 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
442 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
443 SUNXI_FUNCTION(0x0, "gpio_in"),
444 SUNXI_FUNCTION(0x1, "gpio_out"),
445 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
446 SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */
447 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
448 SUNXI_FUNCTION(0x0, "gpio_in"),
449 SUNXI_FUNCTION(0x1, "gpio_out"),
450 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
451 SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */
452 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
453 SUNXI_FUNCTION(0x0, "gpio_in"),
454 SUNXI_FUNCTION(0x1, "gpio_out"),
455 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
456 SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */
457 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
458 SUNXI_FUNCTION(0x0, "gpio_in"),
459 SUNXI_FUNCTION(0x1, "gpio_out"),
460 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
461 SUNXI_FUNCTION(0x3, "sim")), /* DET */
462 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
463 SUNXI_FUNCTION(0x0, "gpio_in"),
464 SUNXI_FUNCTION(0x1, "gpio_out"),
465 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
466 SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */
467 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
468 SUNXI_FUNCTION(0x0, "gpio_in"),
469 SUNXI_FUNCTION(0x1, "gpio_out"),
470 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
471 SUNXI_FUNCTION(0x3, "sim")), /* RST */
472 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
473 SUNXI_FUNCTION(0x0, "gpio_in"),
474 SUNXI_FUNCTION(0x1, "gpio_out"),
475 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
476 SUNXI_FUNCTION(0x3, "sim")), /* SCK */
477 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
478 SUNXI_FUNCTION(0x0, "gpio_in"),
479 SUNXI_FUNCTION(0x1, "gpio_out"),
480 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
481 SUNXI_FUNCTION(0x3, "sim")), /* SDA */
482 /* Hole */
483 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
484 SUNXI_FUNCTION(0x0, "gpio_in"),
485 SUNXI_FUNCTION(0x1, "gpio_out"),
486 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
487 SUNXI_FUNCTION(0x3, "csi0")), /* PCK */
488 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
489 SUNXI_FUNCTION(0x0, "gpio_in"),
490 SUNXI_FUNCTION(0x1, "gpio_out"),
491 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
492 SUNXI_FUNCTION(0x3, "csi0")), /* CK */
493 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
494 SUNXI_FUNCTION(0x0, "gpio_in"),
495 SUNXI_FUNCTION(0x1, "gpio_out"),
496 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
497 SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */
498 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
499 SUNXI_FUNCTION(0x0, "gpio_in"),
500 SUNXI_FUNCTION(0x1, "gpio_out"),
501 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
502 SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */
503 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
504 SUNXI_FUNCTION(0x0, "gpio_in"),
505 SUNXI_FUNCTION(0x1, "gpio_out"),
506 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
507 SUNXI_FUNCTION(0x3, "csi0")), /* D0 */
508 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
509 SUNXI_FUNCTION(0x0, "gpio_in"),
510 SUNXI_FUNCTION(0x1, "gpio_out"),
511 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
512 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
513 SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */
514 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
515 SUNXI_FUNCTION(0x0, "gpio_in"),
516 SUNXI_FUNCTION(0x1, "gpio_out"),
517 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
518 SUNXI_FUNCTION(0x3, "csi0")), /* D2 */
519 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
520 SUNXI_FUNCTION(0x0, "gpio_in"),
521 SUNXI_FUNCTION(0x1, "gpio_out"),
522 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
523 SUNXI_FUNCTION(0x3, "csi0")), /* D3 */
524 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
525 SUNXI_FUNCTION(0x0, "gpio_in"),
526 SUNXI_FUNCTION(0x1, "gpio_out"),
527 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
528 SUNXI_FUNCTION(0x3, "csi0")), /* D4 */
529 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
530 SUNXI_FUNCTION(0x0, "gpio_in"),
531 SUNXI_FUNCTION(0x1, "gpio_out"),
532 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
533 SUNXI_FUNCTION(0x3, "csi0")), /* D5 */
534 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
535 SUNXI_FUNCTION(0x0, "gpio_in"),
536 SUNXI_FUNCTION(0x1, "gpio_out"),
537 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
538 SUNXI_FUNCTION(0x3, "csi0")), /* D6 */
539 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
540 SUNXI_FUNCTION(0x0, "gpio_in"),
541 SUNXI_FUNCTION(0x1, "gpio_out"),
542 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
543 SUNXI_FUNCTION(0x3, "csi0")), /* D7 */
544 /* Hole */
545 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
546 SUNXI_FUNCTION(0x0, "gpio_in"),
547 SUNXI_FUNCTION(0x1, "gpio_out"),
548 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
549 SUNXI_FUNCTION(0x4, "jtag")), /* MSI */
550 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
551 SUNXI_FUNCTION(0x0, "gpio_in"),
552 SUNXI_FUNCTION(0x1, "gpio_out"),
553 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
554 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
555 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
556 SUNXI_FUNCTION(0x0, "gpio_in"),
557 SUNXI_FUNCTION(0x1, "gpio_out"),
558 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
559 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
560 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
561 SUNXI_FUNCTION(0x0, "gpio_in"),
562 SUNXI_FUNCTION(0x1, "gpio_out"),
563 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
564 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
565 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
566 SUNXI_FUNCTION(0x0, "gpio_in"),
567 SUNXI_FUNCTION(0x1, "gpio_out"),
568 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
569 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
570 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
571 SUNXI_FUNCTION(0x0, "gpio_in"),
572 SUNXI_FUNCTION(0x1, "gpio_out"),
573 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
574 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
575 /* Hole */
576 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
577 SUNXI_FUNCTION(0x0, "gpio_in"),
578 SUNXI_FUNCTION(0x1, "gpio_out"),
579 SUNXI_FUNCTION(0x2, "ts1"), /* CLK */
580 SUNXI_FUNCTION(0x3, "csi1"), /* PCK */
581 SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */
582 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
583 SUNXI_FUNCTION(0x0, "gpio_in"),
584 SUNXI_FUNCTION(0x1, "gpio_out"),
585 SUNXI_FUNCTION(0x2, "ts1"), /* ERR */
586 SUNXI_FUNCTION(0x3, "csi1"), /* CK */
587 SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */
588 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
589 SUNXI_FUNCTION(0x0, "gpio_in"),
590 SUNXI_FUNCTION(0x1, "gpio_out"),
591 SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */
592 SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */
593 SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */
594 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
595 SUNXI_FUNCTION(0x0, "gpio_in"),
596 SUNXI_FUNCTION(0x1, "gpio_out"),
597 SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */
598 SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */
599 SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */
600 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
601 SUNXI_FUNCTION(0x0, "gpio_in"),
602 SUNXI_FUNCTION(0x1, "gpio_out"),
603 SUNXI_FUNCTION(0x2, "ts1"), /* D0 */
604 SUNXI_FUNCTION(0x3, "csi1"), /* D0 */
605 SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */
606 SUNXI_FUNCTION(0x5, "csi0")), /* D8 */
607 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
608 SUNXI_FUNCTION(0x0, "gpio_in"),
609 SUNXI_FUNCTION(0x1, "gpio_out"),
610 SUNXI_FUNCTION(0x2, "ts1"), /* D1 */
611 SUNXI_FUNCTION(0x3, "csi1"), /* D1 */
612 SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */
613 SUNXI_FUNCTION(0x5, "csi0")), /* D9 */
614 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
615 SUNXI_FUNCTION(0x0, "gpio_in"),
616 SUNXI_FUNCTION(0x1, "gpio_out"),
617 SUNXI_FUNCTION(0x2, "ts1"), /* D2 */
618 SUNXI_FUNCTION(0x3, "csi1"), /* D2 */
619 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
620 SUNXI_FUNCTION(0x5, "csi0")), /* D10 */
621 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
622 SUNXI_FUNCTION(0x0, "gpio_in"),
623 SUNXI_FUNCTION(0x1, "gpio_out"),
624 SUNXI_FUNCTION(0x2, "ts1"), /* D3 */
625 SUNXI_FUNCTION(0x3, "csi1"), /* D3 */
626 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
627 SUNXI_FUNCTION(0x5, "csi0")), /* D11 */
628 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
629 SUNXI_FUNCTION(0x0, "gpio_in"),
630 SUNXI_FUNCTION(0x1, "gpio_out"),
631 SUNXI_FUNCTION(0x2, "ts1"), /* D4 */
632 SUNXI_FUNCTION(0x3, "csi1"), /* D4 */
633 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
634 SUNXI_FUNCTION(0x5, "csi0")), /* D12 */
635 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
636 SUNXI_FUNCTION(0x0, "gpio_in"),
637 SUNXI_FUNCTION(0x1, "gpio_out"),
638 SUNXI_FUNCTION(0x2, "ts1"), /* D5 */
639 SUNXI_FUNCTION(0x3, "csi1"), /* D5 */
640 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
641 SUNXI_FUNCTION(0x5, "csi0")), /* D13 */
642 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
643 SUNXI_FUNCTION(0x0, "gpio_in"),
644 SUNXI_FUNCTION(0x1, "gpio_out"),
645 SUNXI_FUNCTION(0x2, "ts1"), /* D6 */
646 SUNXI_FUNCTION(0x3, "csi1"), /* D6 */
647 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
648 SUNXI_FUNCTION(0x5, "csi0")), /* D14 */
649 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
650 SUNXI_FUNCTION(0x0, "gpio_in"),
651 SUNXI_FUNCTION(0x1, "gpio_out"),
652 SUNXI_FUNCTION(0x2, "ts1"), /* D7 */
653 SUNXI_FUNCTION(0x3, "csi1"), /* D7 */
654 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
655 SUNXI_FUNCTION(0x5, "csi0")), /* D15 */
656 /* Hole */
657 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0,
658 SUNXI_FUNCTION(0x0, "gpio_in"),
659 SUNXI_FUNCTION(0x1, "gpio_out"),
660 SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */
661 SUNXI_FUNCTION(0x3, "pata"), /* ATAA0 */
662 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
663 SUNXI_FUNCTION_IRQ(0x6, 0), /* EINT0 */
664 SUNXI_FUNCTION(0x7, "csi1")), /* D0 */
665 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1,
666 SUNXI_FUNCTION(0x0, "gpio_in"),
667 SUNXI_FUNCTION(0x1, "gpio_out"),
668 SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */
669 SUNXI_FUNCTION(0x3, "pata"), /* ATAA1 */
670 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
671 SUNXI_FUNCTION_IRQ(0x6, 1), /* EINT1 */
672 SUNXI_FUNCTION(0x7, "csi1")), /* D1 */
673 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2,
674 SUNXI_FUNCTION(0x0, "gpio_in"),
675 SUNXI_FUNCTION(0x1, "gpio_out"),
676 SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */
677 SUNXI_FUNCTION(0x3, "pata"), /* ATAA2 */
678 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
679 SUNXI_FUNCTION_IRQ(0x6, 2), /* EINT2 */
680 SUNXI_FUNCTION(0x7, "csi1")), /* D2 */
681 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3,
682 SUNXI_FUNCTION(0x0, "gpio_in"),
683 SUNXI_FUNCTION(0x1, "gpio_out"),
684 SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */
685 SUNXI_FUNCTION(0x3, "pata"), /* ATAIRQ */
686 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
687 SUNXI_FUNCTION_IRQ(0x6, 3), /* EINT3 */
688 SUNXI_FUNCTION(0x7, "csi1")), /* D3 */
689 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4,
690 SUNXI_FUNCTION(0x0, "gpio_in"),
691 SUNXI_FUNCTION(0x1, "gpio_out"),
692 SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */
693 SUNXI_FUNCTION(0x3, "pata"), /* ATAD0 */
694 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
695 SUNXI_FUNCTION_IRQ(0x6, 4), /* EINT4 */
696 SUNXI_FUNCTION(0x7, "csi1")), /* D4 */
697 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5,
698 SUNXI_FUNCTION(0x0, "gpio_in"),
699 SUNXI_FUNCTION(0x1, "gpio_out"),
700 SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */
701 SUNXI_FUNCTION(0x3, "pata"), /* ATAD1 */
702 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
703 SUNXI_FUNCTION_IRQ(0x6, 5), /* EINT5 */
704 SUNXI_FUNCTION(0x7, "csi1")), /* D5 */
705 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6,
706 SUNXI_FUNCTION(0x0, "gpio_in"),
707 SUNXI_FUNCTION(0x1, "gpio_out"),
708 SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */
709 SUNXI_FUNCTION(0x3, "pata"), /* ATAD2 */
710 SUNXI_FUNCTION(0x4, "uart5"), /* TX */
711 SUNXI_FUNCTION(0x5, "ms"), /* BS */
712 SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */
713 SUNXI_FUNCTION(0x7, "csi1")), /* D6 */
714 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7,
715 SUNXI_FUNCTION(0x0, "gpio_in"),
716 SUNXI_FUNCTION(0x1, "gpio_out"),
717 SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */
718 SUNXI_FUNCTION(0x3, "pata"), /* ATAD3 */
719 SUNXI_FUNCTION(0x4, "uart5"), /* RX */
720 SUNXI_FUNCTION(0x5, "ms"), /* CLK */
721 SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */
722 SUNXI_FUNCTION(0x7, "csi1")), /* D7 */
723 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8,
724 SUNXI_FUNCTION(0x0, "gpio_in"),
725 SUNXI_FUNCTION(0x1, "gpio_out"),
726 SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */
727 SUNXI_FUNCTION(0x3, "pata"), /* ATAD4 */
728 SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */
729 SUNXI_FUNCTION(0x5, "ms"), /* D0 */
730 SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */
731 SUNXI_FUNCTION(0x7, "csi1")), /* D8 */
732 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9,
733 SUNXI_FUNCTION(0x0, "gpio_in"),
734 SUNXI_FUNCTION(0x1, "gpio_out"),
735 SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */
736 SUNXI_FUNCTION(0x3, "pata"), /* ATAD5 */
737 SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */
738 SUNXI_FUNCTION(0x5, "ms"), /* D1 */
739 SUNXI_FUNCTION_IRQ(0x6, 9), /* EINT9 */
740 SUNXI_FUNCTION(0x7, "csi1")), /* D9 */
741 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10,
742 SUNXI_FUNCTION(0x0, "gpio_in"),
743 SUNXI_FUNCTION(0x1, "gpio_out"),
744 SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */
745 SUNXI_FUNCTION(0x3, "pata"), /* ATAD6 */
746 SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */
747 SUNXI_FUNCTION(0x5, "ms"), /* D2 */
748 SUNXI_FUNCTION_IRQ(0x6, 10), /* EINT10 */
749 SUNXI_FUNCTION(0x7, "csi1")), /* D10 */
750 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11,
751 SUNXI_FUNCTION(0x0, "gpio_in"),
752 SUNXI_FUNCTION(0x1, "gpio_out"),
753 SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */
754 SUNXI_FUNCTION(0x3, "pata"), /* ATAD7 */
755 SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */
756 SUNXI_FUNCTION(0x5, "ms"), /* D3 */
757 SUNXI_FUNCTION_IRQ(0x6, 11), /* EINT11 */
758 SUNXI_FUNCTION(0x7, "csi1")), /* D11 */
759 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12,
760 SUNXI_FUNCTION(0x0, "gpio_in"),
761 SUNXI_FUNCTION(0x1, "gpio_out"),
762 SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */
763 SUNXI_FUNCTION(0x3, "pata"), /* ATAD8 */
764 SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */
765 SUNXI_FUNCTION_IRQ(0x6, 12), /* EINT12 */
766 SUNXI_FUNCTION(0x7, "csi1")), /* D12 */
767 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13,
768 SUNXI_FUNCTION(0x0, "gpio_in"),
769 SUNXI_FUNCTION(0x1, "gpio_out"),
770 SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */
771 SUNXI_FUNCTION(0x3, "pata"), /* ATAD9 */
772 SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */
773 SUNXI_FUNCTION(0x5, "sim"), /* RST */
774 SUNXI_FUNCTION_IRQ(0x6, 13), /* EINT13 */
775 SUNXI_FUNCTION(0x7, "csi1")), /* D13 */
776 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14,
777 SUNXI_FUNCTION(0x0, "gpio_in"),
778 SUNXI_FUNCTION(0x1, "gpio_out"),
779 SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */
780 SUNXI_FUNCTION(0x3, "pata"), /* ATAD10 */
781 SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */
782 SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */
783 SUNXI_FUNCTION_IRQ(0x6, 14), /* EINT14 */
784 SUNXI_FUNCTION(0x7, "csi1")), /* D14 */
785 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15,
786 SUNXI_FUNCTION(0x0, "gpio_in"),
787 SUNXI_FUNCTION(0x1, "gpio_out"),
788 SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */
789 SUNXI_FUNCTION(0x3, "pata"), /* ATAD11 */
790 SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */
791 SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */
792 SUNXI_FUNCTION_IRQ(0x6, 15), /* EINT15 */
793 SUNXI_FUNCTION(0x7, "csi1")), /* D15 */
794 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16,
795 SUNXI_FUNCTION(0x0, "gpio_in"),
796 SUNXI_FUNCTION(0x1, "gpio_out"),
797 SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */
798 SUNXI_FUNCTION(0x3, "pata"), /* ATAD12 */
799 SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */
800 SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */
801 SUNXI_FUNCTION(0x7, "csi1")), /* D16 */
802 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17,
803 SUNXI_FUNCTION(0x0, "gpio_in"),
804 SUNXI_FUNCTION(0x1, "gpio_out"),
805 SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */
806 SUNXI_FUNCTION(0x3, "pata"), /* ATAD13 */
807 SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */
808 SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */
809 SUNXI_FUNCTION_IRQ(0x6, 17), /* EINT17 */
810 SUNXI_FUNCTION(0x7, "csi1")), /* D17 */
811 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18,
812 SUNXI_FUNCTION(0x0, "gpio_in"),
813 SUNXI_FUNCTION(0x1, "gpio_out"),
814 SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */
815 SUNXI_FUNCTION(0x3, "pata"), /* ATAD14 */
816 SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */
817 SUNXI_FUNCTION(0x5, "sim"), /* SCK */
818 SUNXI_FUNCTION_IRQ(0x6, 18), /* EINT18 */
819 SUNXI_FUNCTION(0x7, "csi1")), /* D18 */
820 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19,
821 SUNXI_FUNCTION(0x0, "gpio_in"),
822 SUNXI_FUNCTION(0x1, "gpio_out"),
823 SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */
824 SUNXI_FUNCTION(0x3, "pata"), /* ATAD15 */
825 SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */
826 SUNXI_FUNCTION(0x5, "sim"), /* SDA */
827 SUNXI_FUNCTION_IRQ(0x6, 19), /* EINT19 */
828 SUNXI_FUNCTION(0x7, "csi1")), /* D19 */
829 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20,
830 SUNXI_FUNCTION(0x0, "gpio_in"),
831 SUNXI_FUNCTION(0x1, "gpio_out"),
832 SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */
833 SUNXI_FUNCTION(0x3, "pata"), /* ATAOE */
834 SUNXI_FUNCTION(0x4, "can"), /* TX */
835 SUNXI_FUNCTION_IRQ(0x6, 20), /* EINT20 */
836 SUNXI_FUNCTION(0x7, "csi1")), /* D20 */
837 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21,
838 SUNXI_FUNCTION(0x0, "gpio_in"),
839 SUNXI_FUNCTION(0x1, "gpio_out"),
840 SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */
841 SUNXI_FUNCTION(0x3, "pata"), /* ATADREQ */
842 SUNXI_FUNCTION(0x4, "can"), /* RX */
843 SUNXI_FUNCTION_IRQ(0x6, 21), /* EINT21 */
844 SUNXI_FUNCTION(0x7, "csi1")), /* D21 */
845 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22,
846 SUNXI_FUNCTION(0x0, "gpio_in"),
847 SUNXI_FUNCTION(0x1, "gpio_out"),
848 SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */
849 SUNXI_FUNCTION(0x3, "pata"), /* ATADACK */
850 SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */
851 SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */
852 SUNXI_FUNCTION(0x7, "csi1")), /* D22 */
853 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23,
854 SUNXI_FUNCTION(0x0, "gpio_in"),
855 SUNXI_FUNCTION(0x1, "gpio_out"),
856 SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */
857 SUNXI_FUNCTION(0x3, "pata"), /* ATACS0 */
858 SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */
859 SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */
860 SUNXI_FUNCTION(0x7, "csi1")), /* D23 */
861 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24,
862 SUNXI_FUNCTION(0x0, "gpio_in"),
863 SUNXI_FUNCTION(0x1, "gpio_out"),
864 SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */
865 SUNXI_FUNCTION(0x3, "pata"), /* ATACS1 */
866 SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */
867 SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */
868 SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */
869 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25,
870 SUNXI_FUNCTION(0x0, "gpio_in"),
871 SUNXI_FUNCTION(0x1, "gpio_out"),
872 SUNXI_FUNCTION(0x2, "lcd1"), /* DE */
873 SUNXI_FUNCTION(0x3, "pata"), /* ATAIORDY */
874 SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */
875 SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */
876 SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */
877 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26,
878 SUNXI_FUNCTION(0x0, "gpio_in"),
879 SUNXI_FUNCTION(0x1, "gpio_out"),
880 SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */
881 SUNXI_FUNCTION(0x3, "pata"), /* ATAIOR */
882 SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */
883 SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */
884 SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */
885 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27,
886 SUNXI_FUNCTION(0x0, "gpio_in"),
887 SUNXI_FUNCTION(0x1, "gpio_out"),
888 SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */
889 SUNXI_FUNCTION(0x3, "pata"), /* ATAIOW */
890 SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */
891 SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */
892 SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */
893 /* Hole */
894 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0,
895 SUNXI_FUNCTION(0x0, "gpio_in"),
896 SUNXI_FUNCTION(0x1, "gpio_out")),
897 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI1,
898 SUNXI_FUNCTION(0x0, "gpio_in"),
899 SUNXI_FUNCTION(0x1, "gpio_out")),
900 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI2,
901 SUNXI_FUNCTION(0x0, "gpio_in"),
902 SUNXI_FUNCTION(0x1, "gpio_out")),
903 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3,
904 SUNXI_FUNCTION(0x0, "gpio_in"),
905 SUNXI_FUNCTION(0x1, "gpio_out"),
906 SUNXI_FUNCTION(0x2, "pwm")), /* PWM1 */
907 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4,
908 SUNXI_FUNCTION(0x0, "gpio_in"),
909 SUNXI_FUNCTION(0x1, "gpio_out"),
910 SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */
911 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5,
912 SUNXI_FUNCTION(0x0, "gpio_in"),
913 SUNXI_FUNCTION(0x1, "gpio_out"),
914 SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */
915 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6,
916 SUNXI_FUNCTION(0x0, "gpio_in"),
917 SUNXI_FUNCTION(0x1, "gpio_out"),
918 SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */
919 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7,
920 SUNXI_FUNCTION(0x0, "gpio_in"),
921 SUNXI_FUNCTION(0x1, "gpio_out"),
922 SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */
923 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8,
924 SUNXI_FUNCTION(0x0, "gpio_in"),
925 SUNXI_FUNCTION(0x1, "gpio_out"),
926 SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */
927 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9,
928 SUNXI_FUNCTION(0x0, "gpio_in"),
929 SUNXI_FUNCTION(0x1, "gpio_out"),
930 SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */
931 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10,
932 SUNXI_FUNCTION(0x0, "gpio_in"),
933 SUNXI_FUNCTION(0x1, "gpio_out"),
934 SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
935 SUNXI_FUNCTION(0x3, "uart5"), /* TX */
936 SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
937 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11,
938 SUNXI_FUNCTION(0x0, "gpio_in"),
939 SUNXI_FUNCTION(0x1, "gpio_out"),
940 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
941 SUNXI_FUNCTION(0x3, "uart5"), /* RX */
942 SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
943 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12,
944 SUNXI_FUNCTION(0x0, "gpio_in"),
945 SUNXI_FUNCTION(0x1, "gpio_out"),
946 SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
947 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
948 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
949 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13,
950 SUNXI_FUNCTION(0x0, "gpio_in"),
951 SUNXI_FUNCTION(0x1, "gpio_out"),
952 SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
953 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
954 SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
955 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14,
956 SUNXI_FUNCTION(0x0, "gpio_in"),
957 SUNXI_FUNCTION(0x1, "gpio_out"),
958 SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
959 SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
960 SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */
961 SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
962 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15,
963 SUNXI_FUNCTION(0x0, "gpio_in"),
964 SUNXI_FUNCTION(0x1, "gpio_out"),
965 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
966 SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
967 SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */
968 SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
969 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16,
970 SUNXI_FUNCTION(0x0, "gpio_in"),
971 SUNXI_FUNCTION(0x1, "gpio_out"),
972 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
973 SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
974 SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
975 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17,
976 SUNXI_FUNCTION(0x0, "gpio_in"),
977 SUNXI_FUNCTION(0x1, "gpio_out"),
978 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
979 SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
980 SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */
981 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18,
982 SUNXI_FUNCTION(0x0, "gpio_in"),
983 SUNXI_FUNCTION(0x1, "gpio_out"),
984 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
985 SUNXI_FUNCTION(0x3, "uart2"), /* TX */
986 SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */
987 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19,
988 SUNXI_FUNCTION(0x0, "gpio_in"),
989 SUNXI_FUNCTION(0x1, "gpio_out"),
990 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
991 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
992 SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */
993 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20,
994 SUNXI_FUNCTION(0x0, "gpio_in"),
995 SUNXI_FUNCTION(0x1, "gpio_out"),
996 SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */
997 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
998 SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */
999 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21,
1000 SUNXI_FUNCTION(0x0, "gpio_in"),
1001 SUNXI_FUNCTION(0x1, "gpio_out"),
1002 SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */
1003 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
1004 SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */
1005};
1006
1007static const struct sunxi_desc_pin sun5i_a10s_pins[] = {
1008 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
1009 SUNXI_FUNCTION(0x0, "gpio_in"),
1010 SUNXI_FUNCTION(0x1, "gpio_out"),
1011 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
1012 SUNXI_FUNCTION(0x3, "ts0"), /* CLK */
1013 SUNXI_FUNCTION(0x5, "keypad")), /* IN0 */
1014 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
1015 SUNXI_FUNCTION(0x0, "gpio_in"),
1016 SUNXI_FUNCTION(0x1, "gpio_out"),
1017 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
1018 SUNXI_FUNCTION(0x3, "ts0"), /* ERR */
1019 SUNXI_FUNCTION(0x5, "keypad")), /* IN1 */
1020 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
1021 SUNXI_FUNCTION(0x0, "gpio_in"),
1022 SUNXI_FUNCTION(0x1, "gpio_out"),
1023 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
1024 SUNXI_FUNCTION(0x3, "ts0"), /* SYNC */
1025 SUNXI_FUNCTION(0x5, "keypad")), /* IN2 */
1026 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
1027 SUNXI_FUNCTION(0x0, "gpio_in"),
1028 SUNXI_FUNCTION(0x1, "gpio_out"),
1029 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
1030 SUNXI_FUNCTION(0x3, "ts0"), /* DLVD */
1031 SUNXI_FUNCTION(0x5, "keypad")), /* IN3 */
1032 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
1033 SUNXI_FUNCTION(0x0, "gpio_in"),
1034 SUNXI_FUNCTION(0x1, "gpio_out"),
1035 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
1036 SUNXI_FUNCTION(0x3, "ts0"), /* D0 */
1037 SUNXI_FUNCTION(0x5, "keypad")), /* IN4 */
1038 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
1039 SUNXI_FUNCTION(0x0, "gpio_in"),
1040 SUNXI_FUNCTION(0x1, "gpio_out"),
1041 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
1042 SUNXI_FUNCTION(0x3, "ts0"), /* D1 */
1043 SUNXI_FUNCTION(0x5, "keypad")), /* IN5 */
1044 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
1045 SUNXI_FUNCTION(0x0, "gpio_in"),
1046 SUNXI_FUNCTION(0x1, "gpio_out"),
1047 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
1048 SUNXI_FUNCTION(0x3, "ts0"), /* D2 */
1049 SUNXI_FUNCTION(0x5, "keypad")), /* IN6 */
1050 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
1051 SUNXI_FUNCTION(0x0, "gpio_in"),
1052 SUNXI_FUNCTION(0x1, "gpio_out"),
1053 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
1054 SUNXI_FUNCTION(0x3, "ts0"), /* D3 */
1055 SUNXI_FUNCTION(0x5, "keypad")), /* IN7 */
1056 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
1057 SUNXI_FUNCTION(0x0, "gpio_in"),
1058 SUNXI_FUNCTION(0x1, "gpio_out"),
1059 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
1060 SUNXI_FUNCTION(0x3, "ts0"), /* D4 */
1061 SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
1062 SUNXI_FUNCTION(0x5, "keypad")), /* OUT0 */
1063 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
1064 SUNXI_FUNCTION(0x0, "gpio_in"),
1065 SUNXI_FUNCTION(0x1, "gpio_out"),
1066 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
1067 SUNXI_FUNCTION(0x3, "ts0"), /* D5 */
1068 SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
1069 SUNXI_FUNCTION(0x5, "keypad")), /* OUT1 */
1070 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
1071 SUNXI_FUNCTION(0x0, "gpio_in"),
1072 SUNXI_FUNCTION(0x1, "gpio_out"),
1073 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
1074 SUNXI_FUNCTION(0x3, "ts0"), /* D6 */
1075 SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
1076 SUNXI_FUNCTION(0x5, "keypad")), /* OUT2 */
1077 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
1078 SUNXI_FUNCTION(0x0, "gpio_in"),
1079 SUNXI_FUNCTION(0x1, "gpio_out"),
1080 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
1081 SUNXI_FUNCTION(0x3, "ts0"), /* D7 */
1082 SUNXI_FUNCTION(0x4, "uart1"), /* RING */
1083 SUNXI_FUNCTION(0x5, "keypad")), /* OUT3 */
1084 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
1085 SUNXI_FUNCTION(0x0, "gpio_in"),
1086 SUNXI_FUNCTION(0x1, "gpio_out"),
1087 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
1088 SUNXI_FUNCTION(0x3, "uart1"), /* TX */
1089 SUNXI_FUNCTION(0x5, "keypad")), /* OUT4 */
1090 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
1091 SUNXI_FUNCTION(0x0, "gpio_in"),
1092 SUNXI_FUNCTION(0x1, "gpio_out"),
1093 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
1094 SUNXI_FUNCTION(0x3, "uart1"), /* RX */
1095 SUNXI_FUNCTION(0x5, "keypad")), /* OUT5 */
1096 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
1097 SUNXI_FUNCTION(0x0, "gpio_in"),
1098 SUNXI_FUNCTION(0x1, "gpio_out"),
1099 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
1100 SUNXI_FUNCTION(0x3, "uart1"), /* CTS */
1101 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
1102 SUNXI_FUNCTION(0x5, "keypad")), /* OUT6 */
1103 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
1104 SUNXI_FUNCTION(0x0, "gpio_in"),
1105 SUNXI_FUNCTION(0x1, "gpio_out"),
1106 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
1107 SUNXI_FUNCTION(0x3, "uart1"), /* RTS */
1108 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
1109 SUNXI_FUNCTION(0x5, "keypad")), /* OUT7 */
1110 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
1111 SUNXI_FUNCTION(0x0, "gpio_in"),
1112 SUNXI_FUNCTION(0x1, "gpio_out"),
1113 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
1114 SUNXI_FUNCTION(0x3, "uart2")), /* TX */
1115 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
1116 SUNXI_FUNCTION(0x0, "gpio_in"),
1117 SUNXI_FUNCTION(0x1, "gpio_out"),
1118 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
1119 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
1120 SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */
1121 /* Hole */
1122 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
1123 SUNXI_FUNCTION(0x0, "gpio_in"),
1124 SUNXI_FUNCTION(0x1, "gpio_out"),
1125 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
1126 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
1127 SUNXI_FUNCTION(0x0, "gpio_in"),
1128 SUNXI_FUNCTION(0x1, "gpio_out"),
1129 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
1130 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
1131 SUNXI_FUNCTION(0x0, "gpio_in"),
1132 SUNXI_FUNCTION(0x1, "gpio_out"),
1133 SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */
1134 SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */
1135 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
1136 SUNXI_FUNCTION(0x0, "gpio_in"),
1137 SUNXI_FUNCTION(0x1, "gpio_out"),
1138 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
1139 SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */
1140 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
1141 SUNXI_FUNCTION(0x0, "gpio_in"),
1142 SUNXI_FUNCTION(0x1, "gpio_out"),
1143 SUNXI_FUNCTION(0x2, "ir0"), /* RX */
1144 SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */
1145 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
1146 SUNXI_FUNCTION(0x0, "gpio_in"),
1147 SUNXI_FUNCTION(0x1, "gpio_out"),
1148 SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
1149 SUNXI_FUNCTION_IRQ(0x6, 19)), /* EINT19 */
1150 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
1151 SUNXI_FUNCTION(0x0, "gpio_in"),
1152 SUNXI_FUNCTION(0x1, "gpio_out"),
1153 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
1154 SUNXI_FUNCTION_IRQ(0x6, 20)), /* EINT20 */
1155 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
1156 SUNXI_FUNCTION(0x0, "gpio_in"),
1157 SUNXI_FUNCTION(0x1, "gpio_out"),
1158 SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */
1159 SUNXI_FUNCTION_IRQ(0x6, 21)), /* EINT21 */
1160 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8,
1161 SUNXI_FUNCTION(0x0, "gpio_in"),
1162 SUNXI_FUNCTION(0x1, "gpio_out"),
1163 SUNXI_FUNCTION(0x2, "i2s"), /* DO */
1164 SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
1165 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9,
1166 SUNXI_FUNCTION(0x0, "gpio_in"),
1167 SUNXI_FUNCTION(0x1, "gpio_out"),
1168 SUNXI_FUNCTION(0x2, "i2s"), /* DI */
1169 SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
1170 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
1171 SUNXI_FUNCTION(0x0, "gpio_in"),
1172 SUNXI_FUNCTION(0x1, "gpio_out"),
1173 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
1174 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
1175 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11,
1176 SUNXI_FUNCTION(0x0, "gpio_in"),
1177 SUNXI_FUNCTION(0x1, "gpio_out"),
1178 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
1179 SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
1180 SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
1181 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12,
1182 SUNXI_FUNCTION(0x0, "gpio_in"),
1183 SUNXI_FUNCTION(0x1, "gpio_out"),
1184 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
1185 SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
1186 SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
1187 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13,
1188 SUNXI_FUNCTION(0x0, "gpio_in"),
1189 SUNXI_FUNCTION(0x1, "gpio_out"),
1190 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
1191 SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
1192 SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
1193 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14,
1194 SUNXI_FUNCTION(0x0, "gpio_in"),
1195 SUNXI_FUNCTION(0x1, "gpio_out"),
1196 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
1197 SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
1198 SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
1199 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
1200 SUNXI_FUNCTION(0x0, "gpio_in"),
1201 SUNXI_FUNCTION(0x1, "gpio_out"),
1202 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
1203 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
1204 SUNXI_FUNCTION(0x0, "gpio_in"),
1205 SUNXI_FUNCTION(0x1, "gpio_out"),
1206 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
1207 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
1208 SUNXI_FUNCTION(0x0, "gpio_in"),
1209 SUNXI_FUNCTION(0x1, "gpio_out"),
1210 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
1211 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
1212 SUNXI_FUNCTION(0x0, "gpio_in"),
1213 SUNXI_FUNCTION(0x1, "gpio_out"),
1214 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
1215 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19,
1216 SUNXI_FUNCTION(0x0, "gpio_in"),
1217 SUNXI_FUNCTION(0x1, "gpio_out"),
1218 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
1219 SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */
1220 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20,
1221 SUNXI_FUNCTION(0x0, "gpio_in"),
1222 SUNXI_FUNCTION(0x1, "gpio_out"),
1223 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
1224 SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */
1225 /* Hole */
1226 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
1227 SUNXI_FUNCTION(0x0, "gpio_in"),
1228 SUNXI_FUNCTION(0x1, "gpio_out"),
1229 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
1230 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
1231 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
1232 SUNXI_FUNCTION(0x0, "gpio_in"),
1233 SUNXI_FUNCTION(0x1, "gpio_out"),
1234 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
1235 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
1236 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
1237 SUNXI_FUNCTION(0x0, "gpio_in"),
1238 SUNXI_FUNCTION(0x1, "gpio_out"),
1239 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
1240 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
1241 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
1242 SUNXI_FUNCTION(0x0, "gpio_in"),
1243 SUNXI_FUNCTION(0x1, "gpio_out"),
1244 SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
1245 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
1246 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
1247 SUNXI_FUNCTION(0x0, "gpio_in"),
1248 SUNXI_FUNCTION(0x1, "gpio_out"),
1249 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
1250 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
1251 SUNXI_FUNCTION(0x0, "gpio_in"),
1252 SUNXI_FUNCTION(0x1, "gpio_out"),
1253 SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
1254 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
1255 SUNXI_FUNCTION(0x0, "gpio_in"),
1256 SUNXI_FUNCTION(0x1, "gpio_out"),
1257 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
1258 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
1259 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
1260 SUNXI_FUNCTION(0x0, "gpio_in"),
1261 SUNXI_FUNCTION(0x1, "gpio_out"),
1262 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
1263 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
1264 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
1265 SUNXI_FUNCTION(0x0, "gpio_in"),
1266 SUNXI_FUNCTION(0x1, "gpio_out"),
1267 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
1268 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
1269 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
1270 SUNXI_FUNCTION(0x0, "gpio_in"),
1271 SUNXI_FUNCTION(0x1, "gpio_out"),
1272 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
1273 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
1274 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
1275 SUNXI_FUNCTION(0x0, "gpio_in"),
1276 SUNXI_FUNCTION(0x1, "gpio_out"),
1277 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
1278 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
1279 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
1280 SUNXI_FUNCTION(0x0, "gpio_in"),
1281 SUNXI_FUNCTION(0x1, "gpio_out"),
1282 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
1283 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
1284 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
1285 SUNXI_FUNCTION(0x0, "gpio_in"),
1286 SUNXI_FUNCTION(0x1, "gpio_out"),
1287 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
1288 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
1289 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
1290 SUNXI_FUNCTION(0x0, "gpio_in"),
1291 SUNXI_FUNCTION(0x1, "gpio_out"),
1292 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
1293 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
1294 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
1295 SUNXI_FUNCTION(0x0, "gpio_in"),
1296 SUNXI_FUNCTION(0x1, "gpio_out"),
1297 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
1298 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
1299 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
1300 SUNXI_FUNCTION(0x0, "gpio_in"),
1301 SUNXI_FUNCTION(0x1, "gpio_out"),
1302 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
1303 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
1304 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
1305 SUNXI_FUNCTION(0x0, "gpio_in"),
1306 SUNXI_FUNCTION(0x1, "gpio_out"),
1307 SUNXI_FUNCTION(0x2, "nand0"), /* NWP */
1308 SUNXI_FUNCTION(0x4, "uart3")), /* TX */
1309 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
1310 SUNXI_FUNCTION(0x0, "gpio_in"),
1311 SUNXI_FUNCTION(0x1, "gpio_out"),
1312 SUNXI_FUNCTION(0x2, "nand0"), /* NCE2 */
1313 SUNXI_FUNCTION(0x4, "uart3")), /* RX */
1314 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
1315 SUNXI_FUNCTION(0x0, "gpio_in"),
1316 SUNXI_FUNCTION(0x1, "gpio_out"),
1317 SUNXI_FUNCTION(0x2, "nand0"), /* NCE3 */
1318 SUNXI_FUNCTION(0x3, "uart2"), /* TX */
1319 SUNXI_FUNCTION(0x4, "uart3")), /* CTS */
1320 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
1321 SUNXI_FUNCTION(0x0, "gpio_in"),
1322 SUNXI_FUNCTION(0x1, "gpio_out"),
1323 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
1324 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
1325 SUNXI_FUNCTION(0x4, "uart3")), /* RTS */
1326 /* Hole */
1327 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
1328 SUNXI_FUNCTION(0x0, "gpio_in"),
1329 SUNXI_FUNCTION(0x1, "gpio_out"),
1330 SUNXI_FUNCTION(0x2, "lcd0")), /* D0 */
1331 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
1332 SUNXI_FUNCTION(0x0, "gpio_in"),
1333 SUNXI_FUNCTION(0x1, "gpio_out"),
1334 SUNXI_FUNCTION(0x2, "lcd0")), /* D1 */
1335 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
1336 SUNXI_FUNCTION(0x0, "gpio_in"),
1337 SUNXI_FUNCTION(0x1, "gpio_out"),
1338 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
1339 SUNXI_FUNCTION(0x3, "uart2")), /* TX */
1340 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
1341 SUNXI_FUNCTION(0x0, "gpio_in"),
1342 SUNXI_FUNCTION(0x1, "gpio_out"),
1343 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
1344 SUNXI_FUNCTION(0x3, "uart2")), /* RX */
1345 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
1346 SUNXI_FUNCTION(0x0, "gpio_in"),
1347 SUNXI_FUNCTION(0x1, "gpio_out"),
1348 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
1349 SUNXI_FUNCTION(0x3, "uart2")), /* CTS */
1350 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
1351 SUNXI_FUNCTION(0x0, "gpio_in"),
1352 SUNXI_FUNCTION(0x1, "gpio_out"),
1353 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
1354 SUNXI_FUNCTION(0x3, "uart2")), /* RTS */
1355 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
1356 SUNXI_FUNCTION(0x0, "gpio_in"),
1357 SUNXI_FUNCTION(0x1, "gpio_out"),
1358 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
1359 SUNXI_FUNCTION(0x3, "emac")), /* ECRS */
1360 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
1361 SUNXI_FUNCTION(0x0, "gpio_in"),
1362 SUNXI_FUNCTION(0x1, "gpio_out"),
1363 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
1364 SUNXI_FUNCTION(0x3, "emac")), /* ECOL */
1365 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
1366 SUNXI_FUNCTION(0x0, "gpio_in"),
1367 SUNXI_FUNCTION(0x1, "gpio_out"),
1368 SUNXI_FUNCTION(0x2, "lcd0")), /* D8 */
1369 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
1370 SUNXI_FUNCTION(0x0, "gpio_in"),
1371 SUNXI_FUNCTION(0x1, "gpio_out"),
1372 SUNXI_FUNCTION(0x2, "lcd0")), /* D9 */
1373 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
1374 SUNXI_FUNCTION(0x0, "gpio_in"),
1375 SUNXI_FUNCTION(0x1, "gpio_out"),
1376 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
1377 SUNXI_FUNCTION(0x3, "emac")), /* ERXD0 */
1378 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
1379 SUNXI_FUNCTION(0x0, "gpio_in"),
1380 SUNXI_FUNCTION(0x1, "gpio_out"),
1381 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
1382 SUNXI_FUNCTION(0x3, "emac")), /* ERXD1 */
1383 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
1384 SUNXI_FUNCTION(0x0, "gpio_in"),
1385 SUNXI_FUNCTION(0x1, "gpio_out"),
1386 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
1387 SUNXI_FUNCTION(0x3, "emac")), /* ERXD2 */
1388 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
1389 SUNXI_FUNCTION(0x0, "gpio_in"),
1390 SUNXI_FUNCTION(0x1, "gpio_out"),
1391 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
1392 SUNXI_FUNCTION(0x3, "emac")), /* ERXD3 */
1393 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
1394 SUNXI_FUNCTION(0x0, "gpio_in"),
1395 SUNXI_FUNCTION(0x1, "gpio_out"),
1396 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
1397 SUNXI_FUNCTION(0x3, "emac")), /* ERXCK */
1398 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
1399 SUNXI_FUNCTION(0x0, "gpio_in"),
1400 SUNXI_FUNCTION(0x1, "gpio_out"),
1401 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
1402 SUNXI_FUNCTION(0x3, "emac")), /* ERXERR */
1403 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
1404 SUNXI_FUNCTION(0x0, "gpio_in"),
1405 SUNXI_FUNCTION(0x1, "gpio_out"),
1406 SUNXI_FUNCTION(0x2, "lcd0")), /* D16 */
1407 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
1408 SUNXI_FUNCTION(0x0, "gpio_in"),
1409 SUNXI_FUNCTION(0x1, "gpio_out"),
1410 SUNXI_FUNCTION(0x2, "lcd0")), /* D17 */
1411 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
1412 SUNXI_FUNCTION(0x0, "gpio_in"),
1413 SUNXI_FUNCTION(0x1, "gpio_out"),
1414 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
1415 SUNXI_FUNCTION(0x3, "emac")), /* ERXDV */
1416 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
1417 SUNXI_FUNCTION(0x0, "gpio_in"),
1418 SUNXI_FUNCTION(0x1, "gpio_out"),
1419 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
1420 SUNXI_FUNCTION(0x3, "emac")), /* ETXD0 */
1421 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
1422 SUNXI_FUNCTION(0x0, "gpio_in"),
1423 SUNXI_FUNCTION(0x1, "gpio_out"),
1424 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
1425 SUNXI_FUNCTION(0x3, "emac")), /* ETXD1 */
1426 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
1427 SUNXI_FUNCTION(0x0, "gpio_in"),
1428 SUNXI_FUNCTION(0x1, "gpio_out"),
1429 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
1430 SUNXI_FUNCTION(0x3, "emac")), /* ETXD2 */
1431 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
1432 SUNXI_FUNCTION(0x0, "gpio_in"),
1433 SUNXI_FUNCTION(0x1, "gpio_out"),
1434 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
1435 SUNXI_FUNCTION(0x3, "emac")), /* ETXD3 */
1436 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
1437 SUNXI_FUNCTION(0x0, "gpio_in"),
1438 SUNXI_FUNCTION(0x1, "gpio_out"),
1439 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
1440 SUNXI_FUNCTION(0x3, "emac")), /* ETXEN */
1441 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
1442 SUNXI_FUNCTION(0x0, "gpio_in"),
1443 SUNXI_FUNCTION(0x1, "gpio_out"),
1444 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
1445 SUNXI_FUNCTION(0x3, "emac")), /* ETXCK */
1446 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
1447 SUNXI_FUNCTION(0x0, "gpio_in"),
1448 SUNXI_FUNCTION(0x1, "gpio_out"),
1449 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
1450 SUNXI_FUNCTION(0x3, "emac")), /* ETXERR */
1451 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
1452 SUNXI_FUNCTION(0x0, "gpio_in"),
1453 SUNXI_FUNCTION(0x1, "gpio_out"),
1454 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
1455 SUNXI_FUNCTION(0x3, "emac")), /* EMDC */
1456 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
1457 SUNXI_FUNCTION(0x0, "gpio_in"),
1458 SUNXI_FUNCTION(0x1, "gpio_out"),
1459 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
1460 SUNXI_FUNCTION(0x3, "emac")), /* EMDIO */
1461 /* Hole */
1462 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
1463 SUNXI_FUNCTION(0x0, "gpio_in"),
1464 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
1465 SUNXI_FUNCTION(0x3, "csi0"), /* PCK */
1466 SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */
1467 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
1468 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
1469 SUNXI_FUNCTION(0x0, "gpio_in"),
1470 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
1471 SUNXI_FUNCTION(0x3, "csi0"), /* CK */
1472 SUNXI_FUNCTION(0x4, "spi2"), /* CLK */
1473 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
1474 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
1475 SUNXI_FUNCTION(0x0, "gpio_in"),
1476 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
1477 SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */
1478 SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */
1479 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
1480 SUNXI_FUNCTION(0x0, "gpio_in"),
1481 SUNXI_FUNCTION(0x1, "gpio_out"),
1482 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
1483 SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */
1484 SUNXI_FUNCTION(0x4, "spi2")), /* MISO */
1485 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
1486 SUNXI_FUNCTION(0x0, "gpio_in"),
1487 SUNXI_FUNCTION(0x1, "gpio_out"),
1488 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
1489 SUNXI_FUNCTION(0x3, "csi0"), /* D0 */
1490 SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */
1491 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
1492 SUNXI_FUNCTION(0x0, "gpio_in"),
1493 SUNXI_FUNCTION(0x1, "gpio_out"),
1494 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
1495 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
1496 SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */
1497 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
1498 SUNXI_FUNCTION(0x0, "gpio_in"),
1499 SUNXI_FUNCTION(0x1, "gpio_out"),
1500 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
1501 SUNXI_FUNCTION(0x3, "csi0"), /* D2 */
1502 SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */
1503 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
1504 SUNXI_FUNCTION(0x0, "gpio_in"),
1505 SUNXI_FUNCTION(0x1, "gpio_out"),
1506 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
1507 SUNXI_FUNCTION(0x3, "csi0"), /* D3 */
1508 SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */
1509 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
1510 SUNXI_FUNCTION(0x0, "gpio_in"),
1511 SUNXI_FUNCTION(0x1, "gpio_out"),
1512 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
1513 SUNXI_FUNCTION(0x3, "csi0"), /* D4 */
1514 SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */
1515 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
1516 SUNXI_FUNCTION(0x0, "gpio_in"),
1517 SUNXI_FUNCTION(0x1, "gpio_out"),
1518 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
1519 SUNXI_FUNCTION(0x3, "csi0"), /* D5 */
1520 SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */
1521 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
1522 SUNXI_FUNCTION(0x0, "gpio_in"),
1523 SUNXI_FUNCTION(0x1, "gpio_out"),
1524 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
1525 SUNXI_FUNCTION(0x3, "csi0"), /* D6 */
1526 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
1527 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
1528 SUNXI_FUNCTION(0x0, "gpio_in"),
1529 SUNXI_FUNCTION(0x1, "gpio_out"),
1530 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
1531 SUNXI_FUNCTION(0x3, "csi0"), /* D7 */
1532 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
1533 /* Hole */
1534 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
1535 SUNXI_FUNCTION(0x0, "gpio_in"),
1536 SUNXI_FUNCTION(0x1, "gpio_out"),
1537 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
1538 SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
1539 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
1540 SUNXI_FUNCTION(0x0, "gpio_in"),
1541 SUNXI_FUNCTION(0x1, "gpio_out"),
1542 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
1543 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
1544 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
1545 SUNXI_FUNCTION(0x0, "gpio_in"),
1546 SUNXI_FUNCTION(0x1, "gpio_out"),
1547 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
1548 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
1549 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
1550 SUNXI_FUNCTION(0x0, "gpio_in"),
1551 SUNXI_FUNCTION(0x1, "gpio_out"),
1552 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
1553 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
1554 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
1555 SUNXI_FUNCTION(0x0, "gpio_in"),
1556 SUNXI_FUNCTION(0x1, "gpio_out"),
1557 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
1558 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
1559 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
1560 SUNXI_FUNCTION(0x0, "gpio_in"),
1561 SUNXI_FUNCTION(0x1, "gpio_out"),
1562 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
1563 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
1564 /* Hole */
1565 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
1566 SUNXI_FUNCTION(0x0, "gpio_in"),
1567 SUNXI_FUNCTION(0x2, "gps"), /* CLK */
1568 SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */
1569 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
1570 SUNXI_FUNCTION(0x0, "gpio_in"),
1571 SUNXI_FUNCTION(0x2, "gps"), /* SIGN */
1572 SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */
1573 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
1574 SUNXI_FUNCTION(0x0, "gpio_in"),
1575 SUNXI_FUNCTION(0x2, "gps"), /* MAG */
1576 SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */
1577 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
1578 SUNXI_FUNCTION(0x0, "gpio_in"),
1579 SUNXI_FUNCTION(0x1, "gpio_out"),
1580 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
1581 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
1582 SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */
1583 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
1584 SUNXI_FUNCTION(0x0, "gpio_in"),
1585 SUNXI_FUNCTION(0x1, "gpio_out"),
1586 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
1587 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
1588 SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */
1589 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
1590 SUNXI_FUNCTION(0x0, "gpio_in"),
1591 SUNXI_FUNCTION(0x1, "gpio_out"),
1592 SUNXI_FUNCTION(0x2, "mmc1"), /* DO */
1593 SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
1594 SUNXI_FUNCTION_IRQ(0x6, 5)), /* EINT5 */
1595 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
1596 SUNXI_FUNCTION(0x0, "gpio_in"),
1597 SUNXI_FUNCTION(0x1, "gpio_out"),
1598 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
1599 SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
1600 SUNXI_FUNCTION(0x5, "uart2"), /* RTS */
1601 SUNXI_FUNCTION_IRQ(0x6, 6)), /* EINT6 */
1602 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
1603 SUNXI_FUNCTION(0x0, "gpio_in"),
1604 SUNXI_FUNCTION(0x1, "gpio_out"),
1605 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
1606 SUNXI_FUNCTION(0x5, "uart2"), /* TX */
1607 SUNXI_FUNCTION_IRQ(0x6, 7)), /* EINT7 */
1608 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
1609 SUNXI_FUNCTION(0x0, "gpio_in"),
1610 SUNXI_FUNCTION(0x1, "gpio_out"),
1611 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
1612 SUNXI_FUNCTION(0x5, "uart2"), /* RX */
1613 SUNXI_FUNCTION_IRQ(0x6, 8)), /* EINT8 */
1614 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
1615 SUNXI_FUNCTION(0x0, "gpio_in"),
1616 SUNXI_FUNCTION(0x1, "gpio_out"),
1617 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
1618 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
1619 SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */
1620 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
1621 SUNXI_FUNCTION(0x0, "gpio_in"),
1622 SUNXI_FUNCTION(0x1, "gpio_out"),
1623 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
1624 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
1625 SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */
1626 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
1627 SUNXI_FUNCTION(0x0, "gpio_in"),
1628 SUNXI_FUNCTION(0x1, "gpio_out"),
1629 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
1630 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
1631 SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */
1632 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12,
1633 SUNXI_FUNCTION(0x0, "gpio_in"),
1634 SUNXI_FUNCTION(0x1, "gpio_out"),
1635 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
1636 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
1637 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
1638 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG13,
1639 SUNXI_FUNCTION(0x0, "gpio_in"),
1640 SUNXI_FUNCTION(0x1, "gpio_out"),
1641 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
1642 SUNXI_FUNCTION(0x3, "uart3"), /* PWM1 */
1643 SUNXI_FUNCTION(0x5, "uart2"), /* CTS */
1644 SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
1645};
1646
1647static const struct sunxi_desc_pin sun5i_a13_pins[] = {
1648 /* Hole */
1649 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
1650 SUNXI_FUNCTION(0x0, "gpio_in"),
1651 SUNXI_FUNCTION(0x1, "gpio_out"),
1652 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
1653 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
1654 SUNXI_FUNCTION(0x0, "gpio_in"),
1655 SUNXI_FUNCTION(0x1, "gpio_out"),
1656 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
1657 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
1658 SUNXI_FUNCTION(0x0, "gpio_in"),
1659 SUNXI_FUNCTION(0x1, "gpio_out"),
1660 SUNXI_FUNCTION(0x2, "pwm"),
1661 SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */
1662 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
1663 SUNXI_FUNCTION(0x0, "gpio_in"),
1664 SUNXI_FUNCTION(0x1, "gpio_out"),
1665 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
1666 SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */
1667 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
1668 SUNXI_FUNCTION(0x0, "gpio_in"),
1669 SUNXI_FUNCTION(0x1, "gpio_out"),
1670 SUNXI_FUNCTION(0x2, "ir0"), /* RX */
1671 SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */
1672 /* Hole */
1673 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
1674 SUNXI_FUNCTION(0x0, "gpio_in"),
1675 SUNXI_FUNCTION(0x1, "gpio_out"),
1676 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
1677 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
1678 /* Hole */
1679 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
1680 SUNXI_FUNCTION(0x0, "gpio_in"),
1681 SUNXI_FUNCTION(0x1, "gpio_out"),
1682 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
1683 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
1684 SUNXI_FUNCTION(0x0, "gpio_in"),
1685 SUNXI_FUNCTION(0x1, "gpio_out"),
1686 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
1687 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
1688 SUNXI_FUNCTION(0x0, "gpio_in"),
1689 SUNXI_FUNCTION(0x1, "gpio_out"),
1690 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
1691 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
1692 SUNXI_FUNCTION(0x0, "gpio_in"),
1693 SUNXI_FUNCTION(0x1, "gpio_out"),
1694 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
1695 /* Hole */
1696 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
1697 SUNXI_FUNCTION(0x0, "gpio_in"),
1698 SUNXI_FUNCTION(0x1, "gpio_out"),
1699 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
1700 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
1701 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
1702 SUNXI_FUNCTION(0x0, "gpio_in"),
1703 SUNXI_FUNCTION(0x1, "gpio_out"),
1704 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
1705 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
1706 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
1707 SUNXI_FUNCTION(0x0, "gpio_in"),
1708 SUNXI_FUNCTION(0x1, "gpio_out"),
1709 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
1710 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
1711 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
1712 SUNXI_FUNCTION(0x0, "gpio_in"),
1713 SUNXI_FUNCTION(0x1, "gpio_out"),
1714 SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
1715 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
1716 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
1717 SUNXI_FUNCTION(0x0, "gpio_in"),
1718 SUNXI_FUNCTION(0x1, "gpio_out"),
1719 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
1720 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
1721 SUNXI_FUNCTION(0x0, "gpio_in"),
1722 SUNXI_FUNCTION(0x1, "gpio_out"),
1723 SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
1724 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
1725 SUNXI_FUNCTION(0x0, "gpio_in"),
1726 SUNXI_FUNCTION(0x1, "gpio_out"),
1727 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
1728 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
1729 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
1730 SUNXI_FUNCTION(0x0, "gpio_in"),
1731 SUNXI_FUNCTION(0x1, "gpio_out"),
1732 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
1733 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
1734 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
1735 SUNXI_FUNCTION(0x0, "gpio_in"),
1736 SUNXI_FUNCTION(0x1, "gpio_out"),
1737 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
1738 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
1739 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
1740 SUNXI_FUNCTION(0x0, "gpio_in"),
1741 SUNXI_FUNCTION(0x1, "gpio_out"),
1742 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
1743 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
1744 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
1745 SUNXI_FUNCTION(0x0, "gpio_in"),
1746 SUNXI_FUNCTION(0x1, "gpio_out"),
1747 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
1748 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
1749 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
1750 SUNXI_FUNCTION(0x0, "gpio_in"),
1751 SUNXI_FUNCTION(0x1, "gpio_out"),
1752 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
1753 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
1754 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
1755 SUNXI_FUNCTION(0x0, "gpio_in"),
1756 SUNXI_FUNCTION(0x1, "gpio_out"),
1757 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
1758 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
1759 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
1760 SUNXI_FUNCTION(0x0, "gpio_in"),
1761 SUNXI_FUNCTION(0x1, "gpio_out"),
1762 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
1763 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
1764 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
1765 SUNXI_FUNCTION(0x0, "gpio_in"),
1766 SUNXI_FUNCTION(0x1, "gpio_out"),
1767 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
1768 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
1769 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
1770 SUNXI_FUNCTION(0x0, "gpio_in"),
1771 SUNXI_FUNCTION(0x1, "gpio_out"),
1772 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
1773 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
1774 /* Hole */
1775 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
1776 SUNXI_FUNCTION(0x0, "gpio_in"),
1777 SUNXI_FUNCTION(0x1, "gpio_out"),
1778 SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */
1779 SUNXI_FUNCTION(0x4, "uart3")), /* RTS */
1780 /* Hole */
1781 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
1782 SUNXI_FUNCTION(0x0, "gpio_in"),
1783 SUNXI_FUNCTION(0x1, "gpio_out"),
1784 SUNXI_FUNCTION(0x2, "lcd0")), /* D2 */
1785 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
1786 SUNXI_FUNCTION(0x0, "gpio_in"),
1787 SUNXI_FUNCTION(0x1, "gpio_out"),
1788 SUNXI_FUNCTION(0x2, "lcd0")), /* D3 */
1789 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
1790 SUNXI_FUNCTION(0x0, "gpio_in"),
1791 SUNXI_FUNCTION(0x1, "gpio_out"),
1792 SUNXI_FUNCTION(0x2, "lcd0")), /* D4 */
1793 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
1794 SUNXI_FUNCTION(0x0, "gpio_in"),
1795 SUNXI_FUNCTION(0x1, "gpio_out"),
1796 SUNXI_FUNCTION(0x2, "lcd0")), /* D5 */
1797 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
1798 SUNXI_FUNCTION(0x0, "gpio_in"),
1799 SUNXI_FUNCTION(0x1, "gpio_out"),
1800 SUNXI_FUNCTION(0x2, "lcd0")), /* D6 */
1801 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
1802 SUNXI_FUNCTION(0x0, "gpio_in"),
1803 SUNXI_FUNCTION(0x1, "gpio_out"),
1804 SUNXI_FUNCTION(0x2, "lcd0")), /* D7 */
1805 /* Hole */
1806 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
1807 SUNXI_FUNCTION(0x0, "gpio_in"),
1808 SUNXI_FUNCTION(0x1, "gpio_out"),
1809 SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */
1810 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
1811 SUNXI_FUNCTION(0x0, "gpio_in"),
1812 SUNXI_FUNCTION(0x1, "gpio_out"),
1813 SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */
1814 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
1815 SUNXI_FUNCTION(0x0, "gpio_in"),
1816 SUNXI_FUNCTION(0x1, "gpio_out"),
1817 SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */
1818 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
1819 SUNXI_FUNCTION(0x0, "gpio_in"),
1820 SUNXI_FUNCTION(0x1, "gpio_out"),
1821 SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */
1822 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
1823 SUNXI_FUNCTION(0x0, "gpio_in"),
1824 SUNXI_FUNCTION(0x1, "gpio_out"),
1825 SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
1826 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
1827 SUNXI_FUNCTION(0x0, "gpio_in"),
1828 SUNXI_FUNCTION(0x1, "gpio_out"),
1829 SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
1830 /* Hole */
1831 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
1832 SUNXI_FUNCTION(0x0, "gpio_in"),
1833 SUNXI_FUNCTION(0x1, "gpio_out"),
1834 SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */
1835 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
1836 SUNXI_FUNCTION(0x0, "gpio_in"),
1837 SUNXI_FUNCTION(0x1, "gpio_out"),
1838 SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */
1839 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
1840 SUNXI_FUNCTION(0x0, "gpio_in"),
1841 SUNXI_FUNCTION(0x1, "gpio_out"),
1842 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
1843 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
1844 SUNXI_FUNCTION(0x0, "gpio_in"),
1845 SUNXI_FUNCTION(0x1, "gpio_out"),
1846 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
1847 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
1848 SUNXI_FUNCTION(0x0, "gpio_in"),
1849 SUNXI_FUNCTION(0x1, "gpio_out"),
1850 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
1851 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
1852 SUNXI_FUNCTION(0x0, "gpio_in"),
1853 SUNXI_FUNCTION(0x1, "gpio_out"),
1854 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
1855 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
1856 SUNXI_FUNCTION(0x0, "gpio_in"),
1857 SUNXI_FUNCTION(0x1, "gpio_out"),
1858 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
1859 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
1860 SUNXI_FUNCTION(0x0, "gpio_in"),
1861 SUNXI_FUNCTION(0x1, "gpio_out"),
1862 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
1863 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
1864 SUNXI_FUNCTION(0x0, "gpio_in"),
1865 SUNXI_FUNCTION(0x1, "gpio_out"),
1866 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
1867 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
1868 SUNXI_FUNCTION(0x0, "gpio_in"),
1869 SUNXI_FUNCTION(0x1, "gpio_out"),
1870 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
1871 /* Hole */
1872 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
1873 SUNXI_FUNCTION(0x0, "gpio_in"),
1874 SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */
1875 SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */
1876 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
1877 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
1878 SUNXI_FUNCTION(0x0, "gpio_in"),
1879 SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */
1880 SUNXI_FUNCTION(0x4, "spi2"), /* CLK */
1881 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
1882 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
1883 SUNXI_FUNCTION(0x0, "gpio_in"),
1884 SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */
1885 SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */
1886 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
1887 SUNXI_FUNCTION(0x0, "gpio_in"),
1888 SUNXI_FUNCTION(0x1, "gpio_out"),
1889 SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */
1890 SUNXI_FUNCTION(0x4, "spi2")), /* MISO */
1891 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
1892 SUNXI_FUNCTION(0x0, "gpio_in"),
1893 SUNXI_FUNCTION(0x1, "gpio_out"),
1894 SUNXI_FUNCTION(0x3, "csi0"), /* D0 */
1895 SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */
1896 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
1897 SUNXI_FUNCTION(0x0, "gpio_in"),
1898 SUNXI_FUNCTION(0x1, "gpio_out"),
1899 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
1900 SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */
1901 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
1902 SUNXI_FUNCTION(0x0, "gpio_in"),
1903 SUNXI_FUNCTION(0x1, "gpio_out"),
1904 SUNXI_FUNCTION(0x3, "csi0"), /* D2 */
1905 SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */
1906 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
1907 SUNXI_FUNCTION(0x0, "gpio_in"),
1908 SUNXI_FUNCTION(0x1, "gpio_out"),
1909 SUNXI_FUNCTION(0x3, "csi0"), /* D3 */
1910 SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */
1911 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
1912 SUNXI_FUNCTION(0x0, "gpio_in"),
1913 SUNXI_FUNCTION(0x1, "gpio_out"),
1914 SUNXI_FUNCTION(0x3, "csi0"), /* D4 */
1915 SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */
1916 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
1917 SUNXI_FUNCTION(0x0, "gpio_in"),
1918 SUNXI_FUNCTION(0x1, "gpio_out"),
1919 SUNXI_FUNCTION(0x3, "csi0"), /* D5 */
1920 SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */
1921 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
1922 SUNXI_FUNCTION(0x0, "gpio_in"),
1923 SUNXI_FUNCTION(0x1, "gpio_out"),
1924 SUNXI_FUNCTION(0x3, "csi0"), /* D6 */
1925 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
1926 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
1927 SUNXI_FUNCTION(0x0, "gpio_in"),
1928 SUNXI_FUNCTION(0x1, "gpio_out"),
1929 SUNXI_FUNCTION(0x3, "csi0"), /* D7 */
1930 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
1931 /* Hole */
1932 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
1933 SUNXI_FUNCTION(0x0, "gpio_in"),
1934 SUNXI_FUNCTION(0x1, "gpio_out"),
1935 SUNXI_FUNCTION(0x2, "mmc0")), /* D1 */
1936 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
1937 SUNXI_FUNCTION(0x0, "gpio_in"),
1938 SUNXI_FUNCTION(0x1, "gpio_out"),
1939 SUNXI_FUNCTION(0x2, "mmc0")), /* D0 */
1940 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
1941 SUNXI_FUNCTION(0x0, "gpio_in"),
1942 SUNXI_FUNCTION(0x1, "gpio_out"),
1943 SUNXI_FUNCTION(0x2, "mmc0")), /* CLK */
1944 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
1945 SUNXI_FUNCTION(0x0, "gpio_in"),
1946 SUNXI_FUNCTION(0x1, "gpio_out"),
1947 SUNXI_FUNCTION(0x2, "mmc0")), /* CMD */
1948 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
1949 SUNXI_FUNCTION(0x0, "gpio_in"),
1950 SUNXI_FUNCTION(0x1, "gpio_out"),
1951 SUNXI_FUNCTION(0x2, "mmc0")), /* D3 */
1952 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
1953 SUNXI_FUNCTION(0x0, "gpio_in"),
1954 SUNXI_FUNCTION(0x1, "gpio_out"),
1955 SUNXI_FUNCTION(0x2, "mmc0")), /* D2 */
1956 /* Hole */
1957 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
1958 SUNXI_FUNCTION(0x0, "gpio_in"),
1959 SUNXI_FUNCTION(0x1, "gpio_out"),
1960 SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */
1961 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
1962 SUNXI_FUNCTION(0x0, "gpio_in"),
1963 SUNXI_FUNCTION(0x1, "gpio_out"),
1964 SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */
1965 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
1966 SUNXI_FUNCTION(0x0, "gpio_in"),
1967 SUNXI_FUNCTION(0x1, "gpio_out"),
1968 SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */
1969 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
1970 SUNXI_FUNCTION(0x0, "gpio_in"),
1971 SUNXI_FUNCTION(0x1, "gpio_out"),
1972 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
1973 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
1974 SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */
1975 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
1976 SUNXI_FUNCTION(0x0, "gpio_in"),
1977 SUNXI_FUNCTION(0x1, "gpio_out"),
1978 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
1979 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
1980 SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */
1981 /* Hole */
1982 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
1983 SUNXI_FUNCTION(0x0, "gpio_in"),
1984 SUNXI_FUNCTION(0x1, "gpio_out"),
1985 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
1986 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
1987 SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */
1988 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
1989 SUNXI_FUNCTION(0x0, "gpio_in"),
1990 SUNXI_FUNCTION(0x1, "gpio_out"),
1991 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
1992 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
1993 SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */
1994 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
1995 SUNXI_FUNCTION(0x0, "gpio_in"),
1996 SUNXI_FUNCTION(0x1, "gpio_out"),
1997 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
1998 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
1999 SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */
2000 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12,
2001 SUNXI_FUNCTION(0x0, "gpio_in"),
2002 SUNXI_FUNCTION(0x1, "gpio_out"),
2003 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
2004 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
2005 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
2006};
2007
2008static const struct sunxi_desc_pin sun6i_a31_pins[] = {
2009 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
2010 SUNXI_FUNCTION(0x0, "gpio_in"),
2011 SUNXI_FUNCTION(0x1, "gpio_out"),
2012 SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */
2013 SUNXI_FUNCTION(0x3, "lcd1"), /* D0 */
2014 SUNXI_FUNCTION(0x4, "uart1")), /* DTR */
2015 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
2016 SUNXI_FUNCTION(0x0, "gpio_in"),
2017 SUNXI_FUNCTION(0x1, "gpio_out"),
2018 SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */
2019 SUNXI_FUNCTION(0x3, "lcd1"), /* D1 */
2020 SUNXI_FUNCTION(0x4, "uart1")), /* DSR */
2021 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
2022 SUNXI_FUNCTION(0x0, "gpio_in"),
2023 SUNXI_FUNCTION(0x1, "gpio_out"),
2024 SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
2025 SUNXI_FUNCTION(0x3, "lcd1"), /* D2 */
2026 SUNXI_FUNCTION(0x4, "uart1")), /* DCD */
2027 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
2028 SUNXI_FUNCTION(0x0, "gpio_in"),
2029 SUNXI_FUNCTION(0x1, "gpio_out"),
2030 SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
2031 SUNXI_FUNCTION(0x3, "lcd1"), /* D3 */
2032 SUNXI_FUNCTION(0x4, "uart1")), /* RING */
2033 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
2034 SUNXI_FUNCTION(0x0, "gpio_in"),
2035 SUNXI_FUNCTION(0x1, "gpio_out"),
2036 SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */
2037 SUNXI_FUNCTION(0x3, "lcd1"), /* D4 */
2038 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
2039 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
2040 SUNXI_FUNCTION(0x0, "gpio_in"),
2041 SUNXI_FUNCTION(0x1, "gpio_out"),
2042 SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */
2043 SUNXI_FUNCTION(0x3, "lcd1"), /* D5 */
2044 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
2045 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
2046 SUNXI_FUNCTION(0x0, "gpio_in"),
2047 SUNXI_FUNCTION(0x1, "gpio_out"),
2048 SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */
2049 SUNXI_FUNCTION(0x3, "lcd1"), /* D6 */
2050 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */
2051 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
2052 SUNXI_FUNCTION(0x0, "gpio_in"),
2053 SUNXI_FUNCTION(0x1, "gpio_out"),
2054 SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */
2055 SUNXI_FUNCTION(0x3, "lcd1"), /* D7 */
2056 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */
2057 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
2058 SUNXI_FUNCTION(0x0, "gpio_in"),
2059 SUNXI_FUNCTION(0x1, "gpio_out"),
2060 SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */
2061 SUNXI_FUNCTION(0x3, "lcd1")), /* D8 */
2062 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
2063 SUNXI_FUNCTION(0x0, "gpio_in"),
2064 SUNXI_FUNCTION(0x1, "gpio_out"),
2065 SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
2066 SUNXI_FUNCTION(0x3, "lcd1"), /* D9 */
2067 SUNXI_FUNCTION(0x4, "mmc3"), /* CMD */
2068 SUNXI_FUNCTION(0x5, "mmc2")), /* CMD */
2069 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
2070 SUNXI_FUNCTION(0x0, "gpio_in"),
2071 SUNXI_FUNCTION(0x1, "gpio_out"),
2072 SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */
2073 SUNXI_FUNCTION(0x3, "lcd1"), /* D10 */
2074 SUNXI_FUNCTION(0x4, "mmc3"), /* CLK */
2075 SUNXI_FUNCTION(0x5, "mmc2")), /* CLK */
2076 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
2077 SUNXI_FUNCTION(0x0, "gpio_in"),
2078 SUNXI_FUNCTION(0x1, "gpio_out"),
2079 SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */
2080 SUNXI_FUNCTION(0x3, "lcd1"), /* D11 */
2081 SUNXI_FUNCTION(0x4, "mmc3"), /* D0 */
2082 SUNXI_FUNCTION(0x5, "mmc2")), /* D0 */
2083 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
2084 SUNXI_FUNCTION(0x0, "gpio_in"),
2085 SUNXI_FUNCTION(0x1, "gpio_out"),
2086 SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */
2087 SUNXI_FUNCTION(0x3, "lcd1"), /* D12 */
2088 SUNXI_FUNCTION(0x4, "mmc3"), /* D1 */
2089 SUNXI_FUNCTION(0x5, "mmc2")), /* D1 */
2090 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
2091 SUNXI_FUNCTION(0x0, "gpio_in"),
2092 SUNXI_FUNCTION(0x1, "gpio_out"),
2093 SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */
2094 SUNXI_FUNCTION(0x3, "lcd1"), /* D13 */
2095 SUNXI_FUNCTION(0x4, "mmc3"), /* D2 */
2096 SUNXI_FUNCTION(0x5, "mmc2")), /* D2 */
2097 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
2098 SUNXI_FUNCTION(0x0, "gpio_in"),
2099 SUNXI_FUNCTION(0x1, "gpio_out"),
2100 SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */
2101 SUNXI_FUNCTION(0x3, "lcd1"), /* D14 */
2102 SUNXI_FUNCTION(0x4, "mmc3"), /* D3 */
2103 SUNXI_FUNCTION(0x5, "mmc2")), /* D3 */
2104 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
2105 SUNXI_FUNCTION(0x0, "gpio_in"),
2106 SUNXI_FUNCTION(0x1, "gpio_out"),
2107 SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
2108 SUNXI_FUNCTION(0x3, "lcd1")), /* D15 */
2109 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
2110 SUNXI_FUNCTION(0x0, "gpio_in"),
2111 SUNXI_FUNCTION(0x1, "gpio_out"),
2112 SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
2113 SUNXI_FUNCTION(0x3, "lcd1")), /* D16 */
2114 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
2115 SUNXI_FUNCTION(0x0, "gpio_in"),
2116 SUNXI_FUNCTION(0x1, "gpio_out"),
2117 SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
2118 SUNXI_FUNCTION(0x3, "lcd1")), /* D17 */
2119 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA18,
2120 SUNXI_FUNCTION(0x0, "gpio_in"),
2121 SUNXI_FUNCTION(0x1, "gpio_out"),
2122 SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
2123 SUNXI_FUNCTION(0x3, "lcd1")), /* D18 */
2124 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA19,
2125 SUNXI_FUNCTION(0x0, "gpio_in"),
2126 SUNXI_FUNCTION(0x1, "gpio_out"),
2127 SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */
2128 SUNXI_FUNCTION(0x3, "lcd1"), /* D19 */
2129 SUNXI_FUNCTION(0x4, "pwm3")), /* Positive */
2130 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA20,
2131 SUNXI_FUNCTION(0x0, "gpio_in"),
2132 SUNXI_FUNCTION(0x1, "gpio_out"),
2133 SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */
2134 SUNXI_FUNCTION(0x3, "lcd1"), /* D20 */
2135 SUNXI_FUNCTION(0x4, "pwm3")), /* Negative */
2136 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA21,
2137 SUNXI_FUNCTION(0x0, "gpio_in"),
2138 SUNXI_FUNCTION(0x1, "gpio_out"),
2139 SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */
2140 SUNXI_FUNCTION(0x3, "lcd1"), /* D21 */
2141 SUNXI_FUNCTION(0x4, "spi3")), /* CS0 */
2142 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA22,
2143 SUNXI_FUNCTION(0x0, "gpio_in"),
2144 SUNXI_FUNCTION(0x1, "gpio_out"),
2145 SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */
2146 SUNXI_FUNCTION(0x3, "lcd1"), /* D22 */
2147 SUNXI_FUNCTION(0x4, "spi3")), /* CLK */
2148 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA23,
2149 SUNXI_FUNCTION(0x0, "gpio_in"),
2150 SUNXI_FUNCTION(0x1, "gpio_out"),
2151 SUNXI_FUNCTION(0x2, "gmac"), /* COL */
2152 SUNXI_FUNCTION(0x3, "lcd1"), /* D23 */
2153 SUNXI_FUNCTION(0x4, "spi3")), /* MOSI */
2154 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA24,
2155 SUNXI_FUNCTION(0x0, "gpio_in"),
2156 SUNXI_FUNCTION(0x1, "gpio_out"),
2157 SUNXI_FUNCTION(0x2, "gmac"), /* CRS */
2158 SUNXI_FUNCTION(0x3, "lcd1"), /* CLK */
2159 SUNXI_FUNCTION(0x4, "spi3")), /* MISO */
2160 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA25,
2161 SUNXI_FUNCTION(0x0, "gpio_in"),
2162 SUNXI_FUNCTION(0x1, "gpio_out"),
2163 SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */
2164 SUNXI_FUNCTION(0x3, "lcd1"), /* DE */
2165 SUNXI_FUNCTION(0x4, "spi3")), /* CS1 */
2166 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA26,
2167 SUNXI_FUNCTION(0x0, "gpio_in"),
2168 SUNXI_FUNCTION(0x1, "gpio_out"),
2169 SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
2170 SUNXI_FUNCTION(0x3, "lcd1")), /* HSYNC */
2171 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA27,
2172 SUNXI_FUNCTION(0x0, "gpio_in"),
2173 SUNXI_FUNCTION(0x1, "gpio_out"),
2174 SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */
2175 SUNXI_FUNCTION(0x3, "lcd1")), /* VSYNC */
2176 /* Hole */
2177 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
2178 SUNXI_FUNCTION(0x0, "gpio_in"),
2179 SUNXI_FUNCTION(0x1, "gpio_out"),
2180 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
2181 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
2182 SUNXI_FUNCTION(0x4, "csi")), /* MCLK1 */
2183 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
2184 SUNXI_FUNCTION(0x0, "gpio_in"),
2185 SUNXI_FUNCTION(0x1, "gpio_out"),
2186 SUNXI_FUNCTION(0x2, "i2s0")), /* BCLK */
2187 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
2188 SUNXI_FUNCTION(0x0, "gpio_in"),
2189 SUNXI_FUNCTION(0x1, "gpio_out"),
2190 SUNXI_FUNCTION(0x2, "i2s0")), /* LRCK */
2191 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
2192 SUNXI_FUNCTION(0x0, "gpio_in"),
2193 SUNXI_FUNCTION(0x1, "gpio_out"),
2194 SUNXI_FUNCTION(0x2, "i2s0")), /* DO0 */
2195 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
2196 SUNXI_FUNCTION(0x0, "gpio_in"),
2197 SUNXI_FUNCTION(0x1, "gpio_out"),
2198 SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
2199 SUNXI_FUNCTION(0x3, "uart3")), /* RTS */
2200 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
2201 SUNXI_FUNCTION(0x0, "gpio_in"),
2202 SUNXI_FUNCTION(0x1, "gpio_out"),
2203 SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
2204 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
2205 SUNXI_FUNCTION(0x4, "i2c3")), /* SCK */
2206 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
2207 SUNXI_FUNCTION(0x0, "gpio_in"),
2208 SUNXI_FUNCTION(0x1, "gpio_out"),
2209 SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
2210 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
2211 SUNXI_FUNCTION(0x4, "i2c3")), /* SDA */
2212 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
2213 SUNXI_FUNCTION(0x0, "gpio_in"),
2214 SUNXI_FUNCTION(0x1, "gpio_out"),
2215 SUNXI_FUNCTION(0x3, "i2s0")), /* DI */
2216 /* Hole */
2217 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
2218 SUNXI_FUNCTION(0x0, "gpio_in"),
2219 SUNXI_FUNCTION(0x1, "gpio_out"),
2220 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
2221 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
2222 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
2223 SUNXI_FUNCTION(0x0, "gpio_in"),
2224 SUNXI_FUNCTION(0x1, "gpio_out"),
2225 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
2226 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
2227 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
2228 SUNXI_FUNCTION(0x0, "gpio_in"),
2229 SUNXI_FUNCTION(0x1, "gpio_out"),
2230 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
2231 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
2232 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
2233 SUNXI_FUNCTION(0x0, "gpio_in"),
2234 SUNXI_FUNCTION(0x1, "gpio_out"),
2235 SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */
2236 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
2237 SUNXI_FUNCTION(0x0, "gpio_in"),
2238 SUNXI_FUNCTION(0x1, "gpio_out"),
2239 SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
2240 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
2241 SUNXI_FUNCTION(0x0, "gpio_in"),
2242 SUNXI_FUNCTION(0x1, "gpio_out"),
2243 SUNXI_FUNCTION(0x2, "nand0")), /* RE */
2244 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
2245 SUNXI_FUNCTION(0x0, "gpio_in"),
2246 SUNXI_FUNCTION(0x1, "gpio_out"),
2247 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
2248 SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */
2249 SUNXI_FUNCTION(0x4, "mmc3")), /* CMD */
2250 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
2251 SUNXI_FUNCTION(0x0, "gpio_in"),
2252 SUNXI_FUNCTION(0x1, "gpio_out"),
2253 SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
2254 SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */
2255 SUNXI_FUNCTION(0x4, "mmc3")), /* CLK */
2256 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
2257 SUNXI_FUNCTION(0x0, "gpio_in"),
2258 SUNXI_FUNCTION(0x1, "gpio_out"),
2259 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
2260 SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
2261 SUNXI_FUNCTION(0x4, "mmc3")), /* D0 */
2262 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
2263 SUNXI_FUNCTION(0x0, "gpio_in"),
2264 SUNXI_FUNCTION(0x1, "gpio_out"),
2265 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
2266 SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
2267 SUNXI_FUNCTION(0x4, "mmc3")), /* D1 */
2268 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
2269 SUNXI_FUNCTION(0x0, "gpio_in"),
2270 SUNXI_FUNCTION(0x1, "gpio_out"),
2271 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
2272 SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */
2273 SUNXI_FUNCTION(0x4, "mmc3")), /* D2 */
2274 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
2275 SUNXI_FUNCTION(0x0, "gpio_in"),
2276 SUNXI_FUNCTION(0x1, "gpio_out"),
2277 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
2278 SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */
2279 SUNXI_FUNCTION(0x4, "mmc3")), /* D3 */
2280 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
2281 SUNXI_FUNCTION(0x0, "gpio_in"),
2282 SUNXI_FUNCTION(0x1, "gpio_out"),
2283 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
2284 SUNXI_FUNCTION(0x3, "mmc2"), /* D4 */
2285 SUNXI_FUNCTION(0x4, "mmc3")), /* D4 */
2286 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
2287 SUNXI_FUNCTION(0x0, "gpio_in"),
2288 SUNXI_FUNCTION(0x1, "gpio_out"),
2289 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
2290 SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */
2291 SUNXI_FUNCTION(0x4, "mmc3")), /* D5 */
2292 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
2293 SUNXI_FUNCTION(0x0, "gpio_in"),
2294 SUNXI_FUNCTION(0x1, "gpio_out"),
2295 SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
2296 SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */
2297 SUNXI_FUNCTION(0x4, "mmc3")), /* D6 */
2298 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
2299 SUNXI_FUNCTION(0x0, "gpio_in"),
2300 SUNXI_FUNCTION(0x1, "gpio_out"),
2301 SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
2302 SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */
2303 SUNXI_FUNCTION(0x4, "mmc3")), /* D7 */
2304 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
2305 SUNXI_FUNCTION(0x0, "gpio_in"),
2306 SUNXI_FUNCTION(0x1, "gpio_out"),
2307 SUNXI_FUNCTION(0x2, "nand0"), /* DQ8 */
2308 SUNXI_FUNCTION(0x3, "nand1")), /* DQ0 */
2309 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
2310 SUNXI_FUNCTION(0x0, "gpio_in"),
2311 SUNXI_FUNCTION(0x1, "gpio_out"),
2312 SUNXI_FUNCTION(0x2, "nand0"), /* DQ9 */
2313 SUNXI_FUNCTION(0x3, "nand1")), /* DQ1 */
2314 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
2315 SUNXI_FUNCTION(0x0, "gpio_in"),
2316 SUNXI_FUNCTION(0x1, "gpio_out"),
2317 SUNXI_FUNCTION(0x2, "nand0"), /* DQ10 */
2318 SUNXI_FUNCTION(0x3, "nand1")), /* DQ2 */
2319 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
2320 SUNXI_FUNCTION(0x0, "gpio_in"),
2321 SUNXI_FUNCTION(0x1, "gpio_out"),
2322 SUNXI_FUNCTION(0x2, "nand0"), /* DQ11 */
2323 SUNXI_FUNCTION(0x3, "nand1")), /* DQ3 */
2324 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20,
2325 SUNXI_FUNCTION(0x0, "gpio_in"),
2326 SUNXI_FUNCTION(0x1, "gpio_out"),
2327 SUNXI_FUNCTION(0x2, "nand0"), /* DQ12 */
2328 SUNXI_FUNCTION(0x3, "nand1")), /* DQ4 */
2329 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21,
2330 SUNXI_FUNCTION(0x0, "gpio_in"),
2331 SUNXI_FUNCTION(0x1, "gpio_out"),
2332 SUNXI_FUNCTION(0x2, "nand0"), /* DQ13 */
2333 SUNXI_FUNCTION(0x3, "nand1")), /* DQ5 */
2334 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22,
2335 SUNXI_FUNCTION(0x0, "gpio_in"),
2336 SUNXI_FUNCTION(0x1, "gpio_out"),
2337 SUNXI_FUNCTION(0x2, "nand0"), /* DQ14 */
2338 SUNXI_FUNCTION(0x3, "nand1")), /* DQ6 */
2339 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23,
2340 SUNXI_FUNCTION(0x0, "gpio_in"),
2341 SUNXI_FUNCTION(0x1, "gpio_out"),
2342 SUNXI_FUNCTION(0x2, "nand0"), /* DQ15 */
2343 SUNXI_FUNCTION(0x3, "nand1")), /* DQ7 */
2344 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24,
2345 SUNXI_FUNCTION(0x0, "gpio_in"),
2346 SUNXI_FUNCTION(0x1, "gpio_out"),
2347 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
2348 SUNXI_FUNCTION(0x3, "mmc2"), /* RST */
2349 SUNXI_FUNCTION(0x4, "mmc3")), /* RST */
2350 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC25,
2351 SUNXI_FUNCTION(0x0, "gpio_in"),
2352 SUNXI_FUNCTION(0x1, "gpio_out"),
2353 SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */
2354 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC26,
2355 SUNXI_FUNCTION(0x0, "gpio_in"),
2356 SUNXI_FUNCTION(0x1, "gpio_out"),
2357 SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */
2358 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC27,
2359 SUNXI_FUNCTION(0x0, "gpio_in"),
2360 SUNXI_FUNCTION(0x1, "gpio_out"),
2361 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
2362 /* Hole */
2363 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
2364 SUNXI_FUNCTION(0x0, "gpio_in"),
2365 SUNXI_FUNCTION(0x1, "gpio_out"),
2366 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
2367 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
2368 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
2369 SUNXI_FUNCTION(0x0, "gpio_in"),
2370 SUNXI_FUNCTION(0x1, "gpio_out"),
2371 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
2372 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
2373 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
2374 SUNXI_FUNCTION(0x0, "gpio_in"),
2375 SUNXI_FUNCTION(0x1, "gpio_out"),
2376 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
2377 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
2378 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
2379 SUNXI_FUNCTION(0x0, "gpio_in"),
2380 SUNXI_FUNCTION(0x1, "gpio_out"),
2381 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
2382 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
2383 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
2384 SUNXI_FUNCTION(0x0, "gpio_in"),
2385 SUNXI_FUNCTION(0x1, "gpio_out"),
2386 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
2387 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
2388 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
2389 SUNXI_FUNCTION(0x0, "gpio_in"),
2390 SUNXI_FUNCTION(0x1, "gpio_out"),
2391 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
2392 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
2393 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
2394 SUNXI_FUNCTION(0x0, "gpio_in"),
2395 SUNXI_FUNCTION(0x1, "gpio_out"),
2396 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
2397 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
2398 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
2399 SUNXI_FUNCTION(0x0, "gpio_in"),
2400 SUNXI_FUNCTION(0x1, "gpio_out"),
2401 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
2402 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
2403 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
2404 SUNXI_FUNCTION(0x0, "gpio_in"),
2405 SUNXI_FUNCTION(0x1, "gpio_out"),
2406 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
2407 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
2408 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
2409 SUNXI_FUNCTION(0x0, "gpio_in"),
2410 SUNXI_FUNCTION(0x1, "gpio_out"),
2411 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
2412 SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
2413 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
2414 SUNXI_FUNCTION(0x0, "gpio_in"),
2415 SUNXI_FUNCTION(0x1, "gpio_out"),
2416 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
2417 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
2418 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
2419 SUNXI_FUNCTION(0x0, "gpio_in"),
2420 SUNXI_FUNCTION(0x1, "gpio_out"),
2421 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
2422 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
2423 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
2424 SUNXI_FUNCTION(0x0, "gpio_in"),
2425 SUNXI_FUNCTION(0x1, "gpio_out"),
2426 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
2427 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
2428 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
2429 SUNXI_FUNCTION(0x0, "gpio_in"),
2430 SUNXI_FUNCTION(0x1, "gpio_out"),
2431 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
2432 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
2433 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
2434 SUNXI_FUNCTION(0x0, "gpio_in"),
2435 SUNXI_FUNCTION(0x1, "gpio_out"),
2436 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
2437 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
2438 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
2439 SUNXI_FUNCTION(0x0, "gpio_in"),
2440 SUNXI_FUNCTION(0x1, "gpio_out"),
2441 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
2442 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
2443 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
2444 SUNXI_FUNCTION(0x0, "gpio_in"),
2445 SUNXI_FUNCTION(0x1, "gpio_out"),
2446 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
2447 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
2448 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
2449 SUNXI_FUNCTION(0x0, "gpio_in"),
2450 SUNXI_FUNCTION(0x1, "gpio_out"),
2451 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
2452 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
2453 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
2454 SUNXI_FUNCTION(0x0, "gpio_in"),
2455 SUNXI_FUNCTION(0x1, "gpio_out"),
2456 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
2457 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
2458 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
2459 SUNXI_FUNCTION(0x0, "gpio_in"),
2460 SUNXI_FUNCTION(0x1, "gpio_out"),
2461 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
2462 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
2463 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
2464 SUNXI_FUNCTION(0x0, "gpio_in"),
2465 SUNXI_FUNCTION(0x1, "gpio_out"),
2466 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
2467 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
2468 SUNXI_FUNCTION(0x0, "gpio_in"),
2469 SUNXI_FUNCTION(0x1, "gpio_out"),
2470 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
2471 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
2472 SUNXI_FUNCTION(0x0, "gpio_in"),
2473 SUNXI_FUNCTION(0x1, "gpio_out"),
2474 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
2475 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
2476 SUNXI_FUNCTION(0x0, "gpio_in"),
2477 SUNXI_FUNCTION(0x1, "gpio_out"),
2478 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
2479 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
2480 SUNXI_FUNCTION(0x0, "gpio_in"),
2481 SUNXI_FUNCTION(0x1, "gpio_out"),
2482 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
2483 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
2484 SUNXI_FUNCTION(0x0, "gpio_in"),
2485 SUNXI_FUNCTION(0x1, "gpio_out"),
2486 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
2487 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
2488 SUNXI_FUNCTION(0x0, "gpio_in"),
2489 SUNXI_FUNCTION(0x1, "gpio_out"),
2490 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
2491 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
2492 SUNXI_FUNCTION(0x0, "gpio_in"),
2493 SUNXI_FUNCTION(0x1, "gpio_out"),
2494 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
2495 /* Hole */
2496 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
2497 SUNXI_FUNCTION(0x0, "gpio_in"),
2498 SUNXI_FUNCTION(0x1, "gpio_out"),
2499 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
2500 SUNXI_FUNCTION(0x3, "ts")), /* CLK */
2501 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
2502 SUNXI_FUNCTION(0x0, "gpio_in"),
2503 SUNXI_FUNCTION(0x1, "gpio_out"),
2504 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
2505 SUNXI_FUNCTION(0x3, "ts")), /* ERR */
2506 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
2507 SUNXI_FUNCTION(0x0, "gpio_in"),
2508 SUNXI_FUNCTION(0x1, "gpio_out"),
2509 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
2510 SUNXI_FUNCTION(0x3, "ts")), /* SYNC */
2511 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
2512 SUNXI_FUNCTION(0x0, "gpio_in"),
2513 SUNXI_FUNCTION(0x1, "gpio_out"),
2514 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
2515 SUNXI_FUNCTION(0x3, "ts")), /* DVLD */
2516 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
2517 SUNXI_FUNCTION(0x0, "gpio_in"),
2518 SUNXI_FUNCTION(0x1, "gpio_out"),
2519 SUNXI_FUNCTION(0x2, "csi"), /* D0 */
2520 SUNXI_FUNCTION(0x3, "uart5")), /* TX */
2521 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
2522 SUNXI_FUNCTION(0x0, "gpio_in"),
2523 SUNXI_FUNCTION(0x1, "gpio_out"),
2524 SUNXI_FUNCTION(0x2, "csi"), /* D1 */
2525 SUNXI_FUNCTION(0x3, "uart5")), /* RX */
2526 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
2527 SUNXI_FUNCTION(0x0, "gpio_in"),
2528 SUNXI_FUNCTION(0x1, "gpio_out"),
2529 SUNXI_FUNCTION(0x2, "csi"), /* D2 */
2530 SUNXI_FUNCTION(0x3, "uart5")), /* RTS */
2531 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
2532 SUNXI_FUNCTION(0x0, "gpio_in"),
2533 SUNXI_FUNCTION(0x1, "gpio_out"),
2534 SUNXI_FUNCTION(0x2, "csi"), /* D3 */
2535 SUNXI_FUNCTION(0x3, "uart5")), /* CTS */
2536 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
2537 SUNXI_FUNCTION(0x0, "gpio_in"),
2538 SUNXI_FUNCTION(0x1, "gpio_out"),
2539 SUNXI_FUNCTION(0x2, "csi"), /* D4 */
2540 SUNXI_FUNCTION(0x3, "ts")), /* D0 */
2541 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
2542 SUNXI_FUNCTION(0x0, "gpio_in"),
2543 SUNXI_FUNCTION(0x1, "gpio_out"),
2544 SUNXI_FUNCTION(0x2, "csi"), /* D5 */
2545 SUNXI_FUNCTION(0x3, "ts")), /* D1 */
2546 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
2547 SUNXI_FUNCTION(0x0, "gpio_in"),
2548 SUNXI_FUNCTION(0x1, "gpio_out"),
2549 SUNXI_FUNCTION(0x2, "csi"), /* D6 */
2550 SUNXI_FUNCTION(0x3, "ts")), /* D2 */
2551 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
2552 SUNXI_FUNCTION(0x0, "gpio_in"),
2553 SUNXI_FUNCTION(0x1, "gpio_out"),
2554 SUNXI_FUNCTION(0x2, "csi"), /* D7 */
2555 SUNXI_FUNCTION(0x3, "ts")), /* D3 */
2556 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE12,
2557 SUNXI_FUNCTION(0x0, "gpio_in"),
2558 SUNXI_FUNCTION(0x1, "gpio_out"),
2559 SUNXI_FUNCTION(0x2, "csi"), /* D8 */
2560 SUNXI_FUNCTION(0x3, "ts")), /* D4 */
2561 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE13,
2562 SUNXI_FUNCTION(0x0, "gpio_in"),
2563 SUNXI_FUNCTION(0x1, "gpio_out"),
2564 SUNXI_FUNCTION(0x2, "csi"), /* D9 */
2565 SUNXI_FUNCTION(0x3, "ts")), /* D5 */
2566 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE14,
2567 SUNXI_FUNCTION(0x0, "gpio_in"),
2568 SUNXI_FUNCTION(0x1, "gpio_out"),
2569 SUNXI_FUNCTION(0x2, "csi"), /* D10 */
2570 SUNXI_FUNCTION(0x3, "ts")), /* D6 */
2571 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE15,
2572 SUNXI_FUNCTION(0x0, "gpio_in"),
2573 SUNXI_FUNCTION(0x1, "gpio_out"),
2574 SUNXI_FUNCTION(0x2, "csi"), /* D11 */
2575 SUNXI_FUNCTION(0x3, "ts")), /* D7 */
2576 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE16,
2577 SUNXI_FUNCTION(0x0, "gpio_in"),
2578 SUNXI_FUNCTION(0x1, "gpio_out"),
2579 SUNXI_FUNCTION(0x2, "csi")), /* MIPI CSI MCLK */
2580 /* Hole */
2581 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
2582 SUNXI_FUNCTION(0x0, "gpio_in"),
2583 SUNXI_FUNCTION(0x1, "gpio_out"),
2584 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
2585 SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
2586 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
2587 SUNXI_FUNCTION(0x0, "gpio_in"),
2588 SUNXI_FUNCTION(0x1, "gpio_out"),
2589 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
2590 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
2591 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
2592 SUNXI_FUNCTION(0x0, "gpio_in"),
2593 SUNXI_FUNCTION(0x1, "gpio_out"),
2594 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
2595 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
2596 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
2597 SUNXI_FUNCTION(0x0, "gpio_in"),
2598 SUNXI_FUNCTION(0x1, "gpio_out"),
2599 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
2600 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
2601 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
2602 SUNXI_FUNCTION(0x0, "gpio_in"),
2603 SUNXI_FUNCTION(0x1, "gpio_out"),
2604 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
2605 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
2606 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
2607 SUNXI_FUNCTION(0x0, "gpio_in"),
2608 SUNXI_FUNCTION(0x1, "gpio_out"),
2609 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
2610 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
2611 /* Hole */
2612 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
2613 SUNXI_FUNCTION(0x0, "gpio_in"),
2614 SUNXI_FUNCTION(0x1, "gpio_out"),
2615 SUNXI_FUNCTION(0x2, "mmc1")), /* CLK */
2616 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
2617 SUNXI_FUNCTION(0x0, "gpio_in"),
2618 SUNXI_FUNCTION(0x1, "gpio_out"),
2619 SUNXI_FUNCTION(0x2, "mmc1")), /* CMD */
2620 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
2621 SUNXI_FUNCTION(0x0, "gpio_in"),
2622 SUNXI_FUNCTION(0x1, "gpio_out"),
2623 SUNXI_FUNCTION(0x2, "mmc1")), /* D0 */
2624 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
2625 SUNXI_FUNCTION(0x0, "gpio_in"),
2626 SUNXI_FUNCTION(0x1, "gpio_out"),
2627 SUNXI_FUNCTION(0x2, "mmc1")), /* D1 */
2628 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
2629 SUNXI_FUNCTION(0x0, "gpio_in"),
2630 SUNXI_FUNCTION(0x1, "gpio_out"),
2631 SUNXI_FUNCTION(0x2, "mmc1")), /* D2 */
2632 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
2633 SUNXI_FUNCTION(0x0, "gpio_in"),
2634 SUNXI_FUNCTION(0x1, "gpio_out"),
2635 SUNXI_FUNCTION(0x2, "mmc1")), /* D3 */
2636 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
2637 SUNXI_FUNCTION(0x0, "gpio_in"),
2638 SUNXI_FUNCTION(0x1, "gpio_out"),
2639 SUNXI_FUNCTION(0x2, "uart2")), /* TX */
2640 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
2641 SUNXI_FUNCTION(0x0, "gpio_in"),
2642 SUNXI_FUNCTION(0x1, "gpio_out"),
2643 SUNXI_FUNCTION(0x2, "uart2")), /* RX */
2644 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
2645 SUNXI_FUNCTION(0x0, "gpio_in"),
2646 SUNXI_FUNCTION(0x1, "gpio_out"),
2647 SUNXI_FUNCTION(0x2, "uart2")), /* RTS */
2648 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
2649 SUNXI_FUNCTION(0x0, "gpio_in"),
2650 SUNXI_FUNCTION(0x1, "gpio_out"),
2651 SUNXI_FUNCTION(0x2, "uart2")), /* CTS */
2652 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
2653 SUNXI_FUNCTION(0x0, "gpio_in"),
2654 SUNXI_FUNCTION(0x1, "gpio_out"),
2655 SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
2656 SUNXI_FUNCTION(0x3, "usb")), /* DP3 */
2657 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
2658 SUNXI_FUNCTION(0x0, "gpio_in"),
2659 SUNXI_FUNCTION(0x1, "gpio_out"),
2660 SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
2661 SUNXI_FUNCTION(0x3, "usb")), /* DM3 */
2662 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12,
2663 SUNXI_FUNCTION(0x0, "gpio_in"),
2664 SUNXI_FUNCTION(0x1, "gpio_out"),
2665 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
2666 SUNXI_FUNCTION(0x3, "i2s1")), /* MCLK */
2667 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG13,
2668 SUNXI_FUNCTION(0x0, "gpio_in"),
2669 SUNXI_FUNCTION(0x1, "gpio_out"),
2670 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
2671 SUNXI_FUNCTION(0x3, "i2s1")), /* BCLK */
2672 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG14,
2673 SUNXI_FUNCTION(0x0, "gpio_in"),
2674 SUNXI_FUNCTION(0x1, "gpio_out"),
2675 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
2676 SUNXI_FUNCTION(0x3, "i2s1")), /* LRCK */
2677 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG15,
2678 SUNXI_FUNCTION(0x0, "gpio_in"),
2679 SUNXI_FUNCTION(0x1, "gpio_out"),
2680 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
2681 SUNXI_FUNCTION(0x3, "i2s1")), /* DIN */
2682 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG16,
2683 SUNXI_FUNCTION(0x0, "gpio_in"),
2684 SUNXI_FUNCTION(0x1, "gpio_out"),
2685 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
2686 SUNXI_FUNCTION(0x3, "i2s1")), /* DOUT */
2687 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG17,
2688 SUNXI_FUNCTION(0x0, "gpio_in"),
2689 SUNXI_FUNCTION(0x1, "gpio_out"),
2690 SUNXI_FUNCTION(0x2, "uart4")), /* TX */
2691 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG18,
2692 SUNXI_FUNCTION(0x0, "gpio_in"),
2693 SUNXI_FUNCTION(0x1, "gpio_out"),
2694 SUNXI_FUNCTION(0x2, "uart4")), /* RX */
2695 /* Hole */
2696 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0,
2697 SUNXI_FUNCTION(0x0, "gpio_in"),
2698 SUNXI_FUNCTION(0x1, "gpio_out"),
2699 SUNXI_FUNCTION(0x2, "nand1")), /* WE */
2700 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1,
2701 SUNXI_FUNCTION(0x0, "gpio_in"),
2702 SUNXI_FUNCTION(0x1, "gpio_out"),
2703 SUNXI_FUNCTION(0x2, "nand1")), /* ALE */
2704 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2,
2705 SUNXI_FUNCTION(0x0, "gpio_in"),
2706 SUNXI_FUNCTION(0x1, "gpio_out"),
2707 SUNXI_FUNCTION(0x2, "nand1")), /* CLE */
2708 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3,
2709 SUNXI_FUNCTION(0x0, "gpio_in"),
2710 SUNXI_FUNCTION(0x1, "gpio_out"),
2711 SUNXI_FUNCTION(0x2, "nand1")), /* CE1 */
2712 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4,
2713 SUNXI_FUNCTION(0x0, "gpio_in"),
2714 SUNXI_FUNCTION(0x1, "gpio_out"),
2715 SUNXI_FUNCTION(0x2, "nand1")), /* CE0 */
2716 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5,
2717 SUNXI_FUNCTION(0x0, "gpio_in"),
2718 SUNXI_FUNCTION(0x1, "gpio_out"),
2719 SUNXI_FUNCTION(0x2, "nand1")), /* RE */
2720 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6,
2721 SUNXI_FUNCTION(0x0, "gpio_in"),
2722 SUNXI_FUNCTION(0x1, "gpio_out"),
2723 SUNXI_FUNCTION(0x2, "nand1")), /* RB0 */
2724 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7,
2725 SUNXI_FUNCTION(0x0, "gpio_in"),
2726 SUNXI_FUNCTION(0x1, "gpio_out"),
2727 SUNXI_FUNCTION(0x2, "nand1")), /* RB1 */
2728 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8,
2729 SUNXI_FUNCTION(0x0, "gpio_in"),
2730 SUNXI_FUNCTION(0x1, "gpio_out"),
2731 SUNXI_FUNCTION(0x2, "nand1")), /* DQS */
2732 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9,
2733 SUNXI_FUNCTION(0x0, "gpio_in"),
2734 SUNXI_FUNCTION(0x1, "gpio_out"),
2735 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
2736 SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
2737 SUNXI_FUNCTION(0x4, "pwm1")), /* Positive */
2738 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10,
2739 SUNXI_FUNCTION(0x0, "gpio_in"),
2740 SUNXI_FUNCTION(0x1, "gpio_out"),
2741 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
2742 SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
2743 SUNXI_FUNCTION(0x4, "pwm1")), /* Negative */
2744 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11,
2745 SUNXI_FUNCTION(0x0, "gpio_in"),
2746 SUNXI_FUNCTION(0x1, "gpio_out"),
2747 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
2748 SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
2749 SUNXI_FUNCTION(0x4, "pwm2")), /* Positive */
2750 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12,
2751 SUNXI_FUNCTION(0x0, "gpio_in"),
2752 SUNXI_FUNCTION(0x1, "gpio_out"),
2753 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
2754 SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
2755 SUNXI_FUNCTION(0x4, "pwm2")), /* Negative */
2756 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13,
2757 SUNXI_FUNCTION(0x0, "gpio_in"),
2758 SUNXI_FUNCTION(0x1, "gpio_out"),
2759 SUNXI_FUNCTION(0x2, "pwm0")),
2760 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14,
2761 SUNXI_FUNCTION(0x0, "gpio_in"),
2762 SUNXI_FUNCTION(0x1, "gpio_out"),
2763 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
2764 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15,
2765 SUNXI_FUNCTION(0x0, "gpio_in"),
2766 SUNXI_FUNCTION(0x1, "gpio_out"),
2767 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
2768 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16,
2769 SUNXI_FUNCTION(0x0, "gpio_in"),
2770 SUNXI_FUNCTION(0x1, "gpio_out"),
2771 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
2772 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17,
2773 SUNXI_FUNCTION(0x0, "gpio_in"),
2774 SUNXI_FUNCTION(0x1, "gpio_out"),
2775 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
2776 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18,
2777 SUNXI_FUNCTION(0x0, "gpio_in"),
2778 SUNXI_FUNCTION(0x1, "gpio_out"),
2779 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
2780 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19,
2781 SUNXI_FUNCTION(0x0, "gpio_in"),
2782 SUNXI_FUNCTION(0x1, "gpio_out"),
2783 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
2784 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20,
2785 SUNXI_FUNCTION(0x0, "gpio_in"),
2786 SUNXI_FUNCTION(0x1, "gpio_out"),
2787 SUNXI_FUNCTION(0x2, "uart0")), /* TX */
2788 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21,
2789 SUNXI_FUNCTION(0x0, "gpio_in"),
2790 SUNXI_FUNCTION(0x1, "gpio_out"),
2791 SUNXI_FUNCTION(0x2, "uart0")), /* RX */
2792 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22,
2793 SUNXI_FUNCTION(0x0, "gpio_in"),
2794 SUNXI_FUNCTION(0x1, "gpio_out")),
2795 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23,
2796 SUNXI_FUNCTION(0x0, "gpio_in"),
2797 SUNXI_FUNCTION(0x1, "gpio_out")),
2798 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24,
2799 SUNXI_FUNCTION(0x0, "gpio_in"),
2800 SUNXI_FUNCTION(0x1, "gpio_out")),
2801 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25,
2802 SUNXI_FUNCTION(0x0, "gpio_in"),
2803 SUNXI_FUNCTION(0x1, "gpio_out")),
2804 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26,
2805 SUNXI_FUNCTION(0x0, "gpio_in"),
2806 SUNXI_FUNCTION(0x1, "gpio_out")),
2807 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27,
2808 SUNXI_FUNCTION(0x0, "gpio_in"),
2809 SUNXI_FUNCTION(0x1, "gpio_out")),
2810 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH28,
2811 SUNXI_FUNCTION(0x0, "gpio_in"),
2812 SUNXI_FUNCTION(0x1, "gpio_out")),
2813 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH29,
2814 SUNXI_FUNCTION(0x0, "gpio_in"),
2815 SUNXI_FUNCTION(0x1, "gpio_out"),
2816 SUNXI_FUNCTION(0x2, "nand1")), /* CE2 */
2817 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH30,
2818 SUNXI_FUNCTION(0x0, "gpio_in"),
2819 SUNXI_FUNCTION(0x1, "gpio_out"),
2820 SUNXI_FUNCTION(0x2, "nand1")), /* CE3 */
2821};
2822
2823static const struct sunxi_desc_pin sun6i_a31_r_pins[] = {
2824 SUNXI_PIN(SUNXI_PINCTRL_PIN_PL0,
2825 SUNXI_FUNCTION(0x0, "gpio_in"),
2826 SUNXI_FUNCTION(0x1, "gpio_out"),
2827 SUNXI_FUNCTION(0x2, "s_twi"), /* SCK */
2828 SUNXI_FUNCTION(0x3, "s_p2wi")), /* SCK */
2829 SUNXI_PIN(SUNXI_PINCTRL_PIN_PL1,
2830 SUNXI_FUNCTION(0x0, "gpio_in"),
2831 SUNXI_FUNCTION(0x1, "gpio_out"),
2832 SUNXI_FUNCTION(0x2, "s_twi"), /* SDA */
2833 SUNXI_FUNCTION(0x3, "s_p2wi")), /* SDA */
2834 SUNXI_PIN(SUNXI_PINCTRL_PIN_PL2,
2835 SUNXI_FUNCTION(0x0, "gpio_in"),
2836 SUNXI_FUNCTION(0x1, "gpio_out"),
2837 SUNXI_FUNCTION(0x2, "s_uart")), /* TX */
2838 SUNXI_PIN(SUNXI_PINCTRL_PIN_PL3,
2839 SUNXI_FUNCTION(0x0, "gpio_in"),
2840 SUNXI_FUNCTION(0x1, "gpio_out"),
2841 SUNXI_FUNCTION(0x2, "s_uart")), /* RX */
2842 SUNXI_PIN(SUNXI_PINCTRL_PIN_PL4,
2843 SUNXI_FUNCTION(0x0, "gpio_in"),
2844 SUNXI_FUNCTION(0x1, "gpio_out"),
2845 SUNXI_FUNCTION(0x2, "s_ir")), /* RX */
2846 SUNXI_PIN(SUNXI_PINCTRL_PIN_PL5,
2847 SUNXI_FUNCTION(0x0, "gpio_in"),
2848 SUNXI_FUNCTION(0x1, "gpio_out"),
2849 SUNXI_FUNCTION(0x3, "s_jtag")), /* MS */
2850 SUNXI_PIN(SUNXI_PINCTRL_PIN_PL6,
2851 SUNXI_FUNCTION(0x0, "gpio_in"),
2852 SUNXI_FUNCTION(0x1, "gpio_out"),
2853 SUNXI_FUNCTION(0x3, "s_jtag")), /* CK */
2854 SUNXI_PIN(SUNXI_PINCTRL_PIN_PL7,
2855 SUNXI_FUNCTION(0x0, "gpio_in"),
2856 SUNXI_FUNCTION(0x1, "gpio_out"),
2857 SUNXI_FUNCTION(0x3, "s_jtag")), /* DO */
2858 SUNXI_PIN(SUNXI_PINCTRL_PIN_PL8,
2859 SUNXI_FUNCTION(0x0, "gpio_in"),
2860 SUNXI_FUNCTION(0x1, "gpio_out"),
2861 SUNXI_FUNCTION(0x3, "s_jtag")), /* DI */
2862 /* Hole */
2863 SUNXI_PIN(SUNXI_PINCTRL_PIN_PM0,
2864 SUNXI_FUNCTION(0x0, "gpio_in"),
2865 SUNXI_FUNCTION(0x1, "gpio_out")),
2866 SUNXI_PIN(SUNXI_PINCTRL_PIN_PM1,
2867 SUNXI_FUNCTION(0x0, "gpio_in"),
2868 SUNXI_FUNCTION(0x1, "gpio_out")),
2869 SUNXI_PIN(SUNXI_PINCTRL_PIN_PM2,
2870 SUNXI_FUNCTION(0x0, "gpio_in"),
2871 SUNXI_FUNCTION(0x1, "gpio_out"),
2872 SUNXI_FUNCTION(0x3, "1wire")),
2873 SUNXI_PIN(SUNXI_PINCTRL_PIN_PM3,
2874 SUNXI_FUNCTION(0x0, "gpio_in"),
2875 SUNXI_FUNCTION(0x1, "gpio_out")),
2876 SUNXI_PIN(SUNXI_PINCTRL_PIN_PM4,
2877 SUNXI_FUNCTION(0x0, "gpio_in"),
2878 SUNXI_FUNCTION(0x1, "gpio_out")),
2879 SUNXI_PIN(SUNXI_PINCTRL_PIN_PM5,
2880 SUNXI_FUNCTION(0x0, "gpio_in"),
2881 SUNXI_FUNCTION(0x1, "gpio_out")),
2882 SUNXI_PIN(SUNXI_PINCTRL_PIN_PM6,
2883 SUNXI_FUNCTION(0x0, "gpio_in"),
2884 SUNXI_FUNCTION(0x1, "gpio_out")),
2885 SUNXI_PIN(SUNXI_PINCTRL_PIN_PM7,
2886 SUNXI_FUNCTION(0x0, "gpio_in"),
2887 SUNXI_FUNCTION(0x1, "gpio_out"),
2888 SUNXI_FUNCTION(0x3, "rtc")), /* CLKO */
2889};
2890
2891static const struct sunxi_desc_pin sun7i_a20_pins[] = {
2892 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
2893 SUNXI_FUNCTION(0x0, "gpio_in"),
2894 SUNXI_FUNCTION(0x1, "gpio_out"),
2895 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
2896 SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
2897 SUNXI_FUNCTION(0x4, "uart2"), /* RTS */
2898 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD3 */
2899 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
2900 SUNXI_FUNCTION(0x0, "gpio_in"),
2901 SUNXI_FUNCTION(0x1, "gpio_out"),
2902 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
2903 SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
2904 SUNXI_FUNCTION(0x4, "uart2"), /* CTS */
2905 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD2 */
2906 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
2907 SUNXI_FUNCTION(0x0, "gpio_in"),
2908 SUNXI_FUNCTION(0x1, "gpio_out"),
2909 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
2910 SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
2911 SUNXI_FUNCTION(0x4, "uart2"), /* TX */
2912 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD1 */
2913 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
2914 SUNXI_FUNCTION(0x0, "gpio_in"),
2915 SUNXI_FUNCTION(0x1, "gpio_out"),
2916 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
2917 SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
2918 SUNXI_FUNCTION(0x4, "uart2"), /* RX */
2919 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD0 */
2920 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
2921 SUNXI_FUNCTION(0x0, "gpio_in"),
2922 SUNXI_FUNCTION(0x1, "gpio_out"),
2923 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
2924 SUNXI_FUNCTION(0x3, "spi1"), /* CS1 */
2925 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD3 */
2926 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
2927 SUNXI_FUNCTION(0x0, "gpio_in"),
2928 SUNXI_FUNCTION(0x1, "gpio_out"),
2929 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
2930 SUNXI_FUNCTION(0x3, "spi3"), /* CS0 */
2931 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD2 */
2932 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
2933 SUNXI_FUNCTION(0x0, "gpio_in"),
2934 SUNXI_FUNCTION(0x1, "gpio_out"),
2935 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
2936 SUNXI_FUNCTION(0x3, "spi3"), /* CLK */
2937 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD1 */
2938 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
2939 SUNXI_FUNCTION(0x0, "gpio_in"),
2940 SUNXI_FUNCTION(0x1, "gpio_out"),
2941 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
2942 SUNXI_FUNCTION(0x3, "spi3"), /* MOSI */
2943 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD0 */
2944 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
2945 SUNXI_FUNCTION(0x0, "gpio_in"),
2946 SUNXI_FUNCTION(0x1, "gpio_out"),
2947 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
2948 SUNXI_FUNCTION(0x3, "spi3"), /* MISO */
2949 SUNXI_FUNCTION(0x5, "gmac")), /* GRXCK */
2950 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
2951 SUNXI_FUNCTION(0x0, "gpio_in"),
2952 SUNXI_FUNCTION(0x1, "gpio_out"),
2953 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
2954 SUNXI_FUNCTION(0x3, "spi3"), /* CS1 */
2955 SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ERXERR */
2956 SUNXI_FUNCTION(0x6, "i2s1")), /* MCLK */
2957 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
2958 SUNXI_FUNCTION(0x0, "gpio_in"),
2959 SUNXI_FUNCTION(0x1, "gpio_out"),
2960 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
2961 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
2962 SUNXI_FUNCTION(0x5, "gmac")), /* GRXCTL / ERXDV */
2963 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
2964 SUNXI_FUNCTION(0x0, "gpio_in"),
2965 SUNXI_FUNCTION(0x1, "gpio_out"),
2966 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
2967 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
2968 SUNXI_FUNCTION(0x5, "gmac")), /* EMDC */
2969 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
2970 SUNXI_FUNCTION(0x0, "gpio_in"),
2971 SUNXI_FUNCTION(0x1, "gpio_out"),
2972 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
2973 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
2974 SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
2975 SUNXI_FUNCTION(0x5, "gmac")), /* EMDIO */
2976 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
2977 SUNXI_FUNCTION(0x0, "gpio_in"),
2978 SUNXI_FUNCTION(0x1, "gpio_out"),
2979 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
2980 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
2981 SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
2982 SUNXI_FUNCTION(0x5, "gmac")), /* GTXCTL / ETXEN */
2983 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
2984 SUNXI_FUNCTION(0x0, "gpio_in"),
2985 SUNXI_FUNCTION(0x1, "gpio_out"),
2986 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
2987 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
2988 SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
2989 SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ETXCK */
2990 SUNXI_FUNCTION(0x6, "i2s1")), /* BCLK */
2991 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
2992 SUNXI_FUNCTION(0x0, "gpio_in"),
2993 SUNXI_FUNCTION(0x1, "gpio_out"),
2994 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
2995 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
2996 SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
2997 SUNXI_FUNCTION(0x5, "gmac"), /* GTXCK / ECRS */
2998 SUNXI_FUNCTION(0x6, "i2s1")), /* LRCK */
2999 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
3000 SUNXI_FUNCTION(0x0, "gpio_in"),
3001 SUNXI_FUNCTION(0x1, "gpio_out"),
3002 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
3003 SUNXI_FUNCTION(0x3, "can"), /* TX */
3004 SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
3005 SUNXI_FUNCTION(0x5, "gmac"), /* GCLKIN / ECOL */
3006 SUNXI_FUNCTION(0x6, "i2s1")), /* DO */
3007 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
3008 SUNXI_FUNCTION(0x0, "gpio_in"),
3009 SUNXI_FUNCTION(0x1, "gpio_out"),
3010 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
3011 SUNXI_FUNCTION(0x3, "can"), /* RX */
3012 SUNXI_FUNCTION(0x4, "uart1"), /* RING */
3013 SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ETXERR */
3014 SUNXI_FUNCTION(0x6, "i2s1")), /* LRCK */
3015 /* Hole */
3016 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
3017 SUNXI_FUNCTION(0x0, "gpio_in"),
3018 SUNXI_FUNCTION(0x1, "gpio_out"),
3019 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
3020 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
3021 SUNXI_FUNCTION(0x0, "gpio_in"),
3022 SUNXI_FUNCTION(0x1, "gpio_out"),
3023 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
3024 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
3025 SUNXI_FUNCTION(0x0, "gpio_in"),
3026 SUNXI_FUNCTION(0x1, "gpio_out"),
3027 SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */
3028 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
3029 SUNXI_FUNCTION(0x0, "gpio_in"),
3030 SUNXI_FUNCTION(0x1, "gpio_out"),
3031 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
3032 SUNXI_FUNCTION(0x4, "spdif")), /* MCLK */
3033 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
3034 SUNXI_FUNCTION(0x0, "gpio_in"),
3035 SUNXI_FUNCTION(0x1, "gpio_out"),
3036 SUNXI_FUNCTION(0x2, "ir0")), /* RX */
3037 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
3038 SUNXI_FUNCTION(0x0, "gpio_in"),
3039 SUNXI_FUNCTION(0x1, "gpio_out"),
3040 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
3041 SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */
3042 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
3043 SUNXI_FUNCTION(0x0, "gpio_in"),
3044 SUNXI_FUNCTION(0x1, "gpio_out"),
3045 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
3046 SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */
3047 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
3048 SUNXI_FUNCTION(0x0, "gpio_in"),
3049 SUNXI_FUNCTION(0x1, "gpio_out"),
3050 SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
3051 SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */
3052 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8,
3053 SUNXI_FUNCTION(0x0, "gpio_in"),
3054 SUNXI_FUNCTION(0x1, "gpio_out"),
3055 SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */
3056 SUNXI_FUNCTION(0x3, "ac97")), /* DO */
3057 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9,
3058 SUNXI_FUNCTION(0x0, "gpio_in"),
3059 SUNXI_FUNCTION(0x1, "gpio_out"),
3060 SUNXI_FUNCTION(0x2, "i2s0")), /* DO1 */
3061 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
3062 SUNXI_FUNCTION(0x0, "gpio_in"),
3063 SUNXI_FUNCTION(0x1, "gpio_out"),
3064 SUNXI_FUNCTION(0x2, "i2s0")), /* DO2 */
3065 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11,
3066 SUNXI_FUNCTION(0x0, "gpio_in"),
3067 SUNXI_FUNCTION(0x1, "gpio_out"),
3068 SUNXI_FUNCTION(0x2, "i2s0")), /* DO3 */
3069 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12,
3070 SUNXI_FUNCTION(0x0, "gpio_in"),
3071 SUNXI_FUNCTION(0x1, "gpio_out"),
3072 SUNXI_FUNCTION(0x2, "i2s0"), /* DI */
3073 SUNXI_FUNCTION(0x3, "ac97"), /* DI */
3074 SUNXI_FUNCTION(0x4, "spdif")), /* DI */
3075 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13,
3076 SUNXI_FUNCTION(0x0, "gpio_in"),
3077 SUNXI_FUNCTION(0x1, "gpio_out"),
3078 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
3079 SUNXI_FUNCTION(0x4, "spdif")), /* DO */
3080 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14,
3081 SUNXI_FUNCTION(0x0, "gpio_in"),
3082 SUNXI_FUNCTION(0x1, "gpio_out"),
3083 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
3084 SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */
3085 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
3086 SUNXI_FUNCTION(0x0, "gpio_in"),
3087 SUNXI_FUNCTION(0x1, "gpio_out"),
3088 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
3089 SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */
3090 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
3091 SUNXI_FUNCTION(0x0, "gpio_in"),
3092 SUNXI_FUNCTION(0x1, "gpio_out"),
3093 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
3094 SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */
3095 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
3096 SUNXI_FUNCTION(0x0, "gpio_in"),
3097 SUNXI_FUNCTION(0x1, "gpio_out"),
3098 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
3099 SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */
3100 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
3101 SUNXI_FUNCTION(0x0, "gpio_in"),
3102 SUNXI_FUNCTION(0x1, "gpio_out"),
3103 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
3104 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19,
3105 SUNXI_FUNCTION(0x0, "gpio_in"),
3106 SUNXI_FUNCTION(0x1, "gpio_out"),
3107 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
3108 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20,
3109 SUNXI_FUNCTION(0x0, "gpio_in"),
3110 SUNXI_FUNCTION(0x1, "gpio_out"),
3111 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
3112 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21,
3113 SUNXI_FUNCTION(0x0, "gpio_in"),
3114 SUNXI_FUNCTION(0x1, "gpio_out"),
3115 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
3116 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22,
3117 SUNXI_FUNCTION(0x0, "gpio_in"),
3118 SUNXI_FUNCTION(0x1, "gpio_out"),
3119 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
3120 SUNXI_FUNCTION(0x3, "ir1")), /* TX */
3121 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23,
3122 SUNXI_FUNCTION(0x0, "gpio_in"),
3123 SUNXI_FUNCTION(0x1, "gpio_out"),
3124 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
3125 SUNXI_FUNCTION(0x3, "ir1")), /* RX */
3126 /* Hole */
3127 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
3128 SUNXI_FUNCTION(0x0, "gpio_in"),
3129 SUNXI_FUNCTION(0x1, "gpio_out"),
3130 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
3131 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
3132 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
3133 SUNXI_FUNCTION(0x0, "gpio_in"),
3134 SUNXI_FUNCTION(0x1, "gpio_out"),
3135 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
3136 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
3137 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
3138 SUNXI_FUNCTION(0x0, "gpio_in"),
3139 SUNXI_FUNCTION(0x1, "gpio_out"),
3140 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
3141 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
3142 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
3143 SUNXI_FUNCTION(0x0, "gpio_in"),
3144 SUNXI_FUNCTION(0x1, "gpio_out"),
3145 SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */
3146 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
3147 SUNXI_FUNCTION(0x0, "gpio_in"),
3148 SUNXI_FUNCTION(0x1, "gpio_out"),
3149 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
3150 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
3151 SUNXI_FUNCTION(0x0, "gpio_in"),
3152 SUNXI_FUNCTION(0x1, "gpio_out"),
3153 SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */
3154 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
3155 SUNXI_FUNCTION(0x0, "gpio_in"),
3156 SUNXI_FUNCTION(0x1, "gpio_out"),
3157 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
3158 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
3159 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
3160 SUNXI_FUNCTION(0x0, "gpio_in"),
3161 SUNXI_FUNCTION(0x1, "gpio_out"),
3162 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
3163 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
3164 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
3165 SUNXI_FUNCTION(0x0, "gpio_in"),
3166 SUNXI_FUNCTION(0x1, "gpio_out"),
3167 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
3168 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
3169 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
3170 SUNXI_FUNCTION(0x0, "gpio_in"),
3171 SUNXI_FUNCTION(0x1, "gpio_out"),
3172 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
3173 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
3174 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
3175 SUNXI_FUNCTION(0x0, "gpio_in"),
3176 SUNXI_FUNCTION(0x1, "gpio_out"),
3177 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
3178 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
3179 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
3180 SUNXI_FUNCTION(0x0, "gpio_in"),
3181 SUNXI_FUNCTION(0x1, "gpio_out"),
3182 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
3183 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
3184 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
3185 SUNXI_FUNCTION(0x0, "gpio_in"),
3186 SUNXI_FUNCTION(0x1, "gpio_out"),
3187 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */
3188 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
3189 SUNXI_FUNCTION(0x0, "gpio_in"),
3190 SUNXI_FUNCTION(0x1, "gpio_out"),
3191 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */
3192 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
3193 SUNXI_FUNCTION(0x0, "gpio_in"),
3194 SUNXI_FUNCTION(0x1, "gpio_out"),
3195 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */
3196 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
3197 SUNXI_FUNCTION(0x0, "gpio_in"),
3198 SUNXI_FUNCTION(0x1, "gpio_out"),
3199 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */
3200 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
3201 SUNXI_FUNCTION(0x0, "gpio_in"),
3202 SUNXI_FUNCTION(0x1, "gpio_out"),
3203 SUNXI_FUNCTION(0x2, "nand0")), /* NWP */
3204 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
3205 SUNXI_FUNCTION(0x0, "gpio_in"),
3206 SUNXI_FUNCTION(0x1, "gpio_out"),
3207 SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */
3208 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
3209 SUNXI_FUNCTION(0x0, "gpio_in"),
3210 SUNXI_FUNCTION(0x1, "gpio_out"),
3211 SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */
3212 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
3213 SUNXI_FUNCTION(0x0, "gpio_in"),
3214 SUNXI_FUNCTION(0x1, "gpio_out"),
3215 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
3216 SUNXI_FUNCTION(0x3, "spi2"), /* CS0 */
3217 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
3218 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20,
3219 SUNXI_FUNCTION(0x0, "gpio_in"),
3220 SUNXI_FUNCTION(0x1, "gpio_out"),
3221 SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
3222 SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
3223 SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
3224 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21,
3225 SUNXI_FUNCTION(0x0, "gpio_in"),
3226 SUNXI_FUNCTION(0x1, "gpio_out"),
3227 SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
3228 SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
3229 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
3230 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22,
3231 SUNXI_FUNCTION(0x0, "gpio_in"),
3232 SUNXI_FUNCTION(0x1, "gpio_out"),
3233 SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
3234 SUNXI_FUNCTION(0x3, "spi2"), /* MISO */
3235 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
3236 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23,
3237 SUNXI_FUNCTION(0x0, "gpio_in"),
3238 SUNXI_FUNCTION(0x1, "gpio_out"),
3239 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
3240 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24,
3241 SUNXI_FUNCTION(0x0, "gpio_in"),
3242 SUNXI_FUNCTION(0x1, "gpio_out"),
3243 SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */
3244 /* Hole */
3245 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
3246 SUNXI_FUNCTION(0x0, "gpio_in"),
3247 SUNXI_FUNCTION(0x1, "gpio_out"),
3248 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
3249 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
3250 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
3251 SUNXI_FUNCTION(0x0, "gpio_in"),
3252 SUNXI_FUNCTION(0x1, "gpio_out"),
3253 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
3254 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
3255 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
3256 SUNXI_FUNCTION(0x0, "gpio_in"),
3257 SUNXI_FUNCTION(0x1, "gpio_out"),
3258 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
3259 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
3260 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
3261 SUNXI_FUNCTION(0x0, "gpio_in"),
3262 SUNXI_FUNCTION(0x1, "gpio_out"),
3263 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
3264 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
3265 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
3266 SUNXI_FUNCTION(0x0, "gpio_in"),
3267 SUNXI_FUNCTION(0x1, "gpio_out"),
3268 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
3269 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
3270 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
3271 SUNXI_FUNCTION(0x0, "gpio_in"),
3272 SUNXI_FUNCTION(0x1, "gpio_out"),
3273 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
3274 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
3275 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
3276 SUNXI_FUNCTION(0x0, "gpio_in"),
3277 SUNXI_FUNCTION(0x1, "gpio_out"),
3278 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
3279 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
3280 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
3281 SUNXI_FUNCTION(0x0, "gpio_in"),
3282 SUNXI_FUNCTION(0x1, "gpio_out"),
3283 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
3284 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
3285 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
3286 SUNXI_FUNCTION(0x0, "gpio_in"),
3287 SUNXI_FUNCTION(0x1, "gpio_out"),
3288 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
3289 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
3290 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
3291 SUNXI_FUNCTION(0x0, "gpio_in"),
3292 SUNXI_FUNCTION(0x1, "gpio_out"),
3293 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
3294 SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */
3295 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
3296 SUNXI_FUNCTION(0x0, "gpio_in"),
3297 SUNXI_FUNCTION(0x1, "gpio_out"),
3298 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
3299 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
3300 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
3301 SUNXI_FUNCTION(0x0, "gpio_in"),
3302 SUNXI_FUNCTION(0x1, "gpio_out"),
3303 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
3304 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
3305 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
3306 SUNXI_FUNCTION(0x0, "gpio_in"),
3307 SUNXI_FUNCTION(0x1, "gpio_out"),
3308 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
3309 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
3310 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
3311 SUNXI_FUNCTION(0x0, "gpio_in"),
3312 SUNXI_FUNCTION(0x1, "gpio_out"),
3313 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
3314 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
3315 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
3316 SUNXI_FUNCTION(0x0, "gpio_in"),
3317 SUNXI_FUNCTION(0x1, "gpio_out"),
3318 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
3319 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
3320 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
3321 SUNXI_FUNCTION(0x0, "gpio_in"),
3322 SUNXI_FUNCTION(0x1, "gpio_out"),
3323 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
3324 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
3325 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
3326 SUNXI_FUNCTION(0x0, "gpio_in"),
3327 SUNXI_FUNCTION(0x1, "gpio_out"),
3328 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
3329 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
3330 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
3331 SUNXI_FUNCTION(0x0, "gpio_in"),
3332 SUNXI_FUNCTION(0x1, "gpio_out"),
3333 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
3334 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
3335 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
3336 SUNXI_FUNCTION(0x0, "gpio_in"),
3337 SUNXI_FUNCTION(0x1, "gpio_out"),
3338 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
3339 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
3340 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
3341 SUNXI_FUNCTION(0x0, "gpio_in"),
3342 SUNXI_FUNCTION(0x1, "gpio_out"),
3343 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
3344 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
3345 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
3346 SUNXI_FUNCTION(0x0, "gpio_in"),
3347 SUNXI_FUNCTION(0x1, "gpio_out"),
3348 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
3349 SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */
3350 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
3351 SUNXI_FUNCTION(0x0, "gpio_in"),
3352 SUNXI_FUNCTION(0x1, "gpio_out"),
3353 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
3354 SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */
3355 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
3356 SUNXI_FUNCTION(0x0, "gpio_in"),
3357 SUNXI_FUNCTION(0x1, "gpio_out"),
3358 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
3359 SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */
3360 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
3361 SUNXI_FUNCTION(0x0, "gpio_in"),
3362 SUNXI_FUNCTION(0x1, "gpio_out"),
3363 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
3364 SUNXI_FUNCTION(0x3, "sim")), /* DET */
3365 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
3366 SUNXI_FUNCTION(0x0, "gpio_in"),
3367 SUNXI_FUNCTION(0x1, "gpio_out"),
3368 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
3369 SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */
3370 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
3371 SUNXI_FUNCTION(0x0, "gpio_in"),
3372 SUNXI_FUNCTION(0x1, "gpio_out"),
3373 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
3374 SUNXI_FUNCTION(0x3, "sim")), /* RST */
3375 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
3376 SUNXI_FUNCTION(0x0, "gpio_in"),
3377 SUNXI_FUNCTION(0x1, "gpio_out"),
3378 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
3379 SUNXI_FUNCTION(0x3, "sim")), /* SCK */
3380 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
3381 SUNXI_FUNCTION(0x0, "gpio_in"),
3382 SUNXI_FUNCTION(0x1, "gpio_out"),
3383 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
3384 SUNXI_FUNCTION(0x3, "sim")), /* SDA */
3385 /* Hole */
3386 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
3387 SUNXI_FUNCTION(0x0, "gpio_in"),
3388 SUNXI_FUNCTION(0x1, "gpio_out"),
3389 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
3390 SUNXI_FUNCTION(0x3, "csi0")), /* PCK */
3391 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
3392 SUNXI_FUNCTION(0x0, "gpio_in"),
3393 SUNXI_FUNCTION(0x1, "gpio_out"),
3394 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
3395 SUNXI_FUNCTION(0x3, "csi0")), /* CK */
3396 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
3397 SUNXI_FUNCTION(0x0, "gpio_in"),
3398 SUNXI_FUNCTION(0x1, "gpio_out"),
3399 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
3400 SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */
3401 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
3402 SUNXI_FUNCTION(0x0, "gpio_in"),
3403 SUNXI_FUNCTION(0x1, "gpio_out"),
3404 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
3405 SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */
3406 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
3407 SUNXI_FUNCTION(0x0, "gpio_in"),
3408 SUNXI_FUNCTION(0x1, "gpio_out"),
3409 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
3410 SUNXI_FUNCTION(0x3, "csi0")), /* D0 */
3411 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
3412 SUNXI_FUNCTION(0x0, "gpio_in"),
3413 SUNXI_FUNCTION(0x1, "gpio_out"),
3414 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
3415 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
3416 SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */
3417 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
3418 SUNXI_FUNCTION(0x0, "gpio_in"),
3419 SUNXI_FUNCTION(0x1, "gpio_out"),
3420 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
3421 SUNXI_FUNCTION(0x3, "csi0")), /* D2 */
3422 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
3423 SUNXI_FUNCTION(0x0, "gpio_in"),
3424 SUNXI_FUNCTION(0x1, "gpio_out"),
3425 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
3426 SUNXI_FUNCTION(0x3, "csi0")), /* D3 */
3427 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
3428 SUNXI_FUNCTION(0x0, "gpio_in"),
3429 SUNXI_FUNCTION(0x1, "gpio_out"),
3430 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
3431 SUNXI_FUNCTION(0x3, "csi0")), /* D4 */
3432 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
3433 SUNXI_FUNCTION(0x0, "gpio_in"),
3434 SUNXI_FUNCTION(0x1, "gpio_out"),
3435 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
3436 SUNXI_FUNCTION(0x3, "csi0")), /* D5 */
3437 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
3438 SUNXI_FUNCTION(0x0, "gpio_in"),
3439 SUNXI_FUNCTION(0x1, "gpio_out"),
3440 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
3441 SUNXI_FUNCTION(0x3, "csi0")), /* D6 */
3442 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
3443 SUNXI_FUNCTION(0x0, "gpio_in"),
3444 SUNXI_FUNCTION(0x1, "gpio_out"),
3445 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
3446 SUNXI_FUNCTION(0x3, "csi0")), /* D7 */
3447 /* Hole */
3448 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
3449 SUNXI_FUNCTION(0x0, "gpio_in"),
3450 SUNXI_FUNCTION(0x1, "gpio_out"),
3451 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
3452 SUNXI_FUNCTION(0x4, "jtag")), /* MSI */
3453 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
3454 SUNXI_FUNCTION(0x0, "gpio_in"),
3455 SUNXI_FUNCTION(0x1, "gpio_out"),
3456 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
3457 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
3458 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
3459 SUNXI_FUNCTION(0x0, "gpio_in"),
3460 SUNXI_FUNCTION(0x1, "gpio_out"),
3461 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
3462 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
3463 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
3464 SUNXI_FUNCTION(0x0, "gpio_in"),
3465 SUNXI_FUNCTION(0x1, "gpio_out"),
3466 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
3467 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
3468 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
3469 SUNXI_FUNCTION(0x0, "gpio_in"),
3470 SUNXI_FUNCTION(0x1, "gpio_out"),
3471 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
3472 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
3473 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
3474 SUNXI_FUNCTION(0x0, "gpio_in"),
3475 SUNXI_FUNCTION(0x1, "gpio_out"),
3476 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
3477 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
3478 /* Hole */
3479 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
3480 SUNXI_FUNCTION(0x0, "gpio_in"),
3481 SUNXI_FUNCTION(0x1, "gpio_out"),
3482 SUNXI_FUNCTION(0x2, "ts1"), /* CLK */
3483 SUNXI_FUNCTION(0x3, "csi1"), /* PCK */
3484 SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */
3485 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
3486 SUNXI_FUNCTION(0x0, "gpio_in"),
3487 SUNXI_FUNCTION(0x1, "gpio_out"),
3488 SUNXI_FUNCTION(0x2, "ts1"), /* ERR */
3489 SUNXI_FUNCTION(0x3, "csi1"), /* CK */
3490 SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */
3491 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
3492 SUNXI_FUNCTION(0x0, "gpio_in"),
3493 SUNXI_FUNCTION(0x1, "gpio_out"),
3494 SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */
3495 SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */
3496 SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */
3497 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
3498 SUNXI_FUNCTION(0x0, "gpio_in"),
3499 SUNXI_FUNCTION(0x1, "gpio_out"),
3500 SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */
3501 SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */
3502 SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */
3503 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
3504 SUNXI_FUNCTION(0x0, "gpio_in"),
3505 SUNXI_FUNCTION(0x1, "gpio_out"),
3506 SUNXI_FUNCTION(0x2, "ts1"), /* D0 */
3507 SUNXI_FUNCTION(0x3, "csi1"), /* D0 */
3508 SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */
3509 SUNXI_FUNCTION(0x5, "csi0")), /* D8 */
3510 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
3511 SUNXI_FUNCTION(0x0, "gpio_in"),
3512 SUNXI_FUNCTION(0x1, "gpio_out"),
3513 SUNXI_FUNCTION(0x2, "ts1"), /* D1 */
3514 SUNXI_FUNCTION(0x3, "csi1"), /* D1 */
3515 SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */
3516 SUNXI_FUNCTION(0x5, "csi0")), /* D9 */
3517 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
3518 SUNXI_FUNCTION(0x0, "gpio_in"),
3519 SUNXI_FUNCTION(0x1, "gpio_out"),
3520 SUNXI_FUNCTION(0x2, "ts1"), /* D2 */
3521 SUNXI_FUNCTION(0x3, "csi1"), /* D2 */
3522 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
3523 SUNXI_FUNCTION(0x5, "csi0")), /* D10 */
3524 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
3525 SUNXI_FUNCTION(0x0, "gpio_in"),
3526 SUNXI_FUNCTION(0x1, "gpio_out"),
3527 SUNXI_FUNCTION(0x2, "ts1"), /* D3 */
3528 SUNXI_FUNCTION(0x3, "csi1"), /* D3 */
3529 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
3530 SUNXI_FUNCTION(0x5, "csi0")), /* D11 */
3531 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
3532 SUNXI_FUNCTION(0x0, "gpio_in"),
3533 SUNXI_FUNCTION(0x1, "gpio_out"),
3534 SUNXI_FUNCTION(0x2, "ts1"), /* D4 */
3535 SUNXI_FUNCTION(0x3, "csi1"), /* D4 */
3536 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
3537 SUNXI_FUNCTION(0x5, "csi0")), /* D12 */
3538 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
3539 SUNXI_FUNCTION(0x0, "gpio_in"),
3540 SUNXI_FUNCTION(0x1, "gpio_out"),
3541 SUNXI_FUNCTION(0x2, "ts1"), /* D5 */
3542 SUNXI_FUNCTION(0x3, "csi1"), /* D5 */
3543 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
3544 SUNXI_FUNCTION(0x5, "csi0")), /* D13 */
3545 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
3546 SUNXI_FUNCTION(0x0, "gpio_in"),
3547 SUNXI_FUNCTION(0x1, "gpio_out"),
3548 SUNXI_FUNCTION(0x2, "ts1"), /* D6 */
3549 SUNXI_FUNCTION(0x3, "csi1"), /* D6 */
3550 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
3551 SUNXI_FUNCTION(0x5, "csi0")), /* D14 */
3552 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
3553 SUNXI_FUNCTION(0x0, "gpio_in"),
3554 SUNXI_FUNCTION(0x1, "gpio_out"),
3555 SUNXI_FUNCTION(0x2, "ts1"), /* D7 */
3556 SUNXI_FUNCTION(0x3, "csi1"), /* D7 */
3557 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
3558 SUNXI_FUNCTION(0x5, "csi0")), /* D15 */
3559 /* Hole */
3560 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0,
3561 SUNXI_FUNCTION(0x0, "gpio_in"),
3562 SUNXI_FUNCTION(0x1, "gpio_out"),
3563 SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */
3564 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
3565 SUNXI_FUNCTION_IRQ(0x6, 0), /* EINT0 */
3566 SUNXI_FUNCTION(0x7, "csi1")), /* D0 */
3567 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1,
3568 SUNXI_FUNCTION(0x0, "gpio_in"),
3569 SUNXI_FUNCTION(0x1, "gpio_out"),
3570 SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */
3571 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
3572 SUNXI_FUNCTION_IRQ(0x6, 1), /* EINT1 */
3573 SUNXI_FUNCTION(0x7, "csi1")), /* D1 */
3574 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2,
3575 SUNXI_FUNCTION(0x0, "gpio_in"),
3576 SUNXI_FUNCTION(0x1, "gpio_out"),
3577 SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */
3578 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
3579 SUNXI_FUNCTION_IRQ(0x6, 2), /* EINT2 */
3580 SUNXI_FUNCTION(0x7, "csi1")), /* D2 */
3581 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3,
3582 SUNXI_FUNCTION(0x0, "gpio_in"),
3583 SUNXI_FUNCTION(0x1, "gpio_out"),
3584 SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */
3585 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
3586 SUNXI_FUNCTION_IRQ(0x6, 3), /* EINT3 */
3587 SUNXI_FUNCTION(0x7, "csi1")), /* D3 */
3588 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4,
3589 SUNXI_FUNCTION(0x0, "gpio_in"),
3590 SUNXI_FUNCTION(0x1, "gpio_out"),
3591 SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */
3592 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
3593 SUNXI_FUNCTION_IRQ(0x6, 4), /* EINT4 */
3594 SUNXI_FUNCTION(0x7, "csi1")), /* D4 */
3595 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5,
3596 SUNXI_FUNCTION(0x0, "gpio_in"),
3597 SUNXI_FUNCTION(0x1, "gpio_out"),
3598 SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */
3599 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
3600 SUNXI_FUNCTION_IRQ(0x6, 5), /* EINT5 */
3601 SUNXI_FUNCTION(0x7, "csi1")), /* D5 */
3602 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6,
3603 SUNXI_FUNCTION(0x0, "gpio_in"),
3604 SUNXI_FUNCTION(0x1, "gpio_out"),
3605 SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */
3606 SUNXI_FUNCTION(0x4, "uart5"), /* TX */
3607 SUNXI_FUNCTION(0x5, "ms"), /* BS */
3608 SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */
3609 SUNXI_FUNCTION(0x7, "csi1")), /* D6 */
3610 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7,
3611 SUNXI_FUNCTION(0x0, "gpio_in"),
3612 SUNXI_FUNCTION(0x1, "gpio_out"),
3613 SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */
3614 SUNXI_FUNCTION(0x4, "uart5"), /* RX */
3615 SUNXI_FUNCTION(0x5, "ms"), /* CLK */
3616 SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */
3617 SUNXI_FUNCTION(0x7, "csi1")), /* D7 */
3618 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8,
3619 SUNXI_FUNCTION(0x0, "gpio_in"),
3620 SUNXI_FUNCTION(0x1, "gpio_out"),
3621 SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */
3622 SUNXI_FUNCTION(0x3, "emac"), /* ERXD3 */
3623 SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */
3624 SUNXI_FUNCTION(0x5, "ms"), /* D0 */
3625 SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */
3626 SUNXI_FUNCTION(0x7, "csi1")), /* D8 */
3627 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9,
3628 SUNXI_FUNCTION(0x0, "gpio_in"),
3629 SUNXI_FUNCTION(0x1, "gpio_out"),
3630 SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */
3631 SUNXI_FUNCTION(0x3, "emac"), /* ERXD2 */
3632 SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */
3633 SUNXI_FUNCTION(0x5, "ms"), /* D1 */
3634 SUNXI_FUNCTION_IRQ(0x6, 9), /* EINT9 */
3635 SUNXI_FUNCTION(0x7, "csi1")), /* D9 */
3636 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10,
3637 SUNXI_FUNCTION(0x0, "gpio_in"),
3638 SUNXI_FUNCTION(0x1, "gpio_out"),
3639 SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */
3640 SUNXI_FUNCTION(0x3, "emac"), /* ERXD1 */
3641 SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */
3642 SUNXI_FUNCTION(0x5, "ms"), /* D2 */
3643 SUNXI_FUNCTION_IRQ(0x6, 10), /* EINT10 */
3644 SUNXI_FUNCTION(0x7, "csi1")), /* D10 */
3645 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11,
3646 SUNXI_FUNCTION(0x0, "gpio_in"),
3647 SUNXI_FUNCTION(0x1, "gpio_out"),
3648 SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */
3649 SUNXI_FUNCTION(0x3, "emac"), /* ERXD0 */
3650 SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */
3651 SUNXI_FUNCTION(0x5, "ms"), /* D3 */
3652 SUNXI_FUNCTION_IRQ(0x6, 11), /* EINT11 */
3653 SUNXI_FUNCTION(0x7, "csi1")), /* D11 */
3654 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12,
3655 SUNXI_FUNCTION(0x0, "gpio_in"),
3656 SUNXI_FUNCTION(0x1, "gpio_out"),
3657 SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */
3658 SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */
3659 SUNXI_FUNCTION_IRQ(0x6, 12), /* EINT12 */
3660 SUNXI_FUNCTION(0x7, "csi1")), /* D12 */
3661 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13,
3662 SUNXI_FUNCTION(0x0, "gpio_in"),
3663 SUNXI_FUNCTION(0x1, "gpio_out"),
3664 SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */
3665 SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */
3666 SUNXI_FUNCTION(0x5, "sim"), /* RST */
3667 SUNXI_FUNCTION_IRQ(0x6, 13), /* EINT13 */
3668 SUNXI_FUNCTION(0x7, "csi1")), /* D13 */
3669 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14,
3670 SUNXI_FUNCTION(0x0, "gpio_in"),
3671 SUNXI_FUNCTION(0x1, "gpio_out"),
3672 SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */
3673 SUNXI_FUNCTION(0x3, "emac"), /* ETXD3 */
3674 SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */
3675 SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */
3676 SUNXI_FUNCTION_IRQ(0x6, 14), /* EINT14 */
3677 SUNXI_FUNCTION(0x7, "csi1")), /* D14 */
3678 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15,
3679 SUNXI_FUNCTION(0x0, "gpio_in"),
3680 SUNXI_FUNCTION(0x1, "gpio_out"),
3681 SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */
3682 SUNXI_FUNCTION(0x3, "emac"), /* ETXD3 */
3683 SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */
3684 SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */
3685 SUNXI_FUNCTION_IRQ(0x6, 15), /* EINT15 */
3686 SUNXI_FUNCTION(0x7, "csi1")), /* D15 */
3687 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16,
3688 SUNXI_FUNCTION(0x0, "gpio_in"),
3689 SUNXI_FUNCTION(0x1, "gpio_out"),
3690 SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */
3691 SUNXI_FUNCTION(0x3, "emac"), /* ETXD2 */
3692 SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */
3693 SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */
3694 SUNXI_FUNCTION(0x7, "csi1")), /* D16 */
3695 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17,
3696 SUNXI_FUNCTION(0x0, "gpio_in"),
3697 SUNXI_FUNCTION(0x1, "gpio_out"),
3698 SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */
3699 SUNXI_FUNCTION(0x3, "emac"), /* ETXD1 */
3700 SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */
3701 SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */
3702 SUNXI_FUNCTION_IRQ(0x6, 17), /* EINT17 */
3703 SUNXI_FUNCTION(0x7, "csi1")), /* D17 */
3704 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18,
3705 SUNXI_FUNCTION(0x0, "gpio_in"),
3706 SUNXI_FUNCTION(0x1, "gpio_out"),
3707 SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */
3708 SUNXI_FUNCTION(0x3, "emac"), /* ETXD0 */
3709 SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */
3710 SUNXI_FUNCTION(0x5, "sim"), /* SCK */
3711 SUNXI_FUNCTION_IRQ(0x6, 18), /* EINT18 */
3712 SUNXI_FUNCTION(0x7, "csi1")), /* D18 */
3713 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19,
3714 SUNXI_FUNCTION(0x0, "gpio_in"),
3715 SUNXI_FUNCTION(0x1, "gpio_out"),
3716 SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */
3717 SUNXI_FUNCTION(0x3, "emac"), /* ERXERR */
3718 SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */
3719 SUNXI_FUNCTION(0x5, "sim"), /* SDA */
3720 SUNXI_FUNCTION_IRQ(0x6, 19), /* EINT19 */
3721 SUNXI_FUNCTION(0x7, "csi1")), /* D19 */
3722 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20,
3723 SUNXI_FUNCTION(0x0, "gpio_in"),
3724 SUNXI_FUNCTION(0x1, "gpio_out"),
3725 SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */
3726 SUNXI_FUNCTION(0x3, "emac"), /* ERXDV */
3727 SUNXI_FUNCTION(0x4, "can"), /* TX */
3728 SUNXI_FUNCTION_IRQ(0x6, 20), /* EINT20 */
3729 SUNXI_FUNCTION(0x7, "csi1")), /* D20 */
3730 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21,
3731 SUNXI_FUNCTION(0x0, "gpio_in"),
3732 SUNXI_FUNCTION(0x1, "gpio_out"),
3733 SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */
3734 SUNXI_FUNCTION(0x3, "emac"), /* EMDC */
3735 SUNXI_FUNCTION(0x4, "can"), /* RX */
3736 SUNXI_FUNCTION_IRQ(0x6, 21), /* EINT21 */
3737 SUNXI_FUNCTION(0x7, "csi1")), /* D21 */
3738 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22,
3739 SUNXI_FUNCTION(0x0, "gpio_in"),
3740 SUNXI_FUNCTION(0x1, "gpio_out"),
3741 SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */
3742 SUNXI_FUNCTION(0x3, "emac"), /* EMDIO */
3743 SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */
3744 SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */
3745 SUNXI_FUNCTION(0x7, "csi1")), /* D22 */
3746 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23,
3747 SUNXI_FUNCTION(0x0, "gpio_in"),
3748 SUNXI_FUNCTION(0x1, "gpio_out"),
3749 SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */
3750 SUNXI_FUNCTION(0x3, "emac"), /* ETXEN */
3751 SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */
3752 SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */
3753 SUNXI_FUNCTION(0x7, "csi1")), /* D23 */
3754 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24,
3755 SUNXI_FUNCTION(0x0, "gpio_in"),
3756 SUNXI_FUNCTION(0x1, "gpio_out"),
3757 SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */
3758 SUNXI_FUNCTION(0x3, "emac"), /* ETXCK */
3759 SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */
3760 SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */
3761 SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */
3762 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25,
3763 SUNXI_FUNCTION(0x0, "gpio_in"),
3764 SUNXI_FUNCTION(0x1, "gpio_out"),
3765 SUNXI_FUNCTION(0x2, "lcd1"), /* DE */
3766 SUNXI_FUNCTION(0x3, "emac"), /* ECRS */
3767 SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */
3768 SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */
3769 SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */
3770 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26,
3771 SUNXI_FUNCTION(0x0, "gpio_in"),
3772 SUNXI_FUNCTION(0x1, "gpio_out"),
3773 SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */
3774 SUNXI_FUNCTION(0x3, "emac"), /* ECOL */
3775 SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */
3776 SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */
3777 SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */
3778 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27,
3779 SUNXI_FUNCTION(0x0, "gpio_in"),
3780 SUNXI_FUNCTION(0x1, "gpio_out"),
3781 SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */
3782 SUNXI_FUNCTION(0x3, "emac"), /* ETXERR */
3783 SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */
3784 SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */
3785 SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */
3786 /* Hole */
3787 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0,
3788 SUNXI_FUNCTION(0x0, "gpio_in"),
3789 SUNXI_FUNCTION(0x1, "gpio_out"),
3790 SUNXI_FUNCTION(0x3, "i2c3")), /* SCK */
3791 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI1,
3792 SUNXI_FUNCTION(0x0, "gpio_in"),
3793 SUNXI_FUNCTION(0x1, "gpio_out"),
3794 SUNXI_FUNCTION(0x3, "i2c3")), /* SDA */
3795 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI2,
3796 SUNXI_FUNCTION(0x0, "gpio_in"),
3797 SUNXI_FUNCTION(0x1, "gpio_out"),
3798 SUNXI_FUNCTION(0x3, "i2c4")), /* SCK */
3799 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3,
3800 SUNXI_FUNCTION(0x0, "gpio_in"),
3801 SUNXI_FUNCTION(0x1, "gpio_out"),
3802 SUNXI_FUNCTION(0x2, "pwm"), /* PWM1 */
3803 SUNXI_FUNCTION(0x3, "i2c4")), /* SDA */
3804 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4,
3805 SUNXI_FUNCTION(0x0, "gpio_in"),
3806 SUNXI_FUNCTION(0x1, "gpio_out"),
3807 SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */
3808 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5,
3809 SUNXI_FUNCTION(0x0, "gpio_in"),
3810 SUNXI_FUNCTION(0x1, "gpio_out"),
3811 SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */
3812 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6,
3813 SUNXI_FUNCTION(0x0, "gpio_in"),
3814 SUNXI_FUNCTION(0x1, "gpio_out"),
3815 SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */
3816 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7,
3817 SUNXI_FUNCTION(0x0, "gpio_in"),
3818 SUNXI_FUNCTION(0x1, "gpio_out"),
3819 SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */
3820 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8,
3821 SUNXI_FUNCTION(0x0, "gpio_in"),
3822 SUNXI_FUNCTION(0x1, "gpio_out"),
3823 SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */
3824 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9,
3825 SUNXI_FUNCTION(0x0, "gpio_in"),
3826 SUNXI_FUNCTION(0x1, "gpio_out"),
3827 SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */
3828 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10,
3829 SUNXI_FUNCTION(0x0, "gpio_in"),
3830 SUNXI_FUNCTION(0x1, "gpio_out"),
3831 SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
3832 SUNXI_FUNCTION(0x3, "uart5"), /* TX */
3833 SUNXI_FUNCTION_IRQ(0x5, 22)), /* EINT22 */
3834 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11,
3835 SUNXI_FUNCTION(0x0, "gpio_in"),
3836 SUNXI_FUNCTION(0x1, "gpio_out"),
3837 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
3838 SUNXI_FUNCTION(0x3, "uart5"), /* RX */
3839 SUNXI_FUNCTION_IRQ(0x5, 23)), /* EINT23 */
3840 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12,
3841 SUNXI_FUNCTION(0x0, "gpio_in"),
3842 SUNXI_FUNCTION(0x1, "gpio_out"),
3843 SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
3844 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
3845 SUNXI_FUNCTION(0x4, "clk_out_a"), /* CLK_OUT_A */
3846 SUNXI_FUNCTION_IRQ(0x5, 24)), /* EINT24 */
3847 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13,
3848 SUNXI_FUNCTION(0x0, "gpio_in"),
3849 SUNXI_FUNCTION(0x1, "gpio_out"),
3850 SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
3851 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
3852 SUNXI_FUNCTION(0x4, "clk_out_b"), /* CLK_OUT_B */
3853 SUNXI_FUNCTION_IRQ(0x5, 25)), /* EINT25 */
3854 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14,
3855 SUNXI_FUNCTION(0x0, "gpio_in"),
3856 SUNXI_FUNCTION(0x1, "gpio_out"),
3857 SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
3858 SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
3859 SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */
3860 SUNXI_FUNCTION_IRQ(0x5, 26)), /* EINT26 */
3861 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15,
3862 SUNXI_FUNCTION(0x0, "gpio_in"),
3863 SUNXI_FUNCTION(0x1, "gpio_out"),
3864 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
3865 SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
3866 SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */
3867 SUNXI_FUNCTION_IRQ(0x5, 27)), /* EINT27 */
3868 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16,
3869 SUNXI_FUNCTION(0x0, "gpio_in"),
3870 SUNXI_FUNCTION(0x1, "gpio_out"),
3871 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
3872 SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
3873 SUNXI_FUNCTION_IRQ(0x5, 28)), /* EINT28 */
3874 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17,
3875 SUNXI_FUNCTION(0x0, "gpio_in"),
3876 SUNXI_FUNCTION(0x1, "gpio_out"),
3877 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
3878 SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
3879 SUNXI_FUNCTION_IRQ(0x5, 29)), /* EINT29 */
3880 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18,
3881 SUNXI_FUNCTION(0x0, "gpio_in"),
3882 SUNXI_FUNCTION(0x1, "gpio_out"),
3883 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
3884 SUNXI_FUNCTION(0x3, "uart2"), /* TX */
3885 SUNXI_FUNCTION_IRQ(0x5, 30)), /* EINT30 */
3886 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19,
3887 SUNXI_FUNCTION(0x0, "gpio_in"),
3888 SUNXI_FUNCTION(0x1, "gpio_out"),
3889 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
3890 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
3891 SUNXI_FUNCTION_IRQ(0x5, 31)), /* EINT31 */
3892 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20,
3893 SUNXI_FUNCTION(0x0, "gpio_in"),
3894 SUNXI_FUNCTION(0x1, "gpio_out"),
3895 SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */
3896 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
3897 SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */
3898 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21,
3899 SUNXI_FUNCTION(0x0, "gpio_in"),
3900 SUNXI_FUNCTION(0x1, "gpio_out"),
3901 SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */
3902 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
3903 SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */
3904};
3905
3906static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = {
3907 .pins = sun4i_a10_pins,
3908 .npins = ARRAY_SIZE(sun4i_a10_pins),
3909};
3910
3911static const struct sunxi_pinctrl_desc sun5i_a10s_pinctrl_data = {
3912 .pins = sun5i_a10s_pins,
3913 .npins = ARRAY_SIZE(sun5i_a10s_pins),
3914};
3915
3916static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = {
3917 .pins = sun5i_a13_pins,
3918 .npins = ARRAY_SIZE(sun5i_a13_pins),
3919};
3920
3921static const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_data = {
3922 .pins = sun6i_a31_pins,
3923 .npins = ARRAY_SIZE(sun6i_a31_pins),
3924};
3925
3926static const struct sunxi_pinctrl_desc sun6i_a31_r_pinctrl_data = {
3927 .pins = sun6i_a31_r_pins,
3928 .npins = ARRAY_SIZE(sun6i_a31_r_pins),
3929 .pin_base = PL_BASE,
3930};
3931
3932static const struct sunxi_pinctrl_desc sun7i_a20_pinctrl_data = {
3933 .pins = sun7i_a20_pins,
3934 .npins = ARRAY_SIZE(sun7i_a20_pins),
3935};
3936
3937#endif /* __PINCTRL_SUNXI_PINS_H */
diff --git a/drivers/pinctrl/pinctrl-sunxi.h b/drivers/pinctrl/pinctrl-sunxi.h
deleted file mode 100644
index 35d15b229a70..000000000000
--- a/drivers/pinctrl/pinctrl-sunxi.h
+++ /dev/null
@@ -1,617 +0,0 @@
1/*
2 * Allwinner A1X SoCs pinctrl driver.
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#ifndef __PINCTRL_SUNXI_H
14#define __PINCTRL_SUNXI_H
15
16#include <linux/kernel.h>
17#include <linux/spinlock.h>
18
19#define PA_BASE 0
20#define PB_BASE 32
21#define PC_BASE 64
22#define PD_BASE 96
23#define PE_BASE 128
24#define PF_BASE 160
25#define PG_BASE 192
26#define PH_BASE 224
27#define PI_BASE 256
28#define PL_BASE 352
29#define PM_BASE 384
30
31#define SUNXI_PINCTRL_PIN_PA0 PINCTRL_PIN(PA_BASE + 0, "PA0")
32#define SUNXI_PINCTRL_PIN_PA1 PINCTRL_PIN(PA_BASE + 1, "PA1")
33#define SUNXI_PINCTRL_PIN_PA2 PINCTRL_PIN(PA_BASE + 2, "PA2")
34#define SUNXI_PINCTRL_PIN_PA3 PINCTRL_PIN(PA_BASE + 3, "PA3")
35#define SUNXI_PINCTRL_PIN_PA4 PINCTRL_PIN(PA_BASE + 4, "PA4")
36#define SUNXI_PINCTRL_PIN_PA5 PINCTRL_PIN(PA_BASE + 5, "PA5")
37#define SUNXI_PINCTRL_PIN_PA6 PINCTRL_PIN(PA_BASE + 6, "PA6")
38#define SUNXI_PINCTRL_PIN_PA7 PINCTRL_PIN(PA_BASE + 7, "PA7")
39#define SUNXI_PINCTRL_PIN_PA8 PINCTRL_PIN(PA_BASE + 8, "PA8")
40#define SUNXI_PINCTRL_PIN_PA9 PINCTRL_PIN(PA_BASE + 9, "PA9")
41#define SUNXI_PINCTRL_PIN_PA10 PINCTRL_PIN(PA_BASE + 10, "PA10")
42#define SUNXI_PINCTRL_PIN_PA11 PINCTRL_PIN(PA_BASE + 11, "PA11")
43#define SUNXI_PINCTRL_PIN_PA12 PINCTRL_PIN(PA_BASE + 12, "PA12")
44#define SUNXI_PINCTRL_PIN_PA13 PINCTRL_PIN(PA_BASE + 13, "PA13")
45#define SUNXI_PINCTRL_PIN_PA14 PINCTRL_PIN(PA_BASE + 14, "PA14")
46#define SUNXI_PINCTRL_PIN_PA15 PINCTRL_PIN(PA_BASE + 15, "PA15")
47#define SUNXI_PINCTRL_PIN_PA16 PINCTRL_PIN(PA_BASE + 16, "PA16")
48#define SUNXI_PINCTRL_PIN_PA17 PINCTRL_PIN(PA_BASE + 17, "PA17")
49#define SUNXI_PINCTRL_PIN_PA18 PINCTRL_PIN(PA_BASE + 18, "PA18")
50#define SUNXI_PINCTRL_PIN_PA19 PINCTRL_PIN(PA_BASE + 19, "PA19")
51#define SUNXI_PINCTRL_PIN_PA20 PINCTRL_PIN(PA_BASE + 20, "PA20")
52#define SUNXI_PINCTRL_PIN_PA21 PINCTRL_PIN(PA_BASE + 21, "PA21")
53#define SUNXI_PINCTRL_PIN_PA22 PINCTRL_PIN(PA_BASE + 22, "PA22")
54#define SUNXI_PINCTRL_PIN_PA23 PINCTRL_PIN(PA_BASE + 23, "PA23")
55#define SUNXI_PINCTRL_PIN_PA24 PINCTRL_PIN(PA_BASE + 24, "PA24")
56#define SUNXI_PINCTRL_PIN_PA25 PINCTRL_PIN(PA_BASE + 25, "PA25")
57#define SUNXI_PINCTRL_PIN_PA26 PINCTRL_PIN(PA_BASE + 26, "PA26")
58#define SUNXI_PINCTRL_PIN_PA27 PINCTRL_PIN(PA_BASE + 27, "PA27")
59#define SUNXI_PINCTRL_PIN_PA28 PINCTRL_PIN(PA_BASE + 28, "PA28")
60#define SUNXI_PINCTRL_PIN_PA29 PINCTRL_PIN(PA_BASE + 29, "PA29")
61#define SUNXI_PINCTRL_PIN_PA30 PINCTRL_PIN(PA_BASE + 30, "PA30")
62#define SUNXI_PINCTRL_PIN_PA31 PINCTRL_PIN(PA_BASE + 31, "PA31")
63
64#define SUNXI_PINCTRL_PIN_PB0 PINCTRL_PIN(PB_BASE + 0, "PB0")
65#define SUNXI_PINCTRL_PIN_PB1 PINCTRL_PIN(PB_BASE + 1, "PB1")
66#define SUNXI_PINCTRL_PIN_PB2 PINCTRL_PIN(PB_BASE + 2, "PB2")
67#define SUNXI_PINCTRL_PIN_PB3 PINCTRL_PIN(PB_BASE + 3, "PB3")
68#define SUNXI_PINCTRL_PIN_PB4 PINCTRL_PIN(PB_BASE + 4, "PB4")
69#define SUNXI_PINCTRL_PIN_PB5 PINCTRL_PIN(PB_BASE + 5, "PB5")
70#define SUNXI_PINCTRL_PIN_PB6 PINCTRL_PIN(PB_BASE + 6, "PB6")
71#define SUNXI_PINCTRL_PIN_PB7 PINCTRL_PIN(PB_BASE + 7, "PB7")
72#define SUNXI_PINCTRL_PIN_PB8 PINCTRL_PIN(PB_BASE + 8, "PB8")
73#define SUNXI_PINCTRL_PIN_PB9 PINCTRL_PIN(PB_BASE + 9, "PB9")
74#define SUNXI_PINCTRL_PIN_PB10 PINCTRL_PIN(PB_BASE + 10, "PB10")
75#define SUNXI_PINCTRL_PIN_PB11 PINCTRL_PIN(PB_BASE + 11, "PB11")
76#define SUNXI_PINCTRL_PIN_PB12 PINCTRL_PIN(PB_BASE + 12, "PB12")
77#define SUNXI_PINCTRL_PIN_PB13 PINCTRL_PIN(PB_BASE + 13, "PB13")
78#define SUNXI_PINCTRL_PIN_PB14 PINCTRL_PIN(PB_BASE + 14, "PB14")
79#define SUNXI_PINCTRL_PIN_PB15 PINCTRL_PIN(PB_BASE + 15, "PB15")
80#define SUNXI_PINCTRL_PIN_PB16 PINCTRL_PIN(PB_BASE + 16, "PB16")
81#define SUNXI_PINCTRL_PIN_PB17 PINCTRL_PIN(PB_BASE + 17, "PB17")
82#define SUNXI_PINCTRL_PIN_PB18 PINCTRL_PIN(PB_BASE + 18, "PB18")
83#define SUNXI_PINCTRL_PIN_PB19 PINCTRL_PIN(PB_BASE + 19, "PB19")
84#define SUNXI_PINCTRL_PIN_PB20 PINCTRL_PIN(PB_BASE + 20, "PB20")
85#define SUNXI_PINCTRL_PIN_PB21 PINCTRL_PIN(PB_BASE + 21, "PB21")
86#define SUNXI_PINCTRL_PIN_PB22 PINCTRL_PIN(PB_BASE + 22, "PB22")
87#define SUNXI_PINCTRL_PIN_PB23 PINCTRL_PIN(PB_BASE + 23, "PB23")
88#define SUNXI_PINCTRL_PIN_PB24 PINCTRL_PIN(PB_BASE + 24, "PB24")
89#define SUNXI_PINCTRL_PIN_PB25 PINCTRL_PIN(PB_BASE + 25, "PB25")
90#define SUNXI_PINCTRL_PIN_PB26 PINCTRL_PIN(PB_BASE + 26, "PB26")
91#define SUNXI_PINCTRL_PIN_PB27 PINCTRL_PIN(PB_BASE + 27, "PB27")
92#define SUNXI_PINCTRL_PIN_PB28 PINCTRL_PIN(PB_BASE + 28, "PB28")
93#define SUNXI_PINCTRL_PIN_PB29 PINCTRL_PIN(PB_BASE + 29, "PB29")
94#define SUNXI_PINCTRL_PIN_PB30 PINCTRL_PIN(PB_BASE + 30, "PB30")
95#define SUNXI_PINCTRL_PIN_PB31 PINCTRL_PIN(PB_BASE + 31, "PB31")
96
97#define SUNXI_PINCTRL_PIN_PC0 PINCTRL_PIN(PC_BASE + 0, "PC0")
98#define SUNXI_PINCTRL_PIN_PC1 PINCTRL_PIN(PC_BASE + 1, "PC1")
99#define SUNXI_PINCTRL_PIN_PC2 PINCTRL_PIN(PC_BASE + 2, "PC2")
100#define SUNXI_PINCTRL_PIN_PC3 PINCTRL_PIN(PC_BASE + 3, "PC3")
101#define SUNXI_PINCTRL_PIN_PC4 PINCTRL_PIN(PC_BASE + 4, "PC4")
102#define SUNXI_PINCTRL_PIN_PC5 PINCTRL_PIN(PC_BASE + 5, "PC5")
103#define SUNXI_PINCTRL_PIN_PC6 PINCTRL_PIN(PC_BASE + 6, "PC6")
104#define SUNXI_PINCTRL_PIN_PC7 PINCTRL_PIN(PC_BASE + 7, "PC7")
105#define SUNXI_PINCTRL_PIN_PC8 PINCTRL_PIN(PC_BASE + 8, "PC8")
106#define SUNXI_PINCTRL_PIN_PC9 PINCTRL_PIN(PC_BASE + 9, "PC9")
107#define SUNXI_PINCTRL_PIN_PC10 PINCTRL_PIN(PC_BASE + 10, "PC10")
108#define SUNXI_PINCTRL_PIN_PC11 PINCTRL_PIN(PC_BASE + 11, "PC11")
109#define SUNXI_PINCTRL_PIN_PC12 PINCTRL_PIN(PC_BASE + 12, "PC12")
110#define SUNXI_PINCTRL_PIN_PC13 PINCTRL_PIN(PC_BASE + 13, "PC13")
111#define SUNXI_PINCTRL_PIN_PC14 PINCTRL_PIN(PC_BASE + 14, "PC14")
112#define SUNXI_PINCTRL_PIN_PC15 PINCTRL_PIN(PC_BASE + 15, "PC15")
113#define SUNXI_PINCTRL_PIN_PC16 PINCTRL_PIN(PC_BASE + 16, "PC16")
114#define SUNXI_PINCTRL_PIN_PC17 PINCTRL_PIN(PC_BASE + 17, "PC17")
115#define SUNXI_PINCTRL_PIN_PC18 PINCTRL_PIN(PC_BASE + 18, "PC18")
116#define SUNXI_PINCTRL_PIN_PC19 PINCTRL_PIN(PC_BASE + 19, "PC19")
117#define SUNXI_PINCTRL_PIN_PC20 PINCTRL_PIN(PC_BASE + 20, "PC20")
118#define SUNXI_PINCTRL_PIN_PC21 PINCTRL_PIN(PC_BASE + 21, "PC21")
119#define SUNXI_PINCTRL_PIN_PC22 PINCTRL_PIN(PC_BASE + 22, "PC22")
120#define SUNXI_PINCTRL_PIN_PC23 PINCTRL_PIN(PC_BASE + 23, "PC23")
121#define SUNXI_PINCTRL_PIN_PC24 PINCTRL_PIN(PC_BASE + 24, "PC24")
122#define SUNXI_PINCTRL_PIN_PC25 PINCTRL_PIN(PC_BASE + 25, "PC25")
123#define SUNXI_PINCTRL_PIN_PC26 PINCTRL_PIN(PC_BASE + 26, "PC26")
124#define SUNXI_PINCTRL_PIN_PC27 PINCTRL_PIN(PC_BASE + 27, "PC27")
125#define SUNXI_PINCTRL_PIN_PC28 PINCTRL_PIN(PC_BASE + 28, "PC28")
126#define SUNXI_PINCTRL_PIN_PC29 PINCTRL_PIN(PC_BASE + 29, "PC29")
127#define SUNXI_PINCTRL_PIN_PC30 PINCTRL_PIN(PC_BASE + 30, "PC30")
128#define SUNXI_PINCTRL_PIN_PC31 PINCTRL_PIN(PC_BASE + 31, "PC31")
129
130#define SUNXI_PINCTRL_PIN_PD0 PINCTRL_PIN(PD_BASE + 0, "PD0")
131#define SUNXI_PINCTRL_PIN_PD1 PINCTRL_PIN(PD_BASE + 1, "PD1")
132#define SUNXI_PINCTRL_PIN_PD2 PINCTRL_PIN(PD_BASE + 2, "PD2")
133#define SUNXI_PINCTRL_PIN_PD3 PINCTRL_PIN(PD_BASE + 3, "PD3")
134#define SUNXI_PINCTRL_PIN_PD4 PINCTRL_PIN(PD_BASE + 4, "PD4")
135#define SUNXI_PINCTRL_PIN_PD5 PINCTRL_PIN(PD_BASE + 5, "PD5")
136#define SUNXI_PINCTRL_PIN_PD6 PINCTRL_PIN(PD_BASE + 6, "PD6")
137#define SUNXI_PINCTRL_PIN_PD7 PINCTRL_PIN(PD_BASE + 7, "PD7")
138#define SUNXI_PINCTRL_PIN_PD8 PINCTRL_PIN(PD_BASE + 8, "PD8")
139#define SUNXI_PINCTRL_PIN_PD9 PINCTRL_PIN(PD_BASE + 9, "PD9")
140#define SUNXI_PINCTRL_PIN_PD10 PINCTRL_PIN(PD_BASE + 10, "PD10")
141#define SUNXI_PINCTRL_PIN_PD11 PINCTRL_PIN(PD_BASE + 11, "PD11")
142#define SUNXI_PINCTRL_PIN_PD12 PINCTRL_PIN(PD_BASE + 12, "PD12")
143#define SUNXI_PINCTRL_PIN_PD13 PINCTRL_PIN(PD_BASE + 13, "PD13")
144#define SUNXI_PINCTRL_PIN_PD14 PINCTRL_PIN(PD_BASE + 14, "PD14")
145#define SUNXI_PINCTRL_PIN_PD15 PINCTRL_PIN(PD_BASE + 15, "PD15")
146#define SUNXI_PINCTRL_PIN_PD16 PINCTRL_PIN(PD_BASE + 16, "PD16")
147#define SUNXI_PINCTRL_PIN_PD17 PINCTRL_PIN(PD_BASE + 17, "PD17")
148#define SUNXI_PINCTRL_PIN_PD18 PINCTRL_PIN(PD_BASE + 18, "PD18")
149#define SUNXI_PINCTRL_PIN_PD19 PINCTRL_PIN(PD_BASE + 19, "PD19")
150#define SUNXI_PINCTRL_PIN_PD20 PINCTRL_PIN(PD_BASE + 20, "PD20")
151#define SUNXI_PINCTRL_PIN_PD21 PINCTRL_PIN(PD_BASE + 21, "PD21")
152#define SUNXI_PINCTRL_PIN_PD22 PINCTRL_PIN(PD_BASE + 22, "PD22")
153#define SUNXI_PINCTRL_PIN_PD23 PINCTRL_PIN(PD_BASE + 23, "PD23")
154#define SUNXI_PINCTRL_PIN_PD24 PINCTRL_PIN(PD_BASE + 24, "PD24")
155#define SUNXI_PINCTRL_PIN_PD25 PINCTRL_PIN(PD_BASE + 25, "PD25")
156#define SUNXI_PINCTRL_PIN_PD26 PINCTRL_PIN(PD_BASE + 26, "PD26")
157#define SUNXI_PINCTRL_PIN_PD27 PINCTRL_PIN(PD_BASE + 27, "PD27")
158#define SUNXI_PINCTRL_PIN_PD28 PINCTRL_PIN(PD_BASE + 28, "PD28")
159#define SUNXI_PINCTRL_PIN_PD29 PINCTRL_PIN(PD_BASE + 29, "PD29")
160#define SUNXI_PINCTRL_PIN_PD30 PINCTRL_PIN(PD_BASE + 30, "PD30")
161#define SUNXI_PINCTRL_PIN_PD31 PINCTRL_PIN(PD_BASE + 31, "PD31")
162
163#define SUNXI_PINCTRL_PIN_PE0 PINCTRL_PIN(PE_BASE + 0, "PE0")
164#define SUNXI_PINCTRL_PIN_PE1 PINCTRL_PIN(PE_BASE + 1, "PE1")
165#define SUNXI_PINCTRL_PIN_PE2 PINCTRL_PIN(PE_BASE + 2, "PE2")
166#define SUNXI_PINCTRL_PIN_PE3 PINCTRL_PIN(PE_BASE + 3, "PE3")
167#define SUNXI_PINCTRL_PIN_PE4 PINCTRL_PIN(PE_BASE + 4, "PE4")
168#define SUNXI_PINCTRL_PIN_PE5 PINCTRL_PIN(PE_BASE + 5, "PE5")
169#define SUNXI_PINCTRL_PIN_PE6 PINCTRL_PIN(PE_BASE + 6, "PE6")
170#define SUNXI_PINCTRL_PIN_PE7 PINCTRL_PIN(PE_BASE + 7, "PE7")
171#define SUNXI_PINCTRL_PIN_PE8 PINCTRL_PIN(PE_BASE + 8, "PE8")
172#define SUNXI_PINCTRL_PIN_PE9 PINCTRL_PIN(PE_BASE + 9, "PE9")
173#define SUNXI_PINCTRL_PIN_PE10 PINCTRL_PIN(PE_BASE + 10, "PE10")
174#define SUNXI_PINCTRL_PIN_PE11 PINCTRL_PIN(PE_BASE + 11, "PE11")
175#define SUNXI_PINCTRL_PIN_PE12 PINCTRL_PIN(PE_BASE + 12, "PE12")
176#define SUNXI_PINCTRL_PIN_PE13 PINCTRL_PIN(PE_BASE + 13, "PE13")
177#define SUNXI_PINCTRL_PIN_PE14 PINCTRL_PIN(PE_BASE + 14, "PE14")
178#define SUNXI_PINCTRL_PIN_PE15 PINCTRL_PIN(PE_BASE + 15, "PE15")
179#define SUNXI_PINCTRL_PIN_PE16 PINCTRL_PIN(PE_BASE + 16, "PE16")
180#define SUNXI_PINCTRL_PIN_PE17 PINCTRL_PIN(PE_BASE + 17, "PE17")
181#define SUNXI_PINCTRL_PIN_PE18 PINCTRL_PIN(PE_BASE + 18, "PE18")
182#define SUNXI_PINCTRL_PIN_PE19 PINCTRL_PIN(PE_BASE + 19, "PE19")
183#define SUNXI_PINCTRL_PIN_PE20 PINCTRL_PIN(PE_BASE + 20, "PE20")
184#define SUNXI_PINCTRL_PIN_PE21 PINCTRL_PIN(PE_BASE + 21, "PE21")
185#define SUNXI_PINCTRL_PIN_PE22 PINCTRL_PIN(PE_BASE + 22, "PE22")
186#define SUNXI_PINCTRL_PIN_PE23 PINCTRL_PIN(PE_BASE + 23, "PE23")
187#define SUNXI_PINCTRL_PIN_PE24 PINCTRL_PIN(PE_BASE + 24, "PE24")
188#define SUNXI_PINCTRL_PIN_PE25 PINCTRL_PIN(PE_BASE + 25, "PE25")
189#define SUNXI_PINCTRL_PIN_PE26 PINCTRL_PIN(PE_BASE + 26, "PE26")
190#define SUNXI_PINCTRL_PIN_PE27 PINCTRL_PIN(PE_BASE + 27, "PE27")
191#define SUNXI_PINCTRL_PIN_PE28 PINCTRL_PIN(PE_BASE + 28, "PE28")
192#define SUNXI_PINCTRL_PIN_PE29 PINCTRL_PIN(PE_BASE + 29, "PE29")
193#define SUNXI_PINCTRL_PIN_PE30 PINCTRL_PIN(PE_BASE + 30, "PE30")
194#define SUNXI_PINCTRL_PIN_PE31 PINCTRL_PIN(PE_BASE + 31, "PE31")
195
196#define SUNXI_PINCTRL_PIN_PF0 PINCTRL_PIN(PF_BASE + 0, "PF0")
197#define SUNXI_PINCTRL_PIN_PF1 PINCTRL_PIN(PF_BASE + 1, "PF1")
198#define SUNXI_PINCTRL_PIN_PF2 PINCTRL_PIN(PF_BASE + 2, "PF2")
199#define SUNXI_PINCTRL_PIN_PF3 PINCTRL_PIN(PF_BASE + 3, "PF3")
200#define SUNXI_PINCTRL_PIN_PF4 PINCTRL_PIN(PF_BASE + 4, "PF4")
201#define SUNXI_PINCTRL_PIN_PF5 PINCTRL_PIN(PF_BASE + 5, "PF5")
202#define SUNXI_PINCTRL_PIN_PF6 PINCTRL_PIN(PF_BASE + 6, "PF6")
203#define SUNXI_PINCTRL_PIN_PF7 PINCTRL_PIN(PF_BASE + 7, "PF7")
204#define SUNXI_PINCTRL_PIN_PF8 PINCTRL_PIN(PF_BASE + 8, "PF8")
205#define SUNXI_PINCTRL_PIN_PF9 PINCTRL_PIN(PF_BASE + 9, "PF9")
206#define SUNXI_PINCTRL_PIN_PF10 PINCTRL_PIN(PF_BASE + 10, "PF10")
207#define SUNXI_PINCTRL_PIN_PF11 PINCTRL_PIN(PF_BASE + 11, "PF11")
208#define SUNXI_PINCTRL_PIN_PF12 PINCTRL_PIN(PF_BASE + 12, "PF12")
209#define SUNXI_PINCTRL_PIN_PF13 PINCTRL_PIN(PF_BASE + 13, "PF13")
210#define SUNXI_PINCTRL_PIN_PF14 PINCTRL_PIN(PF_BASE + 14, "PF14")
211#define SUNXI_PINCTRL_PIN_PF15 PINCTRL_PIN(PF_BASE + 15, "PF15")
212#define SUNXI_PINCTRL_PIN_PF16 PINCTRL_PIN(PF_BASE + 16, "PF16")
213#define SUNXI_PINCTRL_PIN_PF17 PINCTRL_PIN(PF_BASE + 17, "PF17")
214#define SUNXI_PINCTRL_PIN_PF18 PINCTRL_PIN(PF_BASE + 18, "PF18")
215#define SUNXI_PINCTRL_PIN_PF19 PINCTRL_PIN(PF_BASE + 19, "PF19")
216#define SUNXI_PINCTRL_PIN_PF20 PINCTRL_PIN(PF_BASE + 20, "PF20")
217#define SUNXI_PINCTRL_PIN_PF21 PINCTRL_PIN(PF_BASE + 21, "PF21")
218#define SUNXI_PINCTRL_PIN_PF22 PINCTRL_PIN(PF_BASE + 22, "PF22")
219#define SUNXI_PINCTRL_PIN_PF23 PINCTRL_PIN(PF_BASE + 23, "PF23")
220#define SUNXI_PINCTRL_PIN_PF24 PINCTRL_PIN(PF_BASE + 24, "PF24")
221#define SUNXI_PINCTRL_PIN_PF25 PINCTRL_PIN(PF_BASE + 25, "PF25")
222#define SUNXI_PINCTRL_PIN_PF26 PINCTRL_PIN(PF_BASE + 26, "PF26")
223#define SUNXI_PINCTRL_PIN_PF27 PINCTRL_PIN(PF_BASE + 27, "PF27")
224#define SUNXI_PINCTRL_PIN_PF28 PINCTRL_PIN(PF_BASE + 28, "PF28")
225#define SUNXI_PINCTRL_PIN_PF29 PINCTRL_PIN(PF_BASE + 29, "PF29")
226#define SUNXI_PINCTRL_PIN_PF30 PINCTRL_PIN(PF_BASE + 30, "PF30")
227#define SUNXI_PINCTRL_PIN_PF31 PINCTRL_PIN(PF_BASE + 31, "PF31")
228
229#define SUNXI_PINCTRL_PIN_PG0 PINCTRL_PIN(PG_BASE + 0, "PG0")
230#define SUNXI_PINCTRL_PIN_PG1 PINCTRL_PIN(PG_BASE + 1, "PG1")
231#define SUNXI_PINCTRL_PIN_PG2 PINCTRL_PIN(PG_BASE + 2, "PG2")
232#define SUNXI_PINCTRL_PIN_PG3 PINCTRL_PIN(PG_BASE + 3, "PG3")
233#define SUNXI_PINCTRL_PIN_PG4 PINCTRL_PIN(PG_BASE + 4, "PG4")
234#define SUNXI_PINCTRL_PIN_PG5 PINCTRL_PIN(PG_BASE + 5, "PG5")
235#define SUNXI_PINCTRL_PIN_PG6 PINCTRL_PIN(PG_BASE + 6, "PG6")
236#define SUNXI_PINCTRL_PIN_PG7 PINCTRL_PIN(PG_BASE + 7, "PG7")
237#define SUNXI_PINCTRL_PIN_PG8 PINCTRL_PIN(PG_BASE + 8, "PG8")
238#define SUNXI_PINCTRL_PIN_PG9 PINCTRL_PIN(PG_BASE + 9, "PG9")
239#define SUNXI_PINCTRL_PIN_PG10 PINCTRL_PIN(PG_BASE + 10, "PG10")
240#define SUNXI_PINCTRL_PIN_PG11 PINCTRL_PIN(PG_BASE + 11, "PG11")
241#define SUNXI_PINCTRL_PIN_PG12 PINCTRL_PIN(PG_BASE + 12, "PG12")
242#define SUNXI_PINCTRL_PIN_PG13 PINCTRL_PIN(PG_BASE + 13, "PG13")
243#define SUNXI_PINCTRL_PIN_PG14 PINCTRL_PIN(PG_BASE + 14, "PG14")
244#define SUNXI_PINCTRL_PIN_PG15 PINCTRL_PIN(PG_BASE + 15, "PG15")
245#define SUNXI_PINCTRL_PIN_PG16 PINCTRL_PIN(PG_BASE + 16, "PG16")
246#define SUNXI_PINCTRL_PIN_PG17 PINCTRL_PIN(PG_BASE + 17, "PG17")
247#define SUNXI_PINCTRL_PIN_PG18 PINCTRL_PIN(PG_BASE + 18, "PG18")
248#define SUNXI_PINCTRL_PIN_PG19 PINCTRL_PIN(PG_BASE + 19, "PG19")
249#define SUNXI_PINCTRL_PIN_PG20 PINCTRL_PIN(PG_BASE + 20, "PG20")
250#define SUNXI_PINCTRL_PIN_PG21 PINCTRL_PIN(PG_BASE + 21, "PG21")
251#define SUNXI_PINCTRL_PIN_PG22 PINCTRL_PIN(PG_BASE + 22, "PG22")
252#define SUNXI_PINCTRL_PIN_PG23 PINCTRL_PIN(PG_BASE + 23, "PG23")
253#define SUNXI_PINCTRL_PIN_PG24 PINCTRL_PIN(PG_BASE + 24, "PG24")
254#define SUNXI_PINCTRL_PIN_PG25 PINCTRL_PIN(PG_BASE + 25, "PG25")
255#define SUNXI_PINCTRL_PIN_PG26 PINCTRL_PIN(PG_BASE + 26, "PG26")
256#define SUNXI_PINCTRL_PIN_PG27 PINCTRL_PIN(PG_BASE + 27, "PG27")
257#define SUNXI_PINCTRL_PIN_PG28 PINCTRL_PIN(PG_BASE + 28, "PG28")
258#define SUNXI_PINCTRL_PIN_PG29 PINCTRL_PIN(PG_BASE + 29, "PG29")
259#define SUNXI_PINCTRL_PIN_PG30 PINCTRL_PIN(PG_BASE + 30, "PG30")
260#define SUNXI_PINCTRL_PIN_PG31 PINCTRL_PIN(PG_BASE + 31, "PG31")
261
262#define SUNXI_PINCTRL_PIN_PH0 PINCTRL_PIN(PH_BASE + 0, "PH0")
263#define SUNXI_PINCTRL_PIN_PH1 PINCTRL_PIN(PH_BASE + 1, "PH1")
264#define SUNXI_PINCTRL_PIN_PH2 PINCTRL_PIN(PH_BASE + 2, "PH2")
265#define SUNXI_PINCTRL_PIN_PH3 PINCTRL_PIN(PH_BASE + 3, "PH3")
266#define SUNXI_PINCTRL_PIN_PH4 PINCTRL_PIN(PH_BASE + 4, "PH4")
267#define SUNXI_PINCTRL_PIN_PH5 PINCTRL_PIN(PH_BASE + 5, "PH5")
268#define SUNXI_PINCTRL_PIN_PH6 PINCTRL_PIN(PH_BASE + 6, "PH6")
269#define SUNXI_PINCTRL_PIN_PH7 PINCTRL_PIN(PH_BASE + 7, "PH7")
270#define SUNXI_PINCTRL_PIN_PH8 PINCTRL_PIN(PH_BASE + 8, "PH8")
271#define SUNXI_PINCTRL_PIN_PH9 PINCTRL_PIN(PH_BASE + 9, "PH9")
272#define SUNXI_PINCTRL_PIN_PH10 PINCTRL_PIN(PH_BASE + 10, "PH10")
273#define SUNXI_PINCTRL_PIN_PH11 PINCTRL_PIN(PH_BASE + 11, "PH11")
274#define SUNXI_PINCTRL_PIN_PH12 PINCTRL_PIN(PH_BASE + 12, "PH12")
275#define SUNXI_PINCTRL_PIN_PH13 PINCTRL_PIN(PH_BASE + 13, "PH13")
276#define SUNXI_PINCTRL_PIN_PH14 PINCTRL_PIN(PH_BASE + 14, "PH14")
277#define SUNXI_PINCTRL_PIN_PH15 PINCTRL_PIN(PH_BASE + 15, "PH15")
278#define SUNXI_PINCTRL_PIN_PH16 PINCTRL_PIN(PH_BASE + 16, "PH16")
279#define SUNXI_PINCTRL_PIN_PH17 PINCTRL_PIN(PH_BASE + 17, "PH17")
280#define SUNXI_PINCTRL_PIN_PH18 PINCTRL_PIN(PH_BASE + 18, "PH18")
281#define SUNXI_PINCTRL_PIN_PH19 PINCTRL_PIN(PH_BASE + 19, "PH19")
282#define SUNXI_PINCTRL_PIN_PH20 PINCTRL_PIN(PH_BASE + 20, "PH20")
283#define SUNXI_PINCTRL_PIN_PH21 PINCTRL_PIN(PH_BASE + 21, "PH21")
284#define SUNXI_PINCTRL_PIN_PH22 PINCTRL_PIN(PH_BASE + 22, "PH22")
285#define SUNXI_PINCTRL_PIN_PH23 PINCTRL_PIN(PH_BASE + 23, "PH23")
286#define SUNXI_PINCTRL_PIN_PH24 PINCTRL_PIN(PH_BASE + 24, "PH24")
287#define SUNXI_PINCTRL_PIN_PH25 PINCTRL_PIN(PH_BASE + 25, "PH25")
288#define SUNXI_PINCTRL_PIN_PH26 PINCTRL_PIN(PH_BASE + 26, "PH26")
289#define SUNXI_PINCTRL_PIN_PH27 PINCTRL_PIN(PH_BASE + 27, "PH27")
290#define SUNXI_PINCTRL_PIN_PH28 PINCTRL_PIN(PH_BASE + 28, "PH28")
291#define SUNXI_PINCTRL_PIN_PH29 PINCTRL_PIN(PH_BASE + 29, "PH29")
292#define SUNXI_PINCTRL_PIN_PH30 PINCTRL_PIN(PH_BASE + 30, "PH30")
293#define SUNXI_PINCTRL_PIN_PH31 PINCTRL_PIN(PH_BASE + 31, "PH31")
294
295#define SUNXI_PINCTRL_PIN_PI0 PINCTRL_PIN(PI_BASE + 0, "PI0")
296#define SUNXI_PINCTRL_PIN_PI1 PINCTRL_PIN(PI_BASE + 1, "PI1")
297#define SUNXI_PINCTRL_PIN_PI2 PINCTRL_PIN(PI_BASE + 2, "PI2")
298#define SUNXI_PINCTRL_PIN_PI3 PINCTRL_PIN(PI_BASE + 3, "PI3")
299#define SUNXI_PINCTRL_PIN_PI4 PINCTRL_PIN(PI_BASE + 4, "PI4")
300#define SUNXI_PINCTRL_PIN_PI5 PINCTRL_PIN(PI_BASE + 5, "PI5")
301#define SUNXI_PINCTRL_PIN_PI6 PINCTRL_PIN(PI_BASE + 6, "PI6")
302#define SUNXI_PINCTRL_PIN_PI7 PINCTRL_PIN(PI_BASE + 7, "PI7")
303#define SUNXI_PINCTRL_PIN_PI8 PINCTRL_PIN(PI_BASE + 8, "PI8")
304#define SUNXI_PINCTRL_PIN_PI9 PINCTRL_PIN(PI_BASE + 9, "PI9")
305#define SUNXI_PINCTRL_PIN_PI10 PINCTRL_PIN(PI_BASE + 10, "PI10")
306#define SUNXI_PINCTRL_PIN_PI11 PINCTRL_PIN(PI_BASE + 11, "PI11")
307#define SUNXI_PINCTRL_PIN_PI12 PINCTRL_PIN(PI_BASE + 12, "PI12")
308#define SUNXI_PINCTRL_PIN_PI13 PINCTRL_PIN(PI_BASE + 13, "PI13")
309#define SUNXI_PINCTRL_PIN_PI14 PINCTRL_PIN(PI_BASE + 14, "PI14")
310#define SUNXI_PINCTRL_PIN_PI15 PINCTRL_PIN(PI_BASE + 15, "PI15")
311#define SUNXI_PINCTRL_PIN_PI16 PINCTRL_PIN(PI_BASE + 16, "PI16")
312#define SUNXI_PINCTRL_PIN_PI17 PINCTRL_PIN(PI_BASE + 17, "PI17")
313#define SUNXI_PINCTRL_PIN_PI18 PINCTRL_PIN(PI_BASE + 18, "PI18")
314#define SUNXI_PINCTRL_PIN_PI19 PINCTRL_PIN(PI_BASE + 19, "PI19")
315#define SUNXI_PINCTRL_PIN_PI20 PINCTRL_PIN(PI_BASE + 20, "PI20")
316#define SUNXI_PINCTRL_PIN_PI21 PINCTRL_PIN(PI_BASE + 21, "PI21")
317#define SUNXI_PINCTRL_PIN_PI22 PINCTRL_PIN(PI_BASE + 22, "PI22")
318#define SUNXI_PINCTRL_PIN_PI23 PINCTRL_PIN(PI_BASE + 23, "PI23")
319#define SUNXI_PINCTRL_PIN_PI24 PINCTRL_PIN(PI_BASE + 24, "PI24")
320#define SUNXI_PINCTRL_PIN_PI25 PINCTRL_PIN(PI_BASE + 25, "PI25")
321#define SUNXI_PINCTRL_PIN_PI26 PINCTRL_PIN(PI_BASE + 26, "PI26")
322#define SUNXI_PINCTRL_PIN_PI27 PINCTRL_PIN(PI_BASE + 27, "PI27")
323#define SUNXI_PINCTRL_PIN_PI28 PINCTRL_PIN(PI_BASE + 28, "PI28")
324#define SUNXI_PINCTRL_PIN_PI29 PINCTRL_PIN(PI_BASE + 29, "PI29")
325#define SUNXI_PINCTRL_PIN_PI30 PINCTRL_PIN(PI_BASE + 30, "PI30")
326#define SUNXI_PINCTRL_PIN_PI31 PINCTRL_PIN(PI_BASE + 31, "PI31")
327
328#define SUNXI_PINCTRL_PIN_PL0 PINCTRL_PIN(PL_BASE + 0, "PL0")
329#define SUNXI_PINCTRL_PIN_PL1 PINCTRL_PIN(PL_BASE + 1, "PL1")
330#define SUNXI_PINCTRL_PIN_PL2 PINCTRL_PIN(PL_BASE + 2, "PL2")
331#define SUNXI_PINCTRL_PIN_PL3 PINCTRL_PIN(PL_BASE + 3, "PL3")
332#define SUNXI_PINCTRL_PIN_PL4 PINCTRL_PIN(PL_BASE + 4, "PL4")
333#define SUNXI_PINCTRL_PIN_PL5 PINCTRL_PIN(PL_BASE + 5, "PL5")
334#define SUNXI_PINCTRL_PIN_PL6 PINCTRL_PIN(PL_BASE + 6, "PL6")
335#define SUNXI_PINCTRL_PIN_PL7 PINCTRL_PIN(PL_BASE + 7, "PL7")
336#define SUNXI_PINCTRL_PIN_PL8 PINCTRL_PIN(PL_BASE + 8, "PL8")
337#define SUNXI_PINCTRL_PIN_PL9 PINCTRL_PIN(PL_BASE + 9, "PL9")
338#define SUNXI_PINCTRL_PIN_PL10 PINCTRL_PIN(PL_BASE + 10, "PL10")
339#define SUNXI_PINCTRL_PIN_PL11 PINCTRL_PIN(PL_BASE + 11, "PL11")
340#define SUNXI_PINCTRL_PIN_PL12 PINCTRL_PIN(PL_BASE + 12, "PL12")
341#define SUNXI_PINCTRL_PIN_PL13 PINCTRL_PIN(PL_BASE + 13, "PL13")
342#define SUNXI_PINCTRL_PIN_PL14 PINCTRL_PIN(PL_BASE + 14, "PL14")
343#define SUNXI_PINCTRL_PIN_PL15 PINCTRL_PIN(PL_BASE + 15, "PL15")
344#define SUNXI_PINCTRL_PIN_PL16 PINCTRL_PIN(PL_BASE + 16, "PL16")
345#define SUNXI_PINCTRL_PIN_PL17 PINCTRL_PIN(PL_BASE + 17, "PL17")
346#define SUNXI_PINCTRL_PIN_PL18 PINCTRL_PIN(PL_BASE + 18, "PL18")
347#define SUNXI_PINCTRL_PIN_PL19 PINCTRL_PIN(PL_BASE + 19, "PL19")
348#define SUNXI_PINCTRL_PIN_PL20 PINCTRL_PIN(PL_BASE + 20, "PL20")
349#define SUNXI_PINCTRL_PIN_PL21 PINCTRL_PIN(PL_BASE + 21, "PL21")
350#define SUNXI_PINCTRL_PIN_PL22 PINCTRL_PIN(PL_BASE + 22, "PL22")
351#define SUNXI_PINCTRL_PIN_PL23 PINCTRL_PIN(PL_BASE + 23, "PL23")
352#define SUNXI_PINCTRL_PIN_PL24 PINCTRL_PIN(PL_BASE + 24, "PL24")
353#define SUNXI_PINCTRL_PIN_PL25 PINCTRL_PIN(PL_BASE + 25, "PL25")
354#define SUNXI_PINCTRL_PIN_PL26 PINCTRL_PIN(PL_BASE + 26, "PL26")
355#define SUNXI_PINCTRL_PIN_PL27 PINCTRL_PIN(PL_BASE + 27, "PL27")
356#define SUNXI_PINCTRL_PIN_PL28 PINCTRL_PIN(PL_BASE + 28, "PL28")
357#define SUNXI_PINCTRL_PIN_PL29 PINCTRL_PIN(PL_BASE + 29, "PL29")
358#define SUNXI_PINCTRL_PIN_PL30 PINCTRL_PIN(PL_BASE + 30, "PL30")
359#define SUNXI_PINCTRL_PIN_PL31 PINCTRL_PIN(PL_BASE + 31, "PL31")
360
361#define SUNXI_PINCTRL_PIN_PM0 PINCTRL_PIN(PM_BASE + 0, "PM0")
362#define SUNXI_PINCTRL_PIN_PM1 PINCTRL_PIN(PM_BASE + 1, "PM1")
363#define SUNXI_PINCTRL_PIN_PM2 PINCTRL_PIN(PM_BASE + 2, "PM2")
364#define SUNXI_PINCTRL_PIN_PM3 PINCTRL_PIN(PM_BASE + 3, "PM3")
365#define SUNXI_PINCTRL_PIN_PM4 PINCTRL_PIN(PM_BASE + 4, "PM4")
366#define SUNXI_PINCTRL_PIN_PM5 PINCTRL_PIN(PM_BASE + 5, "PM5")
367#define SUNXI_PINCTRL_PIN_PM6 PINCTRL_PIN(PM_BASE + 6, "PM6")
368#define SUNXI_PINCTRL_PIN_PM7 PINCTRL_PIN(PM_BASE + 7, "PM7")
369#define SUNXI_PINCTRL_PIN_PM8 PINCTRL_PIN(PM_BASE + 8, "PM8")
370#define SUNXI_PINCTRL_PIN_PM9 PINCTRL_PIN(PM_BASE + 9, "PM9")
371#define SUNXI_PINCTRL_PIN_PM10 PINCTRL_PIN(PM_BASE + 10, "PM10")
372#define SUNXI_PINCTRL_PIN_PM11 PINCTRL_PIN(PM_BASE + 11, "PM11")
373#define SUNXI_PINCTRL_PIN_PM12 PINCTRL_PIN(PM_BASE + 12, "PM12")
374#define SUNXI_PINCTRL_PIN_PM13 PINCTRL_PIN(PM_BASE + 13, "PM13")
375#define SUNXI_PINCTRL_PIN_PM14 PINCTRL_PIN(PM_BASE + 14, "PM14")
376#define SUNXI_PINCTRL_PIN_PM15 PINCTRL_PIN(PM_BASE + 15, "PM15")
377#define SUNXI_PINCTRL_PIN_PM16 PINCTRL_PIN(PM_BASE + 16, "PM16")
378#define SUNXI_PINCTRL_PIN_PM17 PINCTRL_PIN(PM_BASE + 17, "PM17")
379#define SUNXI_PINCTRL_PIN_PM18 PINCTRL_PIN(PM_BASE + 18, "PM18")
380#define SUNXI_PINCTRL_PIN_PM19 PINCTRL_PIN(PM_BASE + 19, "PM19")
381#define SUNXI_PINCTRL_PIN_PM20 PINCTRL_PIN(PM_BASE + 20, "PM20")
382#define SUNXI_PINCTRL_PIN_PM21 PINCTRL_PIN(PM_BASE + 21, "PM21")
383#define SUNXI_PINCTRL_PIN_PM22 PINCTRL_PIN(PM_BASE + 22, "PM22")
384#define SUNXI_PINCTRL_PIN_PM23 PINCTRL_PIN(PM_BASE + 23, "PM23")
385#define SUNXI_PINCTRL_PIN_PM24 PINCTRL_PIN(PM_BASE + 24, "PM24")
386#define SUNXI_PINCTRL_PIN_PM25 PINCTRL_PIN(PM_BASE + 25, "PM25")
387#define SUNXI_PINCTRL_PIN_PM26 PINCTRL_PIN(PM_BASE + 26, "PM26")
388#define SUNXI_PINCTRL_PIN_PM27 PINCTRL_PIN(PM_BASE + 27, "PM27")
389#define SUNXI_PINCTRL_PIN_PM28 PINCTRL_PIN(PM_BASE + 28, "PM28")
390#define SUNXI_PINCTRL_PIN_PM29 PINCTRL_PIN(PM_BASE + 29, "PM29")
391#define SUNXI_PINCTRL_PIN_PM30 PINCTRL_PIN(PM_BASE + 30, "PM30")
392#define SUNXI_PINCTRL_PIN_PM31 PINCTRL_PIN(PM_BASE + 31, "PM31")
393
394#define SUNXI_PIN_NAME_MAX_LEN 5
395
396#define BANK_MEM_SIZE 0x24
397#define MUX_REGS_OFFSET 0x0
398#define DATA_REGS_OFFSET 0x10
399#define DLEVEL_REGS_OFFSET 0x14
400#define PULL_REGS_OFFSET 0x1c
401
402#define PINS_PER_BANK 32
403#define MUX_PINS_PER_REG 8
404#define MUX_PINS_BITS 4
405#define MUX_PINS_MASK 0x0f
406#define DATA_PINS_PER_REG 32
407#define DATA_PINS_BITS 1
408#define DATA_PINS_MASK 0x01
409#define DLEVEL_PINS_PER_REG 16
410#define DLEVEL_PINS_BITS 2
411#define DLEVEL_PINS_MASK 0x03
412#define PULL_PINS_PER_REG 16
413#define PULL_PINS_BITS 2
414#define PULL_PINS_MASK 0x03
415
416#define SUNXI_IRQ_NUMBER 32
417
418#define IRQ_CFG_REG 0x200
419#define IRQ_CFG_IRQ_PER_REG 8
420#define IRQ_CFG_IRQ_BITS 4
421#define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1)
422#define IRQ_CTRL_REG 0x210
423#define IRQ_CTRL_IRQ_PER_REG 32
424#define IRQ_CTRL_IRQ_BITS 1
425#define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1)
426#define IRQ_STATUS_REG 0x214
427#define IRQ_STATUS_IRQ_PER_REG 32
428#define IRQ_STATUS_IRQ_BITS 1
429#define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
430
431#define IRQ_EDGE_RISING 0x00
432#define IRQ_EDGE_FALLING 0x01
433#define IRQ_LEVEL_HIGH 0x02
434#define IRQ_LEVEL_LOW 0x03
435#define IRQ_EDGE_BOTH 0x04
436
437struct sunxi_desc_function {
438 const char *name;
439 u8 muxval;
440 u8 irqnum;
441};
442
443struct sunxi_desc_pin {
444 struct pinctrl_pin_desc pin;
445 struct sunxi_desc_function *functions;
446};
447
448struct sunxi_pinctrl_desc {
449 const struct sunxi_desc_pin *pins;
450 int npins;
451 struct pinctrl_gpio_range *ranges;
452 int nranges;
453 unsigned pin_base;
454};
455
456struct sunxi_pinctrl_function {
457 const char *name;
458 const char **groups;
459 unsigned ngroups;
460};
461
462struct sunxi_pinctrl_group {
463 const char *name;
464 unsigned long config;
465 unsigned pin;
466};
467
468struct sunxi_pinctrl {
469 void __iomem *membase;
470 struct gpio_chip *chip;
471 struct sunxi_pinctrl_desc *desc;
472 struct device *dev;
473 struct irq_domain *domain;
474 struct sunxi_pinctrl_function *functions;
475 unsigned nfunctions;
476 struct sunxi_pinctrl_group *groups;
477 unsigned ngroups;
478 int irq;
479 int irq_array[SUNXI_IRQ_NUMBER];
480 spinlock_t lock;
481 struct pinctrl_dev *pctl_dev;
482};
483
484#define SUNXI_PIN(_pin, ...) \
485 { \
486 .pin = _pin, \
487 .functions = (struct sunxi_desc_function[]){ \
488 __VA_ARGS__, { } }, \
489 }
490
491#define SUNXI_FUNCTION(_val, _name) \
492 { \
493 .name = _name, \
494 .muxval = _val, \
495 }
496
497#define SUNXI_FUNCTION_IRQ(_val, _irq) \
498 { \
499 .name = "irq", \
500 .muxval = _val, \
501 .irqnum = _irq, \
502 }
503
504/*
505 * The sunXi PIO registers are organized as is:
506 * 0x00 - 0x0c Muxing values.
507 * 8 pins per register, each pin having a 4bits value
508 * 0x10 Pin values
509 * 32 bits per register, each pin corresponding to one bit
510 * 0x14 - 0x18 Drive level
511 * 16 pins per register, each pin having a 2bits value
512 * 0x1c - 0x20 Pull-Up values
513 * 16 pins per register, each pin having a 2bits value
514 *
515 * This is for the first bank. Each bank will have the same layout,
516 * with an offset being a multiple of 0x24.
517 *
518 * The following functions calculate from the pin number the register
519 * and the bit offset that we should access.
520 */
521static inline u32 sunxi_mux_reg(u16 pin)
522{
523 u8 bank = pin / PINS_PER_BANK;
524 u32 offset = bank * BANK_MEM_SIZE;
525 offset += MUX_REGS_OFFSET;
526 offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04;
527 return round_down(offset, 4);
528}
529
530static inline u32 sunxi_mux_offset(u16 pin)
531{
532 u32 pin_num = pin % MUX_PINS_PER_REG;
533 return pin_num * MUX_PINS_BITS;
534}
535
536static inline u32 sunxi_data_reg(u16 pin)
537{
538 u8 bank = pin / PINS_PER_BANK;
539 u32 offset = bank * BANK_MEM_SIZE;
540 offset += DATA_REGS_OFFSET;
541 offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04;
542 return round_down(offset, 4);
543}
544
545static inline u32 sunxi_data_offset(u16 pin)
546{
547 u32 pin_num = pin % DATA_PINS_PER_REG;
548 return pin_num * DATA_PINS_BITS;
549}
550
551static inline u32 sunxi_dlevel_reg(u16 pin)
552{
553 u8 bank = pin / PINS_PER_BANK;
554 u32 offset = bank * BANK_MEM_SIZE;
555 offset += DLEVEL_REGS_OFFSET;
556 offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04;
557 return round_down(offset, 4);
558}
559
560static inline u32 sunxi_dlevel_offset(u16 pin)
561{
562 u32 pin_num = pin % DLEVEL_PINS_PER_REG;
563 return pin_num * DLEVEL_PINS_BITS;
564}
565
566static inline u32 sunxi_pull_reg(u16 pin)
567{
568 u8 bank = pin / PINS_PER_BANK;
569 u32 offset = bank * BANK_MEM_SIZE;
570 offset += PULL_REGS_OFFSET;
571 offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04;
572 return round_down(offset, 4);
573}
574
575static inline u32 sunxi_pull_offset(u16 pin)
576{
577 u32 pin_num = pin % PULL_PINS_PER_REG;
578 return pin_num * PULL_PINS_BITS;
579}
580
581static inline u32 sunxi_irq_cfg_reg(u16 irq)
582{
583 u8 reg = irq / IRQ_CFG_IRQ_PER_REG * 0x04;
584 return reg + IRQ_CFG_REG;
585}
586
587static inline u32 sunxi_irq_cfg_offset(u16 irq)
588{
589 u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
590 return irq_num * IRQ_CFG_IRQ_BITS;
591}
592
593static inline u32 sunxi_irq_ctrl_reg(u16 irq)
594{
595 u8 reg = irq / IRQ_CTRL_IRQ_PER_REG * 0x04;
596 return reg + IRQ_CTRL_REG;
597}
598
599static inline u32 sunxi_irq_ctrl_offset(u16 irq)
600{
601 u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
602 return irq_num * IRQ_CTRL_IRQ_BITS;
603}
604
605static inline u32 sunxi_irq_status_reg(u16 irq)
606{
607 u8 reg = irq / IRQ_STATUS_IRQ_PER_REG * 0x04;
608 return reg + IRQ_STATUS_REG;
609}
610
611static inline u32 sunxi_irq_status_offset(u16 irq)
612{
613 u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
614 return irq_num * IRQ_STATUS_IRQ_BITS;
615}
616
617#endif /* __PINCTRL_SUNXI_H */
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
new file mode 100644
index 000000000000..3940d098d6cb
--- /dev/null
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -0,0 +1,32 @@
1if ARCH_SUNXI
2
3config PINCTRL_SUNXI
4 bool
5 select PINMUX
6 select GENERIC_PINCONF
7
8config PINCTRL_SUN4I_A10
9 bool
10 select PINCTRL_SUNXI
11
12config PINCTRL_SUN5I_A10S
13 bool
14 select PINCTRL_SUNXI
15
16config PINCTRL_SUN5I_A13
17 bool
18 select PINCTRL_SUNXI
19
20config PINCTRL_SUN6I_A31
21 bool
22 select PINCTRL_SUNXI
23
24config PINCTRL_SUN6I_A31_R
25 bool
26 select PINCTRL_SUNXI
27
28config PINCTRL_SUN7I_A20
29 bool
30 select PINCTRL_SUNXI
31
32endif
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
new file mode 100644
index 000000000000..8e23a15e695d
--- /dev/null
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -0,0 +1,10 @@
1# Core
2obj-$(CONFIG_PINCTRL_SUNXI) += pinctrl-sunxi.o
3
4# SoC Drivers
5obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o
6obj-$(CONFIG_PINCTRL_SUN5I_A10S) += pinctrl-sun5i-a10s.o
7obj-$(CONFIG_PINCTRL_SUN5I_A13) += pinctrl-sun5i-a13.o
8obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o
9obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o
10obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
new file mode 100644
index 000000000000..fa1ff7c7e357
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
@@ -0,0 +1,1039 @@
1/*
2 * Allwinner A10 SoCs pinctrl driver.
3 *
4 * Copyright (C) 2014 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
17#include <linux/pinctrl/pinctrl.h>
18
19#include "pinctrl-sunxi.h"
20
21static const struct sunxi_desc_pin sun4i_a10_pins[] = {
22 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
23 SUNXI_FUNCTION(0x0, "gpio_in"),
24 SUNXI_FUNCTION(0x1, "gpio_out"),
25 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
26 SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
27 SUNXI_FUNCTION(0x4, "uart2")), /* RTS */
28 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
29 SUNXI_FUNCTION(0x0, "gpio_in"),
30 SUNXI_FUNCTION(0x1, "gpio_out"),
31 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
32 SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
33 SUNXI_FUNCTION(0x4, "uart2")), /* CTS */
34 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
35 SUNXI_FUNCTION(0x0, "gpio_in"),
36 SUNXI_FUNCTION(0x1, "gpio_out"),
37 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
38 SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
39 SUNXI_FUNCTION(0x4, "uart2")), /* TX */
40 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
41 SUNXI_FUNCTION(0x0, "gpio_in"),
42 SUNXI_FUNCTION(0x1, "gpio_out"),
43 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
44 SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
45 SUNXI_FUNCTION(0x4, "uart2")), /* RX */
46 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
47 SUNXI_FUNCTION(0x0, "gpio_in"),
48 SUNXI_FUNCTION(0x1, "gpio_out"),
49 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
50 SUNXI_FUNCTION(0x3, "spi1")), /* CS1 */
51 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
52 SUNXI_FUNCTION(0x0, "gpio_in"),
53 SUNXI_FUNCTION(0x1, "gpio_out"),
54 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
55 SUNXI_FUNCTION(0x3, "spi3")), /* CS0 */
56 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
57 SUNXI_FUNCTION(0x0, "gpio_in"),
58 SUNXI_FUNCTION(0x1, "gpio_out"),
59 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
60 SUNXI_FUNCTION(0x3, "spi3")), /* CLK */
61 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
62 SUNXI_FUNCTION(0x0, "gpio_in"),
63 SUNXI_FUNCTION(0x1, "gpio_out"),
64 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
65 SUNXI_FUNCTION(0x3, "spi3")), /* MOSI */
66 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
67 SUNXI_FUNCTION(0x0, "gpio_in"),
68 SUNXI_FUNCTION(0x1, "gpio_out"),
69 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
70 SUNXI_FUNCTION(0x3, "spi3")), /* MISO */
71 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
72 SUNXI_FUNCTION(0x0, "gpio_in"),
73 SUNXI_FUNCTION(0x1, "gpio_out"),
74 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
75 SUNXI_FUNCTION(0x3, "spi3")), /* CS1 */
76 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
77 SUNXI_FUNCTION(0x0, "gpio_in"),
78 SUNXI_FUNCTION(0x1, "gpio_out"),
79 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
80 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
81 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
82 SUNXI_FUNCTION(0x0, "gpio_in"),
83 SUNXI_FUNCTION(0x1, "gpio_out"),
84 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
85 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
86 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
87 SUNXI_FUNCTION(0x0, "gpio_in"),
88 SUNXI_FUNCTION(0x1, "gpio_out"),
89 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
90 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
91 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */
92 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
93 SUNXI_FUNCTION(0x0, "gpio_in"),
94 SUNXI_FUNCTION(0x1, "gpio_out"),
95 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
96 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
97 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */
98 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
99 SUNXI_FUNCTION(0x0, "gpio_in"),
100 SUNXI_FUNCTION(0x1, "gpio_out"),
101 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
102 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
103 SUNXI_FUNCTION(0x4, "uart1")), /* DTR */
104 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
105 SUNXI_FUNCTION(0x0, "gpio_in"),
106 SUNXI_FUNCTION(0x1, "gpio_out"),
107 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
108 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
109 SUNXI_FUNCTION(0x4, "uart1")), /* DSR */
110 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
111 SUNXI_FUNCTION(0x0, "gpio_in"),
112 SUNXI_FUNCTION(0x1, "gpio_out"),
113 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
114 SUNXI_FUNCTION(0x3, "can"), /* TX */
115 SUNXI_FUNCTION(0x4, "uart1")), /* DCD */
116 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
117 SUNXI_FUNCTION(0x0, "gpio_in"),
118 SUNXI_FUNCTION(0x1, "gpio_out"),
119 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
120 SUNXI_FUNCTION(0x3, "can"), /* RX */
121 SUNXI_FUNCTION(0x4, "uart1")), /* RING */
122 /* Hole */
123 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
124 SUNXI_FUNCTION(0x0, "gpio_in"),
125 SUNXI_FUNCTION(0x1, "gpio_out"),
126 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
127 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
128 SUNXI_FUNCTION(0x0, "gpio_in"),
129 SUNXI_FUNCTION(0x1, "gpio_out"),
130 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
131 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
132 SUNXI_FUNCTION(0x0, "gpio_in"),
133 SUNXI_FUNCTION(0x1, "gpio_out"),
134 SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */
135 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
136 SUNXI_FUNCTION(0x0, "gpio_in"),
137 SUNXI_FUNCTION(0x1, "gpio_out"),
138 SUNXI_FUNCTION(0x2, "ir0")), /* TX */
139 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
140 SUNXI_FUNCTION(0x0, "gpio_in"),
141 SUNXI_FUNCTION(0x1, "gpio_out"),
142 SUNXI_FUNCTION(0x2, "ir0")), /* RX */
143 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
144 SUNXI_FUNCTION(0x0, "gpio_in"),
145 SUNXI_FUNCTION(0x1, "gpio_out"),
146 SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
147 SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */
148 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
149 SUNXI_FUNCTION(0x0, "gpio_in"),
150 SUNXI_FUNCTION(0x1, "gpio_out"),
151 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
152 SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */
153 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
154 SUNXI_FUNCTION(0x0, "gpio_in"),
155 SUNXI_FUNCTION(0x1, "gpio_out"),
156 SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */
157 SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */
158 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
159 SUNXI_FUNCTION(0x0, "gpio_in"),
160 SUNXI_FUNCTION(0x1, "gpio_out"),
161 SUNXI_FUNCTION(0x2, "i2s"), /* DO0 */
162 SUNXI_FUNCTION(0x3, "ac97")), /* DO */
163 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
164 SUNXI_FUNCTION(0x0, "gpio_in"),
165 SUNXI_FUNCTION(0x1, "gpio_out"),
166 SUNXI_FUNCTION(0x2, "i2s")), /* DO1 */
167 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
168 SUNXI_FUNCTION(0x0, "gpio_in"),
169 SUNXI_FUNCTION(0x1, "gpio_out"),
170 SUNXI_FUNCTION(0x2, "i2s")), /* DO2 */
171 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
172 SUNXI_FUNCTION(0x0, "gpio_in"),
173 SUNXI_FUNCTION(0x1, "gpio_out"),
174 SUNXI_FUNCTION(0x2, "i2s")), /* DO3 */
175 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
176 SUNXI_FUNCTION(0x0, "gpio_in"),
177 SUNXI_FUNCTION(0x1, "gpio_out"),
178 SUNXI_FUNCTION(0x2, "i2s"), /* DI */
179 SUNXI_FUNCTION(0x3, "ac97")), /* DI */
180 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
181 SUNXI_FUNCTION(0x0, "gpio_in"),
182 SUNXI_FUNCTION(0x1, "gpio_out"),
183 SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */
184 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
185 SUNXI_FUNCTION(0x0, "gpio_in"),
186 SUNXI_FUNCTION(0x1, "gpio_out"),
187 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
188 SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */
189 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
190 SUNXI_FUNCTION(0x0, "gpio_in"),
191 SUNXI_FUNCTION(0x1, "gpio_out"),
192 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
193 SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */
194 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
195 SUNXI_FUNCTION(0x0, "gpio_in"),
196 SUNXI_FUNCTION(0x1, "gpio_out"),
197 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
198 SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */
199 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
200 SUNXI_FUNCTION(0x0, "gpio_in"),
201 SUNXI_FUNCTION(0x1, "gpio_out"),
202 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
203 SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */
204 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
205 SUNXI_FUNCTION(0x0, "gpio_in"),
206 SUNXI_FUNCTION(0x1, "gpio_out"),
207 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
208 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 19),
209 SUNXI_FUNCTION(0x0, "gpio_in"),
210 SUNXI_FUNCTION(0x1, "gpio_out"),
211 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
212 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20),
213 SUNXI_FUNCTION(0x0, "gpio_in"),
214 SUNXI_FUNCTION(0x1, "gpio_out"),
215 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
216 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 21),
217 SUNXI_FUNCTION(0x0, "gpio_in"),
218 SUNXI_FUNCTION(0x1, "gpio_out"),
219 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
220 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 22),
221 SUNXI_FUNCTION(0x0, "gpio_in"),
222 SUNXI_FUNCTION(0x1, "gpio_out"),
223 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
224 SUNXI_FUNCTION(0x3, "ir1")), /* TX */
225 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 23),
226 SUNXI_FUNCTION(0x0, "gpio_in"),
227 SUNXI_FUNCTION(0x1, "gpio_out"),
228 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
229 SUNXI_FUNCTION(0x3, "ir1")), /* RX */
230 /* Hole */
231 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
232 SUNXI_FUNCTION(0x0, "gpio_in"),
233 SUNXI_FUNCTION(0x1, "gpio_out"),
234 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
235 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
236 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
237 SUNXI_FUNCTION(0x0, "gpio_in"),
238 SUNXI_FUNCTION(0x1, "gpio_out"),
239 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
240 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
241 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
242 SUNXI_FUNCTION(0x0, "gpio_in"),
243 SUNXI_FUNCTION(0x1, "gpio_out"),
244 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
245 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
246 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
247 SUNXI_FUNCTION(0x0, "gpio_in"),
248 SUNXI_FUNCTION(0x1, "gpio_out"),
249 SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */
250 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
251 SUNXI_FUNCTION(0x0, "gpio_in"),
252 SUNXI_FUNCTION(0x1, "gpio_out"),
253 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
254 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
255 SUNXI_FUNCTION(0x0, "gpio_in"),
256 SUNXI_FUNCTION(0x1, "gpio_out"),
257 SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */
258 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
259 SUNXI_FUNCTION(0x0, "gpio_in"),
260 SUNXI_FUNCTION(0x1, "gpio_out"),
261 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
262 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
263 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
264 SUNXI_FUNCTION(0x0, "gpio_in"),
265 SUNXI_FUNCTION(0x1, "gpio_out"),
266 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
267 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
268 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
269 SUNXI_FUNCTION(0x0, "gpio_in"),
270 SUNXI_FUNCTION(0x1, "gpio_out"),
271 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
272 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
273 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
274 SUNXI_FUNCTION(0x0, "gpio_in"),
275 SUNXI_FUNCTION(0x1, "gpio_out"),
276 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
277 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
278 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
279 SUNXI_FUNCTION(0x0, "gpio_in"),
280 SUNXI_FUNCTION(0x1, "gpio_out"),
281 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
282 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
283 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
284 SUNXI_FUNCTION(0x0, "gpio_in"),
285 SUNXI_FUNCTION(0x1, "gpio_out"),
286 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
287 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
288 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
289 SUNXI_FUNCTION(0x0, "gpio_in"),
290 SUNXI_FUNCTION(0x1, "gpio_out"),
291 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */
292 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
293 SUNXI_FUNCTION(0x0, "gpio_in"),
294 SUNXI_FUNCTION(0x1, "gpio_out"),
295 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */
296 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
297 SUNXI_FUNCTION(0x0, "gpio_in"),
298 SUNXI_FUNCTION(0x1, "gpio_out"),
299 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */
300 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
301 SUNXI_FUNCTION(0x0, "gpio_in"),
302 SUNXI_FUNCTION(0x1, "gpio_out"),
303 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */
304 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
305 SUNXI_FUNCTION(0x0, "gpio_in"),
306 SUNXI_FUNCTION(0x1, "gpio_out"),
307 SUNXI_FUNCTION(0x2, "nand0")), /* NWP */
308 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
309 SUNXI_FUNCTION(0x0, "gpio_in"),
310 SUNXI_FUNCTION(0x1, "gpio_out"),
311 SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */
312 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
313 SUNXI_FUNCTION(0x0, "gpio_in"),
314 SUNXI_FUNCTION(0x1, "gpio_out"),
315 SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */
316 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
317 SUNXI_FUNCTION(0x0, "gpio_in"),
318 SUNXI_FUNCTION(0x1, "gpio_out"),
319 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
320 SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */
321 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20),
322 SUNXI_FUNCTION(0x0, "gpio_in"),
323 SUNXI_FUNCTION(0x1, "gpio_out"),
324 SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
325 SUNXI_FUNCTION(0x3, "spi2")), /* CLK */
326 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21),
327 SUNXI_FUNCTION(0x0, "gpio_in"),
328 SUNXI_FUNCTION(0x1, "gpio_out"),
329 SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
330 SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */
331 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22),
332 SUNXI_FUNCTION(0x0, "gpio_in"),
333 SUNXI_FUNCTION(0x1, "gpio_out"),
334 SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
335 SUNXI_FUNCTION(0x3, "spi2")), /* MISO */
336 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23),
337 SUNXI_FUNCTION(0x0, "gpio_in"),
338 SUNXI_FUNCTION(0x1, "gpio_out"),
339 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
340 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24),
341 SUNXI_FUNCTION(0x0, "gpio_in"),
342 SUNXI_FUNCTION(0x1, "gpio_out"),
343 SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */
344 /* Hole */
345 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
346 SUNXI_FUNCTION(0x0, "gpio_in"),
347 SUNXI_FUNCTION(0x1, "gpio_out"),
348 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
349 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
350 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
351 SUNXI_FUNCTION(0x0, "gpio_in"),
352 SUNXI_FUNCTION(0x1, "gpio_out"),
353 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
354 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
355 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
356 SUNXI_FUNCTION(0x0, "gpio_in"),
357 SUNXI_FUNCTION(0x1, "gpio_out"),
358 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
359 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
360 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
361 SUNXI_FUNCTION(0x0, "gpio_in"),
362 SUNXI_FUNCTION(0x1, "gpio_out"),
363 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
364 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
365 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
366 SUNXI_FUNCTION(0x0, "gpio_in"),
367 SUNXI_FUNCTION(0x1, "gpio_out"),
368 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
369 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
370 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
371 SUNXI_FUNCTION(0x0, "gpio_in"),
372 SUNXI_FUNCTION(0x1, "gpio_out"),
373 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
374 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
375 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
376 SUNXI_FUNCTION(0x0, "gpio_in"),
377 SUNXI_FUNCTION(0x1, "gpio_out"),
378 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
379 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
380 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
381 SUNXI_FUNCTION(0x0, "gpio_in"),
382 SUNXI_FUNCTION(0x1, "gpio_out"),
383 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
384 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
385 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
386 SUNXI_FUNCTION(0x0, "gpio_in"),
387 SUNXI_FUNCTION(0x1, "gpio_out"),
388 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
389 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
390 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
391 SUNXI_FUNCTION(0x0, "gpio_in"),
392 SUNXI_FUNCTION(0x1, "gpio_out"),
393 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
394 SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */
395 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
396 SUNXI_FUNCTION(0x0, "gpio_in"),
397 SUNXI_FUNCTION(0x1, "gpio_out"),
398 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
399 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
400 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
401 SUNXI_FUNCTION(0x0, "gpio_in"),
402 SUNXI_FUNCTION(0x1, "gpio_out"),
403 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
404 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
405 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
406 SUNXI_FUNCTION(0x0, "gpio_in"),
407 SUNXI_FUNCTION(0x1, "gpio_out"),
408 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
409 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
410 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
411 SUNXI_FUNCTION(0x0, "gpio_in"),
412 SUNXI_FUNCTION(0x1, "gpio_out"),
413 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
414 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
415 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
416 SUNXI_FUNCTION(0x0, "gpio_in"),
417 SUNXI_FUNCTION(0x1, "gpio_out"),
418 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
419 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
420 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
421 SUNXI_FUNCTION(0x0, "gpio_in"),
422 SUNXI_FUNCTION(0x1, "gpio_out"),
423 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
424 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
425 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
426 SUNXI_FUNCTION(0x0, "gpio_in"),
427 SUNXI_FUNCTION(0x1, "gpio_out"),
428 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
429 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
430 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
431 SUNXI_FUNCTION(0x0, "gpio_in"),
432 SUNXI_FUNCTION(0x1, "gpio_out"),
433 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
434 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
435 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
436 SUNXI_FUNCTION(0x0, "gpio_in"),
437 SUNXI_FUNCTION(0x1, "gpio_out"),
438 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
439 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
440 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
441 SUNXI_FUNCTION(0x0, "gpio_in"),
442 SUNXI_FUNCTION(0x1, "gpio_out"),
443 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
444 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
445 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
446 SUNXI_FUNCTION(0x0, "gpio_in"),
447 SUNXI_FUNCTION(0x1, "gpio_out"),
448 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
449 SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */
450 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
451 SUNXI_FUNCTION(0x0, "gpio_in"),
452 SUNXI_FUNCTION(0x1, "gpio_out"),
453 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
454 SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */
455 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
456 SUNXI_FUNCTION(0x0, "gpio_in"),
457 SUNXI_FUNCTION(0x1, "gpio_out"),
458 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
459 SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */
460 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
461 SUNXI_FUNCTION(0x0, "gpio_in"),
462 SUNXI_FUNCTION(0x1, "gpio_out"),
463 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
464 SUNXI_FUNCTION(0x3, "sim")), /* DET */
465 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
466 SUNXI_FUNCTION(0x0, "gpio_in"),
467 SUNXI_FUNCTION(0x1, "gpio_out"),
468 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
469 SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */
470 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
471 SUNXI_FUNCTION(0x0, "gpio_in"),
472 SUNXI_FUNCTION(0x1, "gpio_out"),
473 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
474 SUNXI_FUNCTION(0x3, "sim")), /* RST */
475 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
476 SUNXI_FUNCTION(0x0, "gpio_in"),
477 SUNXI_FUNCTION(0x1, "gpio_out"),
478 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
479 SUNXI_FUNCTION(0x3, "sim")), /* SCK */
480 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
481 SUNXI_FUNCTION(0x0, "gpio_in"),
482 SUNXI_FUNCTION(0x1, "gpio_out"),
483 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
484 SUNXI_FUNCTION(0x3, "sim")), /* SDA */
485 /* Hole */
486 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
487 SUNXI_FUNCTION(0x0, "gpio_in"),
488 SUNXI_FUNCTION(0x1, "gpio_out"),
489 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
490 SUNXI_FUNCTION(0x3, "csi0")), /* PCK */
491 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
492 SUNXI_FUNCTION(0x0, "gpio_in"),
493 SUNXI_FUNCTION(0x1, "gpio_out"),
494 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
495 SUNXI_FUNCTION(0x3, "csi0")), /* CK */
496 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
497 SUNXI_FUNCTION(0x0, "gpio_in"),
498 SUNXI_FUNCTION(0x1, "gpio_out"),
499 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
500 SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */
501 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
502 SUNXI_FUNCTION(0x0, "gpio_in"),
503 SUNXI_FUNCTION(0x1, "gpio_out"),
504 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
505 SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */
506 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
507 SUNXI_FUNCTION(0x0, "gpio_in"),
508 SUNXI_FUNCTION(0x1, "gpio_out"),
509 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
510 SUNXI_FUNCTION(0x3, "csi0")), /* D0 */
511 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
512 SUNXI_FUNCTION(0x0, "gpio_in"),
513 SUNXI_FUNCTION(0x1, "gpio_out"),
514 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
515 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
516 SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */
517 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
518 SUNXI_FUNCTION(0x0, "gpio_in"),
519 SUNXI_FUNCTION(0x1, "gpio_out"),
520 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
521 SUNXI_FUNCTION(0x3, "csi0")), /* D2 */
522 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
523 SUNXI_FUNCTION(0x0, "gpio_in"),
524 SUNXI_FUNCTION(0x1, "gpio_out"),
525 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
526 SUNXI_FUNCTION(0x3, "csi0")), /* D3 */
527 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
528 SUNXI_FUNCTION(0x0, "gpio_in"),
529 SUNXI_FUNCTION(0x1, "gpio_out"),
530 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
531 SUNXI_FUNCTION(0x3, "csi0")), /* D4 */
532 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
533 SUNXI_FUNCTION(0x0, "gpio_in"),
534 SUNXI_FUNCTION(0x1, "gpio_out"),
535 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
536 SUNXI_FUNCTION(0x3, "csi0")), /* D5 */
537 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
538 SUNXI_FUNCTION(0x0, "gpio_in"),
539 SUNXI_FUNCTION(0x1, "gpio_out"),
540 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
541 SUNXI_FUNCTION(0x3, "csi0")), /* D6 */
542 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
543 SUNXI_FUNCTION(0x0, "gpio_in"),
544 SUNXI_FUNCTION(0x1, "gpio_out"),
545 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
546 SUNXI_FUNCTION(0x3, "csi0")), /* D7 */
547 /* Hole */
548 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
549 SUNXI_FUNCTION(0x0, "gpio_in"),
550 SUNXI_FUNCTION(0x1, "gpio_out"),
551 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
552 SUNXI_FUNCTION(0x4, "jtag")), /* MSI */
553 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
554 SUNXI_FUNCTION(0x0, "gpio_in"),
555 SUNXI_FUNCTION(0x1, "gpio_out"),
556 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
557 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
558 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
559 SUNXI_FUNCTION(0x0, "gpio_in"),
560 SUNXI_FUNCTION(0x1, "gpio_out"),
561 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
562 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
563 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
564 SUNXI_FUNCTION(0x0, "gpio_in"),
565 SUNXI_FUNCTION(0x1, "gpio_out"),
566 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
567 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
568 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
569 SUNXI_FUNCTION(0x0, "gpio_in"),
570 SUNXI_FUNCTION(0x1, "gpio_out"),
571 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
572 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
573 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
574 SUNXI_FUNCTION(0x0, "gpio_in"),
575 SUNXI_FUNCTION(0x1, "gpio_out"),
576 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
577 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
578 /* Hole */
579 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
580 SUNXI_FUNCTION(0x0, "gpio_in"),
581 SUNXI_FUNCTION(0x1, "gpio_out"),
582 SUNXI_FUNCTION(0x2, "ts1"), /* CLK */
583 SUNXI_FUNCTION(0x3, "csi1"), /* PCK */
584 SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */
585 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
586 SUNXI_FUNCTION(0x0, "gpio_in"),
587 SUNXI_FUNCTION(0x1, "gpio_out"),
588 SUNXI_FUNCTION(0x2, "ts1"), /* ERR */
589 SUNXI_FUNCTION(0x3, "csi1"), /* CK */
590 SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */
591 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
592 SUNXI_FUNCTION(0x0, "gpio_in"),
593 SUNXI_FUNCTION(0x1, "gpio_out"),
594 SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */
595 SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */
596 SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */
597 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
598 SUNXI_FUNCTION(0x0, "gpio_in"),
599 SUNXI_FUNCTION(0x1, "gpio_out"),
600 SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */
601 SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */
602 SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */
603 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
604 SUNXI_FUNCTION(0x0, "gpio_in"),
605 SUNXI_FUNCTION(0x1, "gpio_out"),
606 SUNXI_FUNCTION(0x2, "ts1"), /* D0 */
607 SUNXI_FUNCTION(0x3, "csi1"), /* D0 */
608 SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */
609 SUNXI_FUNCTION(0x5, "csi0")), /* D8 */
610 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
611 SUNXI_FUNCTION(0x0, "gpio_in"),
612 SUNXI_FUNCTION(0x1, "gpio_out"),
613 SUNXI_FUNCTION(0x2, "ts1"), /* D1 */
614 SUNXI_FUNCTION(0x3, "csi1"), /* D1 */
615 SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */
616 SUNXI_FUNCTION(0x5, "csi0")), /* D9 */
617 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
618 SUNXI_FUNCTION(0x0, "gpio_in"),
619 SUNXI_FUNCTION(0x1, "gpio_out"),
620 SUNXI_FUNCTION(0x2, "ts1"), /* D2 */
621 SUNXI_FUNCTION(0x3, "csi1"), /* D2 */
622 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
623 SUNXI_FUNCTION(0x5, "csi0")), /* D10 */
624 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
625 SUNXI_FUNCTION(0x0, "gpio_in"),
626 SUNXI_FUNCTION(0x1, "gpio_out"),
627 SUNXI_FUNCTION(0x2, "ts1"), /* D3 */
628 SUNXI_FUNCTION(0x3, "csi1"), /* D3 */
629 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
630 SUNXI_FUNCTION(0x5, "csi0")), /* D11 */
631 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
632 SUNXI_FUNCTION(0x0, "gpio_in"),
633 SUNXI_FUNCTION(0x1, "gpio_out"),
634 SUNXI_FUNCTION(0x2, "ts1"), /* D4 */
635 SUNXI_FUNCTION(0x3, "csi1"), /* D4 */
636 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
637 SUNXI_FUNCTION(0x5, "csi0")), /* D12 */
638 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
639 SUNXI_FUNCTION(0x0, "gpio_in"),
640 SUNXI_FUNCTION(0x1, "gpio_out"),
641 SUNXI_FUNCTION(0x2, "ts1"), /* D5 */
642 SUNXI_FUNCTION(0x3, "csi1"), /* D5 */
643 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
644 SUNXI_FUNCTION(0x5, "csi0")), /* D13 */
645 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
646 SUNXI_FUNCTION(0x0, "gpio_in"),
647 SUNXI_FUNCTION(0x1, "gpio_out"),
648 SUNXI_FUNCTION(0x2, "ts1"), /* D6 */
649 SUNXI_FUNCTION(0x3, "csi1"), /* D6 */
650 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
651 SUNXI_FUNCTION(0x5, "csi0")), /* D14 */
652 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
653 SUNXI_FUNCTION(0x0, "gpio_in"),
654 SUNXI_FUNCTION(0x1, "gpio_out"),
655 SUNXI_FUNCTION(0x2, "ts1"), /* D7 */
656 SUNXI_FUNCTION(0x3, "csi1"), /* D7 */
657 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
658 SUNXI_FUNCTION(0x5, "csi0")), /* D15 */
659 /* Hole */
660 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
661 SUNXI_FUNCTION(0x0, "gpio_in"),
662 SUNXI_FUNCTION(0x1, "gpio_out"),
663 SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */
664 SUNXI_FUNCTION(0x3, "pata"), /* ATAA0 */
665 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
666 SUNXI_FUNCTION_IRQ(0x6, 0), /* EINT0 */
667 SUNXI_FUNCTION(0x7, "csi1")), /* D0 */
668 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
669 SUNXI_FUNCTION(0x0, "gpio_in"),
670 SUNXI_FUNCTION(0x1, "gpio_out"),
671 SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */
672 SUNXI_FUNCTION(0x3, "pata"), /* ATAA1 */
673 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
674 SUNXI_FUNCTION_IRQ(0x6, 1), /* EINT1 */
675 SUNXI_FUNCTION(0x7, "csi1")), /* D1 */
676 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
677 SUNXI_FUNCTION(0x0, "gpio_in"),
678 SUNXI_FUNCTION(0x1, "gpio_out"),
679 SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */
680 SUNXI_FUNCTION(0x3, "pata"), /* ATAA2 */
681 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
682 SUNXI_FUNCTION_IRQ(0x6, 2), /* EINT2 */
683 SUNXI_FUNCTION(0x7, "csi1")), /* D2 */
684 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
685 SUNXI_FUNCTION(0x0, "gpio_in"),
686 SUNXI_FUNCTION(0x1, "gpio_out"),
687 SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */
688 SUNXI_FUNCTION(0x3, "pata"), /* ATAIRQ */
689 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
690 SUNXI_FUNCTION_IRQ(0x6, 3), /* EINT3 */
691 SUNXI_FUNCTION(0x7, "csi1")), /* D3 */
692 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
693 SUNXI_FUNCTION(0x0, "gpio_in"),
694 SUNXI_FUNCTION(0x1, "gpio_out"),
695 SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */
696 SUNXI_FUNCTION(0x3, "pata"), /* ATAD0 */
697 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
698 SUNXI_FUNCTION_IRQ(0x6, 4), /* EINT4 */
699 SUNXI_FUNCTION(0x7, "csi1")), /* D4 */
700 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
701 SUNXI_FUNCTION(0x0, "gpio_in"),
702 SUNXI_FUNCTION(0x1, "gpio_out"),
703 SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */
704 SUNXI_FUNCTION(0x3, "pata"), /* ATAD1 */
705 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
706 SUNXI_FUNCTION_IRQ(0x6, 5), /* EINT5 */
707 SUNXI_FUNCTION(0x7, "csi1")), /* D5 */
708 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
709 SUNXI_FUNCTION(0x0, "gpio_in"),
710 SUNXI_FUNCTION(0x1, "gpio_out"),
711 SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */
712 SUNXI_FUNCTION(0x3, "pata"), /* ATAD2 */
713 SUNXI_FUNCTION(0x4, "uart5"), /* TX */
714 SUNXI_FUNCTION(0x5, "ms"), /* BS */
715 SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */
716 SUNXI_FUNCTION(0x7, "csi1")), /* D6 */
717 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
718 SUNXI_FUNCTION(0x0, "gpio_in"),
719 SUNXI_FUNCTION(0x1, "gpio_out"),
720 SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */
721 SUNXI_FUNCTION(0x3, "pata"), /* ATAD3 */
722 SUNXI_FUNCTION(0x4, "uart5"), /* RX */
723 SUNXI_FUNCTION(0x5, "ms"), /* CLK */
724 SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */
725 SUNXI_FUNCTION(0x7, "csi1")), /* D7 */
726 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
727 SUNXI_FUNCTION(0x0, "gpio_in"),
728 SUNXI_FUNCTION(0x1, "gpio_out"),
729 SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */
730 SUNXI_FUNCTION(0x3, "pata"), /* ATAD4 */
731 SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */
732 SUNXI_FUNCTION(0x5, "ms"), /* D0 */
733 SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */
734 SUNXI_FUNCTION(0x7, "csi1")), /* D8 */
735 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
736 SUNXI_FUNCTION(0x0, "gpio_in"),
737 SUNXI_FUNCTION(0x1, "gpio_out"),
738 SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */
739 SUNXI_FUNCTION(0x3, "pata"), /* ATAD5 */
740 SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */
741 SUNXI_FUNCTION(0x5, "ms"), /* D1 */
742 SUNXI_FUNCTION_IRQ(0x6, 9), /* EINT9 */
743 SUNXI_FUNCTION(0x7, "csi1")), /* D9 */
744 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
745 SUNXI_FUNCTION(0x0, "gpio_in"),
746 SUNXI_FUNCTION(0x1, "gpio_out"),
747 SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */
748 SUNXI_FUNCTION(0x3, "pata"), /* ATAD6 */
749 SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */
750 SUNXI_FUNCTION(0x5, "ms"), /* D2 */
751 SUNXI_FUNCTION_IRQ(0x6, 10), /* EINT10 */
752 SUNXI_FUNCTION(0x7, "csi1")), /* D10 */
753 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
754 SUNXI_FUNCTION(0x0, "gpio_in"),
755 SUNXI_FUNCTION(0x1, "gpio_out"),
756 SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */
757 SUNXI_FUNCTION(0x3, "pata"), /* ATAD7 */
758 SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */
759 SUNXI_FUNCTION(0x5, "ms"), /* D3 */
760 SUNXI_FUNCTION_IRQ(0x6, 11), /* EINT11 */
761 SUNXI_FUNCTION(0x7, "csi1")), /* D11 */
762 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
763 SUNXI_FUNCTION(0x0, "gpio_in"),
764 SUNXI_FUNCTION(0x1, "gpio_out"),
765 SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */
766 SUNXI_FUNCTION(0x3, "pata"), /* ATAD8 */
767 SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */
768 SUNXI_FUNCTION_IRQ(0x6, 12), /* EINT12 */
769 SUNXI_FUNCTION(0x7, "csi1")), /* D12 */
770 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
771 SUNXI_FUNCTION(0x0, "gpio_in"),
772 SUNXI_FUNCTION(0x1, "gpio_out"),
773 SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */
774 SUNXI_FUNCTION(0x3, "pata"), /* ATAD9 */
775 SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */
776 SUNXI_FUNCTION(0x5, "sim"), /* RST */
777 SUNXI_FUNCTION_IRQ(0x6, 13), /* EINT13 */
778 SUNXI_FUNCTION(0x7, "csi1")), /* D13 */
779 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
780 SUNXI_FUNCTION(0x0, "gpio_in"),
781 SUNXI_FUNCTION(0x1, "gpio_out"),
782 SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */
783 SUNXI_FUNCTION(0x3, "pata"), /* ATAD10 */
784 SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */
785 SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */
786 SUNXI_FUNCTION_IRQ(0x6, 14), /* EINT14 */
787 SUNXI_FUNCTION(0x7, "csi1")), /* D14 */
788 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
789 SUNXI_FUNCTION(0x0, "gpio_in"),
790 SUNXI_FUNCTION(0x1, "gpio_out"),
791 SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */
792 SUNXI_FUNCTION(0x3, "pata"), /* ATAD11 */
793 SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */
794 SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */
795 SUNXI_FUNCTION_IRQ(0x6, 15), /* EINT15 */
796 SUNXI_FUNCTION(0x7, "csi1")), /* D15 */
797 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
798 SUNXI_FUNCTION(0x0, "gpio_in"),
799 SUNXI_FUNCTION(0x1, "gpio_out"),
800 SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */
801 SUNXI_FUNCTION(0x3, "pata"), /* ATAD12 */
802 SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */
803 SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */
804 SUNXI_FUNCTION(0x7, "csi1")), /* D16 */
805 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
806 SUNXI_FUNCTION(0x0, "gpio_in"),
807 SUNXI_FUNCTION(0x1, "gpio_out"),
808 SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */
809 SUNXI_FUNCTION(0x3, "pata"), /* ATAD13 */
810 SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */
811 SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */
812 SUNXI_FUNCTION_IRQ(0x6, 17), /* EINT17 */
813 SUNXI_FUNCTION(0x7, "csi1")), /* D17 */
814 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
815 SUNXI_FUNCTION(0x0, "gpio_in"),
816 SUNXI_FUNCTION(0x1, "gpio_out"),
817 SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */
818 SUNXI_FUNCTION(0x3, "pata"), /* ATAD14 */
819 SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */
820 SUNXI_FUNCTION(0x5, "sim"), /* SCK */
821 SUNXI_FUNCTION_IRQ(0x6, 18), /* EINT18 */
822 SUNXI_FUNCTION(0x7, "csi1")), /* D18 */
823 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
824 SUNXI_FUNCTION(0x0, "gpio_in"),
825 SUNXI_FUNCTION(0x1, "gpio_out"),
826 SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */
827 SUNXI_FUNCTION(0x3, "pata"), /* ATAD15 */
828 SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */
829 SUNXI_FUNCTION(0x5, "sim"), /* SDA */
830 SUNXI_FUNCTION_IRQ(0x6, 19), /* EINT19 */
831 SUNXI_FUNCTION(0x7, "csi1")), /* D19 */
832 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
833 SUNXI_FUNCTION(0x0, "gpio_in"),
834 SUNXI_FUNCTION(0x1, "gpio_out"),
835 SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */
836 SUNXI_FUNCTION(0x3, "pata"), /* ATAOE */
837 SUNXI_FUNCTION(0x4, "can"), /* TX */
838 SUNXI_FUNCTION_IRQ(0x6, 20), /* EINT20 */
839 SUNXI_FUNCTION(0x7, "csi1")), /* D20 */
840 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
841 SUNXI_FUNCTION(0x0, "gpio_in"),
842 SUNXI_FUNCTION(0x1, "gpio_out"),
843 SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */
844 SUNXI_FUNCTION(0x3, "pata"), /* ATADREQ */
845 SUNXI_FUNCTION(0x4, "can"), /* RX */
846 SUNXI_FUNCTION_IRQ(0x6, 21), /* EINT21 */
847 SUNXI_FUNCTION(0x7, "csi1")), /* D21 */
848 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22),
849 SUNXI_FUNCTION(0x0, "gpio_in"),
850 SUNXI_FUNCTION(0x1, "gpio_out"),
851 SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */
852 SUNXI_FUNCTION(0x3, "pata"), /* ATADACK */
853 SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */
854 SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */
855 SUNXI_FUNCTION(0x7, "csi1")), /* D22 */
856 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23),
857 SUNXI_FUNCTION(0x0, "gpio_in"),
858 SUNXI_FUNCTION(0x1, "gpio_out"),
859 SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */
860 SUNXI_FUNCTION(0x3, "pata"), /* ATACS0 */
861 SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */
862 SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */
863 SUNXI_FUNCTION(0x7, "csi1")), /* D23 */
864 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24),
865 SUNXI_FUNCTION(0x0, "gpio_in"),
866 SUNXI_FUNCTION(0x1, "gpio_out"),
867 SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */
868 SUNXI_FUNCTION(0x3, "pata"), /* ATACS1 */
869 SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */
870 SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */
871 SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */
872 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25),
873 SUNXI_FUNCTION(0x0, "gpio_in"),
874 SUNXI_FUNCTION(0x1, "gpio_out"),
875 SUNXI_FUNCTION(0x2, "lcd1"), /* DE */
876 SUNXI_FUNCTION(0x3, "pata"), /* ATAIORDY */
877 SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */
878 SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */
879 SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */
880 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26),
881 SUNXI_FUNCTION(0x0, "gpio_in"),
882 SUNXI_FUNCTION(0x1, "gpio_out"),
883 SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */
884 SUNXI_FUNCTION(0x3, "pata"), /* ATAIOR */
885 SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */
886 SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */
887 SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */
888 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27),
889 SUNXI_FUNCTION(0x0, "gpio_in"),
890 SUNXI_FUNCTION(0x1, "gpio_out"),
891 SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */
892 SUNXI_FUNCTION(0x3, "pata"), /* ATAIOW */
893 SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */
894 SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */
895 SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */
896 /* Hole */
897 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 0),
898 SUNXI_FUNCTION(0x0, "gpio_in"),
899 SUNXI_FUNCTION(0x1, "gpio_out")),
900 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 1),
901 SUNXI_FUNCTION(0x0, "gpio_in"),
902 SUNXI_FUNCTION(0x1, "gpio_out")),
903 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 2),
904 SUNXI_FUNCTION(0x0, "gpio_in"),
905 SUNXI_FUNCTION(0x1, "gpio_out")),
906 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 3),
907 SUNXI_FUNCTION(0x0, "gpio_in"),
908 SUNXI_FUNCTION(0x1, "gpio_out"),
909 SUNXI_FUNCTION(0x2, "pwm")), /* PWM1 */
910 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 4),
911 SUNXI_FUNCTION(0x0, "gpio_in"),
912 SUNXI_FUNCTION(0x1, "gpio_out"),
913 SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */
914 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 5),
915 SUNXI_FUNCTION(0x0, "gpio_in"),
916 SUNXI_FUNCTION(0x1, "gpio_out"),
917 SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */
918 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 6),
919 SUNXI_FUNCTION(0x0, "gpio_in"),
920 SUNXI_FUNCTION(0x1, "gpio_out"),
921 SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */
922 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 7),
923 SUNXI_FUNCTION(0x0, "gpio_in"),
924 SUNXI_FUNCTION(0x1, "gpio_out"),
925 SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */
926 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 8),
927 SUNXI_FUNCTION(0x0, "gpio_in"),
928 SUNXI_FUNCTION(0x1, "gpio_out"),
929 SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */
930 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 9),
931 SUNXI_FUNCTION(0x0, "gpio_in"),
932 SUNXI_FUNCTION(0x1, "gpio_out"),
933 SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */
934 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 10),
935 SUNXI_FUNCTION(0x0, "gpio_in"),
936 SUNXI_FUNCTION(0x1, "gpio_out"),
937 SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
938 SUNXI_FUNCTION(0x3, "uart5"), /* TX */
939 SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
940 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11),
941 SUNXI_FUNCTION(0x0, "gpio_in"),
942 SUNXI_FUNCTION(0x1, "gpio_out"),
943 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
944 SUNXI_FUNCTION(0x3, "uart5"), /* RX */
945 SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
946 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12),
947 SUNXI_FUNCTION(0x0, "gpio_in"),
948 SUNXI_FUNCTION(0x1, "gpio_out"),
949 SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
950 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
951 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
952 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
953 SUNXI_FUNCTION(0x0, "gpio_in"),
954 SUNXI_FUNCTION(0x1, "gpio_out"),
955 SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
956 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
957 SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
958 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
959 SUNXI_FUNCTION(0x0, "gpio_in"),
960 SUNXI_FUNCTION(0x1, "gpio_out"),
961 SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
962 SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
963 SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */
964 SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
965 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15),
966 SUNXI_FUNCTION(0x0, "gpio_in"),
967 SUNXI_FUNCTION(0x1, "gpio_out"),
968 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
969 SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
970 SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */
971 SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
972 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16),
973 SUNXI_FUNCTION(0x0, "gpio_in"),
974 SUNXI_FUNCTION(0x1, "gpio_out"),
975 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
976 SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
977 SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
978 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 17),
979 SUNXI_FUNCTION(0x0, "gpio_in"),
980 SUNXI_FUNCTION(0x1, "gpio_out"),
981 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
982 SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
983 SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */
984 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18),
985 SUNXI_FUNCTION(0x0, "gpio_in"),
986 SUNXI_FUNCTION(0x1, "gpio_out"),
987 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
988 SUNXI_FUNCTION(0x3, "uart2"), /* TX */
989 SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */
990 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19),
991 SUNXI_FUNCTION(0x0, "gpio_in"),
992 SUNXI_FUNCTION(0x1, "gpio_out"),
993 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
994 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
995 SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */
996 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 20),
997 SUNXI_FUNCTION(0x0, "gpio_in"),
998 SUNXI_FUNCTION(0x1, "gpio_out"),
999 SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */
1000 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
1001 SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */
1002 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 21),
1003 SUNXI_FUNCTION(0x0, "gpio_in"),
1004 SUNXI_FUNCTION(0x1, "gpio_out"),
1005 SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */
1006 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
1007 SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */
1008};
1009
1010static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = {
1011 .pins = sun4i_a10_pins,
1012 .npins = ARRAY_SIZE(sun4i_a10_pins),
1013};
1014
1015static int sun4i_a10_pinctrl_probe(struct platform_device *pdev)
1016{
1017 return sunxi_pinctrl_init(pdev,
1018 &sun4i_a10_pinctrl_data);
1019}
1020
1021static struct of_device_id sun4i_a10_pinctrl_match[] = {
1022 { .compatible = "allwinner,sun4i-a10-pinctrl", },
1023 {}
1024};
1025MODULE_DEVICE_TABLE(of, sun4i_a10_pinctrl_match);
1026
1027static struct platform_driver sun4i_a10_pinctrl_driver = {
1028 .probe = sun4i_a10_pinctrl_probe,
1029 .driver = {
1030 .name = "sun4i-pinctrl",
1031 .owner = THIS_MODULE,
1032 .of_match_table = sun4i_a10_pinctrl_match,
1033 },
1034};
1035module_platform_driver(sun4i_a10_pinctrl_driver);
1036
1037MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
1038MODULE_DESCRIPTION("Allwinner A10 pinctrl driver");
1039MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c b/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c
new file mode 100644
index 000000000000..164d743f526c
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c
@@ -0,0 +1,690 @@
1/*
2 * Allwinner A10s SoCs pinctrl driver.
3 *
4 * Copyright (C) 2014 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
17#include <linux/pinctrl/pinctrl.h>
18
19#include "pinctrl-sunxi.h"
20
21static const struct sunxi_desc_pin sun5i_a10s_pins[] = {
22 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
23 SUNXI_FUNCTION(0x0, "gpio_in"),
24 SUNXI_FUNCTION(0x1, "gpio_out"),
25 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
26 SUNXI_FUNCTION(0x3, "ts0"), /* CLK */
27 SUNXI_FUNCTION(0x5, "keypad")), /* IN0 */
28 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
29 SUNXI_FUNCTION(0x0, "gpio_in"),
30 SUNXI_FUNCTION(0x1, "gpio_out"),
31 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
32 SUNXI_FUNCTION(0x3, "ts0"), /* ERR */
33 SUNXI_FUNCTION(0x5, "keypad")), /* IN1 */
34 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
35 SUNXI_FUNCTION(0x0, "gpio_in"),
36 SUNXI_FUNCTION(0x1, "gpio_out"),
37 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
38 SUNXI_FUNCTION(0x3, "ts0"), /* SYNC */
39 SUNXI_FUNCTION(0x5, "keypad")), /* IN2 */
40 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
41 SUNXI_FUNCTION(0x0, "gpio_in"),
42 SUNXI_FUNCTION(0x1, "gpio_out"),
43 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
44 SUNXI_FUNCTION(0x3, "ts0"), /* DLVD */
45 SUNXI_FUNCTION(0x5, "keypad")), /* IN3 */
46 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
47 SUNXI_FUNCTION(0x0, "gpio_in"),
48 SUNXI_FUNCTION(0x1, "gpio_out"),
49 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
50 SUNXI_FUNCTION(0x3, "ts0"), /* D0 */
51 SUNXI_FUNCTION(0x5, "keypad")), /* IN4 */
52 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
53 SUNXI_FUNCTION(0x0, "gpio_in"),
54 SUNXI_FUNCTION(0x1, "gpio_out"),
55 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
56 SUNXI_FUNCTION(0x3, "ts0"), /* D1 */
57 SUNXI_FUNCTION(0x5, "keypad")), /* IN5 */
58 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
59 SUNXI_FUNCTION(0x0, "gpio_in"),
60 SUNXI_FUNCTION(0x1, "gpio_out"),
61 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
62 SUNXI_FUNCTION(0x3, "ts0"), /* D2 */
63 SUNXI_FUNCTION(0x5, "keypad")), /* IN6 */
64 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
65 SUNXI_FUNCTION(0x0, "gpio_in"),
66 SUNXI_FUNCTION(0x1, "gpio_out"),
67 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
68 SUNXI_FUNCTION(0x3, "ts0"), /* D3 */
69 SUNXI_FUNCTION(0x5, "keypad")), /* IN7 */
70 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
71 SUNXI_FUNCTION(0x0, "gpio_in"),
72 SUNXI_FUNCTION(0x1, "gpio_out"),
73 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
74 SUNXI_FUNCTION(0x3, "ts0"), /* D4 */
75 SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
76 SUNXI_FUNCTION(0x5, "keypad")), /* OUT0 */
77 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
78 SUNXI_FUNCTION(0x0, "gpio_in"),
79 SUNXI_FUNCTION(0x1, "gpio_out"),
80 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
81 SUNXI_FUNCTION(0x3, "ts0"), /* D5 */
82 SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
83 SUNXI_FUNCTION(0x5, "keypad")), /* OUT1 */
84 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
85 SUNXI_FUNCTION(0x0, "gpio_in"),
86 SUNXI_FUNCTION(0x1, "gpio_out"),
87 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
88 SUNXI_FUNCTION(0x3, "ts0"), /* D6 */
89 SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
90 SUNXI_FUNCTION(0x5, "keypad")), /* OUT2 */
91 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
92 SUNXI_FUNCTION(0x0, "gpio_in"),
93 SUNXI_FUNCTION(0x1, "gpio_out"),
94 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
95 SUNXI_FUNCTION(0x3, "ts0"), /* D7 */
96 SUNXI_FUNCTION(0x4, "uart1"), /* RING */
97 SUNXI_FUNCTION(0x5, "keypad")), /* OUT3 */
98 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
99 SUNXI_FUNCTION(0x0, "gpio_in"),
100 SUNXI_FUNCTION(0x1, "gpio_out"),
101 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
102 SUNXI_FUNCTION(0x3, "uart1"), /* TX */
103 SUNXI_FUNCTION(0x5, "keypad")), /* OUT4 */
104 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
105 SUNXI_FUNCTION(0x0, "gpio_in"),
106 SUNXI_FUNCTION(0x1, "gpio_out"),
107 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
108 SUNXI_FUNCTION(0x3, "uart1"), /* RX */
109 SUNXI_FUNCTION(0x5, "keypad")), /* OUT5 */
110 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
111 SUNXI_FUNCTION(0x0, "gpio_in"),
112 SUNXI_FUNCTION(0x1, "gpio_out"),
113 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
114 SUNXI_FUNCTION(0x3, "uart1"), /* CTS */
115 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
116 SUNXI_FUNCTION(0x5, "keypad")), /* OUT6 */
117 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
118 SUNXI_FUNCTION(0x0, "gpio_in"),
119 SUNXI_FUNCTION(0x1, "gpio_out"),
120 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
121 SUNXI_FUNCTION(0x3, "uart1"), /* RTS */
122 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
123 SUNXI_FUNCTION(0x5, "keypad")), /* OUT7 */
124 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
125 SUNXI_FUNCTION(0x0, "gpio_in"),
126 SUNXI_FUNCTION(0x1, "gpio_out"),
127 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
128 SUNXI_FUNCTION(0x3, "uart2")), /* TX */
129 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
130 SUNXI_FUNCTION(0x0, "gpio_in"),
131 SUNXI_FUNCTION(0x1, "gpio_out"),
132 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
133 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
134 SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */
135 /* Hole */
136 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
137 SUNXI_FUNCTION(0x0, "gpio_in"),
138 SUNXI_FUNCTION(0x1, "gpio_out"),
139 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
140 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
141 SUNXI_FUNCTION(0x0, "gpio_in"),
142 SUNXI_FUNCTION(0x1, "gpio_out"),
143 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
144 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
145 SUNXI_FUNCTION(0x0, "gpio_in"),
146 SUNXI_FUNCTION(0x1, "gpio_out"),
147 SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */
148 SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */
149 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
150 SUNXI_FUNCTION(0x0, "gpio_in"),
151 SUNXI_FUNCTION(0x1, "gpio_out"),
152 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
153 SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */
154 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
155 SUNXI_FUNCTION(0x0, "gpio_in"),
156 SUNXI_FUNCTION(0x1, "gpio_out"),
157 SUNXI_FUNCTION(0x2, "ir0"), /* RX */
158 SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */
159 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
160 SUNXI_FUNCTION(0x0, "gpio_in"),
161 SUNXI_FUNCTION(0x1, "gpio_out"),
162 SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
163 SUNXI_FUNCTION_IRQ(0x6, 19)), /* EINT19 */
164 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
165 SUNXI_FUNCTION(0x0, "gpio_in"),
166 SUNXI_FUNCTION(0x1, "gpio_out"),
167 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
168 SUNXI_FUNCTION_IRQ(0x6, 20)), /* EINT20 */
169 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
170 SUNXI_FUNCTION(0x0, "gpio_in"),
171 SUNXI_FUNCTION(0x1, "gpio_out"),
172 SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */
173 SUNXI_FUNCTION_IRQ(0x6, 21)), /* EINT21 */
174 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
175 SUNXI_FUNCTION(0x0, "gpio_in"),
176 SUNXI_FUNCTION(0x1, "gpio_out"),
177 SUNXI_FUNCTION(0x2, "i2s"), /* DO */
178 SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
179 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
180 SUNXI_FUNCTION(0x0, "gpio_in"),
181 SUNXI_FUNCTION(0x1, "gpio_out"),
182 SUNXI_FUNCTION(0x2, "i2s"), /* DI */
183 SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
184 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
185 SUNXI_FUNCTION(0x0, "gpio_in"),
186 SUNXI_FUNCTION(0x1, "gpio_out"),
187 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
188 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
189 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
190 SUNXI_FUNCTION(0x0, "gpio_in"),
191 SUNXI_FUNCTION(0x1, "gpio_out"),
192 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
193 SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
194 SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
195 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
196 SUNXI_FUNCTION(0x0, "gpio_in"),
197 SUNXI_FUNCTION(0x1, "gpio_out"),
198 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
199 SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
200 SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
201 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
202 SUNXI_FUNCTION(0x0, "gpio_in"),
203 SUNXI_FUNCTION(0x1, "gpio_out"),
204 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
205 SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
206 SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
207 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
208 SUNXI_FUNCTION(0x0, "gpio_in"),
209 SUNXI_FUNCTION(0x1, "gpio_out"),
210 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
211 SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
212 SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
213 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
214 SUNXI_FUNCTION(0x0, "gpio_in"),
215 SUNXI_FUNCTION(0x1, "gpio_out"),
216 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
217 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
218 SUNXI_FUNCTION(0x0, "gpio_in"),
219 SUNXI_FUNCTION(0x1, "gpio_out"),
220 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
221 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
222 SUNXI_FUNCTION(0x0, "gpio_in"),
223 SUNXI_FUNCTION(0x1, "gpio_out"),
224 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
225 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
226 SUNXI_FUNCTION(0x0, "gpio_in"),
227 SUNXI_FUNCTION(0x1, "gpio_out"),
228 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
229 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 19),
230 SUNXI_FUNCTION(0x0, "gpio_in"),
231 SUNXI_FUNCTION(0x1, "gpio_out"),
232 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
233 SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */
234 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20),
235 SUNXI_FUNCTION(0x0, "gpio_in"),
236 SUNXI_FUNCTION(0x1, "gpio_out"),
237 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
238 SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */
239 /* Hole */
240 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
241 SUNXI_FUNCTION(0x0, "gpio_in"),
242 SUNXI_FUNCTION(0x1, "gpio_out"),
243 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
244 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
245 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
246 SUNXI_FUNCTION(0x0, "gpio_in"),
247 SUNXI_FUNCTION(0x1, "gpio_out"),
248 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
249 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
250 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
251 SUNXI_FUNCTION(0x0, "gpio_in"),
252 SUNXI_FUNCTION(0x1, "gpio_out"),
253 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
254 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
255 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
256 SUNXI_FUNCTION(0x0, "gpio_in"),
257 SUNXI_FUNCTION(0x1, "gpio_out"),
258 SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
259 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
260 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
261 SUNXI_FUNCTION(0x0, "gpio_in"),
262 SUNXI_FUNCTION(0x1, "gpio_out"),
263 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
264 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
265 SUNXI_FUNCTION(0x0, "gpio_in"),
266 SUNXI_FUNCTION(0x1, "gpio_out"),
267 SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
268 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
269 SUNXI_FUNCTION(0x0, "gpio_in"),
270 SUNXI_FUNCTION(0x1, "gpio_out"),
271 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
272 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
273 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
274 SUNXI_FUNCTION(0x0, "gpio_in"),
275 SUNXI_FUNCTION(0x1, "gpio_out"),
276 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
277 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
278 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
279 SUNXI_FUNCTION(0x0, "gpio_in"),
280 SUNXI_FUNCTION(0x1, "gpio_out"),
281 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
282 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
283 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
284 SUNXI_FUNCTION(0x0, "gpio_in"),
285 SUNXI_FUNCTION(0x1, "gpio_out"),
286 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
287 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
288 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
289 SUNXI_FUNCTION(0x0, "gpio_in"),
290 SUNXI_FUNCTION(0x1, "gpio_out"),
291 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
292 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
293 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
294 SUNXI_FUNCTION(0x0, "gpio_in"),
295 SUNXI_FUNCTION(0x1, "gpio_out"),
296 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
297 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
298 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
299 SUNXI_FUNCTION(0x0, "gpio_in"),
300 SUNXI_FUNCTION(0x1, "gpio_out"),
301 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
302 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
303 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
304 SUNXI_FUNCTION(0x0, "gpio_in"),
305 SUNXI_FUNCTION(0x1, "gpio_out"),
306 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
307 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
308 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
309 SUNXI_FUNCTION(0x0, "gpio_in"),
310 SUNXI_FUNCTION(0x1, "gpio_out"),
311 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
312 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
313 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
314 SUNXI_FUNCTION(0x0, "gpio_in"),
315 SUNXI_FUNCTION(0x1, "gpio_out"),
316 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
317 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
318 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
319 SUNXI_FUNCTION(0x0, "gpio_in"),
320 SUNXI_FUNCTION(0x1, "gpio_out"),
321 SUNXI_FUNCTION(0x2, "nand0"), /* NWP */
322 SUNXI_FUNCTION(0x4, "uart3")), /* TX */
323 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
324 SUNXI_FUNCTION(0x0, "gpio_in"),
325 SUNXI_FUNCTION(0x1, "gpio_out"),
326 SUNXI_FUNCTION(0x2, "nand0"), /* NCE2 */
327 SUNXI_FUNCTION(0x4, "uart3")), /* RX */
328 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
329 SUNXI_FUNCTION(0x0, "gpio_in"),
330 SUNXI_FUNCTION(0x1, "gpio_out"),
331 SUNXI_FUNCTION(0x2, "nand0"), /* NCE3 */
332 SUNXI_FUNCTION(0x3, "uart2"), /* TX */
333 SUNXI_FUNCTION(0x4, "uart3")), /* CTS */
334 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
335 SUNXI_FUNCTION(0x0, "gpio_in"),
336 SUNXI_FUNCTION(0x1, "gpio_out"),
337 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
338 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
339 SUNXI_FUNCTION(0x4, "uart3")), /* RTS */
340 /* Hole */
341 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
342 SUNXI_FUNCTION(0x0, "gpio_in"),
343 SUNXI_FUNCTION(0x1, "gpio_out"),
344 SUNXI_FUNCTION(0x2, "lcd0")), /* D0 */
345 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
346 SUNXI_FUNCTION(0x0, "gpio_in"),
347 SUNXI_FUNCTION(0x1, "gpio_out"),
348 SUNXI_FUNCTION(0x2, "lcd0")), /* D1 */
349 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
350 SUNXI_FUNCTION(0x0, "gpio_in"),
351 SUNXI_FUNCTION(0x1, "gpio_out"),
352 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
353 SUNXI_FUNCTION(0x3, "uart2")), /* TX */
354 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
355 SUNXI_FUNCTION(0x0, "gpio_in"),
356 SUNXI_FUNCTION(0x1, "gpio_out"),
357 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
358 SUNXI_FUNCTION(0x3, "uart2")), /* RX */
359 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
360 SUNXI_FUNCTION(0x0, "gpio_in"),
361 SUNXI_FUNCTION(0x1, "gpio_out"),
362 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
363 SUNXI_FUNCTION(0x3, "uart2")), /* CTS */
364 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
365 SUNXI_FUNCTION(0x0, "gpio_in"),
366 SUNXI_FUNCTION(0x1, "gpio_out"),
367 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
368 SUNXI_FUNCTION(0x3, "uart2")), /* RTS */
369 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
370 SUNXI_FUNCTION(0x0, "gpio_in"),
371 SUNXI_FUNCTION(0x1, "gpio_out"),
372 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
373 SUNXI_FUNCTION(0x3, "emac")), /* ECRS */
374 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
375 SUNXI_FUNCTION(0x0, "gpio_in"),
376 SUNXI_FUNCTION(0x1, "gpio_out"),
377 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
378 SUNXI_FUNCTION(0x3, "emac")), /* ECOL */
379 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
380 SUNXI_FUNCTION(0x0, "gpio_in"),
381 SUNXI_FUNCTION(0x1, "gpio_out"),
382 SUNXI_FUNCTION(0x2, "lcd0")), /* D8 */
383 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
384 SUNXI_FUNCTION(0x0, "gpio_in"),
385 SUNXI_FUNCTION(0x1, "gpio_out"),
386 SUNXI_FUNCTION(0x2, "lcd0")), /* D9 */
387 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
388 SUNXI_FUNCTION(0x0, "gpio_in"),
389 SUNXI_FUNCTION(0x1, "gpio_out"),
390 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
391 SUNXI_FUNCTION(0x3, "emac")), /* ERXD0 */
392 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
393 SUNXI_FUNCTION(0x0, "gpio_in"),
394 SUNXI_FUNCTION(0x1, "gpio_out"),
395 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
396 SUNXI_FUNCTION(0x3, "emac")), /* ERXD1 */
397 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
398 SUNXI_FUNCTION(0x0, "gpio_in"),
399 SUNXI_FUNCTION(0x1, "gpio_out"),
400 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
401 SUNXI_FUNCTION(0x3, "emac")), /* ERXD2 */
402 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
403 SUNXI_FUNCTION(0x0, "gpio_in"),
404 SUNXI_FUNCTION(0x1, "gpio_out"),
405 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
406 SUNXI_FUNCTION(0x3, "emac")), /* ERXD3 */
407 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
408 SUNXI_FUNCTION(0x0, "gpio_in"),
409 SUNXI_FUNCTION(0x1, "gpio_out"),
410 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
411 SUNXI_FUNCTION(0x3, "emac")), /* ERXCK */
412 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
413 SUNXI_FUNCTION(0x0, "gpio_in"),
414 SUNXI_FUNCTION(0x1, "gpio_out"),
415 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
416 SUNXI_FUNCTION(0x3, "emac")), /* ERXERR */
417 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
418 SUNXI_FUNCTION(0x0, "gpio_in"),
419 SUNXI_FUNCTION(0x1, "gpio_out"),
420 SUNXI_FUNCTION(0x2, "lcd0")), /* D16 */
421 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
422 SUNXI_FUNCTION(0x0, "gpio_in"),
423 SUNXI_FUNCTION(0x1, "gpio_out"),
424 SUNXI_FUNCTION(0x2, "lcd0")), /* D17 */
425 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
426 SUNXI_FUNCTION(0x0, "gpio_in"),
427 SUNXI_FUNCTION(0x1, "gpio_out"),
428 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
429 SUNXI_FUNCTION(0x3, "emac")), /* ERXDV */
430 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
431 SUNXI_FUNCTION(0x0, "gpio_in"),
432 SUNXI_FUNCTION(0x1, "gpio_out"),
433 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
434 SUNXI_FUNCTION(0x3, "emac")), /* ETXD0 */
435 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
436 SUNXI_FUNCTION(0x0, "gpio_in"),
437 SUNXI_FUNCTION(0x1, "gpio_out"),
438 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
439 SUNXI_FUNCTION(0x3, "emac")), /* ETXD1 */
440 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
441 SUNXI_FUNCTION(0x0, "gpio_in"),
442 SUNXI_FUNCTION(0x1, "gpio_out"),
443 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
444 SUNXI_FUNCTION(0x3, "emac")), /* ETXD2 */
445 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
446 SUNXI_FUNCTION(0x0, "gpio_in"),
447 SUNXI_FUNCTION(0x1, "gpio_out"),
448 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
449 SUNXI_FUNCTION(0x3, "emac")), /* ETXD3 */
450 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
451 SUNXI_FUNCTION(0x0, "gpio_in"),
452 SUNXI_FUNCTION(0x1, "gpio_out"),
453 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
454 SUNXI_FUNCTION(0x3, "emac")), /* ETXEN */
455 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
456 SUNXI_FUNCTION(0x0, "gpio_in"),
457 SUNXI_FUNCTION(0x1, "gpio_out"),
458 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
459 SUNXI_FUNCTION(0x3, "emac")), /* ETXCK */
460 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
461 SUNXI_FUNCTION(0x0, "gpio_in"),
462 SUNXI_FUNCTION(0x1, "gpio_out"),
463 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
464 SUNXI_FUNCTION(0x3, "emac")), /* ETXERR */
465 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
466 SUNXI_FUNCTION(0x0, "gpio_in"),
467 SUNXI_FUNCTION(0x1, "gpio_out"),
468 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
469 SUNXI_FUNCTION(0x3, "emac")), /* EMDC */
470 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
471 SUNXI_FUNCTION(0x0, "gpio_in"),
472 SUNXI_FUNCTION(0x1, "gpio_out"),
473 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
474 SUNXI_FUNCTION(0x3, "emac")), /* EMDIO */
475 /* Hole */
476 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
477 SUNXI_FUNCTION(0x0, "gpio_in"),
478 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
479 SUNXI_FUNCTION(0x3, "csi0"), /* PCK */
480 SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */
481 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
482 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
483 SUNXI_FUNCTION(0x0, "gpio_in"),
484 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
485 SUNXI_FUNCTION(0x3, "csi0"), /* CK */
486 SUNXI_FUNCTION(0x4, "spi2"), /* CLK */
487 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
488 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
489 SUNXI_FUNCTION(0x0, "gpio_in"),
490 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
491 SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */
492 SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */
493 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
494 SUNXI_FUNCTION(0x0, "gpio_in"),
495 SUNXI_FUNCTION(0x1, "gpio_out"),
496 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
497 SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */
498 SUNXI_FUNCTION(0x4, "spi2")), /* MISO */
499 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
500 SUNXI_FUNCTION(0x0, "gpio_in"),
501 SUNXI_FUNCTION(0x1, "gpio_out"),
502 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
503 SUNXI_FUNCTION(0x3, "csi0"), /* D0 */
504 SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */
505 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
506 SUNXI_FUNCTION(0x0, "gpio_in"),
507 SUNXI_FUNCTION(0x1, "gpio_out"),
508 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
509 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
510 SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */
511 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
512 SUNXI_FUNCTION(0x0, "gpio_in"),
513 SUNXI_FUNCTION(0x1, "gpio_out"),
514 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
515 SUNXI_FUNCTION(0x3, "csi0"), /* D2 */
516 SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */
517 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
518 SUNXI_FUNCTION(0x0, "gpio_in"),
519 SUNXI_FUNCTION(0x1, "gpio_out"),
520 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
521 SUNXI_FUNCTION(0x3, "csi0"), /* D3 */
522 SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */
523 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
524 SUNXI_FUNCTION(0x0, "gpio_in"),
525 SUNXI_FUNCTION(0x1, "gpio_out"),
526 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
527 SUNXI_FUNCTION(0x3, "csi0"), /* D4 */
528 SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */
529 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
530 SUNXI_FUNCTION(0x0, "gpio_in"),
531 SUNXI_FUNCTION(0x1, "gpio_out"),
532 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
533 SUNXI_FUNCTION(0x3, "csi0"), /* D5 */
534 SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */
535 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
536 SUNXI_FUNCTION(0x0, "gpio_in"),
537 SUNXI_FUNCTION(0x1, "gpio_out"),
538 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
539 SUNXI_FUNCTION(0x3, "csi0"), /* D6 */
540 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
541 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
542 SUNXI_FUNCTION(0x0, "gpio_in"),
543 SUNXI_FUNCTION(0x1, "gpio_out"),
544 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
545 SUNXI_FUNCTION(0x3, "csi0"), /* D7 */
546 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
547 /* Hole */
548 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
549 SUNXI_FUNCTION(0x0, "gpio_in"),
550 SUNXI_FUNCTION(0x1, "gpio_out"),
551 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
552 SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
553 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
554 SUNXI_FUNCTION(0x0, "gpio_in"),
555 SUNXI_FUNCTION(0x1, "gpio_out"),
556 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
557 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
558 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
559 SUNXI_FUNCTION(0x0, "gpio_in"),
560 SUNXI_FUNCTION(0x1, "gpio_out"),
561 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
562 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
563 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
564 SUNXI_FUNCTION(0x0, "gpio_in"),
565 SUNXI_FUNCTION(0x1, "gpio_out"),
566 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
567 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
568 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
569 SUNXI_FUNCTION(0x0, "gpio_in"),
570 SUNXI_FUNCTION(0x1, "gpio_out"),
571 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
572 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
573 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
574 SUNXI_FUNCTION(0x0, "gpio_in"),
575 SUNXI_FUNCTION(0x1, "gpio_out"),
576 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
577 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
578 /* Hole */
579 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
580 SUNXI_FUNCTION(0x0, "gpio_in"),
581 SUNXI_FUNCTION(0x2, "gps"), /* CLK */
582 SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */
583 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
584 SUNXI_FUNCTION(0x0, "gpio_in"),
585 SUNXI_FUNCTION(0x2, "gps"), /* SIGN */
586 SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */
587 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
588 SUNXI_FUNCTION(0x0, "gpio_in"),
589 SUNXI_FUNCTION(0x2, "gps"), /* MAG */
590 SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */
591 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
592 SUNXI_FUNCTION(0x0, "gpio_in"),
593 SUNXI_FUNCTION(0x1, "gpio_out"),
594 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
595 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
596 SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */
597 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
598 SUNXI_FUNCTION(0x0, "gpio_in"),
599 SUNXI_FUNCTION(0x1, "gpio_out"),
600 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
601 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
602 SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */
603 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
604 SUNXI_FUNCTION(0x0, "gpio_in"),
605 SUNXI_FUNCTION(0x1, "gpio_out"),
606 SUNXI_FUNCTION(0x2, "mmc1"), /* DO */
607 SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
608 SUNXI_FUNCTION_IRQ(0x6, 5)), /* EINT5 */
609 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
610 SUNXI_FUNCTION(0x0, "gpio_in"),
611 SUNXI_FUNCTION(0x1, "gpio_out"),
612 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
613 SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
614 SUNXI_FUNCTION(0x5, "uart2"), /* RTS */
615 SUNXI_FUNCTION_IRQ(0x6, 6)), /* EINT6 */
616 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
617 SUNXI_FUNCTION(0x0, "gpio_in"),
618 SUNXI_FUNCTION(0x1, "gpio_out"),
619 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
620 SUNXI_FUNCTION(0x5, "uart2"), /* TX */
621 SUNXI_FUNCTION_IRQ(0x6, 7)), /* EINT7 */
622 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
623 SUNXI_FUNCTION(0x0, "gpio_in"),
624 SUNXI_FUNCTION(0x1, "gpio_out"),
625 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
626 SUNXI_FUNCTION(0x5, "uart2"), /* RX */
627 SUNXI_FUNCTION_IRQ(0x6, 8)), /* EINT8 */
628 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
629 SUNXI_FUNCTION(0x0, "gpio_in"),
630 SUNXI_FUNCTION(0x1, "gpio_out"),
631 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
632 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
633 SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */
634 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
635 SUNXI_FUNCTION(0x0, "gpio_in"),
636 SUNXI_FUNCTION(0x1, "gpio_out"),
637 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
638 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
639 SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */
640 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
641 SUNXI_FUNCTION(0x0, "gpio_in"),
642 SUNXI_FUNCTION(0x1, "gpio_out"),
643 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
644 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
645 SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */
646 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
647 SUNXI_FUNCTION(0x0, "gpio_in"),
648 SUNXI_FUNCTION(0x1, "gpio_out"),
649 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
650 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
651 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
652 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
653 SUNXI_FUNCTION(0x0, "gpio_in"),
654 SUNXI_FUNCTION(0x1, "gpio_out"),
655 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
656 SUNXI_FUNCTION(0x3, "uart3"), /* PWM1 */
657 SUNXI_FUNCTION(0x5, "uart2"), /* CTS */
658 SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
659};
660
661static const struct sunxi_pinctrl_desc sun5i_a10s_pinctrl_data = {
662 .pins = sun5i_a10s_pins,
663 .npins = ARRAY_SIZE(sun5i_a10s_pins),
664};
665
666static int sun5i_a10s_pinctrl_probe(struct platform_device *pdev)
667{
668 return sunxi_pinctrl_init(pdev,
669 &sun5i_a10s_pinctrl_data);
670}
671
672static struct of_device_id sun5i_a10s_pinctrl_match[] = {
673 { .compatible = "allwinner,sun5i-a10s-pinctrl", },
674 {}
675};
676MODULE_DEVICE_TABLE(of, sun5i_a10s_pinctrl_match);
677
678static struct platform_driver sun5i_a10s_pinctrl_driver = {
679 .probe = sun5i_a10s_pinctrl_probe,
680 .driver = {
681 .name = "sun5i-a10s-pinctrl",
682 .owner = THIS_MODULE,
683 .of_match_table = sun5i_a10s_pinctrl_match,
684 },
685};
686module_platform_driver(sun5i_a10s_pinctrl_driver);
687
688MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
689MODULE_DESCRIPTION("Allwinner A10s pinctrl driver");
690MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c b/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c
new file mode 100644
index 000000000000..1188a2b7b988
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c
@@ -0,0 +1,411 @@
1/*
2 * Allwinner A13 SoCs pinctrl driver.
3 *
4 * Copyright (C) 2014 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
17#include <linux/pinctrl/pinctrl.h>
18
19#include "pinctrl-sunxi.h"
20
21static const struct sunxi_desc_pin sun5i_a13_pins[] = {
22 /* Hole */
23 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
24 SUNXI_FUNCTION(0x0, "gpio_in"),
25 SUNXI_FUNCTION(0x1, "gpio_out"),
26 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
27 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
28 SUNXI_FUNCTION(0x0, "gpio_in"),
29 SUNXI_FUNCTION(0x1, "gpio_out"),
30 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
31 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
32 SUNXI_FUNCTION(0x0, "gpio_in"),
33 SUNXI_FUNCTION(0x1, "gpio_out"),
34 SUNXI_FUNCTION(0x2, "pwm"),
35 SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */
36 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
37 SUNXI_FUNCTION(0x0, "gpio_in"),
38 SUNXI_FUNCTION(0x1, "gpio_out"),
39 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
40 SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */
41 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
42 SUNXI_FUNCTION(0x0, "gpio_in"),
43 SUNXI_FUNCTION(0x1, "gpio_out"),
44 SUNXI_FUNCTION(0x2, "ir0"), /* RX */
45 SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */
46 /* Hole */
47 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
48 SUNXI_FUNCTION(0x0, "gpio_in"),
49 SUNXI_FUNCTION(0x1, "gpio_out"),
50 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
51 SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
52 /* Hole */
53 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
54 SUNXI_FUNCTION(0x0, "gpio_in"),
55 SUNXI_FUNCTION(0x1, "gpio_out"),
56 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
57 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
58 SUNXI_FUNCTION(0x0, "gpio_in"),
59 SUNXI_FUNCTION(0x1, "gpio_out"),
60 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
61 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
62 SUNXI_FUNCTION(0x0, "gpio_in"),
63 SUNXI_FUNCTION(0x1, "gpio_out"),
64 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
65 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
66 SUNXI_FUNCTION(0x0, "gpio_in"),
67 SUNXI_FUNCTION(0x1, "gpio_out"),
68 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
69 /* Hole */
70 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
71 SUNXI_FUNCTION(0x0, "gpio_in"),
72 SUNXI_FUNCTION(0x1, "gpio_out"),
73 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
74 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
75 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
76 SUNXI_FUNCTION(0x0, "gpio_in"),
77 SUNXI_FUNCTION(0x1, "gpio_out"),
78 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
79 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
80 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
81 SUNXI_FUNCTION(0x0, "gpio_in"),
82 SUNXI_FUNCTION(0x1, "gpio_out"),
83 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
84 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
85 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
86 SUNXI_FUNCTION(0x0, "gpio_in"),
87 SUNXI_FUNCTION(0x1, "gpio_out"),
88 SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
89 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
90 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
91 SUNXI_FUNCTION(0x0, "gpio_in"),
92 SUNXI_FUNCTION(0x1, "gpio_out"),
93 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
94 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
95 SUNXI_FUNCTION(0x0, "gpio_in"),
96 SUNXI_FUNCTION(0x1, "gpio_out"),
97 SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
98 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
99 SUNXI_FUNCTION(0x0, "gpio_in"),
100 SUNXI_FUNCTION(0x1, "gpio_out"),
101 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
102 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
103 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
104 SUNXI_FUNCTION(0x0, "gpio_in"),
105 SUNXI_FUNCTION(0x1, "gpio_out"),
106 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
107 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
108 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
109 SUNXI_FUNCTION(0x0, "gpio_in"),
110 SUNXI_FUNCTION(0x1, "gpio_out"),
111 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
112 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
113 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
114 SUNXI_FUNCTION(0x0, "gpio_in"),
115 SUNXI_FUNCTION(0x1, "gpio_out"),
116 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
117 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
118 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
119 SUNXI_FUNCTION(0x0, "gpio_in"),
120 SUNXI_FUNCTION(0x1, "gpio_out"),
121 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
122 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
123 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
124 SUNXI_FUNCTION(0x0, "gpio_in"),
125 SUNXI_FUNCTION(0x1, "gpio_out"),
126 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
127 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
128 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
129 SUNXI_FUNCTION(0x0, "gpio_in"),
130 SUNXI_FUNCTION(0x1, "gpio_out"),
131 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
132 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
133 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
134 SUNXI_FUNCTION(0x0, "gpio_in"),
135 SUNXI_FUNCTION(0x1, "gpio_out"),
136 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
137 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
138 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
139 SUNXI_FUNCTION(0x0, "gpio_in"),
140 SUNXI_FUNCTION(0x1, "gpio_out"),
141 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
142 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
143 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
144 SUNXI_FUNCTION(0x0, "gpio_in"),
145 SUNXI_FUNCTION(0x1, "gpio_out"),
146 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
147 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
148 /* Hole */
149 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
150 SUNXI_FUNCTION(0x0, "gpio_in"),
151 SUNXI_FUNCTION(0x1, "gpio_out"),
152 SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */
153 SUNXI_FUNCTION(0x4, "uart3")), /* RTS */
154 /* Hole */
155 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
156 SUNXI_FUNCTION(0x0, "gpio_in"),
157 SUNXI_FUNCTION(0x1, "gpio_out"),
158 SUNXI_FUNCTION(0x2, "lcd0")), /* D2 */
159 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
160 SUNXI_FUNCTION(0x0, "gpio_in"),
161 SUNXI_FUNCTION(0x1, "gpio_out"),
162 SUNXI_FUNCTION(0x2, "lcd0")), /* D3 */
163 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
164 SUNXI_FUNCTION(0x0, "gpio_in"),
165 SUNXI_FUNCTION(0x1, "gpio_out"),
166 SUNXI_FUNCTION(0x2, "lcd0")), /* D4 */
167 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
168 SUNXI_FUNCTION(0x0, "gpio_in"),
169 SUNXI_FUNCTION(0x1, "gpio_out"),
170 SUNXI_FUNCTION(0x2, "lcd0")), /* D5 */
171 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
172 SUNXI_FUNCTION(0x0, "gpio_in"),
173 SUNXI_FUNCTION(0x1, "gpio_out"),
174 SUNXI_FUNCTION(0x2, "lcd0")), /* D6 */
175 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
176 SUNXI_FUNCTION(0x0, "gpio_in"),
177 SUNXI_FUNCTION(0x1, "gpio_out"),
178 SUNXI_FUNCTION(0x2, "lcd0")), /* D7 */
179 /* Hole */
180 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
181 SUNXI_FUNCTION(0x0, "gpio_in"),
182 SUNXI_FUNCTION(0x1, "gpio_out"),
183 SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */
184 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
185 SUNXI_FUNCTION(0x0, "gpio_in"),
186 SUNXI_FUNCTION(0x1, "gpio_out"),
187 SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */
188 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
189 SUNXI_FUNCTION(0x0, "gpio_in"),
190 SUNXI_FUNCTION(0x1, "gpio_out"),
191 SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */
192 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
193 SUNXI_FUNCTION(0x0, "gpio_in"),
194 SUNXI_FUNCTION(0x1, "gpio_out"),
195 SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */
196 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
197 SUNXI_FUNCTION(0x0, "gpio_in"),
198 SUNXI_FUNCTION(0x1, "gpio_out"),
199 SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
200 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
201 SUNXI_FUNCTION(0x0, "gpio_in"),
202 SUNXI_FUNCTION(0x1, "gpio_out"),
203 SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
204 /* Hole */
205 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
206 SUNXI_FUNCTION(0x0, "gpio_in"),
207 SUNXI_FUNCTION(0x1, "gpio_out"),
208 SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */
209 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
210 SUNXI_FUNCTION(0x0, "gpio_in"),
211 SUNXI_FUNCTION(0x1, "gpio_out"),
212 SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */
213 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
214 SUNXI_FUNCTION(0x0, "gpio_in"),
215 SUNXI_FUNCTION(0x1, "gpio_out"),
216 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
217 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
218 SUNXI_FUNCTION(0x0, "gpio_in"),
219 SUNXI_FUNCTION(0x1, "gpio_out"),
220 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
221 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
222 SUNXI_FUNCTION(0x0, "gpio_in"),
223 SUNXI_FUNCTION(0x1, "gpio_out"),
224 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
225 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
226 SUNXI_FUNCTION(0x0, "gpio_in"),
227 SUNXI_FUNCTION(0x1, "gpio_out"),
228 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
229 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
230 SUNXI_FUNCTION(0x0, "gpio_in"),
231 SUNXI_FUNCTION(0x1, "gpio_out"),
232 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
233 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
234 SUNXI_FUNCTION(0x0, "gpio_in"),
235 SUNXI_FUNCTION(0x1, "gpio_out"),
236 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
237 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
238 SUNXI_FUNCTION(0x0, "gpio_in"),
239 SUNXI_FUNCTION(0x1, "gpio_out"),
240 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
241 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
242 SUNXI_FUNCTION(0x0, "gpio_in"),
243 SUNXI_FUNCTION(0x1, "gpio_out"),
244 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
245 /* Hole */
246 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
247 SUNXI_FUNCTION(0x0, "gpio_in"),
248 SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */
249 SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */
250 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
251 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
252 SUNXI_FUNCTION(0x0, "gpio_in"),
253 SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */
254 SUNXI_FUNCTION(0x4, "spi2"), /* CLK */
255 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
256 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
257 SUNXI_FUNCTION(0x0, "gpio_in"),
258 SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */
259 SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */
260 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
261 SUNXI_FUNCTION(0x0, "gpio_in"),
262 SUNXI_FUNCTION(0x1, "gpio_out"),
263 SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */
264 SUNXI_FUNCTION(0x4, "spi2")), /* MISO */
265 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
266 SUNXI_FUNCTION(0x0, "gpio_in"),
267 SUNXI_FUNCTION(0x1, "gpio_out"),
268 SUNXI_FUNCTION(0x3, "csi0"), /* D0 */
269 SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */
270 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
271 SUNXI_FUNCTION(0x0, "gpio_in"),
272 SUNXI_FUNCTION(0x1, "gpio_out"),
273 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
274 SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */
275 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
276 SUNXI_FUNCTION(0x0, "gpio_in"),
277 SUNXI_FUNCTION(0x1, "gpio_out"),
278 SUNXI_FUNCTION(0x3, "csi0"), /* D2 */
279 SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */
280 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
281 SUNXI_FUNCTION(0x0, "gpio_in"),
282 SUNXI_FUNCTION(0x1, "gpio_out"),
283 SUNXI_FUNCTION(0x3, "csi0"), /* D3 */
284 SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */
285 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
286 SUNXI_FUNCTION(0x0, "gpio_in"),
287 SUNXI_FUNCTION(0x1, "gpio_out"),
288 SUNXI_FUNCTION(0x3, "csi0"), /* D4 */
289 SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */
290 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
291 SUNXI_FUNCTION(0x0, "gpio_in"),
292 SUNXI_FUNCTION(0x1, "gpio_out"),
293 SUNXI_FUNCTION(0x3, "csi0"), /* D5 */
294 SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */
295 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
296 SUNXI_FUNCTION(0x0, "gpio_in"),
297 SUNXI_FUNCTION(0x1, "gpio_out"),
298 SUNXI_FUNCTION(0x3, "csi0"), /* D6 */
299 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
300 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
301 SUNXI_FUNCTION(0x0, "gpio_in"),
302 SUNXI_FUNCTION(0x1, "gpio_out"),
303 SUNXI_FUNCTION(0x3, "csi0"), /* D7 */
304 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
305 /* Hole */
306 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
307 SUNXI_FUNCTION(0x0, "gpio_in"),
308 SUNXI_FUNCTION(0x1, "gpio_out"),
309 SUNXI_FUNCTION(0x2, "mmc0")), /* D1 */
310 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
311 SUNXI_FUNCTION(0x0, "gpio_in"),
312 SUNXI_FUNCTION(0x1, "gpio_out"),
313 SUNXI_FUNCTION(0x2, "mmc0")), /* D0 */
314 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
315 SUNXI_FUNCTION(0x0, "gpio_in"),
316 SUNXI_FUNCTION(0x1, "gpio_out"),
317 SUNXI_FUNCTION(0x2, "mmc0")), /* CLK */
318 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
319 SUNXI_FUNCTION(0x0, "gpio_in"),
320 SUNXI_FUNCTION(0x1, "gpio_out"),
321 SUNXI_FUNCTION(0x2, "mmc0")), /* CMD */
322 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
323 SUNXI_FUNCTION(0x0, "gpio_in"),
324 SUNXI_FUNCTION(0x1, "gpio_out"),
325 SUNXI_FUNCTION(0x2, "mmc0")), /* D3 */
326 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
327 SUNXI_FUNCTION(0x0, "gpio_in"),
328 SUNXI_FUNCTION(0x1, "gpio_out"),
329 SUNXI_FUNCTION(0x2, "mmc0")), /* D2 */
330 /* Hole */
331 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
332 SUNXI_FUNCTION(0x0, "gpio_in"),
333 SUNXI_FUNCTION(0x1, "gpio_out"),
334 SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */
335 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
336 SUNXI_FUNCTION(0x0, "gpio_in"),
337 SUNXI_FUNCTION(0x1, "gpio_out"),
338 SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */
339 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
340 SUNXI_FUNCTION(0x0, "gpio_in"),
341 SUNXI_FUNCTION(0x1, "gpio_out"),
342 SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */
343 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
344 SUNXI_FUNCTION(0x0, "gpio_in"),
345 SUNXI_FUNCTION(0x1, "gpio_out"),
346 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
347 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
348 SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */
349 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
350 SUNXI_FUNCTION(0x0, "gpio_in"),
351 SUNXI_FUNCTION(0x1, "gpio_out"),
352 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
353 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
354 SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */
355 /* Hole */
356 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
357 SUNXI_FUNCTION(0x0, "gpio_in"),
358 SUNXI_FUNCTION(0x1, "gpio_out"),
359 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
360 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
361 SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */
362 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
363 SUNXI_FUNCTION(0x0, "gpio_in"),
364 SUNXI_FUNCTION(0x1, "gpio_out"),
365 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
366 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
367 SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */
368 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
369 SUNXI_FUNCTION(0x0, "gpio_in"),
370 SUNXI_FUNCTION(0x1, "gpio_out"),
371 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
372 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
373 SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */
374 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
375 SUNXI_FUNCTION(0x0, "gpio_in"),
376 SUNXI_FUNCTION(0x1, "gpio_out"),
377 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
378 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
379 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
380};
381
382static const struct sunxi_pinctrl_desc sun5i_a13_pinctrl_data = {
383 .pins = sun5i_a13_pins,
384 .npins = ARRAY_SIZE(sun5i_a13_pins),
385};
386
387static int sun5i_a13_pinctrl_probe(struct platform_device *pdev)
388{
389 return sunxi_pinctrl_init(pdev,
390 &sun5i_a13_pinctrl_data);
391}
392
393static struct of_device_id sun5i_a13_pinctrl_match[] = {
394 { .compatible = "allwinner,sun5i-a13-pinctrl", },
395 {}
396};
397MODULE_DEVICE_TABLE(of, sun5i_a13_pinctrl_match);
398
399static struct platform_driver sun5i_a13_pinctrl_driver = {
400 .probe = sun5i_a13_pinctrl_probe,
401 .driver = {
402 .name = "sun5i-a13-pinctrl",
403 .owner = THIS_MODULE,
404 .of_match_table = sun5i_a13_pinctrl_match,
405 },
406};
407module_platform_driver(sun5i_a13_pinctrl_driver);
408
409MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
410MODULE_DESCRIPTION("Allwinner A13 pinctrl driver");
411MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
new file mode 100644
index 000000000000..8fcba48e0a42
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
@@ -0,0 +1,141 @@
1/*
2 * Allwinner A31 SoCs special pins pinctrl driver.
3 *
4 * Copyright (C) 2014 Boris Brezillon
5 * Boris Brezillon <boris.brezillon@free-electrons.com>
6 *
7 * Copyright (C) 2014 Maxime Ripard
8 * Maxime Ripard <maxime.ripard@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include <linux/module.h>
16#include <linux/platform_device.h>
17#include <linux/of.h>
18#include <linux/of_device.h>
19#include <linux/pinctrl/pinctrl.h>
20#include <linux/reset.h>
21
22#include "pinctrl-sunxi.h"
23
24static const struct sunxi_desc_pin sun6i_a31_r_pins[] = {
25 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
26 SUNXI_FUNCTION(0x0, "gpio_in"),
27 SUNXI_FUNCTION(0x1, "gpio_out"),
28 SUNXI_FUNCTION(0x2, "s_twi"), /* SCK */
29 SUNXI_FUNCTION(0x3, "s_p2wi")), /* SCK */
30 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
31 SUNXI_FUNCTION(0x0, "gpio_in"),
32 SUNXI_FUNCTION(0x1, "gpio_out"),
33 SUNXI_FUNCTION(0x2, "s_twi"), /* SDA */
34 SUNXI_FUNCTION(0x3, "s_p2wi")), /* SDA */
35 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
36 SUNXI_FUNCTION(0x0, "gpio_in"),
37 SUNXI_FUNCTION(0x1, "gpio_out"),
38 SUNXI_FUNCTION(0x2, "s_uart")), /* TX */
39 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
40 SUNXI_FUNCTION(0x0, "gpio_in"),
41 SUNXI_FUNCTION(0x1, "gpio_out"),
42 SUNXI_FUNCTION(0x2, "s_uart")), /* RX */
43 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
44 SUNXI_FUNCTION(0x0, "gpio_in"),
45 SUNXI_FUNCTION(0x1, "gpio_out"),
46 SUNXI_FUNCTION(0x2, "s_ir")), /* RX */
47 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
48 SUNXI_FUNCTION(0x0, "gpio_in"),
49 SUNXI_FUNCTION(0x1, "gpio_out"),
50 SUNXI_FUNCTION(0x3, "s_jtag")), /* MS */
51 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
52 SUNXI_FUNCTION(0x0, "gpio_in"),
53 SUNXI_FUNCTION(0x1, "gpio_out"),
54 SUNXI_FUNCTION(0x3, "s_jtag")), /* CK */
55 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
56 SUNXI_FUNCTION(0x0, "gpio_in"),
57 SUNXI_FUNCTION(0x1, "gpio_out"),
58 SUNXI_FUNCTION(0x3, "s_jtag")), /* DO */
59 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
60 SUNXI_FUNCTION(0x0, "gpio_in"),
61 SUNXI_FUNCTION(0x1, "gpio_out"),
62 SUNXI_FUNCTION(0x3, "s_jtag")), /* DI */
63 /* Hole */
64 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0),
65 SUNXI_FUNCTION(0x0, "gpio_in"),
66 SUNXI_FUNCTION(0x1, "gpio_out")),
67 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1),
68 SUNXI_FUNCTION(0x0, "gpio_in"),
69 SUNXI_FUNCTION(0x1, "gpio_out")),
70 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2),
71 SUNXI_FUNCTION(0x0, "gpio_in"),
72 SUNXI_FUNCTION(0x1, "gpio_out"),
73 SUNXI_FUNCTION(0x3, "1wire")),
74 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3),
75 SUNXI_FUNCTION(0x0, "gpio_in"),
76 SUNXI_FUNCTION(0x1, "gpio_out")),
77 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4),
78 SUNXI_FUNCTION(0x0, "gpio_in"),
79 SUNXI_FUNCTION(0x1, "gpio_out")),
80 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 5),
81 SUNXI_FUNCTION(0x0, "gpio_in"),
82 SUNXI_FUNCTION(0x1, "gpio_out")),
83 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 6),
84 SUNXI_FUNCTION(0x0, "gpio_in"),
85 SUNXI_FUNCTION(0x1, "gpio_out")),
86 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 7),
87 SUNXI_FUNCTION(0x0, "gpio_in"),
88 SUNXI_FUNCTION(0x1, "gpio_out"),
89 SUNXI_FUNCTION(0x3, "rtc")), /* CLKO */
90};
91
92static const struct sunxi_pinctrl_desc sun6i_a31_r_pinctrl_data = {
93 .pins = sun6i_a31_r_pins,
94 .npins = ARRAY_SIZE(sun6i_a31_r_pins),
95 .pin_base = PL_BASE,
96};
97
98static int sun6i_a31_r_pinctrl_probe(struct platform_device *pdev)
99{
100 struct reset_control *rstc;
101 int ret;
102
103 rstc = devm_reset_control_get(&pdev->dev, NULL);
104 if (IS_ERR(rstc)) {
105 dev_err(&pdev->dev, "Reset controller missing\n");
106 return PTR_ERR(rstc);
107 }
108
109 ret = reset_control_deassert(rstc);
110 if (ret)
111 return ret;
112
113 ret = sunxi_pinctrl_init(pdev,
114 &sun6i_a31_r_pinctrl_data);
115
116 if (ret)
117 reset_control_assert(rstc);
118
119 return ret;
120}
121
122static struct of_device_id sun6i_a31_r_pinctrl_match[] = {
123 { .compatible = "allwinner,sun6i-a31-r-pinctrl", },
124 {}
125};
126MODULE_DEVICE_TABLE(of, sun6i_a31_r_pinctrl_match);
127
128static struct platform_driver sun6i_a31_r_pinctrl_driver = {
129 .probe = sun6i_a31_r_pinctrl_probe,
130 .driver = {
131 .name = "sun6i-a31-r-pinctrl",
132 .owner = THIS_MODULE,
133 .of_match_table = sun6i_a31_r_pinctrl_match,
134 },
135};
136module_platform_driver(sun6i_a31_r_pinctrl_driver);
137
138MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com");
139MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
140MODULE_DESCRIPTION("Allwinner A31 R_PIO pinctrl driver");
141MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
new file mode 100644
index 000000000000..8dea5856458b
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
@@ -0,0 +1,865 @@
1/*
2 * Allwinner A31 SoCs pinctrl driver.
3 *
4 * Copyright (C) 2014 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
17#include <linux/pinctrl/pinctrl.h>
18
19#include "pinctrl-sunxi.h"
20
21static const struct sunxi_desc_pin sun6i_a31_pins[] = {
22 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
23 SUNXI_FUNCTION(0x0, "gpio_in"),
24 SUNXI_FUNCTION(0x1, "gpio_out"),
25 SUNXI_FUNCTION(0x2, "gmac"), /* TXD0 */
26 SUNXI_FUNCTION(0x3, "lcd1"), /* D0 */
27 SUNXI_FUNCTION(0x4, "uart1")), /* DTR */
28 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
29 SUNXI_FUNCTION(0x0, "gpio_in"),
30 SUNXI_FUNCTION(0x1, "gpio_out"),
31 SUNXI_FUNCTION(0x2, "gmac"), /* TXD1 */
32 SUNXI_FUNCTION(0x3, "lcd1"), /* D1 */
33 SUNXI_FUNCTION(0x4, "uart1")), /* DSR */
34 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
35 SUNXI_FUNCTION(0x0, "gpio_in"),
36 SUNXI_FUNCTION(0x1, "gpio_out"),
37 SUNXI_FUNCTION(0x2, "gmac"), /* TXD2 */
38 SUNXI_FUNCTION(0x3, "lcd1"), /* D2 */
39 SUNXI_FUNCTION(0x4, "uart1")), /* DCD */
40 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
41 SUNXI_FUNCTION(0x0, "gpio_in"),
42 SUNXI_FUNCTION(0x1, "gpio_out"),
43 SUNXI_FUNCTION(0x2, "gmac"), /* TXD3 */
44 SUNXI_FUNCTION(0x3, "lcd1"), /* D3 */
45 SUNXI_FUNCTION(0x4, "uart1")), /* RING */
46 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
47 SUNXI_FUNCTION(0x0, "gpio_in"),
48 SUNXI_FUNCTION(0x1, "gpio_out"),
49 SUNXI_FUNCTION(0x2, "gmac"), /* TXD4 */
50 SUNXI_FUNCTION(0x3, "lcd1"), /* D4 */
51 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
52 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
53 SUNXI_FUNCTION(0x0, "gpio_in"),
54 SUNXI_FUNCTION(0x1, "gpio_out"),
55 SUNXI_FUNCTION(0x2, "gmac"), /* TXD5 */
56 SUNXI_FUNCTION(0x3, "lcd1"), /* D5 */
57 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
58 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
59 SUNXI_FUNCTION(0x0, "gpio_in"),
60 SUNXI_FUNCTION(0x1, "gpio_out"),
61 SUNXI_FUNCTION(0x2, "gmac"), /* TXD6 */
62 SUNXI_FUNCTION(0x3, "lcd1"), /* D6 */
63 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */
64 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
65 SUNXI_FUNCTION(0x0, "gpio_in"),
66 SUNXI_FUNCTION(0x1, "gpio_out"),
67 SUNXI_FUNCTION(0x2, "gmac"), /* TXD7 */
68 SUNXI_FUNCTION(0x3, "lcd1"), /* D7 */
69 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */
70 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
71 SUNXI_FUNCTION(0x0, "gpio_in"),
72 SUNXI_FUNCTION(0x1, "gpio_out"),
73 SUNXI_FUNCTION(0x2, "gmac"), /* TXCLK */
74 SUNXI_FUNCTION(0x3, "lcd1")), /* D8 */
75 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
76 SUNXI_FUNCTION(0x0, "gpio_in"),
77 SUNXI_FUNCTION(0x1, "gpio_out"),
78 SUNXI_FUNCTION(0x2, "gmac"), /* TXEN */
79 SUNXI_FUNCTION(0x3, "lcd1"), /* D9 */
80 SUNXI_FUNCTION(0x4, "mmc3"), /* CMD */
81 SUNXI_FUNCTION(0x5, "mmc2")), /* CMD */
82 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
83 SUNXI_FUNCTION(0x0, "gpio_in"),
84 SUNXI_FUNCTION(0x1, "gpio_out"),
85 SUNXI_FUNCTION(0x2, "gmac"), /* GTXCLK */
86 SUNXI_FUNCTION(0x3, "lcd1"), /* D10 */
87 SUNXI_FUNCTION(0x4, "mmc3"), /* CLK */
88 SUNXI_FUNCTION(0x5, "mmc2")), /* CLK */
89 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
90 SUNXI_FUNCTION(0x0, "gpio_in"),
91 SUNXI_FUNCTION(0x1, "gpio_out"),
92 SUNXI_FUNCTION(0x2, "gmac"), /* RXD0 */
93 SUNXI_FUNCTION(0x3, "lcd1"), /* D11 */
94 SUNXI_FUNCTION(0x4, "mmc3"), /* D0 */
95 SUNXI_FUNCTION(0x5, "mmc2")), /* D0 */
96 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
97 SUNXI_FUNCTION(0x0, "gpio_in"),
98 SUNXI_FUNCTION(0x1, "gpio_out"),
99 SUNXI_FUNCTION(0x2, "gmac"), /* RXD1 */
100 SUNXI_FUNCTION(0x3, "lcd1"), /* D12 */
101 SUNXI_FUNCTION(0x4, "mmc3"), /* D1 */
102 SUNXI_FUNCTION(0x5, "mmc2")), /* D1 */
103 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
104 SUNXI_FUNCTION(0x0, "gpio_in"),
105 SUNXI_FUNCTION(0x1, "gpio_out"),
106 SUNXI_FUNCTION(0x2, "gmac"), /* RXD2 */
107 SUNXI_FUNCTION(0x3, "lcd1"), /* D13 */
108 SUNXI_FUNCTION(0x4, "mmc3"), /* D2 */
109 SUNXI_FUNCTION(0x5, "mmc2")), /* D2 */
110 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
111 SUNXI_FUNCTION(0x0, "gpio_in"),
112 SUNXI_FUNCTION(0x1, "gpio_out"),
113 SUNXI_FUNCTION(0x2, "gmac"), /* RXD3 */
114 SUNXI_FUNCTION(0x3, "lcd1"), /* D14 */
115 SUNXI_FUNCTION(0x4, "mmc3"), /* D3 */
116 SUNXI_FUNCTION(0x5, "mmc2")), /* D3 */
117 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
118 SUNXI_FUNCTION(0x0, "gpio_in"),
119 SUNXI_FUNCTION(0x1, "gpio_out"),
120 SUNXI_FUNCTION(0x2, "gmac"), /* RXD4 */
121 SUNXI_FUNCTION(0x3, "lcd1")), /* D15 */
122 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
123 SUNXI_FUNCTION(0x0, "gpio_in"),
124 SUNXI_FUNCTION(0x1, "gpio_out"),
125 SUNXI_FUNCTION(0x2, "gmac"), /* RXD5 */
126 SUNXI_FUNCTION(0x3, "lcd1")), /* D16 */
127 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
128 SUNXI_FUNCTION(0x0, "gpio_in"),
129 SUNXI_FUNCTION(0x1, "gpio_out"),
130 SUNXI_FUNCTION(0x2, "gmac"), /* RXD6 */
131 SUNXI_FUNCTION(0x3, "lcd1")), /* D17 */
132 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
133 SUNXI_FUNCTION(0x0, "gpio_in"),
134 SUNXI_FUNCTION(0x1, "gpio_out"),
135 SUNXI_FUNCTION(0x2, "gmac"), /* RXD7 */
136 SUNXI_FUNCTION(0x3, "lcd1")), /* D18 */
137 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
138 SUNXI_FUNCTION(0x0, "gpio_in"),
139 SUNXI_FUNCTION(0x1, "gpio_out"),
140 SUNXI_FUNCTION(0x2, "gmac"), /* RXDV */
141 SUNXI_FUNCTION(0x3, "lcd1"), /* D19 */
142 SUNXI_FUNCTION(0x4, "pwm3")), /* Positive */
143 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),
144 SUNXI_FUNCTION(0x0, "gpio_in"),
145 SUNXI_FUNCTION(0x1, "gpio_out"),
146 SUNXI_FUNCTION(0x2, "gmac"), /* RXCLK */
147 SUNXI_FUNCTION(0x3, "lcd1"), /* D20 */
148 SUNXI_FUNCTION(0x4, "pwm3")), /* Negative */
149 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),
150 SUNXI_FUNCTION(0x0, "gpio_in"),
151 SUNXI_FUNCTION(0x1, "gpio_out"),
152 SUNXI_FUNCTION(0x2, "gmac"), /* TXERR */
153 SUNXI_FUNCTION(0x3, "lcd1"), /* D21 */
154 SUNXI_FUNCTION(0x4, "spi3")), /* CS0 */
155 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 22),
156 SUNXI_FUNCTION(0x0, "gpio_in"),
157 SUNXI_FUNCTION(0x1, "gpio_out"),
158 SUNXI_FUNCTION(0x2, "gmac"), /* RXERR */
159 SUNXI_FUNCTION(0x3, "lcd1"), /* D22 */
160 SUNXI_FUNCTION(0x4, "spi3")), /* CLK */
161 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 23),
162 SUNXI_FUNCTION(0x0, "gpio_in"),
163 SUNXI_FUNCTION(0x1, "gpio_out"),
164 SUNXI_FUNCTION(0x2, "gmac"), /* COL */
165 SUNXI_FUNCTION(0x3, "lcd1"), /* D23 */
166 SUNXI_FUNCTION(0x4, "spi3")), /* MOSI */
167 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 24),
168 SUNXI_FUNCTION(0x0, "gpio_in"),
169 SUNXI_FUNCTION(0x1, "gpio_out"),
170 SUNXI_FUNCTION(0x2, "gmac"), /* CRS */
171 SUNXI_FUNCTION(0x3, "lcd1"), /* CLK */
172 SUNXI_FUNCTION(0x4, "spi3")), /* MISO */
173 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 25),
174 SUNXI_FUNCTION(0x0, "gpio_in"),
175 SUNXI_FUNCTION(0x1, "gpio_out"),
176 SUNXI_FUNCTION(0x2, "gmac"), /* CLKIN */
177 SUNXI_FUNCTION(0x3, "lcd1"), /* DE */
178 SUNXI_FUNCTION(0x4, "spi3")), /* CS1 */
179 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 26),
180 SUNXI_FUNCTION(0x0, "gpio_in"),
181 SUNXI_FUNCTION(0x1, "gpio_out"),
182 SUNXI_FUNCTION(0x2, "gmac"), /* MDC */
183 SUNXI_FUNCTION(0x3, "lcd1")), /* HSYNC */
184 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 27),
185 SUNXI_FUNCTION(0x0, "gpio_in"),
186 SUNXI_FUNCTION(0x1, "gpio_out"),
187 SUNXI_FUNCTION(0x2, "gmac"), /* MDIO */
188 SUNXI_FUNCTION(0x3, "lcd1")), /* VSYNC */
189 /* Hole */
190 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
191 SUNXI_FUNCTION(0x0, "gpio_in"),
192 SUNXI_FUNCTION(0x1, "gpio_out"),
193 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
194 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
195 SUNXI_FUNCTION(0x4, "csi")), /* MCLK1 */
196 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
197 SUNXI_FUNCTION(0x0, "gpio_in"),
198 SUNXI_FUNCTION(0x1, "gpio_out"),
199 SUNXI_FUNCTION(0x2, "i2s0")), /* BCLK */
200 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
201 SUNXI_FUNCTION(0x0, "gpio_in"),
202 SUNXI_FUNCTION(0x1, "gpio_out"),
203 SUNXI_FUNCTION(0x2, "i2s0")), /* LRCK */
204 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
205 SUNXI_FUNCTION(0x0, "gpio_in"),
206 SUNXI_FUNCTION(0x1, "gpio_out"),
207 SUNXI_FUNCTION(0x2, "i2s0")), /* DO0 */
208 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
209 SUNXI_FUNCTION(0x0, "gpio_in"),
210 SUNXI_FUNCTION(0x1, "gpio_out"),
211 SUNXI_FUNCTION(0x2, "i2s0"), /* DO1 */
212 SUNXI_FUNCTION(0x3, "uart3")), /* RTS */
213 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
214 SUNXI_FUNCTION(0x0, "gpio_in"),
215 SUNXI_FUNCTION(0x1, "gpio_out"),
216 SUNXI_FUNCTION(0x2, "i2s0"), /* DO2 */
217 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
218 SUNXI_FUNCTION(0x4, "i2c3")), /* SCK */
219 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
220 SUNXI_FUNCTION(0x0, "gpio_in"),
221 SUNXI_FUNCTION(0x1, "gpio_out"),
222 SUNXI_FUNCTION(0x2, "i2s0"), /* DO3 */
223 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
224 SUNXI_FUNCTION(0x4, "i2c3")), /* SDA */
225 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
226 SUNXI_FUNCTION(0x0, "gpio_in"),
227 SUNXI_FUNCTION(0x1, "gpio_out"),
228 SUNXI_FUNCTION(0x3, "i2s0")), /* DI */
229 /* Hole */
230 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
231 SUNXI_FUNCTION(0x0, "gpio_in"),
232 SUNXI_FUNCTION(0x1, "gpio_out"),
233 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
234 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
235 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
236 SUNXI_FUNCTION(0x0, "gpio_in"),
237 SUNXI_FUNCTION(0x1, "gpio_out"),
238 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
239 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
240 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
241 SUNXI_FUNCTION(0x0, "gpio_in"),
242 SUNXI_FUNCTION(0x1, "gpio_out"),
243 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
244 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
245 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
246 SUNXI_FUNCTION(0x0, "gpio_in"),
247 SUNXI_FUNCTION(0x1, "gpio_out"),
248 SUNXI_FUNCTION(0x2, "nand0")), /* CE1 */
249 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
250 SUNXI_FUNCTION(0x0, "gpio_in"),
251 SUNXI_FUNCTION(0x1, "gpio_out"),
252 SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
253 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
254 SUNXI_FUNCTION(0x0, "gpio_in"),
255 SUNXI_FUNCTION(0x1, "gpio_out"),
256 SUNXI_FUNCTION(0x2, "nand0")), /* RE */
257 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
258 SUNXI_FUNCTION(0x0, "gpio_in"),
259 SUNXI_FUNCTION(0x1, "gpio_out"),
260 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
261 SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */
262 SUNXI_FUNCTION(0x4, "mmc3")), /* CMD */
263 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
264 SUNXI_FUNCTION(0x0, "gpio_in"),
265 SUNXI_FUNCTION(0x1, "gpio_out"),
266 SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
267 SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */
268 SUNXI_FUNCTION(0x4, "mmc3")), /* CLK */
269 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
270 SUNXI_FUNCTION(0x0, "gpio_in"),
271 SUNXI_FUNCTION(0x1, "gpio_out"),
272 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
273 SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */
274 SUNXI_FUNCTION(0x4, "mmc3")), /* D0 */
275 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
276 SUNXI_FUNCTION(0x0, "gpio_in"),
277 SUNXI_FUNCTION(0x1, "gpio_out"),
278 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
279 SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */
280 SUNXI_FUNCTION(0x4, "mmc3")), /* D1 */
281 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
282 SUNXI_FUNCTION(0x0, "gpio_in"),
283 SUNXI_FUNCTION(0x1, "gpio_out"),
284 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
285 SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */
286 SUNXI_FUNCTION(0x4, "mmc3")), /* D2 */
287 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
288 SUNXI_FUNCTION(0x0, "gpio_in"),
289 SUNXI_FUNCTION(0x1, "gpio_out"),
290 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
291 SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */
292 SUNXI_FUNCTION(0x4, "mmc3")), /* D3 */
293 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
294 SUNXI_FUNCTION(0x0, "gpio_in"),
295 SUNXI_FUNCTION(0x1, "gpio_out"),
296 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
297 SUNXI_FUNCTION(0x3, "mmc2"), /* D4 */
298 SUNXI_FUNCTION(0x4, "mmc3")), /* D4 */
299 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
300 SUNXI_FUNCTION(0x0, "gpio_in"),
301 SUNXI_FUNCTION(0x1, "gpio_out"),
302 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
303 SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */
304 SUNXI_FUNCTION(0x4, "mmc3")), /* D5 */
305 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
306 SUNXI_FUNCTION(0x0, "gpio_in"),
307 SUNXI_FUNCTION(0x1, "gpio_out"),
308 SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
309 SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */
310 SUNXI_FUNCTION(0x4, "mmc3")), /* D6 */
311 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
312 SUNXI_FUNCTION(0x0, "gpio_in"),
313 SUNXI_FUNCTION(0x1, "gpio_out"),
314 SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
315 SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */
316 SUNXI_FUNCTION(0x4, "mmc3")), /* D7 */
317 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
318 SUNXI_FUNCTION(0x0, "gpio_in"),
319 SUNXI_FUNCTION(0x1, "gpio_out"),
320 SUNXI_FUNCTION(0x2, "nand0"), /* DQ8 */
321 SUNXI_FUNCTION(0x3, "nand1")), /* DQ0 */
322 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
323 SUNXI_FUNCTION(0x0, "gpio_in"),
324 SUNXI_FUNCTION(0x1, "gpio_out"),
325 SUNXI_FUNCTION(0x2, "nand0"), /* DQ9 */
326 SUNXI_FUNCTION(0x3, "nand1")), /* DQ1 */
327 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
328 SUNXI_FUNCTION(0x0, "gpio_in"),
329 SUNXI_FUNCTION(0x1, "gpio_out"),
330 SUNXI_FUNCTION(0x2, "nand0"), /* DQ10 */
331 SUNXI_FUNCTION(0x3, "nand1")), /* DQ2 */
332 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
333 SUNXI_FUNCTION(0x0, "gpio_in"),
334 SUNXI_FUNCTION(0x1, "gpio_out"),
335 SUNXI_FUNCTION(0x2, "nand0"), /* DQ11 */
336 SUNXI_FUNCTION(0x3, "nand1")), /* DQ3 */
337 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20),
338 SUNXI_FUNCTION(0x0, "gpio_in"),
339 SUNXI_FUNCTION(0x1, "gpio_out"),
340 SUNXI_FUNCTION(0x2, "nand0"), /* DQ12 */
341 SUNXI_FUNCTION(0x3, "nand1")), /* DQ4 */
342 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21),
343 SUNXI_FUNCTION(0x0, "gpio_in"),
344 SUNXI_FUNCTION(0x1, "gpio_out"),
345 SUNXI_FUNCTION(0x2, "nand0"), /* DQ13 */
346 SUNXI_FUNCTION(0x3, "nand1")), /* DQ5 */
347 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22),
348 SUNXI_FUNCTION(0x0, "gpio_in"),
349 SUNXI_FUNCTION(0x1, "gpio_out"),
350 SUNXI_FUNCTION(0x2, "nand0"), /* DQ14 */
351 SUNXI_FUNCTION(0x3, "nand1")), /* DQ6 */
352 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23),
353 SUNXI_FUNCTION(0x0, "gpio_in"),
354 SUNXI_FUNCTION(0x1, "gpio_out"),
355 SUNXI_FUNCTION(0x2, "nand0"), /* DQ15 */
356 SUNXI_FUNCTION(0x3, "nand1")), /* DQ7 */
357 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24),
358 SUNXI_FUNCTION(0x0, "gpio_in"),
359 SUNXI_FUNCTION(0x1, "gpio_out"),
360 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
361 SUNXI_FUNCTION(0x3, "mmc2"), /* RST */
362 SUNXI_FUNCTION(0x4, "mmc3")), /* RST */
363 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 25),
364 SUNXI_FUNCTION(0x0, "gpio_in"),
365 SUNXI_FUNCTION(0x1, "gpio_out"),
366 SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */
367 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 26),
368 SUNXI_FUNCTION(0x0, "gpio_in"),
369 SUNXI_FUNCTION(0x1, "gpio_out"),
370 SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */
371 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 27),
372 SUNXI_FUNCTION(0x0, "gpio_in"),
373 SUNXI_FUNCTION(0x1, "gpio_out"),
374 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
375 /* Hole */
376 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
377 SUNXI_FUNCTION(0x0, "gpio_in"),
378 SUNXI_FUNCTION(0x1, "gpio_out"),
379 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
380 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
381 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
382 SUNXI_FUNCTION(0x0, "gpio_in"),
383 SUNXI_FUNCTION(0x1, "gpio_out"),
384 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
385 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
386 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
387 SUNXI_FUNCTION(0x0, "gpio_in"),
388 SUNXI_FUNCTION(0x1, "gpio_out"),
389 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
390 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
391 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
392 SUNXI_FUNCTION(0x0, "gpio_in"),
393 SUNXI_FUNCTION(0x1, "gpio_out"),
394 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
395 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
396 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
397 SUNXI_FUNCTION(0x0, "gpio_in"),
398 SUNXI_FUNCTION(0x1, "gpio_out"),
399 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
400 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
401 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
402 SUNXI_FUNCTION(0x0, "gpio_in"),
403 SUNXI_FUNCTION(0x1, "gpio_out"),
404 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
405 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
406 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
407 SUNXI_FUNCTION(0x0, "gpio_in"),
408 SUNXI_FUNCTION(0x1, "gpio_out"),
409 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
410 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
411 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
412 SUNXI_FUNCTION(0x0, "gpio_in"),
413 SUNXI_FUNCTION(0x1, "gpio_out"),
414 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
415 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
416 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
417 SUNXI_FUNCTION(0x0, "gpio_in"),
418 SUNXI_FUNCTION(0x1, "gpio_out"),
419 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
420 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
421 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
422 SUNXI_FUNCTION(0x0, "gpio_in"),
423 SUNXI_FUNCTION(0x1, "gpio_out"),
424 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
425 SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
426 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
427 SUNXI_FUNCTION(0x0, "gpio_in"),
428 SUNXI_FUNCTION(0x1, "gpio_out"),
429 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
430 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
431 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
432 SUNXI_FUNCTION(0x0, "gpio_in"),
433 SUNXI_FUNCTION(0x1, "gpio_out"),
434 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
435 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
436 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
437 SUNXI_FUNCTION(0x0, "gpio_in"),
438 SUNXI_FUNCTION(0x1, "gpio_out"),
439 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
440 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
441 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
442 SUNXI_FUNCTION(0x0, "gpio_in"),
443 SUNXI_FUNCTION(0x1, "gpio_out"),
444 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
445 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
446 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
447 SUNXI_FUNCTION(0x0, "gpio_in"),
448 SUNXI_FUNCTION(0x1, "gpio_out"),
449 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
450 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
451 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
452 SUNXI_FUNCTION(0x0, "gpio_in"),
453 SUNXI_FUNCTION(0x1, "gpio_out"),
454 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
455 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
456 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
457 SUNXI_FUNCTION(0x0, "gpio_in"),
458 SUNXI_FUNCTION(0x1, "gpio_out"),
459 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
460 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
461 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
462 SUNXI_FUNCTION(0x0, "gpio_in"),
463 SUNXI_FUNCTION(0x1, "gpio_out"),
464 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
465 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
466 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
467 SUNXI_FUNCTION(0x0, "gpio_in"),
468 SUNXI_FUNCTION(0x1, "gpio_out"),
469 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
470 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
471 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
472 SUNXI_FUNCTION(0x0, "gpio_in"),
473 SUNXI_FUNCTION(0x1, "gpio_out"),
474 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
475 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
476 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
477 SUNXI_FUNCTION(0x0, "gpio_in"),
478 SUNXI_FUNCTION(0x1, "gpio_out"),
479 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
480 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
481 SUNXI_FUNCTION(0x0, "gpio_in"),
482 SUNXI_FUNCTION(0x1, "gpio_out"),
483 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
484 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
485 SUNXI_FUNCTION(0x0, "gpio_in"),
486 SUNXI_FUNCTION(0x1, "gpio_out"),
487 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
488 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
489 SUNXI_FUNCTION(0x0, "gpio_in"),
490 SUNXI_FUNCTION(0x1, "gpio_out"),
491 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
492 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
493 SUNXI_FUNCTION(0x0, "gpio_in"),
494 SUNXI_FUNCTION(0x1, "gpio_out"),
495 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
496 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
497 SUNXI_FUNCTION(0x0, "gpio_in"),
498 SUNXI_FUNCTION(0x1, "gpio_out"),
499 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
500 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
501 SUNXI_FUNCTION(0x0, "gpio_in"),
502 SUNXI_FUNCTION(0x1, "gpio_out"),
503 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
504 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
505 SUNXI_FUNCTION(0x0, "gpio_in"),
506 SUNXI_FUNCTION(0x1, "gpio_out"),
507 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
508 /* Hole */
509 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
510 SUNXI_FUNCTION(0x0, "gpio_in"),
511 SUNXI_FUNCTION(0x1, "gpio_out"),
512 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
513 SUNXI_FUNCTION(0x3, "ts")), /* CLK */
514 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
515 SUNXI_FUNCTION(0x0, "gpio_in"),
516 SUNXI_FUNCTION(0x1, "gpio_out"),
517 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
518 SUNXI_FUNCTION(0x3, "ts")), /* ERR */
519 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
520 SUNXI_FUNCTION(0x0, "gpio_in"),
521 SUNXI_FUNCTION(0x1, "gpio_out"),
522 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
523 SUNXI_FUNCTION(0x3, "ts")), /* SYNC */
524 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
525 SUNXI_FUNCTION(0x0, "gpio_in"),
526 SUNXI_FUNCTION(0x1, "gpio_out"),
527 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
528 SUNXI_FUNCTION(0x3, "ts")), /* DVLD */
529 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
530 SUNXI_FUNCTION(0x0, "gpio_in"),
531 SUNXI_FUNCTION(0x1, "gpio_out"),
532 SUNXI_FUNCTION(0x2, "csi"), /* D0 */
533 SUNXI_FUNCTION(0x3, "uart5")), /* TX */
534 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
535 SUNXI_FUNCTION(0x0, "gpio_in"),
536 SUNXI_FUNCTION(0x1, "gpio_out"),
537 SUNXI_FUNCTION(0x2, "csi"), /* D1 */
538 SUNXI_FUNCTION(0x3, "uart5")), /* RX */
539 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
540 SUNXI_FUNCTION(0x0, "gpio_in"),
541 SUNXI_FUNCTION(0x1, "gpio_out"),
542 SUNXI_FUNCTION(0x2, "csi"), /* D2 */
543 SUNXI_FUNCTION(0x3, "uart5")), /* RTS */
544 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
545 SUNXI_FUNCTION(0x0, "gpio_in"),
546 SUNXI_FUNCTION(0x1, "gpio_out"),
547 SUNXI_FUNCTION(0x2, "csi"), /* D3 */
548 SUNXI_FUNCTION(0x3, "uart5")), /* CTS */
549 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
550 SUNXI_FUNCTION(0x0, "gpio_in"),
551 SUNXI_FUNCTION(0x1, "gpio_out"),
552 SUNXI_FUNCTION(0x2, "csi"), /* D4 */
553 SUNXI_FUNCTION(0x3, "ts")), /* D0 */
554 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
555 SUNXI_FUNCTION(0x0, "gpio_in"),
556 SUNXI_FUNCTION(0x1, "gpio_out"),
557 SUNXI_FUNCTION(0x2, "csi"), /* D5 */
558 SUNXI_FUNCTION(0x3, "ts")), /* D1 */
559 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
560 SUNXI_FUNCTION(0x0, "gpio_in"),
561 SUNXI_FUNCTION(0x1, "gpio_out"),
562 SUNXI_FUNCTION(0x2, "csi"), /* D6 */
563 SUNXI_FUNCTION(0x3, "ts")), /* D2 */
564 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
565 SUNXI_FUNCTION(0x0, "gpio_in"),
566 SUNXI_FUNCTION(0x1, "gpio_out"),
567 SUNXI_FUNCTION(0x2, "csi"), /* D7 */
568 SUNXI_FUNCTION(0x3, "ts")), /* D3 */
569 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
570 SUNXI_FUNCTION(0x0, "gpio_in"),
571 SUNXI_FUNCTION(0x1, "gpio_out"),
572 SUNXI_FUNCTION(0x2, "csi"), /* D8 */
573 SUNXI_FUNCTION(0x3, "ts")), /* D4 */
574 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
575 SUNXI_FUNCTION(0x0, "gpio_in"),
576 SUNXI_FUNCTION(0x1, "gpio_out"),
577 SUNXI_FUNCTION(0x2, "csi"), /* D9 */
578 SUNXI_FUNCTION(0x3, "ts")), /* D5 */
579 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
580 SUNXI_FUNCTION(0x0, "gpio_in"),
581 SUNXI_FUNCTION(0x1, "gpio_out"),
582 SUNXI_FUNCTION(0x2, "csi"), /* D10 */
583 SUNXI_FUNCTION(0x3, "ts")), /* D6 */
584 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
585 SUNXI_FUNCTION(0x0, "gpio_in"),
586 SUNXI_FUNCTION(0x1, "gpio_out"),
587 SUNXI_FUNCTION(0x2, "csi"), /* D11 */
588 SUNXI_FUNCTION(0x3, "ts")), /* D7 */
589 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
590 SUNXI_FUNCTION(0x0, "gpio_in"),
591 SUNXI_FUNCTION(0x1, "gpio_out"),
592 SUNXI_FUNCTION(0x2, "csi")), /* MIPI CSI MCLK */
593 /* Hole */
594 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
595 SUNXI_FUNCTION(0x0, "gpio_in"),
596 SUNXI_FUNCTION(0x1, "gpio_out"),
597 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
598 SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
599 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
600 SUNXI_FUNCTION(0x0, "gpio_in"),
601 SUNXI_FUNCTION(0x1, "gpio_out"),
602 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
603 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
604 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
605 SUNXI_FUNCTION(0x0, "gpio_in"),
606 SUNXI_FUNCTION(0x1, "gpio_out"),
607 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
608 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
609 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
610 SUNXI_FUNCTION(0x0, "gpio_in"),
611 SUNXI_FUNCTION(0x1, "gpio_out"),
612 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
613 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
614 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
615 SUNXI_FUNCTION(0x0, "gpio_in"),
616 SUNXI_FUNCTION(0x1, "gpio_out"),
617 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
618 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
619 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
620 SUNXI_FUNCTION(0x0, "gpio_in"),
621 SUNXI_FUNCTION(0x1, "gpio_out"),
622 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
623 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
624 /* Hole */
625 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
626 SUNXI_FUNCTION(0x0, "gpio_in"),
627 SUNXI_FUNCTION(0x1, "gpio_out"),
628 SUNXI_FUNCTION(0x2, "mmc1")), /* CLK */
629 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
630 SUNXI_FUNCTION(0x0, "gpio_in"),
631 SUNXI_FUNCTION(0x1, "gpio_out"),
632 SUNXI_FUNCTION(0x2, "mmc1")), /* CMD */
633 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
634 SUNXI_FUNCTION(0x0, "gpio_in"),
635 SUNXI_FUNCTION(0x1, "gpio_out"),
636 SUNXI_FUNCTION(0x2, "mmc1")), /* D0 */
637 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
638 SUNXI_FUNCTION(0x0, "gpio_in"),
639 SUNXI_FUNCTION(0x1, "gpio_out"),
640 SUNXI_FUNCTION(0x2, "mmc1")), /* D1 */
641 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
642 SUNXI_FUNCTION(0x0, "gpio_in"),
643 SUNXI_FUNCTION(0x1, "gpio_out"),
644 SUNXI_FUNCTION(0x2, "mmc1")), /* D2 */
645 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
646 SUNXI_FUNCTION(0x0, "gpio_in"),
647 SUNXI_FUNCTION(0x1, "gpio_out"),
648 SUNXI_FUNCTION(0x2, "mmc1")), /* D3 */
649 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
650 SUNXI_FUNCTION(0x0, "gpio_in"),
651 SUNXI_FUNCTION(0x1, "gpio_out"),
652 SUNXI_FUNCTION(0x2, "uart2")), /* TX */
653 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
654 SUNXI_FUNCTION(0x0, "gpio_in"),
655 SUNXI_FUNCTION(0x1, "gpio_out"),
656 SUNXI_FUNCTION(0x2, "uart2")), /* RX */
657 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
658 SUNXI_FUNCTION(0x0, "gpio_in"),
659 SUNXI_FUNCTION(0x1, "gpio_out"),
660 SUNXI_FUNCTION(0x2, "uart2")), /* RTS */
661 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
662 SUNXI_FUNCTION(0x0, "gpio_in"),
663 SUNXI_FUNCTION(0x1, "gpio_out"),
664 SUNXI_FUNCTION(0x2, "uart2")), /* CTS */
665 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
666 SUNXI_FUNCTION(0x0, "gpio_in"),
667 SUNXI_FUNCTION(0x1, "gpio_out"),
668 SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */
669 SUNXI_FUNCTION(0x3, "usb")), /* DP3 */
670 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
671 SUNXI_FUNCTION(0x0, "gpio_in"),
672 SUNXI_FUNCTION(0x1, "gpio_out"),
673 SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */
674 SUNXI_FUNCTION(0x3, "usb")), /* DM3 */
675 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
676 SUNXI_FUNCTION(0x0, "gpio_in"),
677 SUNXI_FUNCTION(0x1, "gpio_out"),
678 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
679 SUNXI_FUNCTION(0x3, "i2s1")), /* MCLK */
680 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
681 SUNXI_FUNCTION(0x0, "gpio_in"),
682 SUNXI_FUNCTION(0x1, "gpio_out"),
683 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
684 SUNXI_FUNCTION(0x3, "i2s1")), /* BCLK */
685 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
686 SUNXI_FUNCTION(0x0, "gpio_in"),
687 SUNXI_FUNCTION(0x1, "gpio_out"),
688 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
689 SUNXI_FUNCTION(0x3, "i2s1")), /* LRCK */
690 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
691 SUNXI_FUNCTION(0x0, "gpio_in"),
692 SUNXI_FUNCTION(0x1, "gpio_out"),
693 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
694 SUNXI_FUNCTION(0x3, "i2s1")), /* DIN */
695 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16),
696 SUNXI_FUNCTION(0x0, "gpio_in"),
697 SUNXI_FUNCTION(0x1, "gpio_out"),
698 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
699 SUNXI_FUNCTION(0x3, "i2s1")), /* DOUT */
700 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17),
701 SUNXI_FUNCTION(0x0, "gpio_in"),
702 SUNXI_FUNCTION(0x1, "gpio_out"),
703 SUNXI_FUNCTION(0x2, "uart4")), /* TX */
704 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18),
705 SUNXI_FUNCTION(0x0, "gpio_in"),
706 SUNXI_FUNCTION(0x1, "gpio_out"),
707 SUNXI_FUNCTION(0x2, "uart4")), /* RX */
708 /* Hole */
709 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
710 SUNXI_FUNCTION(0x0, "gpio_in"),
711 SUNXI_FUNCTION(0x1, "gpio_out"),
712 SUNXI_FUNCTION(0x2, "nand1")), /* WE */
713 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
714 SUNXI_FUNCTION(0x0, "gpio_in"),
715 SUNXI_FUNCTION(0x1, "gpio_out"),
716 SUNXI_FUNCTION(0x2, "nand1")), /* ALE */
717 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
718 SUNXI_FUNCTION(0x0, "gpio_in"),
719 SUNXI_FUNCTION(0x1, "gpio_out"),
720 SUNXI_FUNCTION(0x2, "nand1")), /* CLE */
721 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
722 SUNXI_FUNCTION(0x0, "gpio_in"),
723 SUNXI_FUNCTION(0x1, "gpio_out"),
724 SUNXI_FUNCTION(0x2, "nand1")), /* CE1 */
725 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
726 SUNXI_FUNCTION(0x0, "gpio_in"),
727 SUNXI_FUNCTION(0x1, "gpio_out"),
728 SUNXI_FUNCTION(0x2, "nand1")), /* CE0 */
729 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
730 SUNXI_FUNCTION(0x0, "gpio_in"),
731 SUNXI_FUNCTION(0x1, "gpio_out"),
732 SUNXI_FUNCTION(0x2, "nand1")), /* RE */
733 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
734 SUNXI_FUNCTION(0x0, "gpio_in"),
735 SUNXI_FUNCTION(0x1, "gpio_out"),
736 SUNXI_FUNCTION(0x2, "nand1")), /* RB0 */
737 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
738 SUNXI_FUNCTION(0x0, "gpio_in"),
739 SUNXI_FUNCTION(0x1, "gpio_out"),
740 SUNXI_FUNCTION(0x2, "nand1")), /* RB1 */
741 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
742 SUNXI_FUNCTION(0x0, "gpio_in"),
743 SUNXI_FUNCTION(0x1, "gpio_out"),
744 SUNXI_FUNCTION(0x2, "nand1")), /* DQS */
745 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
746 SUNXI_FUNCTION(0x0, "gpio_in"),
747 SUNXI_FUNCTION(0x1, "gpio_out"),
748 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
749 SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
750 SUNXI_FUNCTION(0x4, "pwm1")), /* Positive */
751 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
752 SUNXI_FUNCTION(0x0, "gpio_in"),
753 SUNXI_FUNCTION(0x1, "gpio_out"),
754 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
755 SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
756 SUNXI_FUNCTION(0x4, "pwm1")), /* Negative */
757 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
758 SUNXI_FUNCTION(0x0, "gpio_in"),
759 SUNXI_FUNCTION(0x1, "gpio_out"),
760 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
761 SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
762 SUNXI_FUNCTION(0x4, "pwm2")), /* Positive */
763 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
764 SUNXI_FUNCTION(0x0, "gpio_in"),
765 SUNXI_FUNCTION(0x1, "gpio_out"),
766 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
767 SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
768 SUNXI_FUNCTION(0x4, "pwm2")), /* Negative */
769 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
770 SUNXI_FUNCTION(0x0, "gpio_in"),
771 SUNXI_FUNCTION(0x1, "gpio_out"),
772 SUNXI_FUNCTION(0x2, "pwm0")),
773 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
774 SUNXI_FUNCTION(0x0, "gpio_in"),
775 SUNXI_FUNCTION(0x1, "gpio_out"),
776 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
777 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
778 SUNXI_FUNCTION(0x0, "gpio_in"),
779 SUNXI_FUNCTION(0x1, "gpio_out"),
780 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
781 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
782 SUNXI_FUNCTION(0x0, "gpio_in"),
783 SUNXI_FUNCTION(0x1, "gpio_out"),
784 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
785 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
786 SUNXI_FUNCTION(0x0, "gpio_in"),
787 SUNXI_FUNCTION(0x1, "gpio_out"),
788 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
789 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
790 SUNXI_FUNCTION(0x0, "gpio_in"),
791 SUNXI_FUNCTION(0x1, "gpio_out"),
792 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
793 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
794 SUNXI_FUNCTION(0x0, "gpio_in"),
795 SUNXI_FUNCTION(0x1, "gpio_out"),
796 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
797 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
798 SUNXI_FUNCTION(0x0, "gpio_in"),
799 SUNXI_FUNCTION(0x1, "gpio_out"),
800 SUNXI_FUNCTION(0x2, "uart0")), /* TX */
801 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
802 SUNXI_FUNCTION(0x0, "gpio_in"),
803 SUNXI_FUNCTION(0x1, "gpio_out"),
804 SUNXI_FUNCTION(0x2, "uart0")), /* RX */
805 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22),
806 SUNXI_FUNCTION(0x0, "gpio_in"),
807 SUNXI_FUNCTION(0x1, "gpio_out")),
808 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23),
809 SUNXI_FUNCTION(0x0, "gpio_in"),
810 SUNXI_FUNCTION(0x1, "gpio_out")),
811 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24),
812 SUNXI_FUNCTION(0x0, "gpio_in"),
813 SUNXI_FUNCTION(0x1, "gpio_out")),
814 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25),
815 SUNXI_FUNCTION(0x0, "gpio_in"),
816 SUNXI_FUNCTION(0x1, "gpio_out")),
817 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26),
818 SUNXI_FUNCTION(0x0, "gpio_in"),
819 SUNXI_FUNCTION(0x1, "gpio_out")),
820 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27),
821 SUNXI_FUNCTION(0x0, "gpio_in"),
822 SUNXI_FUNCTION(0x1, "gpio_out")),
823 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 28),
824 SUNXI_FUNCTION(0x0, "gpio_in"),
825 SUNXI_FUNCTION(0x1, "gpio_out")),
826 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 29),
827 SUNXI_FUNCTION(0x0, "gpio_in"),
828 SUNXI_FUNCTION(0x1, "gpio_out"),
829 SUNXI_FUNCTION(0x2, "nand1")), /* CE2 */
830 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 30),
831 SUNXI_FUNCTION(0x0, "gpio_in"),
832 SUNXI_FUNCTION(0x1, "gpio_out"),
833 SUNXI_FUNCTION(0x2, "nand1")), /* CE3 */
834};
835
836static const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_data = {
837 .pins = sun6i_a31_pins,
838 .npins = ARRAY_SIZE(sun6i_a31_pins),
839};
840
841static int sun6i_a31_pinctrl_probe(struct platform_device *pdev)
842{
843 return sunxi_pinctrl_init(pdev,
844 &sun6i_a31_pinctrl_data);
845}
846
847static struct of_device_id sun6i_a31_pinctrl_match[] = {
848 { .compatible = "allwinner,sun6i-a31-pinctrl", },
849 {}
850};
851MODULE_DEVICE_TABLE(of, sun6i_a31_pinctrl_match);
852
853static struct platform_driver sun6i_a31_pinctrl_driver = {
854 .probe = sun6i_a31_pinctrl_probe,
855 .driver = {
856 .name = "sun6i-a31-pinctrl",
857 .owner = THIS_MODULE,
858 .of_match_table = sun6i_a31_pinctrl_match,
859 },
860};
861module_platform_driver(sun6i_a31_pinctrl_driver);
862
863MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
864MODULE_DESCRIPTION("Allwinner A31 pinctrl driver");
865MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
new file mode 100644
index 000000000000..d8577ce5f1a4
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
@@ -0,0 +1,1065 @@
1/*
2 * Allwinner A20 SoCs pinctrl driver.
3 *
4 * Copyright (C) 2014 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
17#include <linux/pinctrl/pinctrl.h>
18
19#include "pinctrl-sunxi.h"
20
21static const struct sunxi_desc_pin sun7i_a20_pins[] = {
22 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
23 SUNXI_FUNCTION(0x0, "gpio_in"),
24 SUNXI_FUNCTION(0x1, "gpio_out"),
25 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
26 SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
27 SUNXI_FUNCTION(0x4, "uart2"), /* RTS */
28 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD3 */
29 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
30 SUNXI_FUNCTION(0x0, "gpio_in"),
31 SUNXI_FUNCTION(0x1, "gpio_out"),
32 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
33 SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
34 SUNXI_FUNCTION(0x4, "uart2"), /* CTS */
35 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD2 */
36 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
37 SUNXI_FUNCTION(0x0, "gpio_in"),
38 SUNXI_FUNCTION(0x1, "gpio_out"),
39 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
40 SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
41 SUNXI_FUNCTION(0x4, "uart2"), /* TX */
42 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD1 */
43 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
44 SUNXI_FUNCTION(0x0, "gpio_in"),
45 SUNXI_FUNCTION(0x1, "gpio_out"),
46 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
47 SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
48 SUNXI_FUNCTION(0x4, "uart2"), /* RX */
49 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD0 */
50 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
51 SUNXI_FUNCTION(0x0, "gpio_in"),
52 SUNXI_FUNCTION(0x1, "gpio_out"),
53 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
54 SUNXI_FUNCTION(0x3, "spi1"), /* CS1 */
55 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD3 */
56 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
57 SUNXI_FUNCTION(0x0, "gpio_in"),
58 SUNXI_FUNCTION(0x1, "gpio_out"),
59 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
60 SUNXI_FUNCTION(0x3, "spi3"), /* CS0 */
61 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD2 */
62 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
63 SUNXI_FUNCTION(0x0, "gpio_in"),
64 SUNXI_FUNCTION(0x1, "gpio_out"),
65 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
66 SUNXI_FUNCTION(0x3, "spi3"), /* CLK */
67 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD1 */
68 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
69 SUNXI_FUNCTION(0x0, "gpio_in"),
70 SUNXI_FUNCTION(0x1, "gpio_out"),
71 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
72 SUNXI_FUNCTION(0x3, "spi3"), /* MOSI */
73 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD0 */
74 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
75 SUNXI_FUNCTION(0x0, "gpio_in"),
76 SUNXI_FUNCTION(0x1, "gpio_out"),
77 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
78 SUNXI_FUNCTION(0x3, "spi3"), /* MISO */
79 SUNXI_FUNCTION(0x5, "gmac")), /* GRXCK */
80 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
81 SUNXI_FUNCTION(0x0, "gpio_in"),
82 SUNXI_FUNCTION(0x1, "gpio_out"),
83 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
84 SUNXI_FUNCTION(0x3, "spi3"), /* CS1 */
85 SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ERXERR */
86 SUNXI_FUNCTION(0x6, "i2s1")), /* MCLK */
87 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
88 SUNXI_FUNCTION(0x0, "gpio_in"),
89 SUNXI_FUNCTION(0x1, "gpio_out"),
90 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
91 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
92 SUNXI_FUNCTION(0x5, "gmac")), /* GRXCTL / ERXDV */
93 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
94 SUNXI_FUNCTION(0x0, "gpio_in"),
95 SUNXI_FUNCTION(0x1, "gpio_out"),
96 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
97 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
98 SUNXI_FUNCTION(0x5, "gmac")), /* EMDC */
99 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
100 SUNXI_FUNCTION(0x0, "gpio_in"),
101 SUNXI_FUNCTION(0x1, "gpio_out"),
102 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
103 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
104 SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
105 SUNXI_FUNCTION(0x5, "gmac")), /* EMDIO */
106 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
107 SUNXI_FUNCTION(0x0, "gpio_in"),
108 SUNXI_FUNCTION(0x1, "gpio_out"),
109 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
110 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
111 SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
112 SUNXI_FUNCTION(0x5, "gmac")), /* GTXCTL / ETXEN */
113 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
114 SUNXI_FUNCTION(0x0, "gpio_in"),
115 SUNXI_FUNCTION(0x1, "gpio_out"),
116 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
117 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
118 SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
119 SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ETXCK */
120 SUNXI_FUNCTION(0x6, "i2s1")), /* BCLK */
121 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
122 SUNXI_FUNCTION(0x0, "gpio_in"),
123 SUNXI_FUNCTION(0x1, "gpio_out"),
124 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
125 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
126 SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
127 SUNXI_FUNCTION(0x5, "gmac"), /* GTXCK / ECRS */
128 SUNXI_FUNCTION(0x6, "i2s1")), /* LRCK */
129 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
130 SUNXI_FUNCTION(0x0, "gpio_in"),
131 SUNXI_FUNCTION(0x1, "gpio_out"),
132 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
133 SUNXI_FUNCTION(0x3, "can"), /* TX */
134 SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
135 SUNXI_FUNCTION(0x5, "gmac"), /* GCLKIN / ECOL */
136 SUNXI_FUNCTION(0x6, "i2s1")), /* DO */
137 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
138 SUNXI_FUNCTION(0x0, "gpio_in"),
139 SUNXI_FUNCTION(0x1, "gpio_out"),
140 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
141 SUNXI_FUNCTION(0x3, "can"), /* RX */
142 SUNXI_FUNCTION(0x4, "uart1"), /* RING */
143 SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ETXERR */
144 SUNXI_FUNCTION(0x6, "i2s1")), /* LRCK */
145 /* Hole */
146 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
147 SUNXI_FUNCTION(0x0, "gpio_in"),
148 SUNXI_FUNCTION(0x1, "gpio_out"),
149 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
150 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
151 SUNXI_FUNCTION(0x0, "gpio_in"),
152 SUNXI_FUNCTION(0x1, "gpio_out"),
153 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
154 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
155 SUNXI_FUNCTION(0x0, "gpio_in"),
156 SUNXI_FUNCTION(0x1, "gpio_out"),
157 SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */
158 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
159 SUNXI_FUNCTION(0x0, "gpio_in"),
160 SUNXI_FUNCTION(0x1, "gpio_out"),
161 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
162 SUNXI_FUNCTION(0x4, "spdif")), /* MCLK */
163 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
164 SUNXI_FUNCTION(0x0, "gpio_in"),
165 SUNXI_FUNCTION(0x1, "gpio_out"),
166 SUNXI_FUNCTION(0x2, "ir0")), /* RX */
167 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
168 SUNXI_FUNCTION(0x0, "gpio_in"),
169 SUNXI_FUNCTION(0x1, "gpio_out"),
170 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
171 SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */
172 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
173 SUNXI_FUNCTION(0x0, "gpio_in"),
174 SUNXI_FUNCTION(0x1, "gpio_out"),
175 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
176 SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */
177 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
178 SUNXI_FUNCTION(0x0, "gpio_in"),
179 SUNXI_FUNCTION(0x1, "gpio_out"),
180 SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
181 SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */
182 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
183 SUNXI_FUNCTION(0x0, "gpio_in"),
184 SUNXI_FUNCTION(0x1, "gpio_out"),
185 SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */
186 SUNXI_FUNCTION(0x3, "ac97")), /* DO */
187 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
188 SUNXI_FUNCTION(0x0, "gpio_in"),
189 SUNXI_FUNCTION(0x1, "gpio_out"),
190 SUNXI_FUNCTION(0x2, "i2s0")), /* DO1 */
191 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
192 SUNXI_FUNCTION(0x0, "gpio_in"),
193 SUNXI_FUNCTION(0x1, "gpio_out"),
194 SUNXI_FUNCTION(0x2, "i2s0")), /* DO2 */
195 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
196 SUNXI_FUNCTION(0x0, "gpio_in"),
197 SUNXI_FUNCTION(0x1, "gpio_out"),
198 SUNXI_FUNCTION(0x2, "i2s0")), /* DO3 */
199 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
200 SUNXI_FUNCTION(0x0, "gpio_in"),
201 SUNXI_FUNCTION(0x1, "gpio_out"),
202 SUNXI_FUNCTION(0x2, "i2s0"), /* DI */
203 SUNXI_FUNCTION(0x3, "ac97"), /* DI */
204 SUNXI_FUNCTION(0x4, "spdif")), /* DI */
205 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
206 SUNXI_FUNCTION(0x0, "gpio_in"),
207 SUNXI_FUNCTION(0x1, "gpio_out"),
208 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
209 SUNXI_FUNCTION(0x4, "spdif")), /* DO */
210 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
211 SUNXI_FUNCTION(0x0, "gpio_in"),
212 SUNXI_FUNCTION(0x1, "gpio_out"),
213 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
214 SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */
215 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
216 SUNXI_FUNCTION(0x0, "gpio_in"),
217 SUNXI_FUNCTION(0x1, "gpio_out"),
218 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
219 SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */
220 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
221 SUNXI_FUNCTION(0x0, "gpio_in"),
222 SUNXI_FUNCTION(0x1, "gpio_out"),
223 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
224 SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */
225 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
226 SUNXI_FUNCTION(0x0, "gpio_in"),
227 SUNXI_FUNCTION(0x1, "gpio_out"),
228 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
229 SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */
230 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
231 SUNXI_FUNCTION(0x0, "gpio_in"),
232 SUNXI_FUNCTION(0x1, "gpio_out"),
233 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
234 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 19),
235 SUNXI_FUNCTION(0x0, "gpio_in"),
236 SUNXI_FUNCTION(0x1, "gpio_out"),
237 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
238 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20),
239 SUNXI_FUNCTION(0x0, "gpio_in"),
240 SUNXI_FUNCTION(0x1, "gpio_out"),
241 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
242 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 21),
243 SUNXI_FUNCTION(0x0, "gpio_in"),
244 SUNXI_FUNCTION(0x1, "gpio_out"),
245 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
246 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 22),
247 SUNXI_FUNCTION(0x0, "gpio_in"),
248 SUNXI_FUNCTION(0x1, "gpio_out"),
249 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
250 SUNXI_FUNCTION(0x3, "ir1")), /* TX */
251 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 23),
252 SUNXI_FUNCTION(0x0, "gpio_in"),
253 SUNXI_FUNCTION(0x1, "gpio_out"),
254 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
255 SUNXI_FUNCTION(0x3, "ir1")), /* RX */
256 /* Hole */
257 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
258 SUNXI_FUNCTION(0x0, "gpio_in"),
259 SUNXI_FUNCTION(0x1, "gpio_out"),
260 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
261 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
262 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
263 SUNXI_FUNCTION(0x0, "gpio_in"),
264 SUNXI_FUNCTION(0x1, "gpio_out"),
265 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
266 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
267 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
268 SUNXI_FUNCTION(0x0, "gpio_in"),
269 SUNXI_FUNCTION(0x1, "gpio_out"),
270 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
271 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
272 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
273 SUNXI_FUNCTION(0x0, "gpio_in"),
274 SUNXI_FUNCTION(0x1, "gpio_out"),
275 SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */
276 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
277 SUNXI_FUNCTION(0x0, "gpio_in"),
278 SUNXI_FUNCTION(0x1, "gpio_out"),
279 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
280 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
281 SUNXI_FUNCTION(0x0, "gpio_in"),
282 SUNXI_FUNCTION(0x1, "gpio_out"),
283 SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */
284 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
285 SUNXI_FUNCTION(0x0, "gpio_in"),
286 SUNXI_FUNCTION(0x1, "gpio_out"),
287 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
288 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
289 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
290 SUNXI_FUNCTION(0x0, "gpio_in"),
291 SUNXI_FUNCTION(0x1, "gpio_out"),
292 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
293 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
294 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
295 SUNXI_FUNCTION(0x0, "gpio_in"),
296 SUNXI_FUNCTION(0x1, "gpio_out"),
297 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
298 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
299 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
300 SUNXI_FUNCTION(0x0, "gpio_in"),
301 SUNXI_FUNCTION(0x1, "gpio_out"),
302 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
303 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
304 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
305 SUNXI_FUNCTION(0x0, "gpio_in"),
306 SUNXI_FUNCTION(0x1, "gpio_out"),
307 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
308 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
309 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
310 SUNXI_FUNCTION(0x0, "gpio_in"),
311 SUNXI_FUNCTION(0x1, "gpio_out"),
312 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
313 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
314 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
315 SUNXI_FUNCTION(0x0, "gpio_in"),
316 SUNXI_FUNCTION(0x1, "gpio_out"),
317 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */
318 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
319 SUNXI_FUNCTION(0x0, "gpio_in"),
320 SUNXI_FUNCTION(0x1, "gpio_out"),
321 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */
322 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
323 SUNXI_FUNCTION(0x0, "gpio_in"),
324 SUNXI_FUNCTION(0x1, "gpio_out"),
325 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */
326 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
327 SUNXI_FUNCTION(0x0, "gpio_in"),
328 SUNXI_FUNCTION(0x1, "gpio_out"),
329 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */
330 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
331 SUNXI_FUNCTION(0x0, "gpio_in"),
332 SUNXI_FUNCTION(0x1, "gpio_out"),
333 SUNXI_FUNCTION(0x2, "nand0")), /* NWP */
334 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
335 SUNXI_FUNCTION(0x0, "gpio_in"),
336 SUNXI_FUNCTION(0x1, "gpio_out"),
337 SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */
338 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
339 SUNXI_FUNCTION(0x0, "gpio_in"),
340 SUNXI_FUNCTION(0x1, "gpio_out"),
341 SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */
342 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
343 SUNXI_FUNCTION(0x0, "gpio_in"),
344 SUNXI_FUNCTION(0x1, "gpio_out"),
345 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
346 SUNXI_FUNCTION(0x3, "spi2"), /* CS0 */
347 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
348 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20),
349 SUNXI_FUNCTION(0x0, "gpio_in"),
350 SUNXI_FUNCTION(0x1, "gpio_out"),
351 SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
352 SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
353 SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
354 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21),
355 SUNXI_FUNCTION(0x0, "gpio_in"),
356 SUNXI_FUNCTION(0x1, "gpio_out"),
357 SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
358 SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
359 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
360 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22),
361 SUNXI_FUNCTION(0x0, "gpio_in"),
362 SUNXI_FUNCTION(0x1, "gpio_out"),
363 SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
364 SUNXI_FUNCTION(0x3, "spi2"), /* MISO */
365 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
366 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23),
367 SUNXI_FUNCTION(0x0, "gpio_in"),
368 SUNXI_FUNCTION(0x1, "gpio_out"),
369 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
370 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24),
371 SUNXI_FUNCTION(0x0, "gpio_in"),
372 SUNXI_FUNCTION(0x1, "gpio_out"),
373 SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */
374 /* Hole */
375 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
376 SUNXI_FUNCTION(0x0, "gpio_in"),
377 SUNXI_FUNCTION(0x1, "gpio_out"),
378 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
379 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
380 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
381 SUNXI_FUNCTION(0x0, "gpio_in"),
382 SUNXI_FUNCTION(0x1, "gpio_out"),
383 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
384 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
385 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
386 SUNXI_FUNCTION(0x0, "gpio_in"),
387 SUNXI_FUNCTION(0x1, "gpio_out"),
388 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
389 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
390 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
391 SUNXI_FUNCTION(0x0, "gpio_in"),
392 SUNXI_FUNCTION(0x1, "gpio_out"),
393 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
394 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
395 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
396 SUNXI_FUNCTION(0x0, "gpio_in"),
397 SUNXI_FUNCTION(0x1, "gpio_out"),
398 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
399 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
400 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
401 SUNXI_FUNCTION(0x0, "gpio_in"),
402 SUNXI_FUNCTION(0x1, "gpio_out"),
403 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
404 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
405 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
406 SUNXI_FUNCTION(0x0, "gpio_in"),
407 SUNXI_FUNCTION(0x1, "gpio_out"),
408 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
409 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
410 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
411 SUNXI_FUNCTION(0x0, "gpio_in"),
412 SUNXI_FUNCTION(0x1, "gpio_out"),
413 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
414 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
415 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
416 SUNXI_FUNCTION(0x0, "gpio_in"),
417 SUNXI_FUNCTION(0x1, "gpio_out"),
418 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
419 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
420 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
421 SUNXI_FUNCTION(0x0, "gpio_in"),
422 SUNXI_FUNCTION(0x1, "gpio_out"),
423 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
424 SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */
425 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
426 SUNXI_FUNCTION(0x0, "gpio_in"),
427 SUNXI_FUNCTION(0x1, "gpio_out"),
428 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
429 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
430 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
431 SUNXI_FUNCTION(0x0, "gpio_in"),
432 SUNXI_FUNCTION(0x1, "gpio_out"),
433 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
434 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
435 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
436 SUNXI_FUNCTION(0x0, "gpio_in"),
437 SUNXI_FUNCTION(0x1, "gpio_out"),
438 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
439 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
440 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
441 SUNXI_FUNCTION(0x0, "gpio_in"),
442 SUNXI_FUNCTION(0x1, "gpio_out"),
443 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
444 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
445 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
446 SUNXI_FUNCTION(0x0, "gpio_in"),
447 SUNXI_FUNCTION(0x1, "gpio_out"),
448 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
449 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
450 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
451 SUNXI_FUNCTION(0x0, "gpio_in"),
452 SUNXI_FUNCTION(0x1, "gpio_out"),
453 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
454 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
455 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
456 SUNXI_FUNCTION(0x0, "gpio_in"),
457 SUNXI_FUNCTION(0x1, "gpio_out"),
458 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
459 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
460 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
461 SUNXI_FUNCTION(0x0, "gpio_in"),
462 SUNXI_FUNCTION(0x1, "gpio_out"),
463 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
464 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
465 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
466 SUNXI_FUNCTION(0x0, "gpio_in"),
467 SUNXI_FUNCTION(0x1, "gpio_out"),
468 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
469 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
470 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
471 SUNXI_FUNCTION(0x0, "gpio_in"),
472 SUNXI_FUNCTION(0x1, "gpio_out"),
473 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
474 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
475 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
476 SUNXI_FUNCTION(0x0, "gpio_in"),
477 SUNXI_FUNCTION(0x1, "gpio_out"),
478 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
479 SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */
480 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
481 SUNXI_FUNCTION(0x0, "gpio_in"),
482 SUNXI_FUNCTION(0x1, "gpio_out"),
483 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
484 SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */
485 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
486 SUNXI_FUNCTION(0x0, "gpio_in"),
487 SUNXI_FUNCTION(0x1, "gpio_out"),
488 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
489 SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */
490 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
491 SUNXI_FUNCTION(0x0, "gpio_in"),
492 SUNXI_FUNCTION(0x1, "gpio_out"),
493 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
494 SUNXI_FUNCTION(0x3, "sim")), /* DET */
495 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
496 SUNXI_FUNCTION(0x0, "gpio_in"),
497 SUNXI_FUNCTION(0x1, "gpio_out"),
498 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
499 SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */
500 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
501 SUNXI_FUNCTION(0x0, "gpio_in"),
502 SUNXI_FUNCTION(0x1, "gpio_out"),
503 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
504 SUNXI_FUNCTION(0x3, "sim")), /* RST */
505 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
506 SUNXI_FUNCTION(0x0, "gpio_in"),
507 SUNXI_FUNCTION(0x1, "gpio_out"),
508 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
509 SUNXI_FUNCTION(0x3, "sim")), /* SCK */
510 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
511 SUNXI_FUNCTION(0x0, "gpio_in"),
512 SUNXI_FUNCTION(0x1, "gpio_out"),
513 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
514 SUNXI_FUNCTION(0x3, "sim")), /* SDA */
515 /* Hole */
516 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
517 SUNXI_FUNCTION(0x0, "gpio_in"),
518 SUNXI_FUNCTION(0x1, "gpio_out"),
519 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
520 SUNXI_FUNCTION(0x3, "csi0")), /* PCK */
521 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
522 SUNXI_FUNCTION(0x0, "gpio_in"),
523 SUNXI_FUNCTION(0x1, "gpio_out"),
524 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
525 SUNXI_FUNCTION(0x3, "csi0")), /* CK */
526 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
527 SUNXI_FUNCTION(0x0, "gpio_in"),
528 SUNXI_FUNCTION(0x1, "gpio_out"),
529 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
530 SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */
531 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
532 SUNXI_FUNCTION(0x0, "gpio_in"),
533 SUNXI_FUNCTION(0x1, "gpio_out"),
534 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
535 SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */
536 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
537 SUNXI_FUNCTION(0x0, "gpio_in"),
538 SUNXI_FUNCTION(0x1, "gpio_out"),
539 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
540 SUNXI_FUNCTION(0x3, "csi0")), /* D0 */
541 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
542 SUNXI_FUNCTION(0x0, "gpio_in"),
543 SUNXI_FUNCTION(0x1, "gpio_out"),
544 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
545 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
546 SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */
547 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
548 SUNXI_FUNCTION(0x0, "gpio_in"),
549 SUNXI_FUNCTION(0x1, "gpio_out"),
550 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
551 SUNXI_FUNCTION(0x3, "csi0")), /* D2 */
552 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
553 SUNXI_FUNCTION(0x0, "gpio_in"),
554 SUNXI_FUNCTION(0x1, "gpio_out"),
555 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
556 SUNXI_FUNCTION(0x3, "csi0")), /* D3 */
557 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
558 SUNXI_FUNCTION(0x0, "gpio_in"),
559 SUNXI_FUNCTION(0x1, "gpio_out"),
560 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
561 SUNXI_FUNCTION(0x3, "csi0")), /* D4 */
562 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
563 SUNXI_FUNCTION(0x0, "gpio_in"),
564 SUNXI_FUNCTION(0x1, "gpio_out"),
565 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
566 SUNXI_FUNCTION(0x3, "csi0")), /* D5 */
567 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
568 SUNXI_FUNCTION(0x0, "gpio_in"),
569 SUNXI_FUNCTION(0x1, "gpio_out"),
570 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
571 SUNXI_FUNCTION(0x3, "csi0")), /* D6 */
572 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
573 SUNXI_FUNCTION(0x0, "gpio_in"),
574 SUNXI_FUNCTION(0x1, "gpio_out"),
575 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
576 SUNXI_FUNCTION(0x3, "csi0")), /* D7 */
577 /* Hole */
578 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
579 SUNXI_FUNCTION(0x0, "gpio_in"),
580 SUNXI_FUNCTION(0x1, "gpio_out"),
581 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
582 SUNXI_FUNCTION(0x4, "jtag")), /* MSI */
583 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
584 SUNXI_FUNCTION(0x0, "gpio_in"),
585 SUNXI_FUNCTION(0x1, "gpio_out"),
586 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
587 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
588 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
589 SUNXI_FUNCTION(0x0, "gpio_in"),
590 SUNXI_FUNCTION(0x1, "gpio_out"),
591 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
592 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
593 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
594 SUNXI_FUNCTION(0x0, "gpio_in"),
595 SUNXI_FUNCTION(0x1, "gpio_out"),
596 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
597 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
598 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
599 SUNXI_FUNCTION(0x0, "gpio_in"),
600 SUNXI_FUNCTION(0x1, "gpio_out"),
601 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
602 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
603 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
604 SUNXI_FUNCTION(0x0, "gpio_in"),
605 SUNXI_FUNCTION(0x1, "gpio_out"),
606 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
607 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
608 /* Hole */
609 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
610 SUNXI_FUNCTION(0x0, "gpio_in"),
611 SUNXI_FUNCTION(0x1, "gpio_out"),
612 SUNXI_FUNCTION(0x2, "ts1"), /* CLK */
613 SUNXI_FUNCTION(0x3, "csi1"), /* PCK */
614 SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */
615 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
616 SUNXI_FUNCTION(0x0, "gpio_in"),
617 SUNXI_FUNCTION(0x1, "gpio_out"),
618 SUNXI_FUNCTION(0x2, "ts1"), /* ERR */
619 SUNXI_FUNCTION(0x3, "csi1"), /* CK */
620 SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */
621 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
622 SUNXI_FUNCTION(0x0, "gpio_in"),
623 SUNXI_FUNCTION(0x1, "gpio_out"),
624 SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */
625 SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */
626 SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */
627 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
628 SUNXI_FUNCTION(0x0, "gpio_in"),
629 SUNXI_FUNCTION(0x1, "gpio_out"),
630 SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */
631 SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */
632 SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */
633 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
634 SUNXI_FUNCTION(0x0, "gpio_in"),
635 SUNXI_FUNCTION(0x1, "gpio_out"),
636 SUNXI_FUNCTION(0x2, "ts1"), /* D0 */
637 SUNXI_FUNCTION(0x3, "csi1"), /* D0 */
638 SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */
639 SUNXI_FUNCTION(0x5, "csi0")), /* D8 */
640 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
641 SUNXI_FUNCTION(0x0, "gpio_in"),
642 SUNXI_FUNCTION(0x1, "gpio_out"),
643 SUNXI_FUNCTION(0x2, "ts1"), /* D1 */
644 SUNXI_FUNCTION(0x3, "csi1"), /* D1 */
645 SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */
646 SUNXI_FUNCTION(0x5, "csi0")), /* D9 */
647 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
648 SUNXI_FUNCTION(0x0, "gpio_in"),
649 SUNXI_FUNCTION(0x1, "gpio_out"),
650 SUNXI_FUNCTION(0x2, "ts1"), /* D2 */
651 SUNXI_FUNCTION(0x3, "csi1"), /* D2 */
652 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
653 SUNXI_FUNCTION(0x5, "csi0")), /* D10 */
654 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
655 SUNXI_FUNCTION(0x0, "gpio_in"),
656 SUNXI_FUNCTION(0x1, "gpio_out"),
657 SUNXI_FUNCTION(0x2, "ts1"), /* D3 */
658 SUNXI_FUNCTION(0x3, "csi1"), /* D3 */
659 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
660 SUNXI_FUNCTION(0x5, "csi0")), /* D11 */
661 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
662 SUNXI_FUNCTION(0x0, "gpio_in"),
663 SUNXI_FUNCTION(0x1, "gpio_out"),
664 SUNXI_FUNCTION(0x2, "ts1"), /* D4 */
665 SUNXI_FUNCTION(0x3, "csi1"), /* D4 */
666 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
667 SUNXI_FUNCTION(0x5, "csi0")), /* D12 */
668 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
669 SUNXI_FUNCTION(0x0, "gpio_in"),
670 SUNXI_FUNCTION(0x1, "gpio_out"),
671 SUNXI_FUNCTION(0x2, "ts1"), /* D5 */
672 SUNXI_FUNCTION(0x3, "csi1"), /* D5 */
673 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
674 SUNXI_FUNCTION(0x5, "csi0")), /* D13 */
675 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
676 SUNXI_FUNCTION(0x0, "gpio_in"),
677 SUNXI_FUNCTION(0x1, "gpio_out"),
678 SUNXI_FUNCTION(0x2, "ts1"), /* D6 */
679 SUNXI_FUNCTION(0x3, "csi1"), /* D6 */
680 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
681 SUNXI_FUNCTION(0x5, "csi0")), /* D14 */
682 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
683 SUNXI_FUNCTION(0x0, "gpio_in"),
684 SUNXI_FUNCTION(0x1, "gpio_out"),
685 SUNXI_FUNCTION(0x2, "ts1"), /* D7 */
686 SUNXI_FUNCTION(0x3, "csi1"), /* D7 */
687 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
688 SUNXI_FUNCTION(0x5, "csi0")), /* D15 */
689 /* Hole */
690 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
691 SUNXI_FUNCTION(0x0, "gpio_in"),
692 SUNXI_FUNCTION(0x1, "gpio_out"),
693 SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */
694 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
695 SUNXI_FUNCTION_IRQ(0x6, 0), /* EINT0 */
696 SUNXI_FUNCTION(0x7, "csi1")), /* D0 */
697 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
698 SUNXI_FUNCTION(0x0, "gpio_in"),
699 SUNXI_FUNCTION(0x1, "gpio_out"),
700 SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */
701 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
702 SUNXI_FUNCTION_IRQ(0x6, 1), /* EINT1 */
703 SUNXI_FUNCTION(0x7, "csi1")), /* D1 */
704 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
705 SUNXI_FUNCTION(0x0, "gpio_in"),
706 SUNXI_FUNCTION(0x1, "gpio_out"),
707 SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */
708 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
709 SUNXI_FUNCTION_IRQ(0x6, 2), /* EINT2 */
710 SUNXI_FUNCTION(0x7, "csi1")), /* D2 */
711 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
712 SUNXI_FUNCTION(0x0, "gpio_in"),
713 SUNXI_FUNCTION(0x1, "gpio_out"),
714 SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */
715 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
716 SUNXI_FUNCTION_IRQ(0x6, 3), /* EINT3 */
717 SUNXI_FUNCTION(0x7, "csi1")), /* D3 */
718 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
719 SUNXI_FUNCTION(0x0, "gpio_in"),
720 SUNXI_FUNCTION(0x1, "gpio_out"),
721 SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */
722 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
723 SUNXI_FUNCTION_IRQ(0x6, 4), /* EINT4 */
724 SUNXI_FUNCTION(0x7, "csi1")), /* D4 */
725 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
726 SUNXI_FUNCTION(0x0, "gpio_in"),
727 SUNXI_FUNCTION(0x1, "gpio_out"),
728 SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */
729 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
730 SUNXI_FUNCTION_IRQ(0x6, 5), /* EINT5 */
731 SUNXI_FUNCTION(0x7, "csi1")), /* D5 */
732 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
733 SUNXI_FUNCTION(0x0, "gpio_in"),
734 SUNXI_FUNCTION(0x1, "gpio_out"),
735 SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */
736 SUNXI_FUNCTION(0x4, "uart5"), /* TX */
737 SUNXI_FUNCTION(0x5, "ms"), /* BS */
738 SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */
739 SUNXI_FUNCTION(0x7, "csi1")), /* D6 */
740 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
741 SUNXI_FUNCTION(0x0, "gpio_in"),
742 SUNXI_FUNCTION(0x1, "gpio_out"),
743 SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */
744 SUNXI_FUNCTION(0x4, "uart5"), /* RX */
745 SUNXI_FUNCTION(0x5, "ms"), /* CLK */
746 SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */
747 SUNXI_FUNCTION(0x7, "csi1")), /* D7 */
748 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
749 SUNXI_FUNCTION(0x0, "gpio_in"),
750 SUNXI_FUNCTION(0x1, "gpio_out"),
751 SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */
752 SUNXI_FUNCTION(0x3, "emac"), /* ERXD3 */
753 SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */
754 SUNXI_FUNCTION(0x5, "ms"), /* D0 */
755 SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */
756 SUNXI_FUNCTION(0x7, "csi1")), /* D8 */
757 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
758 SUNXI_FUNCTION(0x0, "gpio_in"),
759 SUNXI_FUNCTION(0x1, "gpio_out"),
760 SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */
761 SUNXI_FUNCTION(0x3, "emac"), /* ERXD2 */
762 SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */
763 SUNXI_FUNCTION(0x5, "ms"), /* D1 */
764 SUNXI_FUNCTION_IRQ(0x6, 9), /* EINT9 */
765 SUNXI_FUNCTION(0x7, "csi1")), /* D9 */
766 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
767 SUNXI_FUNCTION(0x0, "gpio_in"),
768 SUNXI_FUNCTION(0x1, "gpio_out"),
769 SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */
770 SUNXI_FUNCTION(0x3, "emac"), /* ERXD1 */
771 SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */
772 SUNXI_FUNCTION(0x5, "ms"), /* D2 */
773 SUNXI_FUNCTION_IRQ(0x6, 10), /* EINT10 */
774 SUNXI_FUNCTION(0x7, "csi1")), /* D10 */
775 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
776 SUNXI_FUNCTION(0x0, "gpio_in"),
777 SUNXI_FUNCTION(0x1, "gpio_out"),
778 SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */
779 SUNXI_FUNCTION(0x3, "emac"), /* ERXD0 */
780 SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */
781 SUNXI_FUNCTION(0x5, "ms"), /* D3 */
782 SUNXI_FUNCTION_IRQ(0x6, 11), /* EINT11 */
783 SUNXI_FUNCTION(0x7, "csi1")), /* D11 */
784 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
785 SUNXI_FUNCTION(0x0, "gpio_in"),
786 SUNXI_FUNCTION(0x1, "gpio_out"),
787 SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */
788 SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */
789 SUNXI_FUNCTION_IRQ(0x6, 12), /* EINT12 */
790 SUNXI_FUNCTION(0x7, "csi1")), /* D12 */
791 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
792 SUNXI_FUNCTION(0x0, "gpio_in"),
793 SUNXI_FUNCTION(0x1, "gpio_out"),
794 SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */
795 SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */
796 SUNXI_FUNCTION(0x5, "sim"), /* RST */
797 SUNXI_FUNCTION_IRQ(0x6, 13), /* EINT13 */
798 SUNXI_FUNCTION(0x7, "csi1")), /* D13 */
799 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
800 SUNXI_FUNCTION(0x0, "gpio_in"),
801 SUNXI_FUNCTION(0x1, "gpio_out"),
802 SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */
803 SUNXI_FUNCTION(0x3, "emac"), /* ETXD3 */
804 SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */
805 SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */
806 SUNXI_FUNCTION_IRQ(0x6, 14), /* EINT14 */
807 SUNXI_FUNCTION(0x7, "csi1")), /* D14 */
808 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
809 SUNXI_FUNCTION(0x0, "gpio_in"),
810 SUNXI_FUNCTION(0x1, "gpio_out"),
811 SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */
812 SUNXI_FUNCTION(0x3, "emac"), /* ETXD3 */
813 SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */
814 SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */
815 SUNXI_FUNCTION_IRQ(0x6, 15), /* EINT15 */
816 SUNXI_FUNCTION(0x7, "csi1")), /* D15 */
817 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
818 SUNXI_FUNCTION(0x0, "gpio_in"),
819 SUNXI_FUNCTION(0x1, "gpio_out"),
820 SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */
821 SUNXI_FUNCTION(0x3, "emac"), /* ETXD2 */
822 SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */
823 SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */
824 SUNXI_FUNCTION(0x7, "csi1")), /* D16 */
825 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
826 SUNXI_FUNCTION(0x0, "gpio_in"),
827 SUNXI_FUNCTION(0x1, "gpio_out"),
828 SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */
829 SUNXI_FUNCTION(0x3, "emac"), /* ETXD1 */
830 SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */
831 SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */
832 SUNXI_FUNCTION_IRQ(0x6, 17), /* EINT17 */
833 SUNXI_FUNCTION(0x7, "csi1")), /* D17 */
834 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
835 SUNXI_FUNCTION(0x0, "gpio_in"),
836 SUNXI_FUNCTION(0x1, "gpio_out"),
837 SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */
838 SUNXI_FUNCTION(0x3, "emac"), /* ETXD0 */
839 SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */
840 SUNXI_FUNCTION(0x5, "sim"), /* SCK */
841 SUNXI_FUNCTION_IRQ(0x6, 18), /* EINT18 */
842 SUNXI_FUNCTION(0x7, "csi1")), /* D18 */
843 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
844 SUNXI_FUNCTION(0x0, "gpio_in"),
845 SUNXI_FUNCTION(0x1, "gpio_out"),
846 SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */
847 SUNXI_FUNCTION(0x3, "emac"), /* ERXERR */
848 SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */
849 SUNXI_FUNCTION(0x5, "sim"), /* SDA */
850 SUNXI_FUNCTION_IRQ(0x6, 19), /* EINT19 */
851 SUNXI_FUNCTION(0x7, "csi1")), /* D19 */
852 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
853 SUNXI_FUNCTION(0x0, "gpio_in"),
854 SUNXI_FUNCTION(0x1, "gpio_out"),
855 SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */
856 SUNXI_FUNCTION(0x3, "emac"), /* ERXDV */
857 SUNXI_FUNCTION(0x4, "can"), /* TX */
858 SUNXI_FUNCTION_IRQ(0x6, 20), /* EINT20 */
859 SUNXI_FUNCTION(0x7, "csi1")), /* D20 */
860 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
861 SUNXI_FUNCTION(0x0, "gpio_in"),
862 SUNXI_FUNCTION(0x1, "gpio_out"),
863 SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */
864 SUNXI_FUNCTION(0x3, "emac"), /* EMDC */
865 SUNXI_FUNCTION(0x4, "can"), /* RX */
866 SUNXI_FUNCTION_IRQ(0x6, 21), /* EINT21 */
867 SUNXI_FUNCTION(0x7, "csi1")), /* D21 */
868 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22),
869 SUNXI_FUNCTION(0x0, "gpio_in"),
870 SUNXI_FUNCTION(0x1, "gpio_out"),
871 SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */
872 SUNXI_FUNCTION(0x3, "emac"), /* EMDIO */
873 SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */
874 SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */
875 SUNXI_FUNCTION(0x7, "csi1")), /* D22 */
876 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23),
877 SUNXI_FUNCTION(0x0, "gpio_in"),
878 SUNXI_FUNCTION(0x1, "gpio_out"),
879 SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */
880 SUNXI_FUNCTION(0x3, "emac"), /* ETXEN */
881 SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */
882 SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */
883 SUNXI_FUNCTION(0x7, "csi1")), /* D23 */
884 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24),
885 SUNXI_FUNCTION(0x0, "gpio_in"),
886 SUNXI_FUNCTION(0x1, "gpio_out"),
887 SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */
888 SUNXI_FUNCTION(0x3, "emac"), /* ETXCK */
889 SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */
890 SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */
891 SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */
892 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25),
893 SUNXI_FUNCTION(0x0, "gpio_in"),
894 SUNXI_FUNCTION(0x1, "gpio_out"),
895 SUNXI_FUNCTION(0x2, "lcd1"), /* DE */
896 SUNXI_FUNCTION(0x3, "emac"), /* ECRS */
897 SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */
898 SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */
899 SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */
900 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26),
901 SUNXI_FUNCTION(0x0, "gpio_in"),
902 SUNXI_FUNCTION(0x1, "gpio_out"),
903 SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */
904 SUNXI_FUNCTION(0x3, "emac"), /* ECOL */
905 SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */
906 SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */
907 SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */
908 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27),
909 SUNXI_FUNCTION(0x0, "gpio_in"),
910 SUNXI_FUNCTION(0x1, "gpio_out"),
911 SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */
912 SUNXI_FUNCTION(0x3, "emac"), /* ETXERR */
913 SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */
914 SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */
915 SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */
916 /* Hole */
917 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 0),
918 SUNXI_FUNCTION(0x0, "gpio_in"),
919 SUNXI_FUNCTION(0x1, "gpio_out"),
920 SUNXI_FUNCTION(0x3, "i2c3")), /* SCK */
921 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 1),
922 SUNXI_FUNCTION(0x0, "gpio_in"),
923 SUNXI_FUNCTION(0x1, "gpio_out"),
924 SUNXI_FUNCTION(0x3, "i2c3")), /* SDA */
925 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 2),
926 SUNXI_FUNCTION(0x0, "gpio_in"),
927 SUNXI_FUNCTION(0x1, "gpio_out"),
928 SUNXI_FUNCTION(0x3, "i2c4")), /* SCK */
929 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 3),
930 SUNXI_FUNCTION(0x0, "gpio_in"),
931 SUNXI_FUNCTION(0x1, "gpio_out"),
932 SUNXI_FUNCTION(0x2, "pwm"), /* PWM1 */
933 SUNXI_FUNCTION(0x3, "i2c4")), /* SDA */
934 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 4),
935 SUNXI_FUNCTION(0x0, "gpio_in"),
936 SUNXI_FUNCTION(0x1, "gpio_out"),
937 SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */
938 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 5),
939 SUNXI_FUNCTION(0x0, "gpio_in"),
940 SUNXI_FUNCTION(0x1, "gpio_out"),
941 SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */
942 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 6),
943 SUNXI_FUNCTION(0x0, "gpio_in"),
944 SUNXI_FUNCTION(0x1, "gpio_out"),
945 SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */
946 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 7),
947 SUNXI_FUNCTION(0x0, "gpio_in"),
948 SUNXI_FUNCTION(0x1, "gpio_out"),
949 SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */
950 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 8),
951 SUNXI_FUNCTION(0x0, "gpio_in"),
952 SUNXI_FUNCTION(0x1, "gpio_out"),
953 SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */
954 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 9),
955 SUNXI_FUNCTION(0x0, "gpio_in"),
956 SUNXI_FUNCTION(0x1, "gpio_out"),
957 SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */
958 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 10),
959 SUNXI_FUNCTION(0x0, "gpio_in"),
960 SUNXI_FUNCTION(0x1, "gpio_out"),
961 SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
962 SUNXI_FUNCTION(0x3, "uart5"), /* TX */
963 SUNXI_FUNCTION_IRQ(0x5, 22)), /* EINT22 */
964 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11),
965 SUNXI_FUNCTION(0x0, "gpio_in"),
966 SUNXI_FUNCTION(0x1, "gpio_out"),
967 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
968 SUNXI_FUNCTION(0x3, "uart5"), /* RX */
969 SUNXI_FUNCTION_IRQ(0x5, 23)), /* EINT23 */
970 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12),
971 SUNXI_FUNCTION(0x0, "gpio_in"),
972 SUNXI_FUNCTION(0x1, "gpio_out"),
973 SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
974 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
975 SUNXI_FUNCTION(0x4, "clk_out_a"), /* CLK_OUT_A */
976 SUNXI_FUNCTION_IRQ(0x5, 24)), /* EINT24 */
977 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
978 SUNXI_FUNCTION(0x0, "gpio_in"),
979 SUNXI_FUNCTION(0x1, "gpio_out"),
980 SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
981 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
982 SUNXI_FUNCTION(0x4, "clk_out_b"), /* CLK_OUT_B */
983 SUNXI_FUNCTION_IRQ(0x5, 25)), /* EINT25 */
984 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
985 SUNXI_FUNCTION(0x0, "gpio_in"),
986 SUNXI_FUNCTION(0x1, "gpio_out"),
987 SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
988 SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
989 SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */
990 SUNXI_FUNCTION_IRQ(0x5, 26)), /* EINT26 */
991 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15),
992 SUNXI_FUNCTION(0x0, "gpio_in"),
993 SUNXI_FUNCTION(0x1, "gpio_out"),
994 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
995 SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
996 SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */
997 SUNXI_FUNCTION_IRQ(0x5, 27)), /* EINT27 */
998 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16),
999 SUNXI_FUNCTION(0x0, "gpio_in"),
1000 SUNXI_FUNCTION(0x1, "gpio_out"),
1001 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
1002 SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
1003 SUNXI_FUNCTION_IRQ(0x5, 28)), /* EINT28 */
1004 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 17),
1005 SUNXI_FUNCTION(0x0, "gpio_in"),
1006 SUNXI_FUNCTION(0x1, "gpio_out"),
1007 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
1008 SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
1009 SUNXI_FUNCTION_IRQ(0x5, 29)), /* EINT29 */
1010 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18),
1011 SUNXI_FUNCTION(0x0, "gpio_in"),
1012 SUNXI_FUNCTION(0x1, "gpio_out"),
1013 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
1014 SUNXI_FUNCTION(0x3, "uart2"), /* TX */
1015 SUNXI_FUNCTION_IRQ(0x5, 30)), /* EINT30 */
1016 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19),
1017 SUNXI_FUNCTION(0x0, "gpio_in"),
1018 SUNXI_FUNCTION(0x1, "gpio_out"),
1019 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
1020 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
1021 SUNXI_FUNCTION_IRQ(0x5, 31)), /* EINT31 */
1022 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 20),
1023 SUNXI_FUNCTION(0x0, "gpio_in"),
1024 SUNXI_FUNCTION(0x1, "gpio_out"),
1025 SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */
1026 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
1027 SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */
1028 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 21),
1029 SUNXI_FUNCTION(0x0, "gpio_in"),
1030 SUNXI_FUNCTION(0x1, "gpio_out"),
1031 SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */
1032 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
1033 SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */
1034};
1035
1036static const struct sunxi_pinctrl_desc sun7i_a20_pinctrl_data = {
1037 .pins = sun7i_a20_pins,
1038 .npins = ARRAY_SIZE(sun7i_a20_pins),
1039};
1040
1041static int sun7i_a20_pinctrl_probe(struct platform_device *pdev)
1042{
1043 return sunxi_pinctrl_init(pdev,
1044 &sun7i_a20_pinctrl_data);
1045}
1046
1047static struct of_device_id sun7i_a20_pinctrl_match[] = {
1048 { .compatible = "allwinner,sun7i-a20-pinctrl", },
1049 {}
1050};
1051MODULE_DEVICE_TABLE(of, sun7i_a20_pinctrl_match);
1052
1053static struct platform_driver sun7i_a20_pinctrl_driver = {
1054 .probe = sun7i_a20_pinctrl_probe,
1055 .driver = {
1056 .name = "sun7i-a20-pinctrl",
1057 .owner = THIS_MODULE,
1058 .of_match_table = sun7i_a20_pinctrl_match,
1059 },
1060};
1061module_platform_driver(sun7i_a20_pinctrl_driver);
1062
1063MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
1064MODULE_DESCRIPTION("Allwinner A20 pinctrl driver");
1065MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index f086509a28d3..f6522b54ece9 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -26,12 +26,10 @@
26#include <linux/pinctrl/pinconf-generic.h> 26#include <linux/pinctrl/pinconf-generic.h>
27#include <linux/pinctrl/pinmux.h> 27#include <linux/pinctrl/pinmux.h>
28#include <linux/platform_device.h> 28#include <linux/platform_device.h>
29#include <linux/reset.h>
30#include <linux/slab.h> 29#include <linux/slab.h>
31 30
32#include "core.h" 31#include "../core.h"
33#include "pinctrl-sunxi.h" 32#include "pinctrl-sunxi.h"
34#include "pinctrl-sunxi-pins.h"
35 33
36static struct sunxi_pinctrl_group * 34static struct sunxi_pinctrl_group *
37sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group) 35sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
@@ -673,17 +671,6 @@ static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc)
673 } 671 }
674} 672}
675 673
676static struct of_device_id sunxi_pinctrl_match[] = {
677 { .compatible = "allwinner,sun4i-a10-pinctrl", .data = (void *)&sun4i_a10_pinctrl_data },
678 { .compatible = "allwinner,sun5i-a10s-pinctrl", .data = (void *)&sun5i_a10s_pinctrl_data },
679 { .compatible = "allwinner,sun5i-a13-pinctrl", .data = (void *)&sun5i_a13_pinctrl_data },
680 { .compatible = "allwinner,sun6i-a31-pinctrl", .data = (void *)&sun6i_a31_pinctrl_data },
681 { .compatible = "allwinner,sun6i-a31-r-pinctrl", .data = (void *)&sun6i_a31_r_pinctrl_data },
682 { .compatible = "allwinner,sun7i-a20-pinctrl", .data = (void *)&sun7i_a20_pinctrl_data },
683 {}
684};
685MODULE_DEVICE_TABLE(of, sunxi_pinctrl_match);
686
687static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl, 674static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
688 const char *name) 675 const char *name)
689{ 676{
@@ -787,13 +774,13 @@ static int sunxi_pinctrl_build_state(struct platform_device *pdev)
787 return 0; 774 return 0;
788} 775}
789 776
790static int sunxi_pinctrl_probe(struct platform_device *pdev) 777int sunxi_pinctrl_init(struct platform_device *pdev,
778 const struct sunxi_pinctrl_desc *desc)
791{ 779{
792 struct device_node *node = pdev->dev.of_node; 780 struct device_node *node = pdev->dev.of_node;
793 const struct of_device_id *device;
794 struct pinctrl_pin_desc *pins; 781 struct pinctrl_pin_desc *pins;
795 struct sunxi_pinctrl *pctl; 782 struct sunxi_pinctrl *pctl;
796 struct reset_control *rstc; 783 struct resource *res;
797 int i, ret, last_pin; 784 int i, ret, last_pin;
798 struct clk *clk; 785 struct clk *clk;
799 786
@@ -804,15 +791,12 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
804 791
805 spin_lock_init(&pctl->lock); 792 spin_lock_init(&pctl->lock);
806 793
807 pctl->membase = of_iomap(node, 0); 794 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
808 if (!pctl->membase) 795 pctl->membase = devm_ioremap_resource(&pdev->dev, res);
809 return -ENOMEM; 796 if (IS_ERR(pctl->membase))
797 return PTR_ERR(pctl->membase);
810 798
811 device = of_match_device(sunxi_pinctrl_match, &pdev->dev); 799 pctl->desc = desc;
812 if (!device)
813 return -ENODEV;
814
815 pctl->desc = (struct sunxi_pinctrl_desc *)device->data;
816 800
817 ret = sunxi_pinctrl_build_state(pdev); 801 ret = sunxi_pinctrl_build_state(pdev);
818 if (ret) { 802 if (ret) {
@@ -889,17 +873,10 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
889 if (ret) 873 if (ret)
890 goto gpiochip_error; 874 goto gpiochip_error;
891 875
892 rstc = devm_reset_control_get_optional(&pdev->dev, NULL);
893 if (!IS_ERR(rstc)) {
894 ret = reset_control_deassert(rstc);
895 if (ret)
896 goto clk_error;
897 }
898
899 pctl->irq = irq_of_parse_and_map(node, 0); 876 pctl->irq = irq_of_parse_and_map(node, 0);
900 if (!pctl->irq) { 877 if (!pctl->irq) {
901 ret = -EINVAL; 878 ret = -EINVAL;
902 goto rstc_error; 879 goto clk_error;
903 } 880 }
904 881
905 pctl->domain = irq_domain_add_linear(node, SUNXI_IRQ_NUMBER, 882 pctl->domain = irq_domain_add_linear(node, SUNXI_IRQ_NUMBER,
@@ -907,7 +884,7 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
907 if (!pctl->domain) { 884 if (!pctl->domain) {
908 dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); 885 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
909 ret = -ENOMEM; 886 ret = -ENOMEM;
910 goto rstc_error; 887 goto clk_error;
911 } 888 }
912 889
913 for (i = 0; i < SUNXI_IRQ_NUMBER; i++) { 890 for (i = 0; i < SUNXI_IRQ_NUMBER; i++) {
@@ -925,9 +902,6 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
925 902
926 return 0; 903 return 0;
927 904
928rstc_error:
929 if (!IS_ERR(rstc))
930 reset_control_assert(rstc);
931clk_error: 905clk_error:
932 clk_disable_unprepare(clk); 906 clk_disable_unprepare(clk);
933gpiochip_error: 907gpiochip_error:
@@ -937,17 +911,3 @@ pinctrl_error:
937 pinctrl_unregister(pctl->pctl_dev); 911 pinctrl_unregister(pctl->pctl_dev);
938 return ret; 912 return ret;
939} 913}
940
941static struct platform_driver sunxi_pinctrl_driver = {
942 .probe = sunxi_pinctrl_probe,
943 .driver = {
944 .name = "sunxi-pinctrl",
945 .owner = THIS_MODULE,
946 .of_match_table = sunxi_pinctrl_match,
947 },
948};
949module_platform_driver(sunxi_pinctrl_driver);
950
951MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
952MODULE_DESCRIPTION("Allwinner A1X pinctrl driver");
953MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
new file mode 100644
index 000000000000..8169ba598876
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
@@ -0,0 +1,258 @@
1/*
2 * Allwinner A1X SoCs pinctrl driver.
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#ifndef __PINCTRL_SUNXI_H
14#define __PINCTRL_SUNXI_H
15
16#include <linux/kernel.h>
17#include <linux/spinlock.h>
18
19#define PA_BASE 0
20#define PB_BASE 32
21#define PC_BASE 64
22#define PD_BASE 96
23#define PE_BASE 128
24#define PF_BASE 160
25#define PG_BASE 192
26#define PH_BASE 224
27#define PI_BASE 256
28#define PL_BASE 352
29#define PM_BASE 384
30
31#define SUNXI_PINCTRL_PIN(bank, pin) \
32 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
33
34#define SUNXI_PIN_NAME_MAX_LEN 5
35
36#define BANK_MEM_SIZE 0x24
37#define MUX_REGS_OFFSET 0x0
38#define DATA_REGS_OFFSET 0x10
39#define DLEVEL_REGS_OFFSET 0x14
40#define PULL_REGS_OFFSET 0x1c
41
42#define PINS_PER_BANK 32
43#define MUX_PINS_PER_REG 8
44#define MUX_PINS_BITS 4
45#define MUX_PINS_MASK 0x0f
46#define DATA_PINS_PER_REG 32
47#define DATA_PINS_BITS 1
48#define DATA_PINS_MASK 0x01
49#define DLEVEL_PINS_PER_REG 16
50#define DLEVEL_PINS_BITS 2
51#define DLEVEL_PINS_MASK 0x03
52#define PULL_PINS_PER_REG 16
53#define PULL_PINS_BITS 2
54#define PULL_PINS_MASK 0x03
55
56#define SUNXI_IRQ_NUMBER 32
57
58#define IRQ_CFG_REG 0x200
59#define IRQ_CFG_IRQ_PER_REG 8
60#define IRQ_CFG_IRQ_BITS 4
61#define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1)
62#define IRQ_CTRL_REG 0x210
63#define IRQ_CTRL_IRQ_PER_REG 32
64#define IRQ_CTRL_IRQ_BITS 1
65#define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1)
66#define IRQ_STATUS_REG 0x214
67#define IRQ_STATUS_IRQ_PER_REG 32
68#define IRQ_STATUS_IRQ_BITS 1
69#define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
70
71#define IRQ_EDGE_RISING 0x00
72#define IRQ_EDGE_FALLING 0x01
73#define IRQ_LEVEL_HIGH 0x02
74#define IRQ_LEVEL_LOW 0x03
75#define IRQ_EDGE_BOTH 0x04
76
77struct sunxi_desc_function {
78 const char *name;
79 u8 muxval;
80 u8 irqnum;
81};
82
83struct sunxi_desc_pin {
84 struct pinctrl_pin_desc pin;
85 struct sunxi_desc_function *functions;
86};
87
88struct sunxi_pinctrl_desc {
89 const struct sunxi_desc_pin *pins;
90 int npins;
91 unsigned pin_base;
92};
93
94struct sunxi_pinctrl_function {
95 const char *name;
96 const char **groups;
97 unsigned ngroups;
98};
99
100struct sunxi_pinctrl_group {
101 const char *name;
102 unsigned long config;
103 unsigned pin;
104};
105
106struct sunxi_pinctrl {
107 void __iomem *membase;
108 struct gpio_chip *chip;
109 const struct sunxi_pinctrl_desc *desc;
110 struct device *dev;
111 struct irq_domain *domain;
112 struct sunxi_pinctrl_function *functions;
113 unsigned nfunctions;
114 struct sunxi_pinctrl_group *groups;
115 unsigned ngroups;
116 int irq;
117 int irq_array[SUNXI_IRQ_NUMBER];
118 spinlock_t lock;
119 struct pinctrl_dev *pctl_dev;
120};
121
122#define SUNXI_PIN(_pin, ...) \
123 { \
124 .pin = _pin, \
125 .functions = (struct sunxi_desc_function[]){ \
126 __VA_ARGS__, { } }, \
127 }
128
129#define SUNXI_FUNCTION(_val, _name) \
130 { \
131 .name = _name, \
132 .muxval = _val, \
133 }
134
135#define SUNXI_FUNCTION_IRQ(_val, _irq) \
136 { \
137 .name = "irq", \
138 .muxval = _val, \
139 .irqnum = _irq, \
140 }
141
142/*
143 * The sunXi PIO registers are organized as is:
144 * 0x00 - 0x0c Muxing values.
145 * 8 pins per register, each pin having a 4bits value
146 * 0x10 Pin values
147 * 32 bits per register, each pin corresponding to one bit
148 * 0x14 - 0x18 Drive level
149 * 16 pins per register, each pin having a 2bits value
150 * 0x1c - 0x20 Pull-Up values
151 * 16 pins per register, each pin having a 2bits value
152 *
153 * This is for the first bank. Each bank will have the same layout,
154 * with an offset being a multiple of 0x24.
155 *
156 * The following functions calculate from the pin number the register
157 * and the bit offset that we should access.
158 */
159static inline u32 sunxi_mux_reg(u16 pin)
160{
161 u8 bank = pin / PINS_PER_BANK;
162 u32 offset = bank * BANK_MEM_SIZE;
163 offset += MUX_REGS_OFFSET;
164 offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04;
165 return round_down(offset, 4);
166}
167
168static inline u32 sunxi_mux_offset(u16 pin)
169{
170 u32 pin_num = pin % MUX_PINS_PER_REG;
171 return pin_num * MUX_PINS_BITS;
172}
173
174static inline u32 sunxi_data_reg(u16 pin)
175{
176 u8 bank = pin / PINS_PER_BANK;
177 u32 offset = bank * BANK_MEM_SIZE;
178 offset += DATA_REGS_OFFSET;
179 offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04;
180 return round_down(offset, 4);
181}
182
183static inline u32 sunxi_data_offset(u16 pin)
184{
185 u32 pin_num = pin % DATA_PINS_PER_REG;
186 return pin_num * DATA_PINS_BITS;
187}
188
189static inline u32 sunxi_dlevel_reg(u16 pin)
190{
191 u8 bank = pin / PINS_PER_BANK;
192 u32 offset = bank * BANK_MEM_SIZE;
193 offset += DLEVEL_REGS_OFFSET;
194 offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04;
195 return round_down(offset, 4);
196}
197
198static inline u32 sunxi_dlevel_offset(u16 pin)
199{
200 u32 pin_num = pin % DLEVEL_PINS_PER_REG;
201 return pin_num * DLEVEL_PINS_BITS;
202}
203
204static inline u32 sunxi_pull_reg(u16 pin)
205{
206 u8 bank = pin / PINS_PER_BANK;
207 u32 offset = bank * BANK_MEM_SIZE;
208 offset += PULL_REGS_OFFSET;
209 offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04;
210 return round_down(offset, 4);
211}
212
213static inline u32 sunxi_pull_offset(u16 pin)
214{
215 u32 pin_num = pin % PULL_PINS_PER_REG;
216 return pin_num * PULL_PINS_BITS;
217}
218
219static inline u32 sunxi_irq_cfg_reg(u16 irq)
220{
221 u8 reg = irq / IRQ_CFG_IRQ_PER_REG * 0x04;
222 return reg + IRQ_CFG_REG;
223}
224
225static inline u32 sunxi_irq_cfg_offset(u16 irq)
226{
227 u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
228 return irq_num * IRQ_CFG_IRQ_BITS;
229}
230
231static inline u32 sunxi_irq_ctrl_reg(u16 irq)
232{
233 u8 reg = irq / IRQ_CTRL_IRQ_PER_REG * 0x04;
234 return reg + IRQ_CTRL_REG;
235}
236
237static inline u32 sunxi_irq_ctrl_offset(u16 irq)
238{
239 u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
240 return irq_num * IRQ_CTRL_IRQ_BITS;
241}
242
243static inline u32 sunxi_irq_status_reg(u16 irq)
244{
245 u8 reg = irq / IRQ_STATUS_IRQ_PER_REG * 0x04;
246 return reg + IRQ_STATUS_REG;
247}
248
249static inline u32 sunxi_irq_status_offset(u16 irq)
250{
251 u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
252 return irq_num * IRQ_STATUS_IRQ_BITS;
253}
254
255int sunxi_pinctrl_init(struct platform_device *pdev,
256 const struct sunxi_pinctrl_desc *desc);
257
258#endif /* __PINCTRL_SUNXI_H */
generated by cgit v1.2.2 (git 2.25.0) at 2026-05-27 10:54:04 -0400