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authorNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>2016-11-12 11:04:27 -0500
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2017-01-19 14:17:57 -0500
commit5e1595223a2c703b810c567b3071a6cc87af5890 (patch)
treed4fb7a92db7a042738fd78723240408473884f55 /drivers/pinctrl
parentb01bbf221fcc26764c8845c7c6ebd66c230b9157 (diff)
pinctrl: sh-pfc: r8a7795: Use lookup function for bias data
commit d3b861bccdee2fa9963a2b6c64f74a8d752b9315 upstream. There is a bug in the r8a7795 bias code where a WARN() is trigged anytime a pin from PUEN0/PUD0 is accessed. # cat /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins WARNING: CPU: 2 PID: 2391 at drivers/pinctrl/sh-pfc/pfc-r8a7795.c:5364 r8a7795_pinmux_get_bias+0xbc/0xc8 [..] Call trace: [<ffff0000083c442c>] r8a7795_pinmux_get_bias+0xbc/0xc8 [<ffff0000083c37f4>] sh_pfc_pinconf_get+0x194/0x270 [<ffff0000083b0768>] pin_config_get_for_pin+0x20/0x30 [<ffff0000083b11e8>] pinconf_generic_dump_one+0x168/0x188 [<ffff0000083b144c>] pinconf_generic_dump_pins+0x5c/0x98 [<ffff0000083b0628>] pinconf_pins_show+0xc8/0x128 [<ffff0000081fe3bc>] seq_read+0x16c/0x420 [<ffff00000831a110>] full_proxy_read+0x58/0x88 [<ffff0000081d7ad4>] __vfs_read+0x1c/0xf8 [<ffff0000081d8874>] vfs_read+0x84/0x148 [<ffff0000081d9d64>] SyS_read+0x44/0xa0 [<ffff000008082f4c>] __sys_trace_return+0x0/0x4 This is due to the WARN() check if the reg field of the pullups struct is zero, and this should be 0 for pins controlled by the PUEN0/PUD0 registers since PU0 is defined as 0. Change the data structure and use the generic sh_pfc_pin_to_bias_info() function to get the register offset and bit information. Fixes: 560655247b627ac7 ("pinctrl: sh-pfc: r8a7795: Add bias pinconf support") Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7795.c343
1 files changed, 172 insertions, 171 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 2e8cc2adbed7..84cee66b1e08 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -5188,184 +5188,183 @@ static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
5188#define PU5 0x14 5188#define PU5 0x14
5189#define PU6 0x18 5189#define PU6 0x18
5190 5190
5191static const struct { 5191static const struct sh_pfc_bias_info bias_info[] = {
5192 u16 reg : 11; 5192 { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */
5193 u16 bit : 5; 5193 { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */
5194} pullups[] = { 5194 { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */
5195 [RCAR_GP_PIN(2, 11)] = { PU0, 31 }, /* AVB_PHY_INT */ 5195
5196 [RCAR_GP_PIN(2, 10)] = { PU0, 30 }, /* AVB_MAGIC */ 5196 { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */
5197 [RCAR_GP_PIN(2, 9)] = { PU0, 29 }, /* AVB_MDC */ 5197 { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */
5198 5198 { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */
5199 [RCAR_GP_PIN(1, 19)] = { PU1, 31 }, /* A19 */ 5199 { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */
5200 [RCAR_GP_PIN(1, 18)] = { PU1, 30 }, /* A18 */ 5200 { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */
5201 [RCAR_GP_PIN(1, 17)] = { PU1, 29 }, /* A17 */ 5201 { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */
5202 [RCAR_GP_PIN(1, 16)] = { PU1, 28 }, /* A16 */ 5202 { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */
5203 [RCAR_GP_PIN(1, 15)] = { PU1, 27 }, /* A15 */ 5203 { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */
5204 [RCAR_GP_PIN(1, 14)] = { PU1, 26 }, /* A14 */ 5204 { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */
5205 [RCAR_GP_PIN(1, 13)] = { PU1, 25 }, /* A13 */ 5205 { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */
5206 [RCAR_GP_PIN(1, 12)] = { PU1, 24 }, /* A12 */ 5206 { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */
5207 [RCAR_GP_PIN(1, 11)] = { PU1, 23 }, /* A11 */ 5207 { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */
5208 [RCAR_GP_PIN(1, 10)] = { PU1, 22 }, /* A10 */ 5208 { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */
5209 [RCAR_GP_PIN(1, 9)] = { PU1, 21 }, /* A9 */ 5209 { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */
5210 [RCAR_GP_PIN(1, 8)] = { PU1, 20 }, /* A8 */ 5210 { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */
5211 [RCAR_GP_PIN(1, 7)] = { PU1, 19 }, /* A7 */ 5211 { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */
5212 [RCAR_GP_PIN(1, 6)] = { PU1, 18 }, /* A6 */ 5212 { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */
5213 [RCAR_GP_PIN(1, 5)] = { PU1, 17 }, /* A5 */ 5213 { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */
5214 [RCAR_GP_PIN(1, 4)] = { PU1, 16 }, /* A4 */ 5214 { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */
5215 [RCAR_GP_PIN(1, 3)] = { PU1, 15 }, /* A3 */ 5215 { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */
5216 [RCAR_GP_PIN(1, 2)] = { PU1, 14 }, /* A2 */ 5216 { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */
5217 [RCAR_GP_PIN(1, 1)] = { PU1, 13 }, /* A1 */ 5217 { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */
5218 [RCAR_GP_PIN(1, 0)] = { PU1, 12 }, /* A0 */ 5218 { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */
5219 [RCAR_GP_PIN(2, 8)] = { PU1, 11 }, /* PWM2_A */ 5219 { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */
5220 [RCAR_GP_PIN(2, 7)] = { PU1, 10 }, /* PWM1_A */ 5220 { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */
5221 [RCAR_GP_PIN(2, 6)] = { PU1, 9 }, /* PWM0 */ 5221 { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */
5222 [RCAR_GP_PIN(2, 5)] = { PU1, 8 }, /* IRQ5 */ 5222 { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */
5223 [RCAR_GP_PIN(2, 4)] = { PU1, 7 }, /* IRQ4 */ 5223 { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */
5224 [RCAR_GP_PIN(2, 3)] = { PU1, 6 }, /* IRQ3 */ 5224 { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */
5225 [RCAR_GP_PIN(2, 2)] = { PU1, 5 }, /* IRQ2 */ 5225 { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
5226 [RCAR_GP_PIN(2, 1)] = { PU1, 4 }, /* IRQ1 */ 5226 { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */
5227 [RCAR_GP_PIN(2, 0)] = { PU1, 3 }, /* IRQ0 */ 5227 { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */
5228 [RCAR_GP_PIN(2, 14)] = { PU1, 2 }, /* AVB_AVTP_CAPTURE_A */ 5228
5229 [RCAR_GP_PIN(2, 13)] = { PU1, 1 }, /* AVB_AVTP_MATCH_A */ 5229 { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */
5230 [RCAR_GP_PIN(2, 12)] = { PU1, 0 }, /* AVB_LINK */ 5230 { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */
5231 5231 { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */
5232 [RCAR_GP_PIN(7, 3)] = { PU2, 29 }, /* HDMI1_CEC */ 5232 { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */
5233 [RCAR_GP_PIN(7, 2)] = { PU2, 28 }, /* HDMI0_CEC */ 5233 { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */
5234 [RCAR_GP_PIN(7, 1)] = { PU2, 27 }, /* AVS2 */ 5234 { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */
5235 [RCAR_GP_PIN(7, 0)] = { PU2, 26 }, /* AVS1 */ 5235 { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */
5236 [RCAR_GP_PIN(0, 15)] = { PU2, 25 }, /* D15 */ 5236 { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */
5237 [RCAR_GP_PIN(0, 14)] = { PU2, 24 }, /* D14 */ 5237 { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */
5238 [RCAR_GP_PIN(0, 13)] = { PU2, 23 }, /* D13 */ 5238 { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */
5239 [RCAR_GP_PIN(0, 12)] = { PU2, 22 }, /* D12 */ 5239 { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */
5240 [RCAR_GP_PIN(0, 11)] = { PU2, 21 }, /* D11 */ 5240 { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */
5241 [RCAR_GP_PIN(0, 10)] = { PU2, 20 }, /* D10 */ 5241 { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */
5242 [RCAR_GP_PIN(0, 9)] = { PU2, 19 }, /* D9 */ 5242 { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */
5243 [RCAR_GP_PIN(0, 8)] = { PU2, 18 }, /* D8 */ 5243 { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */
5244 [RCAR_GP_PIN(0, 7)] = { PU2, 17 }, /* D7 */ 5244 { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */
5245 [RCAR_GP_PIN(0, 6)] = { PU2, 16 }, /* D6 */ 5245 { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */
5246 [RCAR_GP_PIN(0, 5)] = { PU2, 15 }, /* D5 */ 5246 { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */
5247 [RCAR_GP_PIN(0, 4)] = { PU2, 14 }, /* D4 */ 5247 { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */
5248 [RCAR_GP_PIN(0, 3)] = { PU2, 13 }, /* D3 */ 5248 { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */
5249 [RCAR_GP_PIN(0, 2)] = { PU2, 12 }, /* D2 */ 5249 { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */
5250 [RCAR_GP_PIN(0, 1)] = { PU2, 11 }, /* D1 */ 5250 { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */
5251 [RCAR_GP_PIN(0, 0)] = { PU2, 10 }, /* D0 */ 5251 { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */
5252 [RCAR_GP_PIN(1, 27)] = { PU2, 8 }, /* EX_WAIT0_A */ 5252 { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */
5253 [RCAR_GP_PIN(1, 26)] = { PU2, 7 }, /* WE1_N */ 5253 { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */
5254 [RCAR_GP_PIN(1, 25)] = { PU2, 6 }, /* WE0_N */ 5254 { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */
5255 [RCAR_GP_PIN(1, 24)] = { PU2, 5 }, /* RD_WR_N */ 5255 { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */
5256 [RCAR_GP_PIN(1, 23)] = { PU2, 4 }, /* RD_N */ 5256 { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */
5257 [RCAR_GP_PIN(1, 22)] = { PU2, 3 }, /* BS_N */ 5257
5258 [RCAR_GP_PIN(1, 21)] = { PU2, 2 }, /* CS1_N_A26 */ 5258 { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */
5259 [RCAR_GP_PIN(1, 20)] = { PU2, 1 }, /* CS0_N */ 5259 { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */
5260 5260 { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */
5261 [RCAR_GP_PIN(4, 9)] = { PU3, 31 }, /* SD3_DAT0 */ 5261 { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */
5262 [RCAR_GP_PIN(4, 8)] = { PU3, 30 }, /* SD3_CMD */ 5262 { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */
5263 [RCAR_GP_PIN(4, 7)] = { PU3, 29 }, /* SD3_CLK */ 5263 { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */
5264 [RCAR_GP_PIN(4, 6)] = { PU3, 28 }, /* SD2_DS */ 5264 { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */
5265 [RCAR_GP_PIN(4, 5)] = { PU3, 27 }, /* SD2_DAT3 */ 5265 { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */
5266 [RCAR_GP_PIN(4, 4)] = { PU3, 26 }, /* SD2_DAT2 */ 5266 { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */
5267 [RCAR_GP_PIN(4, 3)] = { PU3, 25 }, /* SD2_DAT1 */ 5267 { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */
5268 [RCAR_GP_PIN(4, 2)] = { PU3, 24 }, /* SD2_DAT0 */ 5268 { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */
5269 [RCAR_GP_PIN(4, 1)] = { PU3, 23 }, /* SD2_CMD */ 5269 { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */
5270 [RCAR_GP_PIN(4, 0)] = { PU3, 22 }, /* SD2_CLK */ 5270 { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */
5271 [RCAR_GP_PIN(3, 11)] = { PU3, 21 }, /* SD1_DAT3 */ 5271 { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */
5272 [RCAR_GP_PIN(3, 10)] = { PU3, 20 }, /* SD1_DAT2 */ 5272 { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */
5273 [RCAR_GP_PIN(3, 9)] = { PU3, 19 }, /* SD1_DAT1 */ 5273 { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */
5274 [RCAR_GP_PIN(3, 8)] = { PU3, 18 }, /* SD1_DAT0 */ 5274 { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */
5275 [RCAR_GP_PIN(3, 7)] = { PU3, 17 }, /* SD1_CMD */ 5275 { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */
5276 [RCAR_GP_PIN(3, 6)] = { PU3, 16 }, /* SD1_CLK */ 5276 { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */
5277 [RCAR_GP_PIN(3, 5)] = { PU3, 15 }, /* SD0_DAT3 */ 5277 { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */
5278 [RCAR_GP_PIN(3, 4)] = { PU3, 14 }, /* SD0_DAT2 */ 5278 { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */
5279 [RCAR_GP_PIN(3, 3)] = { PU3, 13 }, /* SD0_DAT1 */ 5279 { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */
5280 [RCAR_GP_PIN(3, 2)] = { PU3, 12 }, /* SD0_DAT0 */ 5280
5281 [RCAR_GP_PIN(3, 1)] = { PU3, 11 }, /* SD0_CMD */ 5281 { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */
5282 [RCAR_GP_PIN(3, 0)] = { PU3, 10 }, /* SD0_CLK */ 5282 { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */
5283 5283 { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */
5284 [RCAR_GP_PIN(5, 19)] = { PU4, 31 }, /* MSIOF0_SS1 */ 5284 { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */
5285 [RCAR_GP_PIN(5, 18)] = { PU4, 30 }, /* MSIOF0_SYNC */ 5285 { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */
5286 [RCAR_GP_PIN(5, 17)] = { PU4, 29 }, /* MSIOF0_SCK */ 5286 { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */
5287 [RCAR_GP_PIN(5, 16)] = { PU4, 28 }, /* HRTS0_N */ 5287 { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */
5288 [RCAR_GP_PIN(5, 15)] = { PU4, 27 }, /* HCTS0_N */ 5288 { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */
5289 [RCAR_GP_PIN(5, 14)] = { PU4, 26 }, /* HTX0 */ 5289 { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */
5290 [RCAR_GP_PIN(5, 13)] = { PU4, 25 }, /* HRX0 */ 5290 { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */
5291 [RCAR_GP_PIN(5, 12)] = { PU4, 24 }, /* HSCK0 */ 5291 { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */
5292 [RCAR_GP_PIN(5, 11)] = { PU4, 23 }, /* RX2_A */ 5292 { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */
5293 [RCAR_GP_PIN(5, 10)] = { PU4, 22 }, /* TX2_A */ 5293 { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */
5294 [RCAR_GP_PIN(5, 9)] = { PU4, 21 }, /* SCK2 */ 5294 { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */
5295 [RCAR_GP_PIN(5, 8)] = { PU4, 20 }, /* RTS1_N_TANS */ 5295 { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */
5296 [RCAR_GP_PIN(5, 7)] = { PU4, 19 }, /* CTS1_N */ 5296 { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */
5297 [RCAR_GP_PIN(5, 6)] = { PU4, 18 }, /* TX1_A */ 5297 { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */
5298 [RCAR_GP_PIN(5, 5)] = { PU4, 17 }, /* RX1_A */ 5298 { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */
5299 [RCAR_GP_PIN(5, 4)] = { PU4, 16 }, /* RTS0_N_TANS */ 5299 { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */
5300 [RCAR_GP_PIN(5, 3)] = { PU4, 15 }, /* CTS0_N */ 5300 { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */
5301 [RCAR_GP_PIN(5, 2)] = { PU4, 14 }, /* TX0 */ 5301 { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */
5302 [RCAR_GP_PIN(5, 1)] = { PU4, 13 }, /* RX0 */ 5302 { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */
5303 [RCAR_GP_PIN(5, 0)] = { PU4, 12 }, /* SCK0 */ 5303 { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */
5304 [RCAR_GP_PIN(3, 15)] = { PU4, 11 }, /* SD1_WP */ 5304 { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */
5305 [RCAR_GP_PIN(3, 14)] = { PU4, 10 }, /* SD1_CD */ 5305 { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */
5306 [RCAR_GP_PIN(3, 13)] = { PU4, 9 }, /* SD0_WP */ 5306 { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */
5307 [RCAR_GP_PIN(3, 12)] = { PU4, 8 }, /* SD0_CD */ 5307 { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */
5308 [RCAR_GP_PIN(4, 17)] = { PU4, 7 }, /* SD3_DS */ 5308 { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */
5309 [RCAR_GP_PIN(4, 16)] = { PU4, 6 }, /* SD3_DAT7 */ 5309 { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */
5310 [RCAR_GP_PIN(4, 15)] = { PU4, 5 }, /* SD3_DAT6 */ 5310 { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */
5311 [RCAR_GP_PIN(4, 14)] = { PU4, 4 }, /* SD3_DAT5 */ 5311 { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */
5312 [RCAR_GP_PIN(4, 13)] = { PU4, 3 }, /* SD3_DAT4 */ 5312 { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */
5313 [RCAR_GP_PIN(4, 12)] = { PU4, 2 }, /* SD3_DAT3 */ 5313
5314 [RCAR_GP_PIN(4, 11)] = { PU4, 1 }, /* SD3_DAT2 */ 5314 { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */
5315 [RCAR_GP_PIN(4, 10)] = { PU4, 0 }, /* SD3_DAT1 */ 5315 { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */
5316 5316 { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */
5317 [RCAR_GP_PIN(6, 24)] = { PU5, 31 }, /* USB0_PWEN */ 5317 { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */
5318 [RCAR_GP_PIN(6, 23)] = { PU5, 30 }, /* AUDIO_CLKB_B */ 5318 { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */
5319 [RCAR_GP_PIN(6, 22)] = { PU5, 29 }, /* AUDIO_CLKA_A */ 5319 { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */
5320 [RCAR_GP_PIN(6, 21)] = { PU5, 28 }, /* SSI_SDATA9_A */ 5320 { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */
5321 [RCAR_GP_PIN(6, 20)] = { PU5, 27 }, /* SSI_SDATA8 */ 5321 { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */
5322 [RCAR_GP_PIN(6, 19)] = { PU5, 26 }, /* SSI_SDATA7 */ 5322 { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */
5323 [RCAR_GP_PIN(6, 18)] = { PU5, 25 }, /* SSI_WS78 */ 5323 { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */
5324 [RCAR_GP_PIN(6, 17)] = { PU5, 24 }, /* SSI_SCK78 */ 5324 { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */
5325 [RCAR_GP_PIN(6, 16)] = { PU5, 23 }, /* SSI_SDATA6 */ 5325 { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */
5326 [RCAR_GP_PIN(6, 15)] = { PU5, 22 }, /* SSI_WS6 */ 5326 { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */
5327 [RCAR_GP_PIN(6, 14)] = { PU5, 21 }, /* SSI_SCK6 */ 5327 { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */
5328 [RCAR_GP_PIN(6, 13)] = { PU5, 20 }, /* SSI_SDATA5 */ 5328 { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */
5329 [RCAR_GP_PIN(6, 12)] = { PU5, 19 }, /* SSI_WS5 */ 5329 { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */
5330 [RCAR_GP_PIN(6, 11)] = { PU5, 18 }, /* SSI_SCK5 */ 5330 { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */
5331 [RCAR_GP_PIN(6, 10)] = { PU5, 17 }, /* SSI_SDATA4 */ 5331 { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */
5332 [RCAR_GP_PIN(6, 9)] = { PU5, 16 }, /* SSI_WS4 */ 5332 { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS34 */
5333 [RCAR_GP_PIN(6, 8)] = { PU5, 15 }, /* SSI_SCK4 */ 5333 { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK34 */
5334 [RCAR_GP_PIN(6, 7)] = { PU5, 14 }, /* SSI_SDATA3 */ 5334 { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */
5335 [RCAR_GP_PIN(6, 6)] = { PU5, 13 }, /* SSI_WS34 */ 5335 { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */
5336 [RCAR_GP_PIN(6, 5)] = { PU5, 12 }, /* SSI_SCK34 */ 5336 { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */
5337 [RCAR_GP_PIN(6, 4)] = { PU5, 11 }, /* SSI_SDATA2_A */ 5337 { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */
5338 [RCAR_GP_PIN(6, 3)] = { PU5, 10 }, /* SSI_SDATA1_A */ 5338 { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */
5339 [RCAR_GP_PIN(6, 2)] = { PU5, 9 }, /* SSI_SDATA0 */ 5339 { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */
5340 [RCAR_GP_PIN(6, 1)] = { PU5, 8 }, /* SSI_WS01239 */ 5340 { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */
5341 [RCAR_GP_PIN(6, 0)] = { PU5, 7 }, /* SSI_SCK01239 */ 5341 { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */
5342 [RCAR_GP_PIN(5, 25)] = { PU5, 5 }, /* MLB_DAT */ 5342 { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */
5343 [RCAR_GP_PIN(5, 24)] = { PU5, 4 }, /* MLB_SIG */ 5343 { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */
5344 [RCAR_GP_PIN(5, 23)] = { PU5, 3 }, /* MLB_CLK */ 5344 { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */
5345 [RCAR_GP_PIN(5, 22)] = { PU5, 2 }, /* MSIOF0_RXD */ 5345
5346 [RCAR_GP_PIN(5, 21)] = { PU5, 1 }, /* MSIOF0_SS2 */ 5346 { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB31_OVC */
5347 [RCAR_GP_PIN(5, 20)] = { PU5, 0 }, /* MSIOF0_TXD */ 5347 { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB31_PWEN */
5348 5348 { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */
5349 [RCAR_GP_PIN(6, 31)] = { PU6, 6 }, /* USB31_OVC */ 5349 { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */
5350 [RCAR_GP_PIN(6, 30)] = { PU6, 5 }, /* USB31_PWEN */ 5350 { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */
5351 [RCAR_GP_PIN(6, 29)] = { PU6, 4 }, /* USB30_OVC */ 5351 { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */
5352 [RCAR_GP_PIN(6, 28)] = { PU6, 3 }, /* USB30_PWEN */ 5352 { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */
5353 [RCAR_GP_PIN(6, 27)] = { PU6, 2 }, /* USB1_OVC */
5354 [RCAR_GP_PIN(6, 26)] = { PU6, 1 }, /* USB1_PWEN */
5355 [RCAR_GP_PIN(6, 25)] = { PU6, 0 }, /* USB0_OVC */
5356}; 5353};
5357 5354
5358static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc, 5355static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
5359 unsigned int pin) 5356 unsigned int pin)
5360{ 5357{
5358 const struct sh_pfc_bias_info *info;
5361 u32 reg; 5359 u32 reg;
5362 u32 bit; 5360 u32 bit;
5363 5361
5364 if (WARN_ON_ONCE(!pullups[pin].reg)) 5362 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
5363 if (!info)
5365 return PIN_CONFIG_BIAS_DISABLE; 5364 return PIN_CONFIG_BIAS_DISABLE;
5366 5365
5367 reg = pullups[pin].reg; 5366 reg = info->reg;
5368 bit = BIT(pullups[pin].bit); 5367 bit = BIT(info->bit);
5369 5368
5370 if (sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit) { 5369 if (sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit) {
5371 if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit) 5370 if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
@@ -5379,15 +5378,17 @@ static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
5379static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, 5378static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
5380 unsigned int bias) 5379 unsigned int bias)
5381{ 5380{
5381 const struct sh_pfc_bias_info *info;
5382 u32 enable, updown; 5382 u32 enable, updown;
5383 u32 reg; 5383 u32 reg;
5384 u32 bit; 5384 u32 bit;
5385 5385
5386 if (WARN_ON_ONCE(!pullups[pin].reg)) 5386 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
5387 if (!info)
5387 return; 5388 return;
5388 5389
5389 reg = pullups[pin].reg; 5390 reg = info->reg;
5390 bit = BIT(pullups[pin].bit); 5391 bit = BIT(info->bit);
5391 5392
5392 enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit; 5393 enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
5393 if (bias != PIN_CONFIG_BIAS_DISABLE) 5394 if (bias != PIN_CONFIG_BIAS_DISABLE)
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-26 21:48:04 -0400