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authorLinus Torvalds <torvalds@linux-foundation.org>2014-10-07 20:56:28 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-10-07 20:56:28 -0400
commit2b425a3f112aa24666fc5f415c8bf0e9132bb6c0 (patch)
treea99433c188dd5632ad496caff3608dc273940bf4 /drivers/pinctrl
parentc91662cb18f00f225c74816353f222b6997131ca (diff)
parent2cdef8f4e1ac28adc81326758a7767c18479a95d (diff)
Merge tag 'pinctrl-v3.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control changes from Linus Walleij: "This is the bulk of pin control changes for the v3.18 development series: - New drivers for the Freescale i.MX21, Qualcomm APQ8084 pin controllers. - Incremental new features on the Rockchip, atlas 6, OMAP, AM437x, APQ8064, prima2, AT91, Tegra, i.MX, Berlin and Nomadik. - Push Freescale drivers down into their own subdirectory. - Assorted sprays of syntax and semantic fixes" * tag 'pinctrl-v3.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (48 commits) pinctrl: specify bindings for pins and groups pinctrl: nomadik: improve GPIO debug prints pinctrl: abx500: refactor DT parser to take two paths pinctrl: abx500: use helpers for map allocation/free pinctrl: alter device tree bindings for functions pinctrl: nomadik: refactor DT parser to take two paths pinctrl: nomadik: use utils map free function pinctrl: nomadik: use util function to reserve maps pinctrl: qcom: use restart_notifier mechanism for ps_hold pinctrl: sh-pfc: sh73a0: Remove unnecessary SoC data allocation pinctrl: berlin: fix the dt_free_map function pinctrl: at91: disable PD or PU before enabling PU or PD pinctrl: st: remove gpiochip in failure cases pinctrl: at91: Fix error handling while doing gpiochio_irqchip_add pinctrl: at91: Fix failure path in at91_gpio_probe path pinctrl: lantiq: Release gpiochip resources in fail case pinctrl: imx: detect uninitialized pins pinctrl: tegra: Add MIPI pad control pinctrl: at91: Switch to using managed clk_get pinctrl: adi2: Remove duplicate gpiochip_remove_pin_ranges ...
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/Kconfig103
-rw-r--r--drivers/pinctrl/Makefile23
-rw-r--r--drivers/pinctrl/berlin/berlin.c29
-rw-r--r--drivers/pinctrl/freescale/Kconfig108
-rw-r--r--drivers/pinctrl/freescale/Makefile19
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx.c (renamed from drivers/pinctrl/pinctrl-imx.c)17
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx.h (renamed from drivers/pinctrl/pinctrl-imx.h)7
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx1-core.c (renamed from drivers/pinctrl/pinctrl-imx1-core.c)8
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx1.c (renamed from drivers/pinctrl/pinctrl-imx1.c)0
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx1.h (renamed from drivers/pinctrl/pinctrl-imx1.h)0
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx21.c342
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx23.c (renamed from drivers/pinctrl/pinctrl-imx23.c)2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx25.c (renamed from drivers/pinctrl/pinctrl-imx25.c)2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx27.c (renamed from drivers/pinctrl/pinctrl-imx27.c)2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx28.c (renamed from drivers/pinctrl/pinctrl-imx28.c)2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx35.c (renamed from drivers/pinctrl/pinctrl-imx35.c)2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx50.c (renamed from drivers/pinctrl/pinctrl-imx50.c)2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx51.c (renamed from drivers/pinctrl/pinctrl-imx51.c)2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx53.c (renamed from drivers/pinctrl/pinctrl-imx53.c)2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx6dl.c (renamed from drivers/pinctrl/pinctrl-imx6dl.c)2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx6q.c (renamed from drivers/pinctrl/pinctrl-imx6q.c)2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx6sl.c (renamed from drivers/pinctrl/pinctrl-imx6sl.c)3
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx6sx.c (renamed from drivers/pinctrl/pinctrl-imx6sx.c)2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-mxs.c (renamed from drivers/pinctrl/pinctrl-mxs.c)8
-rw-r--r--drivers/pinctrl/freescale/pinctrl-mxs.h (renamed from drivers/pinctrl/pinctrl-mxs.h)0
-rw-r--r--drivers/pinctrl/freescale/pinctrl-vf610.c (renamed from drivers/pinctrl/pinctrl-vf610.c)2
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-mvebu.c6
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-abx500.c99
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-nomadik.c142
-rw-r--r--drivers/pinctrl/pinctrl-adi2.c7
-rw-r--r--drivers/pinctrl/pinctrl-as3722.c4
-rw-r--r--drivers/pinctrl/pinctrl-at91.c212
-rw-r--r--drivers/pinctrl/pinctrl-bcm281xx.c8
-rw-r--r--drivers/pinctrl/pinctrl-bcm2835.c4
-rw-r--r--drivers/pinctrl/pinctrl-lantiq.c8
-rw-r--r--drivers/pinctrl/pinctrl-palmas.c5
-rw-r--r--drivers/pinctrl/pinctrl-rockchip.c6
-rw-r--r--drivers/pinctrl/pinctrl-single.c18
-rw-r--r--drivers/pinctrl/pinctrl-st.c7
-rw-r--r--drivers/pinctrl/pinctrl-tb10x.c4
-rw-r--r--drivers/pinctrl/pinctrl-tegra-xusb.c8
-rw-r--r--drivers/pinctrl/pinctrl-tegra.c7
-rw-r--r--drivers/pinctrl/pinctrl-tegra114.c2
-rw-r--r--drivers/pinctrl/pinctrl-tegra124.c69
-rw-r--r--drivers/pinctrl/pinctrl-tegra20.c2
-rw-r--r--drivers/pinctrl/pinctrl-tegra30.c2
-rw-r--r--drivers/pinctrl/pinctrl-tz1090-pdc.c7
-rw-r--r--drivers/pinctrl/pinctrl-tz1090.c6
-rw-r--r--drivers/pinctrl/pinctrl-u300.c6
-rw-r--r--drivers/pinctrl/pinctrl-xway.c2
-rw-r--r--drivers/pinctrl/pinmux.c10
-rw-r--r--drivers/pinctrl/qcom/Kconfig8
-rw-r--r--drivers/pinctrl/qcom/Makefile1
-rw-r--r--drivers/pinctrl/qcom/pinctrl-apq8064.c9
-rw-r--r--drivers/pinctrl/qcom/pinctrl-apq8084.c1245
-rw-r--r--drivers/pinctrl/qcom/pinctrl-ipq8064.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm.c49
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm.h3
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm8960.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm8x74.c2
-rw-r--r--drivers/pinctrl/samsung/pinctrl-exynos5440.c7
-rw-r--r--drivers/pinctrl/samsung/pinctrl-samsung.c7
-rw-r--r--drivers/pinctrl/sh-pfc/core.c10
-rw-r--r--drivers/pinctrl/sh-pfc/core.h1
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a73a4.c4
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7740.c4
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7372.c4
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh73a0.c23
-rw-r--r--drivers/pinctrl/sh-pfc/pinctrl.c6
-rw-r--r--drivers/pinctrl/sh-pfc/sh_pfc.h1
-rw-r--r--drivers/pinctrl/sirf/pinctrl-atlas6.c129
-rw-r--r--drivers/pinctrl/sirf/pinctrl-prima2.c173
-rw-r--r--drivers/pinctrl/sirf/pinctrl-sirf.c72
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear.c4
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear1310.c2
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear1340.c2
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear300.c2
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear310.c2
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear320.c2
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sunxi.c8
-rw-r--r--drivers/pinctrl/vt8500/pinctrl-wmt.c8
81 files changed, 2561 insertions, 573 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index bfd2c2e9f6cd..64d06b52f98a 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -97,95 +97,6 @@ config PINCTRL_BCM281XX
97 BCM28145, and BCM28155 SoCs. This driver requires the pinctrl 97 BCM28145, and BCM28155 SoCs. This driver requires the pinctrl
98 framework. GPIO is provided by a separate GPIO driver. 98 framework. GPIO is provided by a separate GPIO driver.
99 99
100config PINCTRL_IMX
101 bool
102 select PINMUX
103 select PINCONF
104
105config PINCTRL_IMX1_CORE
106 bool
107 select PINMUX
108 select PINCONF
109
110config PINCTRL_IMX1
111 bool "IMX1 pinctrl driver"
112 depends on SOC_IMX1
113 select PINCTRL_IMX1_CORE
114 help
115 Say Y here to enable the imx1 pinctrl driver
116
117config PINCTRL_IMX27
118 bool "IMX27 pinctrl driver"
119 depends on SOC_IMX27
120 select PINCTRL_IMX1_CORE
121 help
122 Say Y here to enable the imx27 pinctrl driver
123
124
125config PINCTRL_IMX25
126 bool "IMX25 pinctrl driver"
127 depends on OF
128 depends on SOC_IMX25
129 select PINCTRL_IMX
130 help
131 Say Y here to enable the imx25 pinctrl driver
132
133config PINCTRL_IMX35
134 bool "IMX35 pinctrl driver"
135 depends on SOC_IMX35
136 select PINCTRL_IMX
137 help
138 Say Y here to enable the imx35 pinctrl driver
139
140config PINCTRL_IMX50
141 bool "IMX50 pinctrl driver"
142 depends on SOC_IMX50
143 select PINCTRL_IMX
144 help
145 Say Y here to enable the imx50 pinctrl driver
146
147config PINCTRL_IMX51
148 bool "IMX51 pinctrl driver"
149 depends on SOC_IMX51
150 select PINCTRL_IMX
151 help
152 Say Y here to enable the imx51 pinctrl driver
153
154config PINCTRL_IMX53
155 bool "IMX53 pinctrl driver"
156 depends on SOC_IMX53
157 select PINCTRL_IMX
158 help
159 Say Y here to enable the imx53 pinctrl driver
160
161config PINCTRL_IMX6Q
162 bool "IMX6Q/DL pinctrl driver"
163 depends on SOC_IMX6Q
164 select PINCTRL_IMX
165 help
166 Say Y here to enable the imx6q/dl pinctrl driver
167
168config PINCTRL_IMX6SL
169 bool "IMX6SL pinctrl driver"
170 depends on SOC_IMX6SL
171 select PINCTRL_IMX
172 help
173 Say Y here to enable the imx6sl pinctrl driver
174
175config PINCTRL_IMX6SX
176 bool "IMX6SX pinctrl driver"
177 depends on SOC_IMX6SX
178 select PINCTRL_IMX
179 help
180 Say Y here to enable the imx6sx pinctrl driver
181
182config PINCTRL_VF610
183 bool "Freescale Vybrid VF610 pinctrl driver"
184 depends on SOC_VF610
185 select PINCTRL_IMX
186 help
187 Say Y here to enable the Freescale Vybrid VF610 pinctrl driver
188
189config PINCTRL_LANTIQ 100config PINCTRL_LANTIQ
190 bool 101 bool
191 depends on LANTIQ 102 depends on LANTIQ
@@ -197,19 +108,6 @@ config PINCTRL_FALCON
197 depends on SOC_FALCON 108 depends on SOC_FALCON
198 depends on PINCTRL_LANTIQ 109 depends on PINCTRL_LANTIQ
199 110
200config PINCTRL_MXS
201 bool
202 select PINMUX
203 select PINCONF
204
205config PINCTRL_IMX23
206 bool
207 select PINCTRL_MXS
208
209config PINCTRL_IMX28
210 bool
211 select PINCTRL_MXS
212
213config PINCTRL_ROCKCHIP 111config PINCTRL_ROCKCHIP
214 bool 112 bool
215 select PINMUX 113 select PINMUX
@@ -306,6 +204,7 @@ config PINCTRL_PALMAS
306 TPS65913, TPS80036 etc. 204 TPS65913, TPS80036 etc.
307 205
308source "drivers/pinctrl/berlin/Kconfig" 206source "drivers/pinctrl/berlin/Kconfig"
207source "drivers/pinctrl/freescale/Kconfig"
309source "drivers/pinctrl/mvebu/Kconfig" 208source "drivers/pinctrl/mvebu/Kconfig"
310source "drivers/pinctrl/nomadik/Kconfig" 209source "drivers/pinctrl/nomadik/Kconfig"
311source "drivers/pinctrl/qcom/Kconfig" 210source "drivers/pinctrl/qcom/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 05d227508c95..51f52d32859e 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -17,23 +17,7 @@ obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
17obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o 17obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
18obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o 18obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
19obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o 19obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
20obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
21obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
22obj-$(CONFIG_PINCTRL_IMX1) += pinctrl-imx1.o
23obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o
24obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o
25obj-$(CONFIG_PINCTRL_IMX50) += pinctrl-imx50.o
26obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o
27obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
28obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
29obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o
30obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o
31obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o
32obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o 20obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
33obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
34obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
35obj-$(CONFIG_PINCTRL_IMX25) += pinctrl-imx25.o
36obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
37obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o 21obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
38obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o 22obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
39obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o 23obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
@@ -52,15 +36,14 @@ obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
52obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o 36obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
53obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o 37obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o
54obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o 38obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
55obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
56 39
57obj-$(CONFIG_ARCH_BERLIN) += berlin/ 40obj-$(CONFIG_ARCH_BERLIN) += berlin/
41obj-y += freescale/
58obj-$(CONFIG_PLAT_ORION) += mvebu/ 42obj-$(CONFIG_PLAT_ORION) += mvebu/
59obj-y += nomadik/ 43obj-y += nomadik/
60obj-$(CONFIG_ARCH_QCOM) += qcom/ 44obj-$(CONFIG_ARCH_QCOM) += qcom/
61obj-$(CONFIG_PLAT_SAMSUNG) += samsung/ 45obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/
62obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/ 46obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/
63obj-$(CONFIG_SUPERH) += sh-pfc/
64obj-$(CONFIG_PLAT_SPEAR) += spear/ 47obj-$(CONFIG_PLAT_SPEAR) += spear/
65obj-$(CONFIG_ARCH_SUNXI) += sunxi/ 48obj-$(CONFIG_ARCH_SUNXI) += sunxi/
66obj-$(CONFIG_ARCH_VT8500) += vt8500/ 49obj-$(CONFIG_ARCH_VT8500) += vt8500/
diff --git a/drivers/pinctrl/berlin/berlin.c b/drivers/pinctrl/berlin/berlin.c
index 86db2235ab00..7f0b0f93242b 100644
--- a/drivers/pinctrl/berlin/berlin.c
+++ b/drivers/pinctrl/berlin/berlin.c
@@ -99,30 +99,11 @@ static int berlin_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrl_dev,
99 return 0; 99 return 0;
100} 100}
101 101
102static void berlin_pinctrl_dt_free_map(struct pinctrl_dev *pctrl_dev,
103 struct pinctrl_map *map,
104 unsigned nmaps)
105{
106 int i;
107
108 for (i = 0; i < nmaps; i++) {
109 if (map[i].type == PIN_MAP_TYPE_MUX_GROUP) {
110 kfree(map[i].data.mux.group);
111
112 /* a function can be applied to multiple groups */
113 if (i == 0)
114 kfree(map[i].data.mux.function);
115 }
116 }
117
118 kfree(map);
119}
120
121static const struct pinctrl_ops berlin_pinctrl_ops = { 102static const struct pinctrl_ops berlin_pinctrl_ops = {
122 .get_groups_count = &berlin_pinctrl_get_group_count, 103 .get_groups_count = &berlin_pinctrl_get_group_count,
123 .get_group_name = &berlin_pinctrl_get_group_name, 104 .get_group_name = &berlin_pinctrl_get_group_name,
124 .dt_node_to_map = &berlin_pinctrl_dt_node_to_map, 105 .dt_node_to_map = &berlin_pinctrl_dt_node_to_map,
125 .dt_free_map = &berlin_pinctrl_dt_free_map, 106 .dt_free_map = &pinctrl_utils_dt_free_map,
126}; 107};
127 108
128static int berlin_pinmux_get_functions_count(struct pinctrl_dev *pctrl_dev) 109static int berlin_pinmux_get_functions_count(struct pinctrl_dev *pctrl_dev)
@@ -170,9 +151,9 @@ berlin_pinctrl_find_function_by_name(struct berlin_pinctrl *pctrl,
170 return NULL; 151 return NULL;
171} 152}
172 153
173static int berlin_pinmux_enable(struct pinctrl_dev *pctrl_dev, 154static int berlin_pinmux_set(struct pinctrl_dev *pctrl_dev,
174 unsigned function, 155 unsigned function,
175 unsigned group) 156 unsigned group)
176{ 157{
177 struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev); 158 struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
178 const struct berlin_desc_group *group_desc = pctrl->desc->groups + group; 159 const struct berlin_desc_group *group_desc = pctrl->desc->groups + group;
@@ -197,7 +178,7 @@ static const struct pinmux_ops berlin_pinmux_ops = {
197 .get_functions_count = &berlin_pinmux_get_functions_count, 178 .get_functions_count = &berlin_pinmux_get_functions_count,
198 .get_function_name = &berlin_pinmux_get_function_name, 179 .get_function_name = &berlin_pinmux_get_function_name,
199 .get_function_groups = &berlin_pinmux_get_function_groups, 180 .get_function_groups = &berlin_pinmux_get_function_groups,
200 .enable = &berlin_pinmux_enable, 181 .set_mux = &berlin_pinmux_set,
201}; 182};
202 183
203static int berlin_pinctrl_add_function(struct berlin_pinctrl *pctrl, 184static int berlin_pinctrl_add_function(struct berlin_pinctrl *pctrl,
diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig
new file mode 100644
index 000000000000..16aac38793fe
--- /dev/null
+++ b/drivers/pinctrl/freescale/Kconfig
@@ -0,0 +1,108 @@
1config PINCTRL_IMX
2 bool
3 select PINMUX
4 select PINCONF
5
6config PINCTRL_IMX1_CORE
7 bool
8 select PINMUX
9 select PINCONF
10
11config PINCTRL_IMX1
12 bool "IMX1 pinctrl driver"
13 depends on SOC_IMX1
14 select PINCTRL_IMX1_CORE
15 help
16 Say Y here to enable the imx1 pinctrl driver
17
18config PINCTRL_IMX21
19 bool "i.MX21 pinctrl driver"
20 depends on SOC_IMX21
21 select PINCTRL_IMX1_CORE
22 help
23 Say Y here to enable the i.MX21 pinctrl driver
24
25config PINCTRL_IMX27
26 bool "IMX27 pinctrl driver"
27 depends on SOC_IMX27
28 select PINCTRL_IMX1_CORE
29 help
30 Say Y here to enable the imx27 pinctrl driver
31
32
33config PINCTRL_IMX25
34 bool "IMX25 pinctrl driver"
35 depends on OF
36 depends on SOC_IMX25
37 select PINCTRL_IMX
38 help
39 Say Y here to enable the imx25 pinctrl driver
40
41config PINCTRL_IMX35
42 bool "IMX35 pinctrl driver"
43 depends on SOC_IMX35
44 select PINCTRL_IMX
45 help
46 Say Y here to enable the imx35 pinctrl driver
47
48config PINCTRL_IMX50
49 bool "IMX50 pinctrl driver"
50 depends on SOC_IMX50
51 select PINCTRL_IMX
52 help
53 Say Y here to enable the imx50 pinctrl driver
54
55config PINCTRL_IMX51
56 bool "IMX51 pinctrl driver"
57 depends on SOC_IMX51
58 select PINCTRL_IMX
59 help
60 Say Y here to enable the imx51 pinctrl driver
61
62config PINCTRL_IMX53
63 bool "IMX53 pinctrl driver"
64 depends on SOC_IMX53
65 select PINCTRL_IMX
66 help
67 Say Y here to enable the imx53 pinctrl driver
68
69config PINCTRL_IMX6Q
70 bool "IMX6Q/DL pinctrl driver"
71 depends on SOC_IMX6Q
72 select PINCTRL_IMX
73 help
74 Say Y here to enable the imx6q/dl pinctrl driver
75
76config PINCTRL_IMX6SL
77 bool "IMX6SL pinctrl driver"
78 depends on SOC_IMX6SL
79 select PINCTRL_IMX
80 help
81 Say Y here to enable the imx6sl pinctrl driver
82
83config PINCTRL_IMX6SX
84 bool "IMX6SX pinctrl driver"
85 depends on SOC_IMX6SX
86 select PINCTRL_IMX
87 help
88 Say Y here to enable the imx6sx pinctrl driver
89
90config PINCTRL_VF610
91 bool "Freescale Vybrid VF610 pinctrl driver"
92 depends on SOC_VF610
93 select PINCTRL_IMX
94 help
95 Say Y here to enable the Freescale Vybrid VF610 pinctrl driver
96
97config PINCTRL_MXS
98 bool
99 select PINMUX
100 select PINCONF
101
102config PINCTRL_IMX23
103 bool
104 select PINCTRL_MXS
105
106config PINCTRL_IMX28
107 bool
108 select PINCTRL_MXS
diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile
new file mode 100644
index 000000000000..bba73c22f043
--- /dev/null
+++ b/drivers/pinctrl/freescale/Makefile
@@ -0,0 +1,19 @@
1# Freescale pin control drivers
2obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
3obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
4obj-$(CONFIG_PINCTRL_IMX1) += pinctrl-imx1.o
5obj-$(CONFIG_PINCTRL_IMX21) += pinctrl-imx21.o
6obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o
7obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o
8obj-$(CONFIG_PINCTRL_IMX50) += pinctrl-imx50.o
9obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o
10obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
11obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
12obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o
13obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o
14obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o
15obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
16obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
17obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
18obj-$(CONFIG_PINCTRL_IMX25) += pinctrl-imx25.o
19obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
index 946d594a64dd..f2446769247f 100644
--- a/drivers/pinctrl/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -24,7 +24,7 @@
24#include <linux/pinctrl/pinmux.h> 24#include <linux/pinctrl/pinmux.h>
25#include <linux/slab.h> 25#include <linux/slab.h>
26 26
27#include "core.h" 27#include "../core.h"
28#include "pinctrl-imx.h" 28#include "pinctrl-imx.h"
29 29
30/* The bits in CONFIG cell defined in binding doc*/ 30/* The bits in CONFIG cell defined in binding doc*/
@@ -179,8 +179,8 @@ static const struct pinctrl_ops imx_pctrl_ops = {
179 179
180}; 180};
181 181
182static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, 182static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
183 unsigned group) 183 unsigned group)
184{ 184{
185 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 185 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
186 const struct imx_pinctrl_soc_info *info = ipctl->info; 186 const struct imx_pinctrl_soc_info *info = ipctl->info;
@@ -204,7 +204,7 @@ static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
204 pin_id = pin->pin; 204 pin_id = pin->pin;
205 pin_reg = &info->pin_regs[pin_id]; 205 pin_reg = &info->pin_regs[pin_id];
206 206
207 if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->mux_reg) { 207 if (pin_reg->mux_reg == -1) {
208 dev_err(ipctl->dev, "Pin(%s) does not support mux function\n", 208 dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
209 info->pins[pin_id].name); 209 info->pins[pin_id].name);
210 return -EINVAL; 210 return -EINVAL;
@@ -298,7 +298,7 @@ static const struct pinmux_ops imx_pmx_ops = {
298 .get_functions_count = imx_pmx_get_funcs_count, 298 .get_functions_count = imx_pmx_get_funcs_count,
299 .get_function_name = imx_pmx_get_func_name, 299 .get_function_name = imx_pmx_get_func_name,
300 .get_function_groups = imx_pmx_get_groups, 300 .get_function_groups = imx_pmx_get_groups,
301 .enable = imx_pmx_enable, 301 .set_mux = imx_pmx_set,
302}; 302};
303 303
304static int imx_pinconf_get(struct pinctrl_dev *pctldev, 304static int imx_pinconf_get(struct pinctrl_dev *pctldev,
@@ -308,7 +308,7 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev,
308 const struct imx_pinctrl_soc_info *info = ipctl->info; 308 const struct imx_pinctrl_soc_info *info = ipctl->info;
309 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; 309 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
310 310
311 if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) { 311 if (pin_reg->conf_reg == -1) {
312 dev_err(info->dev, "Pin(%s) does not support config function\n", 312 dev_err(info->dev, "Pin(%s) does not support config function\n",
313 info->pins[pin_id].name); 313 info->pins[pin_id].name);
314 return -EINVAL; 314 return -EINVAL;
@@ -331,7 +331,7 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
331 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id]; 331 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
332 int i; 332 int i;
333 333
334 if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) { 334 if (pin_reg->conf_reg == -1) {
335 dev_err(info->dev, "Pin(%s) does not support config function\n", 335 dev_err(info->dev, "Pin(%s) does not support config function\n",
336 info->pins[pin_id].name); 336 info->pins[pin_id].name);
337 return -EINVAL; 337 return -EINVAL;
@@ -586,10 +586,11 @@ int imx_pinctrl_probe(struct platform_device *pdev,
586 if (!ipctl) 586 if (!ipctl)
587 return -ENOMEM; 587 return -ENOMEM;
588 588
589 info->pin_regs = devm_kzalloc(&pdev->dev, sizeof(*info->pin_regs) * 589 info->pin_regs = devm_kmalloc(&pdev->dev, sizeof(*info->pin_regs) *
590 info->npins, GFP_KERNEL); 590 info->npins, GFP_KERNEL);
591 if (!info->pin_regs) 591 if (!info->pin_regs)
592 return -ENOMEM; 592 return -ENOMEM;
593 memset(info->pin_regs, 0xff, sizeof(*info->pin_regs) * info->npins);
593 594
594 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 595 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
595 ipctl->base = devm_ioremap_resource(&pdev->dev, res); 596 ipctl->base = devm_ioremap_resource(&pdev->dev, res);
diff --git a/drivers/pinctrl/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h
index db408b057000..49e55d39f7c8 100644
--- a/drivers/pinctrl/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -67,8 +67,8 @@ struct imx_pmx_func {
67 * @conf_reg: config register offset 67 * @conf_reg: config register offset
68 */ 68 */
69struct imx_pin_reg { 69struct imx_pin_reg {
70 u16 mux_reg; 70 s16 mux_reg;
71 u16 conf_reg; 71 s16 conf_reg;
72}; 72};
73 73
74struct imx_pinctrl_soc_info { 74struct imx_pinctrl_soc_info {
@@ -83,8 +83,7 @@ struct imx_pinctrl_soc_info {
83 unsigned int flags; 83 unsigned int flags;
84}; 84};
85 85
86#define ZERO_OFFSET_VALID 0x1 86#define SHARE_MUX_CONF_REG 0x1
87#define SHARE_MUX_CONF_REG 0x2
88 87
89#define NO_MUX 0x0 88#define NO_MUX 0x0
90#define NO_PAD 0x0 89#define NO_PAD 0x0
diff --git a/drivers/pinctrl/pinctrl-imx1-core.c b/drivers/pinctrl/freescale/pinctrl-imx1-core.c
index 483420757c9f..5ac59fbb2440 100644
--- a/drivers/pinctrl/pinctrl-imx1-core.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx1-core.c
@@ -28,7 +28,7 @@
28#include <linux/pinctrl/pinmux.h> 28#include <linux/pinctrl/pinmux.h>
29#include <linux/slab.h> 29#include <linux/slab.h>
30 30
31#include "core.h" 31#include "../core.h"
32#include "pinctrl-imx1.h" 32#include "pinctrl-imx1.h"
33 33
34struct imx1_pinctrl { 34struct imx1_pinctrl {
@@ -298,8 +298,8 @@ static const struct pinctrl_ops imx1_pctrl_ops = {
298 298
299}; 299};
300 300
301static int imx1_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, 301static int imx1_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
302 unsigned group) 302 unsigned group)
303{ 303{
304 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); 304 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
305 const struct imx1_pinctrl_soc_info *info = ipctl->info; 305 const struct imx1_pinctrl_soc_info *info = ipctl->info;
@@ -385,7 +385,7 @@ static const struct pinmux_ops imx1_pmx_ops = {
385 .get_functions_count = imx1_pmx_get_funcs_count, 385 .get_functions_count = imx1_pmx_get_funcs_count,
386 .get_function_name = imx1_pmx_get_func_name, 386 .get_function_name = imx1_pmx_get_func_name,
387 .get_function_groups = imx1_pmx_get_groups, 387 .get_function_groups = imx1_pmx_get_groups,
388 .enable = imx1_pmx_enable, 388 .set_mux = imx1_pmx_set,
389}; 389};
390 390
391static int imx1_pinconf_get(struct pinctrl_dev *pctldev, 391static int imx1_pinconf_get(struct pinctrl_dev *pctldev,
diff --git a/drivers/pinctrl/pinctrl-imx1.c b/drivers/pinctrl/freescale/pinctrl-imx1.c
index 533a6e519648..533a6e519648 100644
--- a/drivers/pinctrl/pinctrl-imx1.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx1.c
diff --git a/drivers/pinctrl/pinctrl-imx1.h b/drivers/pinctrl/freescale/pinctrl-imx1.h
index 692a54c15cda..692a54c15cda 100644
--- a/drivers/pinctrl/pinctrl-imx1.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx1.h
diff --git a/drivers/pinctrl/freescale/pinctrl-imx21.c b/drivers/pinctrl/freescale/pinctrl-imx21.c
new file mode 100644
index 000000000000..1b3b2311b033
--- /dev/null
+++ b/drivers/pinctrl/freescale/pinctrl-imx21.c
@@ -0,0 +1,342 @@
1/*
2 * i.MX21 pinctrl driver based on imx pinmux core
3 *
4 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
15#include <linux/pinctrl/pinctrl.h>
16
17#include "pinctrl-imx1.h"
18
19#define PAD_ID(port, pin) ((port) * 32 + (pin))
20#define PA 0
21#define PB 1
22#define PC 2
23#define PD 3
24#define PE 4
25#define PF 5
26
27enum imx21_pads {
28 MX21_PAD_LSCLK = PAD_ID(PA, 5),
29 MX21_PAD_LD0 = PAD_ID(PA, 6),
30 MX21_PAD_LD1 = PAD_ID(PA, 7),
31 MX21_PAD_LD2 = PAD_ID(PA, 8),
32 MX21_PAD_LD3 = PAD_ID(PA, 9),
33 MX21_PAD_LD4 = PAD_ID(PA, 10),
34 MX21_PAD_LD5 = PAD_ID(PA, 11),
35 MX21_PAD_LD6 = PAD_ID(PA, 12),
36 MX21_PAD_LD7 = PAD_ID(PA, 13),
37 MX21_PAD_LD8 = PAD_ID(PA, 14),
38 MX21_PAD_LD9 = PAD_ID(PA, 15),
39 MX21_PAD_LD10 = PAD_ID(PA, 16),
40 MX21_PAD_LD11 = PAD_ID(PA, 17),
41 MX21_PAD_LD12 = PAD_ID(PA, 18),
42 MX21_PAD_LD13 = PAD_ID(PA, 19),
43 MX21_PAD_LD14 = PAD_ID(PA, 20),
44 MX21_PAD_LD15 = PAD_ID(PA, 21),
45 MX21_PAD_LD16 = PAD_ID(PA, 22),
46 MX21_PAD_LD17 = PAD_ID(PA, 23),
47 MX21_PAD_REV = PAD_ID(PA, 24),
48 MX21_PAD_CLS = PAD_ID(PA, 25),
49 MX21_PAD_PS = PAD_ID(PA, 26),
50 MX21_PAD_SPL_SPR = PAD_ID(PA, 27),
51 MX21_PAD_HSYNC = PAD_ID(PA, 28),
52 MX21_PAD_VSYNC = PAD_ID(PA, 29),
53 MX21_PAD_CONTRAST = PAD_ID(PA, 30),
54 MX21_PAD_OE_ACD = PAD_ID(PA, 31),
55 MX21_PAD_SD2_D0 = PAD_ID(PB, 4),
56 MX21_PAD_SD2_D1 = PAD_ID(PB, 5),
57 MX21_PAD_SD2_D2 = PAD_ID(PB, 6),
58 MX21_PAD_SD2_D3 = PAD_ID(PB, 7),
59 MX21_PAD_SD2_CMD = PAD_ID(PB, 8),
60 MX21_PAD_SD2_CLK = PAD_ID(PB, 9),
61 MX21_PAD_CSI_D0 = PAD_ID(PB, 10),
62 MX21_PAD_CSI_D1 = PAD_ID(PB, 11),
63 MX21_PAD_CSI_D2 = PAD_ID(PB, 12),
64 MX21_PAD_CSI_D3 = PAD_ID(PB, 13),
65 MX21_PAD_CSI_D4 = PAD_ID(PB, 14),
66 MX21_PAD_CSI_MCLK = PAD_ID(PB, 15),
67 MX21_PAD_CSI_PIXCLK = PAD_ID(PB, 16),
68 MX21_PAD_CSI_D5 = PAD_ID(PB, 17),
69 MX21_PAD_CSI_D6 = PAD_ID(PB, 18),
70 MX21_PAD_CSI_D7 = PAD_ID(PB, 19),
71 MX21_PAD_CSI_VSYNC = PAD_ID(PB, 20),
72 MX21_PAD_CSI_HSYNC = PAD_ID(PB, 21),
73 MX21_PAD_USB_BYP = PAD_ID(PB, 22),
74 MX21_PAD_USB_PWR = PAD_ID(PB, 23),
75 MX21_PAD_USB_OC = PAD_ID(PB, 24),
76 MX21_PAD_USBH_ON = PAD_ID(PB, 25),
77 MX21_PAD_USBH1_FS = PAD_ID(PB, 26),
78 MX21_PAD_USBH1_OE = PAD_ID(PB, 27),
79 MX21_PAD_USBH1_TXDM = PAD_ID(PB, 28),
80 MX21_PAD_USBH1_TXDP = PAD_ID(PB, 29),
81 MX21_PAD_USBH1_RXDM = PAD_ID(PB, 30),
82 MX21_PAD_USBH1_RXDP = PAD_ID(PB, 31),
83 MX21_PAD_USBG_SDA = PAD_ID(PC, 5),
84 MX21_PAD_USBG_SCL = PAD_ID(PC, 6),
85 MX21_PAD_USBG_ON = PAD_ID(PC, 7),
86 MX21_PAD_USBG_FS = PAD_ID(PC, 8),
87 MX21_PAD_USBG_OE = PAD_ID(PC, 9),
88 MX21_PAD_USBG_TXDM = PAD_ID(PC, 10),
89 MX21_PAD_USBG_TXDP = PAD_ID(PC, 11),
90 MX21_PAD_USBG_RXDM = PAD_ID(PC, 12),
91 MX21_PAD_USBG_RXDP = PAD_ID(PC, 13),
92 MX21_PAD_TOUT = PAD_ID(PC, 14),
93 MX21_PAD_TIN = PAD_ID(PC, 15),
94 MX21_PAD_SAP_FS = PAD_ID(PC, 16),
95 MX21_PAD_SAP_RXD = PAD_ID(PC, 17),
96 MX21_PAD_SAP_TXD = PAD_ID(PC, 18),
97 MX21_PAD_SAP_CLK = PAD_ID(PC, 19),
98 MX21_PAD_SSI1_FS = PAD_ID(PC, 20),
99 MX21_PAD_SSI1_RXD = PAD_ID(PC, 21),
100 MX21_PAD_SSI1_TXD = PAD_ID(PC, 22),
101 MX21_PAD_SSI1_CLK = PAD_ID(PC, 23),
102 MX21_PAD_SSI2_FS = PAD_ID(PC, 24),
103 MX21_PAD_SSI2_RXD = PAD_ID(PC, 25),
104 MX21_PAD_SSI2_TXD = PAD_ID(PC, 26),
105 MX21_PAD_SSI2_CLK = PAD_ID(PC, 27),
106 MX21_PAD_SSI3_FS = PAD_ID(PC, 28),
107 MX21_PAD_SSI3_RXD = PAD_ID(PC, 29),
108 MX21_PAD_SSI3_TXD = PAD_ID(PC, 30),
109 MX21_PAD_SSI3_CLK = PAD_ID(PC, 31),
110 MX21_PAD_I2C_DATA = PAD_ID(PD, 17),
111 MX21_PAD_I2C_CLK = PAD_ID(PD, 18),
112 MX21_PAD_CSPI2_SS2 = PAD_ID(PD, 19),
113 MX21_PAD_CSPI2_SS1 = PAD_ID(PD, 20),
114 MX21_PAD_CSPI2_SS0 = PAD_ID(PD, 21),
115 MX21_PAD_CSPI2_SCLK = PAD_ID(PD, 22),
116 MX21_PAD_CSPI2_MISO = PAD_ID(PD, 23),
117 MX21_PAD_CSPI2_MOSI = PAD_ID(PD, 24),
118 MX21_PAD_CSPI1_RDY = PAD_ID(PD, 25),
119 MX21_PAD_CSPI1_SS2 = PAD_ID(PD, 26),
120 MX21_PAD_CSPI1_SS1 = PAD_ID(PD, 27),
121 MX21_PAD_CSPI1_SS0 = PAD_ID(PD, 28),
122 MX21_PAD_CSPI1_SCLK = PAD_ID(PD, 29),
123 MX21_PAD_CSPI1_MISO = PAD_ID(PD, 30),
124 MX21_PAD_CSPI1_MOSI = PAD_ID(PD, 31),
125 MX21_PAD_TEST_WB2 = PAD_ID(PE, 0),
126 MX21_PAD_TEST_WB1 = PAD_ID(PE, 1),
127 MX21_PAD_TEST_WB0 = PAD_ID(PE, 2),
128 MX21_PAD_UART2_CTS = PAD_ID(PE, 3),
129 MX21_PAD_UART2_RTS = PAD_ID(PE, 4),
130 MX21_PAD_PWMO = PAD_ID(PE, 5),
131 MX21_PAD_UART2_TXD = PAD_ID(PE, 6),
132 MX21_PAD_UART2_RXD = PAD_ID(PE, 7),
133 MX21_PAD_UART3_TXD = PAD_ID(PE, 8),
134 MX21_PAD_UART3_RXD = PAD_ID(PE, 9),
135 MX21_PAD_UART3_CTS = PAD_ID(PE, 10),
136 MX21_PAD_UART3_RTS = PAD_ID(PE, 11),
137 MX21_PAD_UART1_TXD = PAD_ID(PE, 12),
138 MX21_PAD_UART1_RXD = PAD_ID(PE, 13),
139 MX21_PAD_UART1_CTS = PAD_ID(PE, 14),
140 MX21_PAD_UART1_RTS = PAD_ID(PE, 15),
141 MX21_PAD_RTCK = PAD_ID(PE, 16),
142 MX21_PAD_RESET_OUT = PAD_ID(PE, 17),
143 MX21_PAD_SD1_D0 = PAD_ID(PE, 18),
144 MX21_PAD_SD1_D1 = PAD_ID(PE, 19),
145 MX21_PAD_SD1_D2 = PAD_ID(PE, 20),
146 MX21_PAD_SD1_D3 = PAD_ID(PE, 21),
147 MX21_PAD_SD1_CMD = PAD_ID(PE, 22),
148 MX21_PAD_SD1_CLK = PAD_ID(PE, 23),
149 MX21_PAD_NFRB = PAD_ID(PF, 0),
150 MX21_PAD_NFCE = PAD_ID(PF, 1),
151 MX21_PAD_NFWP = PAD_ID(PF, 2),
152 MX21_PAD_NFCLE = PAD_ID(PF, 3),
153 MX21_PAD_NFALE = PAD_ID(PF, 4),
154 MX21_PAD_NFRE = PAD_ID(PF, 5),
155 MX21_PAD_NFWE = PAD_ID(PF, 6),
156 MX21_PAD_NFIO0 = PAD_ID(PF, 7),
157 MX21_PAD_NFIO1 = PAD_ID(PF, 8),
158 MX21_PAD_NFIO2 = PAD_ID(PF, 9),
159 MX21_PAD_NFIO3 = PAD_ID(PF, 10),
160 MX21_PAD_NFIO4 = PAD_ID(PF, 11),
161 MX21_PAD_NFIO5 = PAD_ID(PF, 12),
162 MX21_PAD_NFIO6 = PAD_ID(PF, 13),
163 MX21_PAD_NFIO7 = PAD_ID(PF, 14),
164 MX21_PAD_CLKO = PAD_ID(PF, 15),
165 MX21_PAD_RESERVED = PAD_ID(PF, 16),
166 MX21_PAD_CS4 = PAD_ID(PF, 21),
167 MX21_PAD_CS5 = PAD_ID(PF, 22),
168};
169
170/* Pad names for the pinmux subsystem */
171static const struct pinctrl_pin_desc imx21_pinctrl_pads[] = {
172 IMX_PINCTRL_PIN(MX21_PAD_LSCLK),
173 IMX_PINCTRL_PIN(MX21_PAD_LD0),
174 IMX_PINCTRL_PIN(MX21_PAD_LD1),
175 IMX_PINCTRL_PIN(MX21_PAD_LD2),
176 IMX_PINCTRL_PIN(MX21_PAD_LD3),
177 IMX_PINCTRL_PIN(MX21_PAD_LD4),
178 IMX_PINCTRL_PIN(MX21_PAD_LD5),
179 IMX_PINCTRL_PIN(MX21_PAD_LD6),
180 IMX_PINCTRL_PIN(MX21_PAD_LD7),
181 IMX_PINCTRL_PIN(MX21_PAD_LD8),
182 IMX_PINCTRL_PIN(MX21_PAD_LD9),
183 IMX_PINCTRL_PIN(MX21_PAD_LD10),
184 IMX_PINCTRL_PIN(MX21_PAD_LD11),
185 IMX_PINCTRL_PIN(MX21_PAD_LD12),
186 IMX_PINCTRL_PIN(MX21_PAD_LD13),
187 IMX_PINCTRL_PIN(MX21_PAD_LD14),
188 IMX_PINCTRL_PIN(MX21_PAD_LD15),
189 IMX_PINCTRL_PIN(MX21_PAD_LD16),
190 IMX_PINCTRL_PIN(MX21_PAD_LD17),
191 IMX_PINCTRL_PIN(MX21_PAD_REV),
192 IMX_PINCTRL_PIN(MX21_PAD_CLS),
193 IMX_PINCTRL_PIN(MX21_PAD_PS),
194 IMX_PINCTRL_PIN(MX21_PAD_SPL_SPR),
195 IMX_PINCTRL_PIN(MX21_PAD_HSYNC),
196 IMX_PINCTRL_PIN(MX21_PAD_VSYNC),
197 IMX_PINCTRL_PIN(MX21_PAD_CONTRAST),
198 IMX_PINCTRL_PIN(MX21_PAD_OE_ACD),
199 IMX_PINCTRL_PIN(MX21_PAD_SD2_D0),
200 IMX_PINCTRL_PIN(MX21_PAD_SD2_D1),
201 IMX_PINCTRL_PIN(MX21_PAD_SD2_D2),
202 IMX_PINCTRL_PIN(MX21_PAD_SD2_D3),
203 IMX_PINCTRL_PIN(MX21_PAD_SD2_CMD),
204 IMX_PINCTRL_PIN(MX21_PAD_SD2_CLK),
205 IMX_PINCTRL_PIN(MX21_PAD_CSI_D0),
206 IMX_PINCTRL_PIN(MX21_PAD_CSI_D1),
207 IMX_PINCTRL_PIN(MX21_PAD_CSI_D2),
208 IMX_PINCTRL_PIN(MX21_PAD_CSI_D3),
209 IMX_PINCTRL_PIN(MX21_PAD_CSI_D4),
210 IMX_PINCTRL_PIN(MX21_PAD_CSI_MCLK),
211 IMX_PINCTRL_PIN(MX21_PAD_CSI_PIXCLK),
212 IMX_PINCTRL_PIN(MX21_PAD_CSI_D5),
213 IMX_PINCTRL_PIN(MX21_PAD_CSI_D6),
214 IMX_PINCTRL_PIN(MX21_PAD_CSI_D7),
215 IMX_PINCTRL_PIN(MX21_PAD_CSI_VSYNC),
216 IMX_PINCTRL_PIN(MX21_PAD_CSI_HSYNC),
217 IMX_PINCTRL_PIN(MX21_PAD_USB_BYP),
218 IMX_PINCTRL_PIN(MX21_PAD_USB_PWR),
219 IMX_PINCTRL_PIN(MX21_PAD_USB_OC),
220 IMX_PINCTRL_PIN(MX21_PAD_USBH_ON),
221 IMX_PINCTRL_PIN(MX21_PAD_USBH1_FS),
222 IMX_PINCTRL_PIN(MX21_PAD_USBH1_OE),
223 IMX_PINCTRL_PIN(MX21_PAD_USBH1_TXDM),
224 IMX_PINCTRL_PIN(MX21_PAD_USBH1_TXDP),
225 IMX_PINCTRL_PIN(MX21_PAD_USBH1_RXDM),
226 IMX_PINCTRL_PIN(MX21_PAD_USBH1_RXDP),
227 IMX_PINCTRL_PIN(MX21_PAD_USBG_SDA),
228 IMX_PINCTRL_PIN(MX21_PAD_USBG_SCL),
229 IMX_PINCTRL_PIN(MX21_PAD_USBG_ON),
230 IMX_PINCTRL_PIN(MX21_PAD_USBG_FS),
231 IMX_PINCTRL_PIN(MX21_PAD_USBG_OE),
232 IMX_PINCTRL_PIN(MX21_PAD_USBG_TXDM),
233 IMX_PINCTRL_PIN(MX21_PAD_USBG_TXDP),
234 IMX_PINCTRL_PIN(MX21_PAD_USBG_RXDM),
235 IMX_PINCTRL_PIN(MX21_PAD_USBG_RXDP),
236 IMX_PINCTRL_PIN(MX21_PAD_TOUT),
237 IMX_PINCTRL_PIN(MX21_PAD_TIN),
238 IMX_PINCTRL_PIN(MX21_PAD_SAP_FS),
239 IMX_PINCTRL_PIN(MX21_PAD_SAP_RXD),
240 IMX_PINCTRL_PIN(MX21_PAD_SAP_TXD),
241 IMX_PINCTRL_PIN(MX21_PAD_SAP_CLK),
242 IMX_PINCTRL_PIN(MX21_PAD_SSI1_FS),
243 IMX_PINCTRL_PIN(MX21_PAD_SSI1_RXD),
244 IMX_PINCTRL_PIN(MX21_PAD_SSI1_TXD),
245 IMX_PINCTRL_PIN(MX21_PAD_SSI1_CLK),
246 IMX_PINCTRL_PIN(MX21_PAD_SSI2_FS),
247 IMX_PINCTRL_PIN(MX21_PAD_SSI2_RXD),
248 IMX_PINCTRL_PIN(MX21_PAD_SSI2_TXD),
249 IMX_PINCTRL_PIN(MX21_PAD_SSI2_CLK),
250 IMX_PINCTRL_PIN(MX21_PAD_SSI3_FS),
251 IMX_PINCTRL_PIN(MX21_PAD_SSI3_RXD),
252 IMX_PINCTRL_PIN(MX21_PAD_SSI3_TXD),
253 IMX_PINCTRL_PIN(MX21_PAD_SSI3_CLK),
254 IMX_PINCTRL_PIN(MX21_PAD_I2C_DATA),
255 IMX_PINCTRL_PIN(MX21_PAD_I2C_CLK),
256 IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS2),
257 IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS1),
258 IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS0),
259 IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SCLK),
260 IMX_PINCTRL_PIN(MX21_PAD_CSPI2_MISO),
261 IMX_PINCTRL_PIN(MX21_PAD_CSPI2_MOSI),
262 IMX_PINCTRL_PIN(MX21_PAD_CSPI1_RDY),
263 IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS2),
264 IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS1),
265 IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS0),
266 IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SCLK),
267 IMX_PINCTRL_PIN(MX21_PAD_CSPI1_MISO),
268 IMX_PINCTRL_PIN(MX21_PAD_CSPI1_MOSI),
269 IMX_PINCTRL_PIN(MX21_PAD_TEST_WB2),
270 IMX_PINCTRL_PIN(MX21_PAD_TEST_WB1),
271 IMX_PINCTRL_PIN(MX21_PAD_TEST_WB0),
272 IMX_PINCTRL_PIN(MX21_PAD_UART2_CTS),
273 IMX_PINCTRL_PIN(MX21_PAD_UART2_RTS),
274 IMX_PINCTRL_PIN(MX21_PAD_PWMO),
275 IMX_PINCTRL_PIN(MX21_PAD_UART2_TXD),
276 IMX_PINCTRL_PIN(MX21_PAD_UART2_RXD),
277 IMX_PINCTRL_PIN(MX21_PAD_UART3_TXD),
278 IMX_PINCTRL_PIN(MX21_PAD_UART3_RXD),
279 IMX_PINCTRL_PIN(MX21_PAD_UART3_CTS),
280 IMX_PINCTRL_PIN(MX21_PAD_UART3_RTS),
281 IMX_PINCTRL_PIN(MX21_PAD_UART1_TXD),
282 IMX_PINCTRL_PIN(MX21_PAD_UART1_RXD),
283 IMX_PINCTRL_PIN(MX21_PAD_UART1_CTS),
284 IMX_PINCTRL_PIN(MX21_PAD_UART1_RTS),
285 IMX_PINCTRL_PIN(MX21_PAD_RTCK),
286 IMX_PINCTRL_PIN(MX21_PAD_RESET_OUT),
287 IMX_PINCTRL_PIN(MX21_PAD_SD1_D0),
288 IMX_PINCTRL_PIN(MX21_PAD_SD1_D1),
289 IMX_PINCTRL_PIN(MX21_PAD_SD1_D2),
290 IMX_PINCTRL_PIN(MX21_PAD_SD1_D3),
291 IMX_PINCTRL_PIN(MX21_PAD_SD1_CMD),
292 IMX_PINCTRL_PIN(MX21_PAD_SD1_CLK),
293 IMX_PINCTRL_PIN(MX21_PAD_NFRB),
294 IMX_PINCTRL_PIN(MX21_PAD_NFCE),
295 IMX_PINCTRL_PIN(MX21_PAD_NFWP),
296 IMX_PINCTRL_PIN(MX21_PAD_NFCLE),
297 IMX_PINCTRL_PIN(MX21_PAD_NFALE),
298 IMX_PINCTRL_PIN(MX21_PAD_NFRE),
299 IMX_PINCTRL_PIN(MX21_PAD_NFWE),
300 IMX_PINCTRL_PIN(MX21_PAD_NFIO0),
301 IMX_PINCTRL_PIN(MX21_PAD_NFIO1),
302 IMX_PINCTRL_PIN(MX21_PAD_NFIO2),
303 IMX_PINCTRL_PIN(MX21_PAD_NFIO3),
304 IMX_PINCTRL_PIN(MX21_PAD_NFIO4),
305 IMX_PINCTRL_PIN(MX21_PAD_NFIO5),
306 IMX_PINCTRL_PIN(MX21_PAD_NFIO6),
307 IMX_PINCTRL_PIN(MX21_PAD_NFIO7),
308 IMX_PINCTRL_PIN(MX21_PAD_CLKO),
309 IMX_PINCTRL_PIN(MX21_PAD_RESERVED),
310 IMX_PINCTRL_PIN(MX21_PAD_CS4),
311 IMX_PINCTRL_PIN(MX21_PAD_CS5),
312};
313
314static struct imx1_pinctrl_soc_info imx21_pinctrl_info = {
315 .pins = imx21_pinctrl_pads,
316 .npins = ARRAY_SIZE(imx21_pinctrl_pads),
317};
318
319static int __init imx21_pinctrl_probe(struct platform_device *pdev)
320{
321 return imx1_pinctrl_core_probe(pdev, &imx21_pinctrl_info);
322}
323
324static const struct of_device_id imx21_pinctrl_of_match[] = {
325 { .compatible = "fsl,imx21-iomuxc", },
326 { }
327};
328MODULE_DEVICE_TABLE(of, imx21_pinctrl_of_match);
329
330static struct platform_driver imx21_pinctrl_driver = {
331 .driver = {
332 .name = "imx21-pinctrl",
333 .owner = THIS_MODULE,
334 .of_match_table = imx21_pinctrl_of_match,
335 },
336 .remove = imx1_pinctrl_core_remove,
337};
338module_platform_driver_probe(imx21_pinctrl_driver, imx21_pinctrl_probe);
339
340MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
341MODULE_DESCRIPTION("Freescale i.MX21 pinctrl driver");
342MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/pinctrl-imx23.c b/drivers/pinctrl/freescale/pinctrl-imx23.c
index e76d75c9d1ba..df79096becb0 100644
--- a/drivers/pinctrl/pinctrl-imx23.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx23.c
@@ -272,7 +272,7 @@ static int imx23_pinctrl_probe(struct platform_device *pdev)
272 return mxs_pinctrl_probe(pdev, &imx23_pinctrl_data); 272 return mxs_pinctrl_probe(pdev, &imx23_pinctrl_data);
273} 273}
274 274
275static struct of_device_id imx23_pinctrl_of_match[] = { 275static const struct of_device_id imx23_pinctrl_of_match[] = {
276 { .compatible = "fsl,imx23-pinctrl", }, 276 { .compatible = "fsl,imx23-pinctrl", },
277 { /* sentinel */ } 277 { /* sentinel */ }
278}; 278};
diff --git a/drivers/pinctrl/pinctrl-imx25.c b/drivers/pinctrl/freescale/pinctrl-imx25.c
index 1aae1b61c4dc..550e6d77ac2b 100644
--- a/drivers/pinctrl/pinctrl-imx25.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx25.c
@@ -315,7 +315,7 @@ static struct imx_pinctrl_soc_info imx25_pinctrl_info = {
315 .npins = ARRAY_SIZE(imx25_pinctrl_pads), 315 .npins = ARRAY_SIZE(imx25_pinctrl_pads),
316}; 316};
317 317
318static struct of_device_id imx25_pinctrl_of_match[] = { 318static const struct of_device_id imx25_pinctrl_of_match[] = {
319 { .compatible = "fsl,imx25-iomuxc", }, 319 { .compatible = "fsl,imx25-iomuxc", },
320 { /* sentinel */ } 320 { /* sentinel */ }
321}; 321};
diff --git a/drivers/pinctrl/pinctrl-imx27.c b/drivers/pinctrl/freescale/pinctrl-imx27.c
index f8dfefb69968..945eccadea74 100644
--- a/drivers/pinctrl/pinctrl-imx27.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx27.c
@@ -389,7 +389,7 @@ static struct imx1_pinctrl_soc_info imx27_pinctrl_info = {
389 .npins = ARRAY_SIZE(imx27_pinctrl_pads), 389 .npins = ARRAY_SIZE(imx27_pinctrl_pads),
390}; 390};
391 391
392static struct of_device_id imx27_pinctrl_of_match[] = { 392static const struct of_device_id imx27_pinctrl_of_match[] = {
393 { .compatible = "fsl,imx27-iomuxc", }, 393 { .compatible = "fsl,imx27-iomuxc", },
394 { /* sentinel */ } 394 { /* sentinel */ }
395}; 395};
diff --git a/drivers/pinctrl/pinctrl-imx28.c b/drivers/pinctrl/freescale/pinctrl-imx28.c
index 79c9c8d296af..3bd45da21229 100644
--- a/drivers/pinctrl/pinctrl-imx28.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx28.c
@@ -388,7 +388,7 @@ static int imx28_pinctrl_probe(struct platform_device *pdev)
388 return mxs_pinctrl_probe(pdev, &imx28_pinctrl_data); 388 return mxs_pinctrl_probe(pdev, &imx28_pinctrl_data);
389} 389}
390 390
391static struct of_device_id imx28_pinctrl_of_match[] = { 391static const struct of_device_id imx28_pinctrl_of_match[] = {
392 { .compatible = "fsl,imx28-pinctrl", }, 392 { .compatible = "fsl,imx28-pinctrl", },
393 { /* sentinel */ } 393 { /* sentinel */ }
394}; 394};
diff --git a/drivers/pinctrl/pinctrl-imx35.c b/drivers/pinctrl/freescale/pinctrl-imx35.c
index 278a04ae8940..6bfbcd0112c1 100644
--- a/drivers/pinctrl/pinctrl-imx35.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx35.c
@@ -1005,7 +1005,7 @@ static struct imx_pinctrl_soc_info imx35_pinctrl_info = {
1005 .npins = ARRAY_SIZE(imx35_pinctrl_pads), 1005 .npins = ARRAY_SIZE(imx35_pinctrl_pads),
1006}; 1006};
1007 1007
1008static struct of_device_id imx35_pinctrl_of_match[] = { 1008static const struct of_device_id imx35_pinctrl_of_match[] = {
1009 { .compatible = "fsl,imx35-iomuxc", }, 1009 { .compatible = "fsl,imx35-iomuxc", },
1010 { /* sentinel */ } 1010 { /* sentinel */ }
1011}; 1011};
diff --git a/drivers/pinctrl/pinctrl-imx50.c b/drivers/pinctrl/freescale/pinctrl-imx50.c
index b06feed1b038..e8bd604ab147 100644
--- a/drivers/pinctrl/pinctrl-imx50.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx50.c
@@ -391,7 +391,7 @@ static struct imx_pinctrl_soc_info imx50_pinctrl_info = {
391 .npins = ARRAY_SIZE(imx50_pinctrl_pads), 391 .npins = ARRAY_SIZE(imx50_pinctrl_pads),
392}; 392};
393 393
394static struct of_device_id imx50_pinctrl_of_match[] = { 394static const struct of_device_id imx50_pinctrl_of_match[] = {
395 { .compatible = "fsl,imx50-iomuxc", }, 395 { .compatible = "fsl,imx50-iomuxc", },
396 { /* sentinel */ } 396 { /* sentinel */ }
397}; 397};
diff --git a/drivers/pinctrl/pinctrl-imx51.c b/drivers/pinctrl/freescale/pinctrl-imx51.c
index 19ab182bef61..b818051db7c9 100644
--- a/drivers/pinctrl/pinctrl-imx51.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx51.c
@@ -768,7 +768,7 @@ static struct imx_pinctrl_soc_info imx51_pinctrl_info = {
768 .npins = ARRAY_SIZE(imx51_pinctrl_pads), 768 .npins = ARRAY_SIZE(imx51_pinctrl_pads),
769}; 769};
770 770
771static struct of_device_id imx51_pinctrl_of_match[] = { 771static const struct of_device_id imx51_pinctrl_of_match[] = {
772 { .compatible = "fsl,imx51-iomuxc", }, 772 { .compatible = "fsl,imx51-iomuxc", },
773 { /* sentinel */ } 773 { /* sentinel */ }
774}; 774};
diff --git a/drivers/pinctrl/pinctrl-imx53.c b/drivers/pinctrl/freescale/pinctrl-imx53.c
index f8d45c4cfde7..1884d53cf750 100644
--- a/drivers/pinctrl/pinctrl-imx53.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx53.c
@@ -454,7 +454,7 @@ static struct imx_pinctrl_soc_info imx53_pinctrl_info = {
454 .npins = ARRAY_SIZE(imx53_pinctrl_pads), 454 .npins = ARRAY_SIZE(imx53_pinctrl_pads),
455}; 455};
456 456
457static struct of_device_id imx53_pinctrl_of_match[] = { 457static const struct of_device_id imx53_pinctrl_of_match[] = {
458 { .compatible = "fsl,imx53-iomuxc", }, 458 { .compatible = "fsl,imx53-iomuxc", },
459 { /* sentinel */ } 459 { /* sentinel */ }
460}; 460};
diff --git a/drivers/pinctrl/pinctrl-imx6dl.c b/drivers/pinctrl/freescale/pinctrl-imx6dl.c
index db2a1489bd99..656c4b08cc2e 100644
--- a/drivers/pinctrl/pinctrl-imx6dl.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6dl.c
@@ -460,7 +460,7 @@ static struct imx_pinctrl_soc_info imx6dl_pinctrl_info = {
460 .npins = ARRAY_SIZE(imx6dl_pinctrl_pads), 460 .npins = ARRAY_SIZE(imx6dl_pinctrl_pads),
461}; 461};
462 462
463static struct of_device_id imx6dl_pinctrl_of_match[] = { 463static const struct of_device_id imx6dl_pinctrl_of_match[] = {
464 { .compatible = "fsl,imx6dl-iomuxc", }, 464 { .compatible = "fsl,imx6dl-iomuxc", },
465 { /* sentinel */ } 465 { /* sentinel */ }
466}; 466};
diff --git a/drivers/pinctrl/pinctrl-imx6q.c b/drivers/pinctrl/freescale/pinctrl-imx6q.c
index 8eb5ac1bd5f6..59bb5b4ec0f6 100644
--- a/drivers/pinctrl/pinctrl-imx6q.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6q.c
@@ -466,7 +466,7 @@ static struct imx_pinctrl_soc_info imx6q_pinctrl_info = {
466 .npins = ARRAY_SIZE(imx6q_pinctrl_pads), 466 .npins = ARRAY_SIZE(imx6q_pinctrl_pads),
467}; 467};
468 468
469static struct of_device_id imx6q_pinctrl_of_match[] = { 469static const struct of_device_id imx6q_pinctrl_of_match[] = {
470 { .compatible = "fsl,imx6q-iomuxc", }, 470 { .compatible = "fsl,imx6q-iomuxc", },
471 { /* sentinel */ } 471 { /* sentinel */ }
472}; 472};
diff --git a/drivers/pinctrl/pinctrl-imx6sl.c b/drivers/pinctrl/freescale/pinctrl-imx6sl.c
index f21b7389df3c..e0924bd7b98c 100644
--- a/drivers/pinctrl/pinctrl-imx6sl.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6sl.c
@@ -366,10 +366,11 @@ static struct imx_pinctrl_soc_info imx6sl_pinctrl_info = {
366 .npins = ARRAY_SIZE(imx6sl_pinctrl_pads), 366 .npins = ARRAY_SIZE(imx6sl_pinctrl_pads),
367}; 367};
368 368
369static struct of_device_id imx6sl_pinctrl_of_match[] = { 369static const struct of_device_id imx6sl_pinctrl_of_match[] = {
370 { .compatible = "fsl,imx6sl-iomuxc", }, 370 { .compatible = "fsl,imx6sl-iomuxc", },
371 { /* sentinel */ } 371 { /* sentinel */ }
372}; 372};
373MODULE_DEVICE_TABLE(of, imx6sl_pinctrl_of_match);
373 374
374static int imx6sl_pinctrl_probe(struct platform_device *pdev) 375static int imx6sl_pinctrl_probe(struct platform_device *pdev)
375{ 376{
diff --git a/drivers/pinctrl/pinctrl-imx6sx.c b/drivers/pinctrl/freescale/pinctrl-imx6sx.c
index 09758a56b9df..840344c8580d 100644
--- a/drivers/pinctrl/pinctrl-imx6sx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6sx.c
@@ -370,7 +370,7 @@ static struct imx_pinctrl_soc_info imx6sx_pinctrl_info = {
370 .npins = ARRAY_SIZE(imx6sx_pinctrl_pads), 370 .npins = ARRAY_SIZE(imx6sx_pinctrl_pads),
371}; 371};
372 372
373static struct of_device_id imx6sx_pinctrl_of_match[] = { 373static const struct of_device_id imx6sx_pinctrl_of_match[] = {
374 { .compatible = "fsl,imx6sx-iomuxc", }, 374 { .compatible = "fsl,imx6sx-iomuxc", },
375 { /* sentinel */ } 375 { /* sentinel */ }
376}; 376};
diff --git a/drivers/pinctrl/pinctrl-mxs.c b/drivers/pinctrl/freescale/pinctrl-mxs.c
index 40c76f26998c..f98c6bb0f769 100644
--- a/drivers/pinctrl/pinctrl-mxs.c
+++ b/drivers/pinctrl/freescale/pinctrl-mxs.c
@@ -21,7 +21,7 @@
21#include <linux/pinctrl/pinmux.h> 21#include <linux/pinctrl/pinmux.h>
22#include <linux/platform_device.h> 22#include <linux/platform_device.h>
23#include <linux/slab.h> 23#include <linux/slab.h>
24#include "core.h" 24#include "../core.h"
25#include "pinctrl-mxs.h" 25#include "pinctrl-mxs.h"
26 26
27#define SUFFIX_LEN 4 27#define SUFFIX_LEN 4
@@ -195,8 +195,8 @@ static int mxs_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
195 return 0; 195 return 0;
196} 196}
197 197
198static int mxs_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned selector, 198static int mxs_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
199 unsigned group) 199 unsigned group)
200{ 200{
201 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev); 201 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
202 struct mxs_group *g = &d->soc->groups[group]; 202 struct mxs_group *g = &d->soc->groups[group];
@@ -223,7 +223,7 @@ static const struct pinmux_ops mxs_pinmux_ops = {
223 .get_functions_count = mxs_pinctrl_get_funcs_count, 223 .get_functions_count = mxs_pinctrl_get_funcs_count,
224 .get_function_name = mxs_pinctrl_get_func_name, 224 .get_function_name = mxs_pinctrl_get_func_name,
225 .get_function_groups = mxs_pinctrl_get_func_groups, 225 .get_function_groups = mxs_pinctrl_get_func_groups,
226 .enable = mxs_pinctrl_enable, 226 .set_mux = mxs_pinctrl_set_mux,
227}; 227};
228 228
229static int mxs_pinconf_get(struct pinctrl_dev *pctldev, 229static int mxs_pinconf_get(struct pinctrl_dev *pctldev,
diff --git a/drivers/pinctrl/pinctrl-mxs.h b/drivers/pinctrl/freescale/pinctrl-mxs.h
index fdd88d0bae22..fdd88d0bae22 100644
--- a/drivers/pinctrl/pinctrl-mxs.h
+++ b/drivers/pinctrl/freescale/pinctrl-mxs.h
diff --git a/drivers/pinctrl/pinctrl-vf610.c b/drivers/pinctrl/freescale/pinctrl-vf610.c
index bddd913d28ba..b788e1578954 100644
--- a/drivers/pinctrl/pinctrl-vf610.c
+++ b/drivers/pinctrl/freescale/pinctrl-vf610.c
@@ -299,7 +299,7 @@ static const struct pinctrl_pin_desc vf610_pinctrl_pads[] = {
299static struct imx_pinctrl_soc_info vf610_pinctrl_info = { 299static struct imx_pinctrl_soc_info vf610_pinctrl_info = {
300 .pins = vf610_pinctrl_pads, 300 .pins = vf610_pinctrl_pads,
301 .npins = ARRAY_SIZE(vf610_pinctrl_pads), 301 .npins = ARRAY_SIZE(vf610_pinctrl_pads),
302 .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG, 302 .flags = SHARE_MUX_CONF_REG,
303}; 303};
304 304
305static struct of_device_id vf610_pinctrl_of_match[] = { 305static struct of_device_id vf610_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c
index 9908374f8f92..f3b426cdaf8f 100644
--- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c
+++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c
@@ -259,8 +259,8 @@ static int mvebu_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned fid,
259 return 0; 259 return 0;
260} 260}
261 261
262static int mvebu_pinmux_enable(struct pinctrl_dev *pctldev, unsigned fid, 262static int mvebu_pinmux_set(struct pinctrl_dev *pctldev, unsigned fid,
263 unsigned gid) 263 unsigned gid)
264{ 264{
265 struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 265 struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
266 struct mvebu_pinctrl_function *func = &pctl->functions[fid]; 266 struct mvebu_pinctrl_function *func = &pctl->functions[fid];
@@ -344,7 +344,7 @@ static const struct pinmux_ops mvebu_pinmux_ops = {
344 .get_function_groups = mvebu_pinmux_get_groups, 344 .get_function_groups = mvebu_pinmux_get_groups,
345 .gpio_request_enable = mvebu_pinmux_gpio_request_enable, 345 .gpio_request_enable = mvebu_pinmux_gpio_request_enable,
346 .gpio_set_direction = mvebu_pinmux_gpio_set_direction, 346 .gpio_set_direction = mvebu_pinmux_gpio_set_direction,
347 .enable = mvebu_pinmux_enable, 347 .set_mux = mvebu_pinmux_set,
348}; 348};
349 349
350static int mvebu_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 350static int mvebu_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
diff --git a/drivers/pinctrl/nomadik/pinctrl-abx500.c b/drivers/pinctrl/nomadik/pinctrl-abx500.c
index 8c6fd8d4dd3c..47f493149863 100644
--- a/drivers/pinctrl/nomadik/pinctrl-abx500.c
+++ b/drivers/pinctrl/nomadik/pinctrl-abx500.c
@@ -34,6 +34,7 @@
34#include "pinctrl-abx500.h" 34#include "pinctrl-abx500.h"
35#include "../core.h" 35#include "../core.h"
36#include "../pinconf.h" 36#include "../pinconf.h"
37#include "../pinctrl-utils.h"
37 38
38/* 39/*
39 * The AB9540 and AB8540 GPIO support are extended versions 40 * The AB9540 and AB8540 GPIO support are extended versions
@@ -708,8 +709,8 @@ static int abx500_pmx_get_func_groups(struct pinctrl_dev *pctldev,
708 return 0; 709 return 0;
709} 710}
710 711
711static int abx500_pmx_enable(struct pinctrl_dev *pctldev, unsigned function, 712static int abx500_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
712 unsigned group) 713 unsigned group)
713{ 714{
714 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); 715 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
715 struct gpio_chip *chip = &pct->chip; 716 struct gpio_chip *chip = &pct->chip;
@@ -783,7 +784,7 @@ static const struct pinmux_ops abx500_pinmux_ops = {
783 .get_functions_count = abx500_pmx_get_funcs_cnt, 784 .get_functions_count = abx500_pmx_get_funcs_cnt,
784 .get_function_name = abx500_pmx_get_func_name, 785 .get_function_name = abx500_pmx_get_func_name,
785 .get_function_groups = abx500_pmx_get_func_groups, 786 .get_function_groups = abx500_pmx_get_func_groups,
786 .enable = abx500_pmx_enable, 787 .set_mux = abx500_pmx_set,
787 .gpio_request_enable = abx500_gpio_request_enable, 788 .gpio_request_enable = abx500_gpio_request_enable,
788 .gpio_disable_free = abx500_gpio_disable_free, 789 .gpio_disable_free = abx500_gpio_disable_free,
789}; 790};
@@ -826,41 +827,6 @@ static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev,
826 chip->base + offset - 1); 827 chip->base + offset - 1);
827} 828}
828 829
829static void abx500_dt_free_map(struct pinctrl_dev *pctldev,
830 struct pinctrl_map *map, unsigned num_maps)
831{
832 int i;
833
834 for (i = 0; i < num_maps; i++)
835 if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
836 kfree(map[i].data.configs.configs);
837 kfree(map);
838}
839
840static int abx500_dt_reserve_map(struct pinctrl_map **map,
841 unsigned *reserved_maps,
842 unsigned *num_maps,
843 unsigned reserve)
844{
845 unsigned old_num = *reserved_maps;
846 unsigned new_num = *num_maps + reserve;
847 struct pinctrl_map *new_map;
848
849 if (old_num >= new_num)
850 return 0;
851
852 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
853 if (!new_map)
854 return -ENOMEM;
855
856 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
857
858 *map = new_map;
859 *reserved_maps = new_num;
860
861 return 0;
862}
863
864static int abx500_dt_add_map_mux(struct pinctrl_map **map, 830static int abx500_dt_add_map_mux(struct pinctrl_map **map,
865 unsigned *reserved_maps, 831 unsigned *reserved_maps,
866 unsigned *num_maps, const char *group, 832 unsigned *num_maps, const char *group,
@@ -926,19 +892,32 @@ static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev,
926 unsigned long *configs; 892 unsigned long *configs;
927 unsigned int nconfigs = 0; 893 unsigned int nconfigs = 0;
928 bool has_config = 0; 894 bool has_config = 0;
929 unsigned reserve = 0;
930 struct property *prop; 895 struct property *prop;
931 const char *group, *gpio_name; 896 const char *group, *gpio_name;
932 struct device_node *np_config; 897 struct device_node *np_config;
933 898
934 ret = of_property_read_string(np, "ste,function", &function); 899 ret = of_property_read_string(np, "ste,function", &function);
935 if (ret >= 0) 900 if (ret >= 0) {
936 reserve = 1; 901 ret = of_property_count_strings(np, "ste,pins");
902 if (ret < 0)
903 goto exit;
904
905 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
906 num_maps, ret);
907 if (ret < 0)
908 goto exit;
909
910 of_property_for_each_string(np, "ste,pins", prop, group) {
911 ret = abx500_dt_add_map_mux(map, reserved_maps,
912 num_maps, group, function);
913 if (ret < 0)
914 goto exit;
915 }
916 }
937 917
938 ret = pinconf_generic_parse_dt_config(np, &configs, &nconfigs); 918 ret = pinconf_generic_parse_dt_config(np, &configs, &nconfigs);
939 if (nconfigs) 919 if (nconfigs)
940 has_config = 1; 920 has_config = 1;
941
942 np_config = of_parse_phandle(np, "ste,config", 0); 921 np_config = of_parse_phandle(np, "ste,config", 0);
943 if (np_config) { 922 if (np_config) {
944 ret = pinconf_generic_parse_dt_config(np_config, &configs, 923 ret = pinconf_generic_parse_dt_config(np_config, &configs,
@@ -947,28 +926,18 @@ static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev,
947 goto exit; 926 goto exit;
948 has_config |= nconfigs; 927 has_config |= nconfigs;
949 } 928 }
929 if (has_config) {
930 ret = of_property_count_strings(np, "ste,pins");
931 if (ret < 0)
932 goto exit;
950 933
951 ret = of_property_count_strings(np, "ste,pins"); 934 ret = pinctrl_utils_reserve_map(pctldev, map,
952 if (ret < 0) 935 reserved_maps,
953 goto exit; 936 num_maps, ret);
954 937 if (ret < 0)
955 if (has_config) 938 goto exit;
956 reserve++;
957
958 reserve *= ret;
959
960 ret = abx500_dt_reserve_map(map, reserved_maps, num_maps, reserve);
961 if (ret < 0)
962 goto exit;
963 939
964 of_property_for_each_string(np, "ste,pins", prop, group) { 940 of_property_for_each_string(np, "ste,pins", prop, group) {
965 if (function) {
966 ret = abx500_dt_add_map_mux(map, reserved_maps,
967 num_maps, group, function);
968 if (ret < 0)
969 goto exit;
970 }
971 if (has_config) {
972 gpio_name = abx500_find_pin_name(pctldev, group); 941 gpio_name = abx500_find_pin_name(pctldev, group);
973 942
974 ret = abx500_dt_add_map_configs(map, reserved_maps, 943 ret = abx500_dt_add_map_configs(map, reserved_maps,
@@ -976,8 +945,8 @@ static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev,
976 if (ret < 0) 945 if (ret < 0)
977 goto exit; 946 goto exit;
978 } 947 }
979
980 } 948 }
949
981exit: 950exit:
982 return ret; 951 return ret;
983} 952}
@@ -998,7 +967,7 @@ static int abx500_dt_node_to_map(struct pinctrl_dev *pctldev,
998 ret = abx500_dt_subnode_to_map(pctldev, np, map, 967 ret = abx500_dt_subnode_to_map(pctldev, np, map,
999 &reserved_maps, num_maps); 968 &reserved_maps, num_maps);
1000 if (ret < 0) { 969 if (ret < 0) {
1001 abx500_dt_free_map(pctldev, *map, *num_maps); 970 pinctrl_utils_dt_free_map(pctldev, *map, *num_maps);
1002 return ret; 971 return ret;
1003 } 972 }
1004 } 973 }
@@ -1012,7 +981,7 @@ static const struct pinctrl_ops abx500_pinctrl_ops = {
1012 .get_group_pins = abx500_get_group_pins, 981 .get_group_pins = abx500_get_group_pins,
1013 .pin_dbg_show = abx500_pin_dbg_show, 982 .pin_dbg_show = abx500_pin_dbg_show,
1014 .dt_node_to_map = abx500_dt_node_to_map, 983 .dt_node_to_map = abx500_dt_node_to_map,
1015 .dt_free_map = abx500_dt_free_map, 984 .dt_free_map = pinctrl_utils_dt_free_map,
1016}; 985};
1017 986
1018static int abx500_pin_config_get(struct pinctrl_dev *pctldev, 987static int abx500_pin_config_get(struct pinctrl_dev *pctldev,
diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c
index e7cab07eef47..3c29d9187146 100644
--- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c
+++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c
@@ -32,6 +32,7 @@
32#include <linux/pinctrl/consumer.h> 32#include <linux/pinctrl/consumer.h>
33#include "pinctrl-nomadik.h" 33#include "pinctrl-nomadik.h"
34#include "../core.h" 34#include "../core.h"
35#include "../pinctrl-utils.h"
35 36
36/* 37/*
37 * The GPIO module in the Nomadik family of Systems-on-Chip is an 38 * The GPIO module in the Nomadik family of Systems-on-Chip is an
@@ -985,6 +986,7 @@ static void nmk_gpio_dbg_show_one(struct seq_file *s,
985 container_of(chip, struct nmk_gpio_chip, chip); 986 container_of(chip, struct nmk_gpio_chip, chip);
986 int mode; 987 int mode;
987 bool is_out; 988 bool is_out;
989 bool data_out;
988 bool pull; 990 bool pull;
989 u32 bit = 1 << offset; 991 u32 bit = 1 << offset;
990 const char *modes[] = { 992 const char *modes[] = {
@@ -997,28 +999,41 @@ static void nmk_gpio_dbg_show_one(struct seq_file *s,
997 [NMK_GPIO_ALT_C+3] = "altC3", 999 [NMK_GPIO_ALT_C+3] = "altC3",
998 [NMK_GPIO_ALT_C+4] = "altC4", 1000 [NMK_GPIO_ALT_C+4] = "altC4",
999 }; 1001 };
1002 const char *pulls[] = {
1003 "none ",
1004 "pull down",
1005 "pull up ",
1006 };
1000 1007
1001 clk_enable(nmk_chip->clk); 1008 clk_enable(nmk_chip->clk);
1002 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit); 1009 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit);
1003 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); 1010 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
1011 data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & bit);
1004 mode = nmk_gpio_get_mode(gpio); 1012 mode = nmk_gpio_get_mode(gpio);
1005 if ((mode == NMK_GPIO_ALT_C) && pctldev) 1013 if ((mode == NMK_GPIO_ALT_C) && pctldev)
1006 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio); 1014 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio);
1007 1015
1008 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s", 1016 if (is_out) {
1009 gpio, label ?: "(none)", 1017 seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s",
1010 is_out ? "out" : "in ", 1018 gpio,
1011 chip->get 1019 label ?: "(none)",
1012 ? (chip->get(chip, offset) ? "hi" : "lo") 1020 data_out ? "hi" : "lo",
1013 : "? ", 1021 (mode < 0) ? "unknown" : modes[mode]);
1014 (mode < 0) ? "unknown" : modes[mode], 1022 } else {
1015 pull ? "pull" : "none");
1016
1017 if (!is_out) {
1018 int irq = gpio_to_irq(gpio); 1023 int irq = gpio_to_irq(gpio);
1019 struct irq_desc *desc = irq_to_desc(irq); 1024 struct irq_desc *desc = irq_to_desc(irq);
1025 int pullidx = 0;
1020 1026
1021 /* This races with request_irq(), set_irq_type(), 1027 if (pull)
1028 pullidx = data_out ? 1 : 2;
1029
1030 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s",
1031 gpio,
1032 label ?: "(none)",
1033 pulls[pullidx],
1034 (mode < 0) ? "unknown" : modes[mode]);
1035 /*
1036 * This races with request_irq(), set_irq_type(),
1022 * and set_irq_wake() ... but those are "rare". 1037 * and set_irq_wake() ... but those are "rare".
1023 */ 1038 */
1024 if (irq > 0 && desc && desc->action) { 1039 if (irq > 0 && desc && desc->action) {
@@ -1338,39 +1353,6 @@ static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1338 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset); 1353 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
1339} 1354}
1340 1355
1341static void nmk_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
1342 struct pinctrl_map *map, unsigned num_maps)
1343{
1344 int i;
1345
1346 for (i = 0; i < num_maps; i++)
1347 if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
1348 kfree(map[i].data.configs.configs);
1349 kfree(map);
1350}
1351
1352static int nmk_dt_reserve_map(struct pinctrl_map **map, unsigned *reserved_maps,
1353 unsigned *num_maps, unsigned reserve)
1354{
1355 unsigned old_num = *reserved_maps;
1356 unsigned new_num = *num_maps + reserve;
1357 struct pinctrl_map *new_map;
1358
1359 if (old_num >= new_num)
1360 return 0;
1361
1362 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
1363 if (!new_map)
1364 return -ENOMEM;
1365
1366 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
1367
1368 *map = new_map;
1369 *reserved_maps = new_num;
1370
1371 return 0;
1372}
1373
1374static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, 1356static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
1375 unsigned *num_maps, const char *group, 1357 unsigned *num_maps, const char *group,
1376 const char *function) 1358 const char *function)
@@ -1537,51 +1519,55 @@ static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
1537 const char *function = NULL; 1519 const char *function = NULL;
1538 unsigned long configs = 0; 1520 unsigned long configs = 0;
1539 bool has_config = 0; 1521 bool has_config = 0;
1540 unsigned reserve = 0;
1541 struct property *prop; 1522 struct property *prop;
1542 const char *group, *gpio_name; 1523 const char *group, *gpio_name;
1543 struct device_node *np_config; 1524 struct device_node *np_config;
1544 1525
1545 ret = of_property_read_string(np, "ste,function", &function); 1526 ret = of_property_read_string(np, "ste,function", &function);
1546 if (ret >= 0) 1527 if (ret >= 0) {
1547 reserve = 1; 1528 ret = of_property_count_strings(np, "ste,pins");
1548 1529 if (ret < 0)
1549 has_config = nmk_pinctrl_dt_get_config(np, &configs); 1530 goto exit;
1550 1531
1551 np_config = of_parse_phandle(np, "ste,config", 0); 1532 ret = pinctrl_utils_reserve_map(pctldev, map,
1552 if (np_config) 1533 reserved_maps,
1553 has_config |= nmk_pinctrl_dt_get_config(np_config, &configs); 1534 num_maps, ret);
1554 1535 if (ret < 0)
1555 ret = of_property_count_strings(np, "ste,pins"); 1536 goto exit;
1556 if (ret < 0) 1537
1557 goto exit; 1538 of_property_for_each_string(np, "ste,pins", prop, group) {
1558
1559 if (has_config)
1560 reserve++;
1561
1562 reserve *= ret;
1563
1564 ret = nmk_dt_reserve_map(map, reserved_maps, num_maps, reserve);
1565 if (ret < 0)
1566 goto exit;
1567
1568 of_property_for_each_string(np, "ste,pins", prop, group) {
1569 if (function) {
1570 ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps, 1539 ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps,
1571 group, function); 1540 group, function);
1572 if (ret < 0) 1541 if (ret < 0)
1573 goto exit; 1542 goto exit;
1574 } 1543 }
1575 if (has_config) { 1544 }
1545
1546 has_config = nmk_pinctrl_dt_get_config(np, &configs);
1547 np_config = of_parse_phandle(np, "ste,config", 0);
1548 if (np_config)
1549 has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);
1550 if (has_config) {
1551 ret = of_property_count_strings(np, "ste,pins");
1552 if (ret < 0)
1553 goto exit;
1554 ret = pinctrl_utils_reserve_map(pctldev, map,
1555 reserved_maps,
1556 num_maps, ret);
1557 if (ret < 0)
1558 goto exit;
1559
1560 of_property_for_each_string(np, "ste,pins", prop, group) {
1576 gpio_name = nmk_find_pin_name(pctldev, group); 1561 gpio_name = nmk_find_pin_name(pctldev, group);
1577 1562
1578 ret = nmk_dt_add_map_configs(map, reserved_maps, num_maps, 1563 ret = nmk_dt_add_map_configs(map, reserved_maps,
1579 gpio_name, &configs, 1); 1564 num_maps,
1565 gpio_name, &configs, 1);
1580 if (ret < 0) 1566 if (ret < 0)
1581 goto exit; 1567 goto exit;
1582 } 1568 }
1583
1584 } 1569 }
1570
1585exit: 1571exit:
1586 return ret; 1572 return ret;
1587} 1573}
@@ -1602,7 +1588,7 @@ static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
1602 ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map, 1588 ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map,
1603 &reserved_maps, num_maps); 1589 &reserved_maps, num_maps);
1604 if (ret < 0) { 1590 if (ret < 0) {
1605 nmk_pinctrl_dt_free_map(pctldev, *map, *num_maps); 1591 pinctrl_utils_dt_free_map(pctldev, *map, *num_maps);
1606 return ret; 1592 return ret;
1607 } 1593 }
1608 } 1594 }
@@ -1616,7 +1602,7 @@ static const struct pinctrl_ops nmk_pinctrl_ops = {
1616 .get_group_pins = nmk_get_group_pins, 1602 .get_group_pins = nmk_get_group_pins,
1617 .pin_dbg_show = nmk_pin_dbg_show, 1603 .pin_dbg_show = nmk_pin_dbg_show,
1618 .dt_node_to_map = nmk_pinctrl_dt_node_to_map, 1604 .dt_node_to_map = nmk_pinctrl_dt_node_to_map,
1619 .dt_free_map = nmk_pinctrl_dt_free_map, 1605 .dt_free_map = pinctrl_utils_dt_free_map,
1620}; 1606};
1621 1607
1622static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 1608static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
@@ -1647,8 +1633,8 @@ static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1647 return 0; 1633 return 0;
1648} 1634}
1649 1635
1650static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function, 1636static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
1651 unsigned group) 1637 unsigned group)
1652{ 1638{
1653 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1639 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1654 const struct nmk_pingroup *g; 1640 const struct nmk_pingroup *g;
@@ -1810,7 +1796,7 @@ static const struct pinmux_ops nmk_pinmux_ops = {
1810 .get_functions_count = nmk_pmx_get_funcs_cnt, 1796 .get_functions_count = nmk_pmx_get_funcs_cnt,
1811 .get_function_name = nmk_pmx_get_func_name, 1797 .get_function_name = nmk_pmx_get_func_name,
1812 .get_function_groups = nmk_pmx_get_func_groups, 1798 .get_function_groups = nmk_pmx_get_func_groups,
1813 .enable = nmk_pmx_enable, 1799 .set_mux = nmk_pmx_set,
1814 .gpio_request_enable = nmk_gpio_request_enable, 1800 .gpio_request_enable = nmk_gpio_request_enable,
1815 .gpio_disable_free = nmk_gpio_disable_free, 1801 .gpio_disable_free = nmk_gpio_disable_free,
1816}; 1802};
diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c
index b092b93c67a1..8434439c5017 100644
--- a/drivers/pinctrl/pinctrl-adi2.c
+++ b/drivers/pinctrl/pinctrl-adi2.c
@@ -619,8 +619,8 @@ static struct pinctrl_ops adi_pctrl_ops = {
619 .get_group_pins = adi_get_group_pins, 619 .get_group_pins = adi_get_group_pins,
620}; 620};
621 621
622static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned func_id, 622static int adi_pinmux_set(struct pinctrl_dev *pctldev, unsigned func_id,
623 unsigned group_id) 623 unsigned group_id)
624{ 624{
625 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev); 625 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
626 struct gpio_port *port; 626 struct gpio_port *port;
@@ -698,7 +698,7 @@ static int adi_pinmux_request_gpio(struct pinctrl_dev *pctldev,
698} 698}
699 699
700static struct pinmux_ops adi_pinmux_ops = { 700static struct pinmux_ops adi_pinmux_ops = {
701 .enable = adi_pinmux_enable, 701 .set_mux = adi_pinmux_set,
702 .get_functions_count = adi_pinmux_get_funcs_count, 702 .get_functions_count = adi_pinmux_get_funcs_count,
703 .get_function_name = adi_pinmux_get_func_name, 703 .get_function_name = adi_pinmux_get_func_name,
704 .get_function_groups = adi_pinmux_get_groups, 704 .get_function_groups = adi_pinmux_get_groups,
@@ -1041,7 +1041,6 @@ static int adi_gpio_remove(struct platform_device *pdev)
1041 u8 offset; 1041 u8 offset;
1042 1042
1043 list_del(&port->node); 1043 list_del(&port->node);
1044 gpiochip_remove_pin_ranges(&port->chip);
1045 gpiochip_remove(&port->chip); 1044 gpiochip_remove(&port->chip);
1046 if (port->pint) { 1045 if (port->pint) {
1047 for (offset = 0; offset < port->width; offset++) 1046 for (offset = 0; offset < port->width; offset++)
diff --git a/drivers/pinctrl/pinctrl-as3722.c b/drivers/pinctrl/pinctrl-as3722.c
index 0e4ec91f4d49..1f790a4b83fe 100644
--- a/drivers/pinctrl/pinctrl-as3722.c
+++ b/drivers/pinctrl/pinctrl-as3722.c
@@ -230,7 +230,7 @@ static int as3722_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
230 return 0; 230 return 0;
231} 231}
232 232
233static int as3722_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function, 233static int as3722_pinctrl_set(struct pinctrl_dev *pctldev, unsigned function,
234 unsigned group) 234 unsigned group)
235{ 235{
236 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev); 236 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
@@ -327,7 +327,7 @@ static const struct pinmux_ops as3722_pinmux_ops = {
327 .get_functions_count = as3722_pinctrl_get_funcs_count, 327 .get_functions_count = as3722_pinctrl_get_funcs_count,
328 .get_function_name = as3722_pinctrl_get_func_name, 328 .get_function_name = as3722_pinctrl_get_func_name,
329 .get_function_groups = as3722_pinctrl_get_func_groups, 329 .get_function_groups = as3722_pinctrl_get_func_groups,
330 .enable = as3722_pinctrl_enable, 330 .set_mux = as3722_pinctrl_set,
331 .gpio_request_enable = as3722_pinctrl_gpio_request_enable, 331 .gpio_request_enable = as3722_pinctrl_gpio_request_enable,
332 .gpio_set_direction = as3722_pinctrl_gpio_set_direction, 332 .gpio_set_direction = as3722_pinctrl_gpio_set_direction,
333}; 333};
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 60464a2648aa..354a81d40925 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -58,11 +58,28 @@ static int gpio_banks;
58#define DEGLITCH (1 << 2) 58#define DEGLITCH (1 << 2)
59#define PULL_DOWN (1 << 3) 59#define PULL_DOWN (1 << 3)
60#define DIS_SCHMIT (1 << 4) 60#define DIS_SCHMIT (1 << 4)
61#define DRIVE_STRENGTH_SHIFT 5
62#define DRIVE_STRENGTH_MASK 0x3
63#define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
61#define DEBOUNCE (1 << 16) 64#define DEBOUNCE (1 << 16)
62#define DEBOUNCE_VAL_SHIFT 17 65#define DEBOUNCE_VAL_SHIFT 17
63#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT) 66#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
64 67
65/** 68/**
69 * These defines will translated the dt binding settings to our internal
70 * settings. They are not necessarily the same value as the register setting.
71 * The actual drive strength current of low, medium and high must be looked up
72 * from the corresponding device datasheet. This value is different for pins
73 * that are even in the same banks. It is also dependent on VCC.
74 * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
75 * strength when there is no dt config for it.
76 */
77#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
78#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
79#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
80#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
81
82/**
66 * struct at91_pmx_func - describes AT91 pinmux functions 83 * struct at91_pmx_func - describes AT91 pinmux functions
67 * @name: the name of this specific function 84 * @name: the name of this specific function
68 * @groups: corresponding pin groups 85 * @groups: corresponding pin groups
@@ -148,6 +165,9 @@ struct at91_pinctrl_mux_ops {
148 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on); 165 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
149 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin); 166 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
150 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask); 167 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
168 unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
169 void (*set_drivestrength)(void __iomem *pio, unsigned pin,
170 u32 strength);
151 /* irq */ 171 /* irq */
152 int (*irq_type)(struct irq_data *d, unsigned type); 172 int (*irq_type)(struct irq_data *d, unsigned type);
153}; 173};
@@ -315,6 +335,30 @@ static unsigned pin_to_mask(unsigned int pin)
315 return 1 << pin; 335 return 1 << pin;
316} 336}
317 337
338static unsigned two_bit_pin_value_shift_amount(unsigned int pin)
339{
340 /* return the shift value for a pin for "two bit" per pin registers,
341 * i.e. drive strength */
342 return 2*((pin >= MAX_NB_GPIO_PER_BANK/2)
343 ? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
344}
345
346static unsigned sama5d3_get_drive_register(unsigned int pin)
347{
348 /* drive strength is split between two registers
349 * with two bits per pin */
350 return (pin >= MAX_NB_GPIO_PER_BANK/2)
351 ? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1;
352}
353
354static unsigned at91sam9x5_get_drive_register(unsigned int pin)
355{
356 /* drive strength is split between two registers
357 * with two bits per pin */
358 return (pin >= MAX_NB_GPIO_PER_BANK/2)
359 ? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1;
360}
361
318static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask) 362static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
319{ 363{
320 writel_relaxed(mask, pio + PIO_IDR); 364 writel_relaxed(mask, pio + PIO_IDR);
@@ -327,6 +371,9 @@ static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
327 371
328static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) 372static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
329{ 373{
374 if (on)
375 writel_relaxed(mask, pio + PIO_PPDDR);
376
330 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR)); 377 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
331} 378}
332 379
@@ -455,6 +502,9 @@ static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
455 502
456static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on) 503static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
457{ 504{
505 if (is_on)
506 __raw_writel(mask, pio + PIO_PUDR);
507
458 __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); 508 __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
459} 509}
460 510
@@ -468,6 +518,79 @@ static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
468 return (__raw_readl(pio + PIO_SCHMITT) >> pin) & 0x1; 518 return (__raw_readl(pio + PIO_SCHMITT) >> pin) & 0x1;
469} 519}
470 520
521static inline u32 read_drive_strength(void __iomem *reg, unsigned pin)
522{
523 unsigned tmp = __raw_readl(reg);
524
525 tmp = tmp >> two_bit_pin_value_shift_amount(pin);
526
527 return tmp & DRIVE_STRENGTH_MASK;
528}
529
530static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
531 unsigned pin)
532{
533 unsigned tmp = read_drive_strength(pio +
534 sama5d3_get_drive_register(pin), pin);
535
536 /* SAMA5 strength is 1:1 with our defines,
537 * except 0 is equivalent to low per datasheet */
538 if (!tmp)
539 tmp = DRIVE_STRENGTH_LOW;
540
541 return tmp;
542}
543
544static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
545 unsigned pin)
546{
547 unsigned tmp = read_drive_strength(pio +
548 at91sam9x5_get_drive_register(pin), pin);
549
550 /* strength is inverse in SAM9x5s hardware with the pinctrl defines
551 * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
552 tmp = DRIVE_STRENGTH_HI - tmp;
553
554 return tmp;
555}
556
557static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
558{
559 unsigned tmp = __raw_readl(reg);
560 unsigned shift = two_bit_pin_value_shift_amount(pin);
561
562 tmp &= ~(DRIVE_STRENGTH_MASK << shift);
563 tmp |= strength << shift;
564
565 __raw_writel(tmp, reg);
566}
567
568static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin,
569 u32 setting)
570{
571 /* do nothing if setting is zero */
572 if (!setting)
573 return;
574
575 /* strength is 1 to 1 with setting for SAMA5 */
576 set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting);
577}
578
579static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
580 u32 setting)
581{
582 /* do nothing if setting is zero */
583 if (!setting)
584 return;
585
586 /* strength is inverse on SAM9x5s with our defines
587 * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
588 setting = DRIVE_STRENGTH_HI - setting;
589
590 set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
591 setting);
592}
593
471static struct at91_pinctrl_mux_ops at91rm9200_ops = { 594static struct at91_pinctrl_mux_ops at91rm9200_ops = {
472 .get_periph = at91_mux_get_periph, 595 .get_periph = at91_mux_get_periph,
473 .mux_A_periph = at91_mux_set_A_periph, 596 .mux_A_periph = at91_mux_set_A_periph,
@@ -491,6 +614,27 @@ static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
491 .set_pulldown = at91_mux_pio3_set_pulldown, 614 .set_pulldown = at91_mux_pio3_set_pulldown,
492 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig, 615 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
493 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig, 616 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
617 .get_drivestrength = at91_mux_sam9x5_get_drivestrength,
618 .set_drivestrength = at91_mux_sam9x5_set_drivestrength,
619 .irq_type = alt_gpio_irq_type,
620};
621
622static struct at91_pinctrl_mux_ops sama5d3_ops = {
623 .get_periph = at91_mux_pio3_get_periph,
624 .mux_A_periph = at91_mux_pio3_set_A_periph,
625 .mux_B_periph = at91_mux_pio3_set_B_periph,
626 .mux_C_periph = at91_mux_pio3_set_C_periph,
627 .mux_D_periph = at91_mux_pio3_set_D_periph,
628 .get_deglitch = at91_mux_pio3_get_deglitch,
629 .set_deglitch = at91_mux_pio3_set_deglitch,
630 .get_debounce = at91_mux_pio3_get_debounce,
631 .set_debounce = at91_mux_pio3_set_debounce,
632 .get_pulldown = at91_mux_pio3_get_pulldown,
633 .set_pulldown = at91_mux_pio3_set_pulldown,
634 .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
635 .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
636 .get_drivestrength = at91_mux_sama5d3_get_drivestrength,
637 .set_drivestrength = at91_mux_sama5d3_set_drivestrength,
494 .irq_type = alt_gpio_irq_type, 638 .irq_type = alt_gpio_irq_type,
495}; 639};
496 640
@@ -554,8 +698,8 @@ static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
554 writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER)); 698 writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
555} 699}
556 700
557static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, 701static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
558 unsigned group) 702 unsigned group)
559{ 703{
560 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 704 struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
561 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf; 705 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
@@ -684,7 +828,7 @@ static const struct pinmux_ops at91_pmx_ops = {
684 .get_functions_count = at91_pmx_get_funcs_count, 828 .get_functions_count = at91_pmx_get_funcs_count,
685 .get_function_name = at91_pmx_get_func_name, 829 .get_function_name = at91_pmx_get_func_name,
686 .get_function_groups = at91_pmx_get_groups, 830 .get_function_groups = at91_pmx_get_groups,
687 .enable = at91_pmx_enable, 831 .set_mux = at91_pmx_set,
688 .gpio_request_enable = at91_gpio_request_enable, 832 .gpio_request_enable = at91_gpio_request_enable,
689 .gpio_disable_free = at91_gpio_disable_free, 833 .gpio_disable_free = at91_gpio_disable_free,
690}; 834};
@@ -716,6 +860,9 @@ static int at91_pinconf_get(struct pinctrl_dev *pctldev,
716 *config |= PULL_DOWN; 860 *config |= PULL_DOWN;
717 if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin)) 861 if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
718 *config |= DIS_SCHMIT; 862 *config |= DIS_SCHMIT;
863 if (info->ops->get_drivestrength)
864 *config |= (info->ops->get_drivestrength(pio, pin)
865 << DRIVE_STRENGTH_SHIFT);
719 866
720 return 0; 867 return 0;
721} 868}
@@ -729,6 +876,7 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
729 void __iomem *pio; 876 void __iomem *pio;
730 int i; 877 int i;
731 unsigned long config; 878 unsigned long config;
879 unsigned pin;
732 880
733 for (i = 0; i < num_configs; i++) { 881 for (i = 0; i < num_configs; i++) {
734 config = configs[i]; 882 config = configs[i];
@@ -737,7 +885,8 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
737 "%s:%d, pin_id=%d, config=0x%lx", 885 "%s:%d, pin_id=%d, config=0x%lx",
738 __func__, __LINE__, pin_id, config); 886 __func__, __LINE__, pin_id, config);
739 pio = pin_to_controller(info, pin_to_bank(pin_id)); 887 pio = pin_to_controller(info, pin_to_bank(pin_id));
740 mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK); 888 pin = pin_id % MAX_NB_GPIO_PER_BANK;
889 mask = pin_to_mask(pin);
741 890
742 if (config & PULL_UP && config & PULL_DOWN) 891 if (config & PULL_UP && config & PULL_DOWN)
743 return -EINVAL; 892 return -EINVAL;
@@ -753,6 +902,10 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
753 info->ops->set_pulldown(pio, mask, config & PULL_DOWN); 902 info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
754 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT) 903 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
755 info->ops->disable_schmitt_trig(pio, mask); 904 info->ops->disable_schmitt_trig(pio, mask);
905 if (info->ops->set_drivestrength)
906 info->ops->set_drivestrength(pio, pin,
907 (config & DRIVE_STRENGTH)
908 >> DRIVE_STRENGTH_SHIFT);
756 909
757 } /* for each config */ 910 } /* for each config */
758 911
@@ -768,6 +921,15 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
768 } \ 921 } \
769} while (0) 922} while (0)
770 923
924#define DBG_SHOW_FLAG_MASKED(mask,flag) do { \
925 if ((config & mask) == flag) { \
926 if (num_conf) \
927 seq_puts(s, "|"); \
928 seq_puts(s, #flag); \
929 num_conf++; \
930 } \
931} while (0)
932
771static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev, 933static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
772 struct seq_file *s, unsigned pin_id) 934 struct seq_file *s, unsigned pin_id)
773{ 935{
@@ -781,6 +943,9 @@ static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
781 DBG_SHOW_FLAG(PULL_DOWN); 943 DBG_SHOW_FLAG(PULL_DOWN);
782 DBG_SHOW_FLAG(DIS_SCHMIT); 944 DBG_SHOW_FLAG(DIS_SCHMIT);
783 DBG_SHOW_FLAG(DEGLITCH); 945 DBG_SHOW_FLAG(DEGLITCH);
946 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW);
947 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED);
948 DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI);
784 DBG_SHOW_FLAG(DEBOUNCE); 949 DBG_SHOW_FLAG(DEBOUNCE);
785 if (config & DEBOUNCE) { 950 if (config & DEBOUNCE) {
786 val = config >> DEBOUNCE_VAL_SHIFT; 951 val = config >> DEBOUNCE_VAL_SHIFT;
@@ -945,6 +1110,7 @@ static int at91_pinctrl_parse_functions(struct device_node *np,
945} 1110}
946 1111
947static struct of_device_id at91_pinctrl_of_match[] = { 1112static struct of_device_id at91_pinctrl_of_match[] = {
1113 { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
948 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops }, 1114 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
949 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops }, 1115 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
950 { /* sentinel */ } 1116 { /* sentinel */ }
@@ -1445,7 +1611,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1445 /* now it may re-trigger */ 1611 /* now it may re-trigger */
1446} 1612}
1447 1613
1448static int at91_gpio_of_irq_setup(struct device_node *node, 1614static int at91_gpio_of_irq_setup(struct platform_device *pdev,
1449 struct at91_gpio_chip *at91_gpio) 1615 struct at91_gpio_chip *at91_gpio)
1450{ 1616{
1451 struct at91_gpio_chip *prev = NULL; 1617 struct at91_gpio_chip *prev = NULL;
@@ -1470,9 +1636,11 @@ static int at91_gpio_of_irq_setup(struct device_node *node,
1470 0, 1636 0,
1471 handle_edge_irq, 1637 handle_edge_irq,
1472 IRQ_TYPE_EDGE_BOTH); 1638 IRQ_TYPE_EDGE_BOTH);
1473 if (ret) 1639 if (ret) {
1474 panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n", 1640 dev_err(&pdev->dev, "at91_gpio.%d: Couldn't add irqchip to gpiochip.\n",
1475 at91_gpio->pioc_idx); 1641 at91_gpio->pioc_idx);
1642 return ret;
1643 }
1476 1644
1477 /* Setup chained handler */ 1645 /* Setup chained handler */
1478 if (at91_gpio->pioc_idx) 1646 if (at91_gpio->pioc_idx)
@@ -1575,19 +1743,22 @@ static int at91_gpio_probe(struct platform_device *pdev)
1575 at91_chip->pioc_virq = irq; 1743 at91_chip->pioc_virq = irq;
1576 at91_chip->pioc_idx = alias_idx; 1744 at91_chip->pioc_idx = alias_idx;
1577 1745
1578 at91_chip->clock = clk_get(&pdev->dev, NULL); 1746 at91_chip->clock = devm_clk_get(&pdev->dev, NULL);
1579 if (IS_ERR(at91_chip->clock)) { 1747 if (IS_ERR(at91_chip->clock)) {
1580 dev_err(&pdev->dev, "failed to get clock, ignoring.\n"); 1748 dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
1749 ret = PTR_ERR(at91_chip->clock);
1581 goto err; 1750 goto err;
1582 } 1751 }
1583 1752
1584 if (clk_prepare(at91_chip->clock)) 1753 ret = clk_prepare(at91_chip->clock);
1585 goto clk_prep_err; 1754 if (ret)
1755 goto clk_prepare_err;
1586 1756
1587 /* enable PIO controller's clock */ 1757 /* enable PIO controller's clock */
1588 if (clk_enable(at91_chip->clock)) { 1758 ret = clk_enable(at91_chip->clock);
1759 if (ret) {
1589 dev_err(&pdev->dev, "failed to enable clock, ignoring.\n"); 1760 dev_err(&pdev->dev, "failed to enable clock, ignoring.\n");
1590 goto clk_err; 1761 goto clk_enable_err;
1591 } 1762 }
1592 1763
1593 at91_chip->chip = at91_gpio_template; 1764 at91_chip->chip = at91_gpio_template;
@@ -1612,7 +1783,7 @@ static int at91_gpio_probe(struct platform_device *pdev)
1612 1783
1613 if (!names) { 1784 if (!names) {
1614 ret = -ENOMEM; 1785 ret = -ENOMEM;
1615 goto clk_err; 1786 goto clk_enable_err;
1616 } 1787 }
1617 1788
1618 for (i = 0; i < chip->ngpio; i++) 1789 for (i = 0; i < chip->ngpio; i++)
@@ -1630,23 +1801,28 @@ static int at91_gpio_probe(struct platform_device *pdev)
1630 1801
1631 ret = gpiochip_add(chip); 1802 ret = gpiochip_add(chip);
1632 if (ret) 1803 if (ret)
1633 goto clk_err; 1804 goto gpiochip_add_err;
1634 1805
1635 gpio_chips[alias_idx] = at91_chip; 1806 gpio_chips[alias_idx] = at91_chip;
1636 gpio_banks = max(gpio_banks, alias_idx + 1); 1807 gpio_banks = max(gpio_banks, alias_idx + 1);
1637 1808
1638 at91_gpio_probe_fixup(); 1809 at91_gpio_probe_fixup();
1639 1810
1640 at91_gpio_of_irq_setup(np, at91_chip); 1811 ret = at91_gpio_of_irq_setup(pdev, at91_chip);
1812 if (ret)
1813 goto irq_setup_err;
1641 1814
1642 dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase); 1815 dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
1643 1816
1644 return 0; 1817 return 0;
1645 1818
1646clk_err: 1819irq_setup_err:
1820 gpiochip_remove(chip);
1821gpiochip_add_err:
1822 clk_disable(at91_chip->clock);
1823clk_enable_err:
1647 clk_unprepare(at91_chip->clock); 1824 clk_unprepare(at91_chip->clock);
1648clk_prep_err: 1825clk_prepare_err:
1649 clk_put(at91_chip->clock);
1650err: 1826err:
1651 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx); 1827 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
1652 1828
diff --git a/drivers/pinctrl/pinctrl-bcm281xx.c b/drivers/pinctrl/pinctrl-bcm281xx.c
index c5ca9e633fff..a26e0c2ba33e 100644
--- a/drivers/pinctrl/pinctrl-bcm281xx.c
+++ b/drivers/pinctrl/pinctrl-bcm281xx.c
@@ -1055,9 +1055,9 @@ static int bcm281xx_pinctrl_get_fcn_groups(struct pinctrl_dev *pctldev,
1055 return 0; 1055 return 0;
1056} 1056}
1057 1057
1058static int bcm281xx_pinmux_enable(struct pinctrl_dev *pctldev, 1058static int bcm281xx_pinmux_set(struct pinctrl_dev *pctldev,
1059 unsigned function, 1059 unsigned function,
1060 unsigned group) 1060 unsigned group)
1061{ 1061{
1062 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev); 1062 struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1063 const struct bcm281xx_pin_function *f = &pdata->functions[function]; 1063 const struct bcm281xx_pin_function *f = &pdata->functions[function];
@@ -1084,7 +1084,7 @@ static struct pinmux_ops bcm281xx_pinctrl_pinmux_ops = {
1084 .get_functions_count = bcm281xx_pinctrl_get_fcns_count, 1084 .get_functions_count = bcm281xx_pinctrl_get_fcns_count,
1085 .get_function_name = bcm281xx_pinctrl_get_fcn_name, 1085 .get_function_name = bcm281xx_pinctrl_get_fcn_name,
1086 .get_function_groups = bcm281xx_pinctrl_get_fcn_groups, 1086 .get_function_groups = bcm281xx_pinctrl_get_fcn_groups,
1087 .enable = bcm281xx_pinmux_enable, 1087 .set_mux = bcm281xx_pinmux_set,
1088}; 1088};
1089 1089
1090static int bcm281xx_pinctrl_pin_config_get(struct pinctrl_dev *pctldev, 1090static int bcm281xx_pinctrl_pin_config_get(struct pinctrl_dev *pctldev,
diff --git a/drivers/pinctrl/pinctrl-bcm2835.c b/drivers/pinctrl/pinctrl-bcm2835.c
index 5bcfd7ace0cd..eabba02f71f9 100644
--- a/drivers/pinctrl/pinctrl-bcm2835.c
+++ b/drivers/pinctrl/pinctrl-bcm2835.c
@@ -830,7 +830,7 @@ static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
830 return 0; 830 return 0;
831} 831}
832 832
833static int bcm2835_pmx_enable(struct pinctrl_dev *pctldev, 833static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
834 unsigned func_selector, 834 unsigned func_selector,
835 unsigned group_selector) 835 unsigned group_selector)
836{ 836{
@@ -869,7 +869,7 @@ static const struct pinmux_ops bcm2835_pmx_ops = {
869 .get_functions_count = bcm2835_pmx_get_functions_count, 869 .get_functions_count = bcm2835_pmx_get_functions_count,
870 .get_function_name = bcm2835_pmx_get_function_name, 870 .get_function_name = bcm2835_pmx_get_function_name,
871 .get_function_groups = bcm2835_pmx_get_function_groups, 871 .get_function_groups = bcm2835_pmx_get_function_groups,
872 .enable = bcm2835_pmx_enable, 872 .set_mux = bcm2835_pmx_set,
873 .gpio_disable_free = bcm2835_pmx_gpio_disable_free, 873 .gpio_disable_free = bcm2835_pmx_gpio_disable_free,
874 .gpio_set_direction = bcm2835_pmx_gpio_set_direction, 874 .gpio_set_direction = bcm2835_pmx_gpio_set_direction,
875}; 875};
diff --git a/drivers/pinctrl/pinctrl-lantiq.c b/drivers/pinctrl/pinctrl-lantiq.c
index d22ca252b80d..296e5b37f768 100644
--- a/drivers/pinctrl/pinctrl-lantiq.c
+++ b/drivers/pinctrl/pinctrl-lantiq.c
@@ -257,9 +257,9 @@ static int match_group_mux(const struct ltq_pin_group *grp,
257 return ret; 257 return ret;
258} 258}
259 259
260static int ltq_pmx_enable(struct pinctrl_dev *pctrldev, 260static int ltq_pmx_set(struct pinctrl_dev *pctrldev,
261 unsigned func, 261 unsigned func,
262 unsigned group) 262 unsigned group)
263{ 263{
264 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); 264 struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
265 const struct ltq_pin_group *pin_grp = &info->grps[group]; 265 const struct ltq_pin_group *pin_grp = &info->grps[group];
@@ -316,7 +316,7 @@ static const struct pinmux_ops ltq_pmx_ops = {
316 .get_functions_count = ltq_pmx_func_count, 316 .get_functions_count = ltq_pmx_func_count,
317 .get_function_name = ltq_pmx_func_name, 317 .get_function_name = ltq_pmx_func_name,
318 .get_function_groups = ltq_pmx_get_groups, 318 .get_function_groups = ltq_pmx_get_groups,
319 .enable = ltq_pmx_enable, 319 .set_mux = ltq_pmx_set,
320 .gpio_request_enable = ltq_pmx_gpio_request_enable, 320 .gpio_request_enable = ltq_pmx_gpio_request_enable,
321}; 321};
322 322
diff --git a/drivers/pinctrl/pinctrl-palmas.c b/drivers/pinctrl/pinctrl-palmas.c
index f13d0e78a41c..e3079d3d19fe 100644
--- a/drivers/pinctrl/pinctrl-palmas.c
+++ b/drivers/pinctrl/pinctrl-palmas.c
@@ -685,7 +685,8 @@ static int palmas_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
685 return 0; 685 return 0;
686} 686}
687 687
688static int palmas_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function, 688static int palmas_pinctrl_set_mux(struct pinctrl_dev *pctldev,
689 unsigned function,
689 unsigned group) 690 unsigned group)
690{ 691{
691 struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev); 692 struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
@@ -742,7 +743,7 @@ static const struct pinmux_ops palmas_pinmux_ops = {
742 .get_functions_count = palmas_pinctrl_get_funcs_count, 743 .get_functions_count = palmas_pinctrl_get_funcs_count,
743 .get_function_name = palmas_pinctrl_get_func_name, 744 .get_function_name = palmas_pinctrl_get_func_name,
744 .get_function_groups = palmas_pinctrl_get_func_groups, 745 .get_function_groups = palmas_pinctrl_get_func_groups,
745 .enable = palmas_pinctrl_enable, 746 .set_mux = palmas_pinctrl_set_mux,
746}; 747};
747 748
748static int palmas_pinconf_get(struct pinctrl_dev *pctldev, 749static int palmas_pinconf_get(struct pinctrl_dev *pctldev,
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 0c372a300cb8..016f4578e494 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -816,8 +816,8 @@ static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
816 return 0; 816 return 0;
817} 817}
818 818
819static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, 819static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
820 unsigned group) 820 unsigned group)
821{ 821{
822 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 822 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
823 const unsigned int *pins = info->groups[group].pins; 823 const unsigned int *pins = info->groups[group].pins;
@@ -892,7 +892,7 @@ static const struct pinmux_ops rockchip_pmx_ops = {
892 .get_functions_count = rockchip_pmx_get_funcs_count, 892 .get_functions_count = rockchip_pmx_get_funcs_count,
893 .get_function_name = rockchip_pmx_get_func_name, 893 .get_function_name = rockchip_pmx_get_func_name,
894 .get_function_groups = rockchip_pmx_get_groups, 894 .get_function_groups = rockchip_pmx_get_groups,
895 .enable = rockchip_pmx_enable, 895 .set_mux = rockchip_pmx_set,
896 .gpio_set_direction = rockchip_pmx_gpio_set_direction, 896 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
897}; 897};
898 898
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 95dd9cf55cb3..fb94b772ad62 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -447,7 +447,7 @@ static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
447 return 0; 447 return 0;
448} 448}
449 449
450static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector, 450static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
451 unsigned group) 451 unsigned group)
452{ 452{
453 struct pcs_device *pcs; 453 struct pcs_device *pcs;
@@ -519,7 +519,7 @@ static const struct pinmux_ops pcs_pinmux_ops = {
519 .get_functions_count = pcs_get_functions_count, 519 .get_functions_count = pcs_get_functions_count,
520 .get_function_name = pcs_get_function_name, 520 .get_function_name = pcs_get_function_name,
521 .get_function_groups = pcs_get_function_groups, 521 .get_function_groups = pcs_get_function_groups,
522 .enable = pcs_enable, 522 .set_mux = pcs_set_mux,
523 .gpio_request_enable = pcs_request_gpio, 523 .gpio_request_enable = pcs_request_gpio,
524}; 524};
525 525
@@ -1981,6 +1981,18 @@ static const struct pcs_soc_data pinctrl_single_omap_wkup = {
1981 .irq_status_mask = (1 << 15), /* OMAP_WAKEUP_EVENT */ 1981 .irq_status_mask = (1 << 15), /* OMAP_WAKEUP_EVENT */
1982}; 1982};
1983 1983
1984static const struct pcs_soc_data pinctrl_single_dra7 = {
1985 .flags = PCS_QUIRK_SHARED_IRQ,
1986 .irq_enable_mask = (1 << 24), /* WAKEUPENABLE */
1987 .irq_status_mask = (1 << 25), /* WAKEUPEVENT */
1988};
1989
1990static const struct pcs_soc_data pinctrl_single_am437x = {
1991 .flags = PCS_QUIRK_SHARED_IRQ,
1992 .irq_enable_mask = (1 << 29), /* OMAP_WAKEUP_EN */
1993 .irq_status_mask = (1 << 30), /* OMAP_WAKEUP_EVENT */
1994};
1995
1984static const struct pcs_soc_data pinctrl_single = { 1996static const struct pcs_soc_data pinctrl_single = {
1985}; 1997};
1986 1998
@@ -1992,6 +2004,8 @@ static struct of_device_id pcs_of_match[] = {
1992 { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup }, 2004 { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1993 { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup }, 2005 { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
1994 { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup }, 2006 { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
2007 { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
2008 { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
1995 { .compatible = "pinctrl-single", .data = &pinctrl_single }, 2009 { .compatible = "pinctrl-single", .data = &pinctrl_single },
1996 { .compatible = "pinconf-single", .data = &pinconf_single }, 2010 { .compatible = "pinconf-single", .data = &pinconf_single },
1997 { }, 2011 { },
diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
index 5475374d803f..4b1792aad3d8 100644
--- a/drivers/pinctrl/pinctrl-st.c
+++ b/drivers/pinctrl/pinctrl-st.c
@@ -914,8 +914,8 @@ static struct st_pio_control *st_get_pio_control(
914 return &bank->pc; 914 return &bank->pc;
915} 915}
916 916
917static int st_pmx_enable(struct pinctrl_dev *pctldev, unsigned fselector, 917static int st_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
918 unsigned group) 918 unsigned group)
919{ 919{
920 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 920 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
921 struct st_pinconf *conf = info->groups[group].pin_conf; 921 struct st_pinconf *conf = info->groups[group].pin_conf;
@@ -951,7 +951,7 @@ static struct pinmux_ops st_pmxops = {
951 .get_functions_count = st_pmx_get_funcs_count, 951 .get_functions_count = st_pmx_get_funcs_count,
952 .get_function_name = st_pmx_get_fname, 952 .get_function_name = st_pmx_get_fname,
953 .get_function_groups = st_pmx_get_groups, 953 .get_function_groups = st_pmx_get_groups,
954 .enable = st_pmx_enable, 954 .set_mux = st_pmx_set_mux,
955 .gpio_set_direction = st_pmx_set_gpio_direction, 955 .gpio_set_direction = st_pmx_set_gpio_direction,
956}; 956};
957 957
@@ -1517,6 +1517,7 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info,
1517 0, handle_simple_irq, 1517 0, handle_simple_irq,
1518 IRQ_TYPE_LEVEL_LOW); 1518 IRQ_TYPE_LEVEL_LOW);
1519 if (err) { 1519 if (err) {
1520 gpiochip_remove(&bank->gpio_chip);
1520 dev_info(dev, "could not add irqchip\n"); 1521 dev_info(dev, "could not add irqchip\n");
1521 return err; 1522 return err;
1522 } 1523 }
diff --git a/drivers/pinctrl/pinctrl-tb10x.c b/drivers/pinctrl/pinctrl-tb10x.c
index 71c5d4f0c538..3b9bfcf717ac 100644
--- a/drivers/pinctrl/pinctrl-tb10x.c
+++ b/drivers/pinctrl/pinctrl-tb10x.c
@@ -697,7 +697,7 @@ static void tb10x_gpio_disable_free(struct pinctrl_dev *pctl,
697 mutex_unlock(&state->mutex); 697 mutex_unlock(&state->mutex);
698} 698}
699 699
700static int tb10x_pctl_enable(struct pinctrl_dev *pctl, 700static int tb10x_pctl_set_mux(struct pinctrl_dev *pctl,
701 unsigned func_selector, unsigned group_selector) 701 unsigned func_selector, unsigned group_selector)
702{ 702{
703 struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl); 703 struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
@@ -744,7 +744,7 @@ static struct pinmux_ops tb10x_pinmux_ops = {
744 .get_function_groups = tb10x_get_function_groups, 744 .get_function_groups = tb10x_get_function_groups,
745 .gpio_request_enable = tb10x_gpio_request_enable, 745 .gpio_request_enable = tb10x_gpio_request_enable,
746 .gpio_disable_free = tb10x_gpio_disable_free, 746 .gpio_disable_free = tb10x_gpio_disable_free,
747 .enable = tb10x_pctl_enable, 747 .set_mux = tb10x_pctl_set_mux,
748}; 748};
749 749
750static struct pinctrl_desc tb10x_pindesc = { 750static struct pinctrl_desc tb10x_pindesc = {
diff --git a/drivers/pinctrl/pinctrl-tegra-xusb.c b/drivers/pinctrl/pinctrl-tegra-xusb.c
index e641b4226c42..1631ec94fb02 100644
--- a/drivers/pinctrl/pinctrl-tegra-xusb.c
+++ b/drivers/pinctrl/pinctrl-tegra-xusb.c
@@ -281,9 +281,9 @@ static int tegra_xusb_padctl_get_function_groups(struct pinctrl_dev *pinctrl,
281 return 0; 281 return 0;
282} 282}
283 283
284static int tegra_xusb_padctl_pinmux_enable(struct pinctrl_dev *pinctrl, 284static int tegra_xusb_padctl_pinmux_set(struct pinctrl_dev *pinctrl,
285 unsigned int function, 285 unsigned int function,
286 unsigned int group) 286 unsigned int group)
287{ 287{
288 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl); 288 struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
289 const struct tegra_xusb_padctl_lane *lane; 289 const struct tegra_xusb_padctl_lane *lane;
@@ -311,7 +311,7 @@ static const struct pinmux_ops tegra_xusb_padctl_pinmux_ops = {
311 .get_functions_count = tegra_xusb_padctl_get_functions_count, 311 .get_functions_count = tegra_xusb_padctl_get_functions_count,
312 .get_function_name = tegra_xusb_padctl_get_function_name, 312 .get_function_name = tegra_xusb_padctl_get_function_name,
313 .get_function_groups = tegra_xusb_padctl_get_function_groups, 313 .get_function_groups = tegra_xusb_padctl_get_function_groups,
314 .enable = tegra_xusb_padctl_pinmux_enable, 314 .set_mux = tegra_xusb_padctl_pinmux_set,
315}; 315};
316 316
317static int tegra_xusb_padctl_pinconf_group_get(struct pinctrl_dev *pinctrl, 317static int tegra_xusb_padctl_pinconf_group_get(struct pinctrl_dev *pinctrl,
diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c
index 150af5503c09..e5949d51bc52 100644
--- a/drivers/pinctrl/pinctrl-tegra.c
+++ b/drivers/pinctrl/pinctrl-tegra.c
@@ -262,8 +262,9 @@ static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
262 return 0; 262 return 0;
263} 263}
264 264
265static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function, 265static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
266 unsigned group) 266 unsigned function,
267 unsigned group)
267{ 268{
268 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 269 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
269 const struct tegra_pingroup *g; 270 const struct tegra_pingroup *g;
@@ -294,7 +295,7 @@ static const struct pinmux_ops tegra_pinmux_ops = {
294 .get_functions_count = tegra_pinctrl_get_funcs_count, 295 .get_functions_count = tegra_pinctrl_get_funcs_count,
295 .get_function_name = tegra_pinctrl_get_func_name, 296 .get_function_name = tegra_pinctrl_get_func_name,
296 .get_function_groups = tegra_pinctrl_get_func_groups, 297 .get_function_groups = tegra_pinctrl_get_func_groups,
297 .enable = tegra_pinctrl_enable, 298 .set_mux = tegra_pinctrl_set_mux,
298}; 299};
299 300
300static int tegra_pinconf_reg(struct tegra_pmx *pmx, 301static int tegra_pinconf_reg(struct tegra_pmx *pmx,
diff --git a/drivers/pinctrl/pinctrl-tegra114.c b/drivers/pinctrl/pinctrl-tegra114.c
index 33614baab4c0..a3db85b0b75f 100644
--- a/drivers/pinctrl/pinctrl-tegra114.c
+++ b/drivers/pinctrl/pinctrl-tegra114.c
@@ -1850,7 +1850,7 @@ static int tegra114_pinctrl_probe(struct platform_device *pdev)
1850 return tegra_pinctrl_probe(pdev, &tegra114_pinctrl); 1850 return tegra_pinctrl_probe(pdev, &tegra114_pinctrl);
1851} 1851}
1852 1852
1853static struct of_device_id tegra114_pinctrl_of_match[] = { 1853static const struct of_device_id tegra114_pinctrl_of_match[] = {
1854 { .compatible = "nvidia,tegra114-pinmux", }, 1854 { .compatible = "nvidia,tegra114-pinmux", },
1855 { }, 1855 { },
1856}; 1856};
diff --git a/drivers/pinctrl/pinctrl-tegra124.c b/drivers/pinctrl/pinctrl-tegra124.c
index e80797e20017..2f9b75c14967 100644
--- a/drivers/pinctrl/pinctrl-tegra124.c
+++ b/drivers/pinctrl/pinctrl-tegra124.c
@@ -224,6 +224,16 @@
224#define TEGRA_PIN_OWR _PIN(5) 224#define TEGRA_PIN_OWR _PIN(5)
225#define TEGRA_PIN_CLK_32K_IN _PIN(6) 225#define TEGRA_PIN_CLK_32K_IN _PIN(6)
226#define TEGRA_PIN_JTAG_RTCK _PIN(7) 226#define TEGRA_PIN_JTAG_RTCK _PIN(7)
227#define TEGRA_PIN_DSI_B_CLK_P _PIN(8)
228#define TEGRA_PIN_DSI_B_CLK_N _PIN(9)
229#define TEGRA_PIN_DSI_B_D0_P _PIN(10)
230#define TEGRA_PIN_DSI_B_D0_N _PIN(11)
231#define TEGRA_PIN_DSI_B_D1_P _PIN(12)
232#define TEGRA_PIN_DSI_B_D1_N _PIN(13)
233#define TEGRA_PIN_DSI_B_D2_P _PIN(14)
234#define TEGRA_PIN_DSI_B_D2_N _PIN(15)
235#define TEGRA_PIN_DSI_B_D3_P _PIN(16)
236#define TEGRA_PIN_DSI_B_D3_N _PIN(17)
227 237
228static const struct pinctrl_pin_desc tegra124_pins[] = { 238static const struct pinctrl_pin_desc tegra124_pins[] = {
229 PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"), 239 PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
@@ -417,6 +427,16 @@ static const struct pinctrl_pin_desc tegra124_pins[] = {
417 PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"), 427 PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
418 PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"), 428 PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
419 PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"), 429 PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
430 PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_P, "DSI_B_CLK_P"),
431 PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_N, "DSI_B_CLK_N"),
432 PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_P, "DSI_B_D0_P"),
433 PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_N, "DSI_B_D0_N"),
434 PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_P, "DSI_B_D1_P"),
435 PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_N, "DSI_B_D1_N"),
436 PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_P, "DSI_B_D2_P"),
437 PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_N, "DSI_B_D2_N"),
438 PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_P, "DSI_B_D3_P"),
439 PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_N, "DSI_B_D3_N"),
420}; 440};
421 441
422static const unsigned clk_32k_out_pa0_pins[] = { 442static const unsigned clk_32k_out_pa0_pins[] = {
@@ -1495,6 +1515,19 @@ static const unsigned drive_ao4_pins[] = {
1495 TEGRA_PIN_JTAG_RTCK, 1515 TEGRA_PIN_JTAG_RTCK,
1496}; 1516};
1497 1517
1518static const unsigned mipi_pad_ctrl_dsi_b_pins[] = {
1519 TEGRA_PIN_DSI_B_CLK_P,
1520 TEGRA_PIN_DSI_B_CLK_N,
1521 TEGRA_PIN_DSI_B_D0_P,
1522 TEGRA_PIN_DSI_B_D0_N,
1523 TEGRA_PIN_DSI_B_D1_P,
1524 TEGRA_PIN_DSI_B_D1_N,
1525 TEGRA_PIN_DSI_B_D2_P,
1526 TEGRA_PIN_DSI_B_D2_N,
1527 TEGRA_PIN_DSI_B_D3_P,
1528 TEGRA_PIN_DSI_B_D3_N,
1529};
1530
1498enum tegra_mux { 1531enum tegra_mux {
1499 TEGRA_MUX_BLINK, 1532 TEGRA_MUX_BLINK,
1500 TEGRA_MUX_CCLA, 1533 TEGRA_MUX_CCLA,
@@ -1580,6 +1613,8 @@ enum tegra_mux {
1580 TEGRA_MUX_VI_ALT3, 1613 TEGRA_MUX_VI_ALT3,
1581 TEGRA_MUX_VIMCLK2, 1614 TEGRA_MUX_VIMCLK2,
1582 TEGRA_MUX_VIMCLK2_ALT, 1615 TEGRA_MUX_VIMCLK2_ALT,
1616 TEGRA_MUX_CSI,
1617 TEGRA_MUX_DSI_B,
1583}; 1618};
1584 1619
1585#define FUNCTION(fname) \ 1620#define FUNCTION(fname) \
@@ -1672,10 +1707,13 @@ static struct tegra_function tegra124_functions[] = {
1672 FUNCTION(vi_alt3), 1707 FUNCTION(vi_alt3),
1673 FUNCTION(vimclk2), 1708 FUNCTION(vimclk2),
1674 FUNCTION(vimclk2_alt), 1709 FUNCTION(vimclk2_alt),
1710 FUNCTION(csi),
1711 FUNCTION(dsi_b),
1675}; 1712};
1676 1713
1677#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */ 1714#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
1678#define PINGROUP_REG_A 0x3000 /* bank 1 */ 1715#define PINGROUP_REG_A 0x3000 /* bank 1 */
1716#define MIPI_PAD_CTRL_PINGROUP_REG_A 0x820 /* bank 2 */
1679 1717
1680#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A) 1718#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
1681 1719
@@ -1744,6 +1782,32 @@ static struct tegra_function tegra124_functions[] = {
1744 .drvtype_bit = PINGROUP_BIT_##drvtype(6), \ 1782 .drvtype_bit = PINGROUP_BIT_##drvtype(6), \
1745 } 1783 }
1746 1784
1785#define MIPI_PAD_CTRL_PINGROUP_REG_Y(r) ((r) - MIPI_PAD_CTRL_PINGROUP_REG_A)
1786
1787#define MIPI_PAD_CTRL_PINGROUP(pg_name, r, b, f0, f1) \
1788 { \
1789 .name = "mipi_pad_ctrl_" #pg_name, \
1790 .pins = mipi_pad_ctrl_##pg_name##_pins, \
1791 .npins = ARRAY_SIZE(mipi_pad_ctrl_##pg_name##_pins), \
1792 .funcs = { \
1793 TEGRA_MUX_ ## f0, \
1794 TEGRA_MUX_ ## f1, \
1795 TEGRA_MUX_RSVD3, \
1796 TEGRA_MUX_RSVD4, \
1797 }, \
1798 .mux_reg = MIPI_PAD_CTRL_PINGROUP_REG_Y(r), \
1799 .mux_bank = 2, \
1800 .mux_bit = b, \
1801 .pupd_reg = -1, \
1802 .tri_reg = -1, \
1803 .einput_bit = -1, \
1804 .odrain_bit = -1, \
1805 .lock_bit = -1, \
1806 .ioreset_bit = -1, \
1807 .rcv_sel_bit = -1, \
1808 .drv_reg = -1, \
1809 }
1810
1747static const struct tegra_pingroup tegra124_groups[] = { 1811static const struct tegra_pingroup tegra124_groups[] = {
1748 /* pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel */ 1812 /* pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel */
1749 PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, 0x3000, N, N, N), 1813 PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, 0x3000, N, N, N),
@@ -1979,6 +2043,9 @@ static const struct tegra_pingroup tegra124_groups[] = {
1979 DRV_PINGROUP(hv0, 0x9b4, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N), 2043 DRV_PINGROUP(hv0, 0x9b4, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N),
1980 DRV_PINGROUP(sdio4, 0x9c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 2044 DRV_PINGROUP(sdio4, 0x9c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
1981 DRV_PINGROUP(ao4, 0x9c8, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), 2045 DRV_PINGROUP(ao4, 0x9c8, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
2046
2047 /* pg_name, r b f0, f1 */
2048 MIPI_PAD_CTRL_PINGROUP(dsi_b, 0x820, 1, CSI, DSI_B)
1982}; 2049};
1983 2050
1984static const struct tegra_pinctrl_soc_data tegra124_pinctrl = { 2051static const struct tegra_pinctrl_soc_data tegra124_pinctrl = {
@@ -1996,7 +2063,7 @@ static int tegra124_pinctrl_probe(struct platform_device *pdev)
1996 return tegra_pinctrl_probe(pdev, &tegra124_pinctrl); 2063 return tegra_pinctrl_probe(pdev, &tegra124_pinctrl);
1997} 2064}
1998 2065
1999static struct of_device_id tegra124_pinctrl_of_match[] = { 2066static const struct of_device_id tegra124_pinctrl_of_match[] = {
2000 { .compatible = "nvidia,tegra124-pinmux", }, 2067 { .compatible = "nvidia,tegra124-pinmux", },
2001 { }, 2068 { },
2002}; 2069};
diff --git a/drivers/pinctrl/pinctrl-tegra20.c b/drivers/pinctrl/pinctrl-tegra20.c
index 7563ebc9c791..c9805d2e71b0 100644
--- a/drivers/pinctrl/pinctrl-tegra20.c
+++ b/drivers/pinctrl/pinctrl-tegra20.c
@@ -2228,7 +2228,7 @@ static int tegra20_pinctrl_probe(struct platform_device *pdev)
2228 return tegra_pinctrl_probe(pdev, &tegra20_pinctrl); 2228 return tegra_pinctrl_probe(pdev, &tegra20_pinctrl);
2229} 2229}
2230 2230
2231static struct of_device_id tegra20_pinctrl_of_match[] = { 2231static const struct of_device_id tegra20_pinctrl_of_match[] = {
2232 { .compatible = "nvidia,tegra20-pinmux", }, 2232 { .compatible = "nvidia,tegra20-pinmux", },
2233 { }, 2233 { },
2234}; 2234};
diff --git a/drivers/pinctrl/pinctrl-tegra30.c b/drivers/pinctrl/pinctrl-tegra30.c
index fe2d2cf78ad9..e7b72e916558 100644
--- a/drivers/pinctrl/pinctrl-tegra30.c
+++ b/drivers/pinctrl/pinctrl-tegra30.c
@@ -2484,7 +2484,7 @@ static int tegra30_pinctrl_probe(struct platform_device *pdev)
2484 return tegra_pinctrl_probe(pdev, &tegra30_pinctrl); 2484 return tegra_pinctrl_probe(pdev, &tegra30_pinctrl);
2485} 2485}
2486 2486
2487static struct of_device_id tegra30_pinctrl_of_match[] = { 2487static const struct of_device_id tegra30_pinctrl_of_match[] = {
2488 { .compatible = "nvidia,tegra30-pinmux", }, 2488 { .compatible = "nvidia,tegra30-pinmux", },
2489 { }, 2489 { },
2490}; 2490};
diff --git a/drivers/pinctrl/pinctrl-tz1090-pdc.c b/drivers/pinctrl/pinctrl-tz1090-pdc.c
index 41e81a35cabb..3bb6a3b78864 100644
--- a/drivers/pinctrl/pinctrl-tz1090-pdc.c
+++ b/drivers/pinctrl/pinctrl-tz1090-pdc.c
@@ -547,8 +547,9 @@ static void tz1090_pdc_pinctrl_mux(struct tz1090_pdc_pmx *pmx,
547 __global_unlock2(flags); 547 __global_unlock2(flags);
548} 548}
549 549
550static int tz1090_pdc_pinctrl_enable(struct pinctrl_dev *pctldev, 550static int tz1090_pdc_pinctrl_set_mux(struct pinctrl_dev *pctldev,
551 unsigned int function, unsigned int group) 551 unsigned int function,
552 unsigned int group)
552{ 553{
553 struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 554 struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
554 const struct tz1090_pdc_pingroup *grp = &tz1090_pdc_groups[group]; 555 const struct tz1090_pdc_pingroup *grp = &tz1090_pdc_groups[group];
@@ -634,7 +635,7 @@ static struct pinmux_ops tz1090_pdc_pinmux_ops = {
634 .get_functions_count = tz1090_pdc_pinctrl_get_funcs_count, 635 .get_functions_count = tz1090_pdc_pinctrl_get_funcs_count,
635 .get_function_name = tz1090_pdc_pinctrl_get_func_name, 636 .get_function_name = tz1090_pdc_pinctrl_get_func_name,
636 .get_function_groups = tz1090_pdc_pinctrl_get_func_groups, 637 .get_function_groups = tz1090_pdc_pinctrl_get_func_groups,
637 .enable = tz1090_pdc_pinctrl_enable, 638 .set_mux = tz1090_pdc_pinctrl_set_mux,
638 .gpio_request_enable = tz1090_pdc_pinctrl_gpio_request_enable, 639 .gpio_request_enable = tz1090_pdc_pinctrl_gpio_request_enable,
639 .gpio_disable_free = tz1090_pdc_pinctrl_gpio_disable_free, 640 .gpio_disable_free = tz1090_pdc_pinctrl_gpio_disable_free,
640}; 641};
diff --git a/drivers/pinctrl/pinctrl-tz1090.c b/drivers/pinctrl/pinctrl-tz1090.c
index 24082216842e..48d36413b99f 100644
--- a/drivers/pinctrl/pinctrl-tz1090.c
+++ b/drivers/pinctrl/pinctrl-tz1090.c
@@ -1415,8 +1415,8 @@ found_mux:
1415 * the effect is the same as enabling the function on each individual pin in the 1415 * the effect is the same as enabling the function on each individual pin in the
1416 * group. 1416 * group.
1417 */ 1417 */
1418static int tz1090_pinctrl_enable(struct pinctrl_dev *pctldev, 1418static int tz1090_pinctrl_set_mux(struct pinctrl_dev *pctldev,
1419 unsigned int function, unsigned int group) 1419 unsigned int function, unsigned int group)
1420{ 1420{
1421 struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 1421 struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
1422 struct tz1090_pingroup *grp; 1422 struct tz1090_pingroup *grp;
@@ -1517,7 +1517,7 @@ static struct pinmux_ops tz1090_pinmux_ops = {
1517 .get_functions_count = tz1090_pinctrl_get_funcs_count, 1517 .get_functions_count = tz1090_pinctrl_get_funcs_count,
1518 .get_function_name = tz1090_pinctrl_get_func_name, 1518 .get_function_name = tz1090_pinctrl_get_func_name,
1519 .get_function_groups = tz1090_pinctrl_get_func_groups, 1519 .get_function_groups = tz1090_pinctrl_get_func_groups,
1520 .enable = tz1090_pinctrl_enable, 1520 .set_mux = tz1090_pinctrl_set_mux,
1521 .gpio_request_enable = tz1090_pinctrl_gpio_request_enable, 1521 .gpio_request_enable = tz1090_pinctrl_gpio_request_enable,
1522 .gpio_disable_free = tz1090_pinctrl_gpio_disable_free, 1522 .gpio_disable_free = tz1090_pinctrl_gpio_disable_free,
1523}; 1523};
diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c
index 0959bb36450f..e9c7113d81f2 100644
--- a/drivers/pinctrl/pinctrl-u300.c
+++ b/drivers/pinctrl/pinctrl-u300.c
@@ -955,8 +955,8 @@ static void u300_pmx_endisable(struct u300_pmx *upmx, unsigned selector,
955 } 955 }
956} 956}
957 957
958static int u300_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, 958static int u300_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
959 unsigned group) 959 unsigned group)
960{ 960{
961 struct u300_pmx *upmx; 961 struct u300_pmx *upmx;
962 962
@@ -994,7 +994,7 @@ static const struct pinmux_ops u300_pmx_ops = {
994 .get_functions_count = u300_pmx_get_funcs_count, 994 .get_functions_count = u300_pmx_get_funcs_count,
995 .get_function_name = u300_pmx_get_func_name, 995 .get_function_name = u300_pmx_get_func_name,
996 .get_function_groups = u300_pmx_get_groups, 996 .get_function_groups = u300_pmx_get_groups,
997 .enable = u300_pmx_enable, 997 .set_mux = u300_pmx_set_mux,
998}; 998};
999 999
1000static int u300_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin, 1000static int u300_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c
index e66f4cae7633..37040ab42890 100644
--- a/drivers/pinctrl/pinctrl-xway.c
+++ b/drivers/pinctrl/pinctrl-xway.c
@@ -801,6 +801,7 @@ static int pinmux_xway_probe(struct platform_device *pdev)
801 of_gpiochip_add(&xway_chip); 801 of_gpiochip_add(&xway_chip);
802 ret = gpiochip_add(&xway_chip); 802 ret = gpiochip_add(&xway_chip);
803 if (ret) { 803 if (ret) {
804 of_gpiochip_remove(&xway_chip);
804 dev_err(&pdev->dev, "Failed to register gpio chip\n"); 805 dev_err(&pdev->dev, "Failed to register gpio chip\n");
805 return ret; 806 return ret;
806 } 807 }
@@ -822,6 +823,7 @@ static int pinmux_xway_probe(struct platform_device *pdev)
822 /* register with the generic lantiq layer */ 823 /* register with the generic lantiq layer */
823 ret = ltq_pinctrl_register(pdev, &xway_info); 824 ret = ltq_pinctrl_register(pdev, &xway_info);
824 if (ret) { 825 if (ret) {
826 gpiochip_remove(&xway_chip);
825 dev_err(&pdev->dev, "Failed to register pinctrl driver\n"); 827 dev_err(&pdev->dev, "Failed to register pinctrl driver\n");
826 return ret; 828 return ret;
827 } 829 }
diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c
index c055daf9a80f..b874458dcb88 100644
--- a/drivers/pinctrl/pinmux.c
+++ b/drivers/pinctrl/pinmux.c
@@ -41,7 +41,7 @@ int pinmux_check_ops(struct pinctrl_dev *pctldev)
41 !ops->get_functions_count || 41 !ops->get_functions_count ||
42 !ops->get_function_name || 42 !ops->get_function_name ||
43 !ops->get_function_groups || 43 !ops->get_function_groups ||
44 !ops->enable) { 44 !ops->set_mux) {
45 dev_err(pctldev->dev, "pinmux ops lacks necessary functions\n"); 45 dev_err(pctldev->dev, "pinmux ops lacks necessary functions\n");
46 return -EINVAL; 46 return -EINVAL;
47 } 47 }
@@ -445,15 +445,15 @@ int pinmux_enable_setting(struct pinctrl_setting const *setting)
445 desc->mux_setting = &(setting->data.mux); 445 desc->mux_setting = &(setting->data.mux);
446 } 446 }
447 447
448 ret = ops->enable(pctldev, setting->data.mux.func, 448 ret = ops->set_mux(pctldev, setting->data.mux.func,
449 setting->data.mux.group); 449 setting->data.mux.group);
450 450
451 if (ret) 451 if (ret)
452 goto err_enable; 452 goto err_set_mux;
453 453
454 return 0; 454 return 0;
455 455
456err_enable: 456err_set_mux:
457 for (i = 0; i < num_pins; i++) { 457 for (i = 0; i < num_pins; i++) {
458 desc = pin_desc_get(pctldev, pins[i]); 458 desc = pin_desc_get(pctldev, pins[i]);
459 if (desc) 459 if (desc)
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index d160a710d704..81275af9638b 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -15,6 +15,14 @@ config PINCTRL_APQ8064
15 This is the pinctrl, pinmux, pinconf and gpiolib driver for the 15 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
16 Qualcomm TLMM block found in the Qualcomm APQ8064 platform. 16 Qualcomm TLMM block found in the Qualcomm APQ8064 platform.
17 17
18config PINCTRL_APQ8084
19 tristate "Qualcomm APQ8084 pin controller driver"
20 depends on GPIOLIB && OF
21 select PINCTRL_MSM
22 help
23 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
24 Qualcomm TLMM block found in the Qualcomm APQ8084 platform.
25
18config PINCTRL_IPQ8064 26config PINCTRL_IPQ8064
19 tristate "Qualcomm IPQ8064 pin controller driver" 27 tristate "Qualcomm IPQ8064 pin controller driver"
20 depends on GPIOLIB && OF 28 depends on GPIOLIB && OF
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 2a02602d715c..ba8519fcd8d3 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -1,6 +1,7 @@
1# Qualcomm pin control drivers 1# Qualcomm pin control drivers
2obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o 2obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o
3obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o 3obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
4obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
4obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o 5obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
5obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o 6obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o
6obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o 7obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8064.c b/drivers/pinctrl/qcom/pinctrl-apq8064.c
index feb6f152f9b7..c832d7d6b912 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8064.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8064.c
@@ -258,6 +258,7 @@ static const unsigned int sdc3_data_pins[] = { 95 };
258 .intr_status_bit = 0, \ 258 .intr_status_bit = 0, \
259 .intr_ack_high = 1, \ 259 .intr_ack_high = 1, \
260 .intr_target_bit = 0, \ 260 .intr_target_bit = 0, \
261 .intr_target_kpss_val = 4, \
261 .intr_raw_status_bit = 3, \ 262 .intr_raw_status_bit = 3, \
262 .intr_polarity_bit = 1, \ 263 .intr_polarity_bit = 1, \
263 .intr_detection_bit = 2, \ 264 .intr_detection_bit = 2, \
@@ -283,6 +284,7 @@ static const unsigned int sdc3_data_pins[] = { 95 };
283 .intr_enable_bit = -1, \ 284 .intr_enable_bit = -1, \
284 .intr_status_bit = -1, \ 285 .intr_status_bit = -1, \
285 .intr_target_bit = -1, \ 286 .intr_target_bit = -1, \
287 .intr_target_kpss_val = -1, \
286 .intr_raw_status_bit = -1, \ 288 .intr_raw_status_bit = -1, \
287 .intr_polarity_bit = -1, \ 289 .intr_polarity_bit = -1, \
288 .intr_detection_bit = -1, \ 290 .intr_detection_bit = -1, \
@@ -324,6 +326,7 @@ enum apq8064_functions {
324 APQ_MUX_tsif1, 326 APQ_MUX_tsif1,
325 APQ_MUX_tsif2, 327 APQ_MUX_tsif2,
326 APQ_MUX_usb2_hsic, 328 APQ_MUX_usb2_hsic,
329 APQ_MUX_ps_hold,
327 APQ_MUX_NA, 330 APQ_MUX_NA,
328}; 331};
329 332
@@ -351,6 +354,9 @@ static const char * const gpio_groups[] = {
351 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", 354 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
352 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89" 355 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89"
353}; 356};
357static const char * const ps_hold_groups[] = {
358 "gpio78"
359};
354static const char * const gsbi1_groups[] = { 360static const char * const gsbi1_groups[] = {
355 "gpio18", "gpio19", "gpio20", "gpio21" 361 "gpio18", "gpio19", "gpio20", "gpio21"
356}; 362};
@@ -477,6 +483,7 @@ static const struct msm_function apq8064_functions[] = {
477 FUNCTION(tsif1), 483 FUNCTION(tsif1),
478 FUNCTION(tsif2), 484 FUNCTION(tsif2),
479 FUNCTION(usb2_hsic), 485 FUNCTION(usb2_hsic),
486 FUNCTION(ps_hold),
480}; 487};
481 488
482static const struct msm_pingroup apq8064_groups[] = { 489static const struct msm_pingroup apq8064_groups[] = {
@@ -558,7 +565,7 @@ static const struct msm_pingroup apq8064_groups[] = {
558 PINGROUP(75, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 565 PINGROUP(75, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
559 PINGROUP(76, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 566 PINGROUP(76, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
560 PINGROUP(77, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 567 PINGROUP(77, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
561 PINGROUP(78, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 568 PINGROUP(78, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA),
562 PINGROUP(79, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 569 PINGROUP(79, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
563 PINGROUP(80, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 570 PINGROUP(80, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
564 PINGROUP(81, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA), 571 PINGROUP(81, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8084.c b/drivers/pinctrl/qcom/pinctrl-apq8084.c
new file mode 100644
index 000000000000..138cbf6134a5
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-apq8084.c
@@ -0,0 +1,1245 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/platform_device.h>
18#include <linux/pinctrl/pinctrl.h>
19
20#include "pinctrl-msm.h"
21
22static const struct pinctrl_pin_desc apq8084_pins[] = {
23 PINCTRL_PIN(0, "GPIO_0"),
24 PINCTRL_PIN(1, "GPIO_1"),
25 PINCTRL_PIN(2, "GPIO_2"),
26 PINCTRL_PIN(3, "GPIO_3"),
27 PINCTRL_PIN(4, "GPIO_4"),
28 PINCTRL_PIN(5, "GPIO_5"),
29 PINCTRL_PIN(6, "GPIO_6"),
30 PINCTRL_PIN(7, "GPIO_7"),
31 PINCTRL_PIN(8, "GPIO_8"),
32 PINCTRL_PIN(9, "GPIO_9"),
33 PINCTRL_PIN(10, "GPIO_10"),
34 PINCTRL_PIN(11, "GPIO_11"),
35 PINCTRL_PIN(12, "GPIO_12"),
36 PINCTRL_PIN(13, "GPIO_13"),
37 PINCTRL_PIN(14, "GPIO_14"),
38 PINCTRL_PIN(15, "GPIO_15"),
39 PINCTRL_PIN(16, "GPIO_16"),
40 PINCTRL_PIN(17, "GPIO_17"),
41 PINCTRL_PIN(18, "GPIO_18"),
42 PINCTRL_PIN(19, "GPIO_19"),
43 PINCTRL_PIN(20, "GPIO_20"),
44 PINCTRL_PIN(21, "GPIO_21"),
45 PINCTRL_PIN(22, "GPIO_22"),
46 PINCTRL_PIN(23, "GPIO_23"),
47 PINCTRL_PIN(24, "GPIO_24"),
48 PINCTRL_PIN(25, "GPIO_25"),
49 PINCTRL_PIN(26, "GPIO_26"),
50 PINCTRL_PIN(27, "GPIO_27"),
51 PINCTRL_PIN(28, "GPIO_28"),
52 PINCTRL_PIN(29, "GPIO_29"),
53 PINCTRL_PIN(30, "GPIO_30"),
54 PINCTRL_PIN(31, "GPIO_31"),
55 PINCTRL_PIN(32, "GPIO_32"),
56 PINCTRL_PIN(33, "GPIO_33"),
57 PINCTRL_PIN(34, "GPIO_34"),
58 PINCTRL_PIN(35, "GPIO_35"),
59 PINCTRL_PIN(36, "GPIO_36"),
60 PINCTRL_PIN(37, "GPIO_37"),
61 PINCTRL_PIN(38, "GPIO_38"),
62 PINCTRL_PIN(39, "GPIO_39"),
63 PINCTRL_PIN(40, "GPIO_40"),
64 PINCTRL_PIN(41, "GPIO_41"),
65 PINCTRL_PIN(42, "GPIO_42"),
66 PINCTRL_PIN(43, "GPIO_43"),
67 PINCTRL_PIN(44, "GPIO_44"),
68 PINCTRL_PIN(45, "GPIO_45"),
69 PINCTRL_PIN(46, "GPIO_46"),
70 PINCTRL_PIN(47, "GPIO_47"),
71 PINCTRL_PIN(48, "GPIO_48"),
72 PINCTRL_PIN(49, "GPIO_49"),
73 PINCTRL_PIN(50, "GPIO_50"),
74 PINCTRL_PIN(51, "GPIO_51"),
75 PINCTRL_PIN(52, "GPIO_52"),
76 PINCTRL_PIN(53, "GPIO_53"),
77 PINCTRL_PIN(54, "GPIO_54"),
78 PINCTRL_PIN(55, "GPIO_55"),
79 PINCTRL_PIN(56, "GPIO_56"),
80 PINCTRL_PIN(57, "GPIO_57"),
81 PINCTRL_PIN(58, "GPIO_58"),
82 PINCTRL_PIN(59, "GPIO_59"),
83 PINCTRL_PIN(60, "GPIO_60"),
84 PINCTRL_PIN(61, "GPIO_61"),
85 PINCTRL_PIN(62, "GPIO_62"),
86 PINCTRL_PIN(63, "GPIO_63"),
87 PINCTRL_PIN(64, "GPIO_64"),
88 PINCTRL_PIN(65, "GPIO_65"),
89 PINCTRL_PIN(66, "GPIO_66"),
90 PINCTRL_PIN(67, "GPIO_67"),
91 PINCTRL_PIN(68, "GPIO_68"),
92 PINCTRL_PIN(69, "GPIO_69"),
93 PINCTRL_PIN(70, "GPIO_70"),
94 PINCTRL_PIN(71, "GPIO_71"),
95 PINCTRL_PIN(72, "GPIO_72"),
96 PINCTRL_PIN(73, "GPIO_73"),
97 PINCTRL_PIN(74, "GPIO_74"),
98 PINCTRL_PIN(75, "GPIO_75"),
99 PINCTRL_PIN(76, "GPIO_76"),
100 PINCTRL_PIN(77, "GPIO_77"),
101 PINCTRL_PIN(78, "GPIO_78"),
102 PINCTRL_PIN(79, "GPIO_79"),
103 PINCTRL_PIN(80, "GPIO_80"),
104 PINCTRL_PIN(81, "GPIO_81"),
105 PINCTRL_PIN(82, "GPIO_82"),
106 PINCTRL_PIN(83, "GPIO_83"),
107 PINCTRL_PIN(84, "GPIO_84"),
108 PINCTRL_PIN(85, "GPIO_85"),
109 PINCTRL_PIN(86, "GPIO_86"),
110 PINCTRL_PIN(87, "GPIO_87"),
111 PINCTRL_PIN(88, "GPIO_88"),
112 PINCTRL_PIN(89, "GPIO_89"),
113 PINCTRL_PIN(90, "GPIO_90"),
114 PINCTRL_PIN(91, "GPIO_91"),
115 PINCTRL_PIN(92, "GPIO_92"),
116 PINCTRL_PIN(93, "GPIO_93"),
117 PINCTRL_PIN(94, "GPIO_94"),
118 PINCTRL_PIN(95, "GPIO_95"),
119 PINCTRL_PIN(96, "GPIO_96"),
120 PINCTRL_PIN(97, "GPIO_97"),
121 PINCTRL_PIN(98, "GPIO_98"),
122 PINCTRL_PIN(99, "GPIO_99"),
123 PINCTRL_PIN(100, "GPIO_100"),
124 PINCTRL_PIN(101, "GPIO_101"),
125 PINCTRL_PIN(102, "GPIO_102"),
126 PINCTRL_PIN(103, "GPIO_103"),
127 PINCTRL_PIN(104, "GPIO_104"),
128 PINCTRL_PIN(105, "GPIO_105"),
129 PINCTRL_PIN(106, "GPIO_106"),
130 PINCTRL_PIN(107, "GPIO_107"),
131 PINCTRL_PIN(108, "GPIO_108"),
132 PINCTRL_PIN(109, "GPIO_109"),
133 PINCTRL_PIN(110, "GPIO_110"),
134 PINCTRL_PIN(111, "GPIO_111"),
135 PINCTRL_PIN(112, "GPIO_112"),
136 PINCTRL_PIN(113, "GPIO_113"),
137 PINCTRL_PIN(114, "GPIO_114"),
138 PINCTRL_PIN(115, "GPIO_115"),
139 PINCTRL_PIN(116, "GPIO_116"),
140 PINCTRL_PIN(117, "GPIO_117"),
141 PINCTRL_PIN(118, "GPIO_118"),
142 PINCTRL_PIN(119, "GPIO_119"),
143 PINCTRL_PIN(120, "GPIO_120"),
144 PINCTRL_PIN(121, "GPIO_121"),
145 PINCTRL_PIN(122, "GPIO_122"),
146 PINCTRL_PIN(123, "GPIO_123"),
147 PINCTRL_PIN(124, "GPIO_124"),
148 PINCTRL_PIN(125, "GPIO_125"),
149 PINCTRL_PIN(126, "GPIO_126"),
150 PINCTRL_PIN(127, "GPIO_127"),
151 PINCTRL_PIN(128, "GPIO_128"),
152 PINCTRL_PIN(129, "GPIO_129"),
153 PINCTRL_PIN(130, "GPIO_130"),
154 PINCTRL_PIN(131, "GPIO_131"),
155 PINCTRL_PIN(132, "GPIO_132"),
156 PINCTRL_PIN(133, "GPIO_133"),
157 PINCTRL_PIN(134, "GPIO_134"),
158 PINCTRL_PIN(135, "GPIO_135"),
159 PINCTRL_PIN(136, "GPIO_136"),
160 PINCTRL_PIN(137, "GPIO_137"),
161 PINCTRL_PIN(138, "GPIO_138"),
162 PINCTRL_PIN(139, "GPIO_139"),
163 PINCTRL_PIN(140, "GPIO_140"),
164 PINCTRL_PIN(141, "GPIO_141"),
165 PINCTRL_PIN(142, "GPIO_142"),
166 PINCTRL_PIN(143, "GPIO_143"),
167 PINCTRL_PIN(144, "GPIO_144"),
168 PINCTRL_PIN(145, "GPIO_145"),
169 PINCTRL_PIN(146, "GPIO_146"),
170
171 PINCTRL_PIN(147, "SDC1_CLK"),
172 PINCTRL_PIN(148, "SDC1_CMD"),
173 PINCTRL_PIN(149, "SDC1_DATA"),
174 PINCTRL_PIN(150, "SDC2_CLK"),
175 PINCTRL_PIN(151, "SDC2_CMD"),
176 PINCTRL_PIN(152, "SDC2_DATA"),
177};
178
179#define DECLARE_APQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin }
180
181DECLARE_APQ_GPIO_PINS(0);
182DECLARE_APQ_GPIO_PINS(1);
183DECLARE_APQ_GPIO_PINS(2);
184DECLARE_APQ_GPIO_PINS(3);
185DECLARE_APQ_GPIO_PINS(4);
186DECLARE_APQ_GPIO_PINS(5);
187DECLARE_APQ_GPIO_PINS(6);
188DECLARE_APQ_GPIO_PINS(7);
189DECLARE_APQ_GPIO_PINS(8);
190DECLARE_APQ_GPIO_PINS(9);
191DECLARE_APQ_GPIO_PINS(10);
192DECLARE_APQ_GPIO_PINS(11);
193DECLARE_APQ_GPIO_PINS(12);
194DECLARE_APQ_GPIO_PINS(13);
195DECLARE_APQ_GPIO_PINS(14);
196DECLARE_APQ_GPIO_PINS(15);
197DECLARE_APQ_GPIO_PINS(16);
198DECLARE_APQ_GPIO_PINS(17);
199DECLARE_APQ_GPIO_PINS(18);
200DECLARE_APQ_GPIO_PINS(19);
201DECLARE_APQ_GPIO_PINS(20);
202DECLARE_APQ_GPIO_PINS(21);
203DECLARE_APQ_GPIO_PINS(22);
204DECLARE_APQ_GPIO_PINS(23);
205DECLARE_APQ_GPIO_PINS(24);
206DECLARE_APQ_GPIO_PINS(25);
207DECLARE_APQ_GPIO_PINS(26);
208DECLARE_APQ_GPIO_PINS(27);
209DECLARE_APQ_GPIO_PINS(28);
210DECLARE_APQ_GPIO_PINS(29);
211DECLARE_APQ_GPIO_PINS(30);
212DECLARE_APQ_GPIO_PINS(31);
213DECLARE_APQ_GPIO_PINS(32);
214DECLARE_APQ_GPIO_PINS(33);
215DECLARE_APQ_GPIO_PINS(34);
216DECLARE_APQ_GPIO_PINS(35);
217DECLARE_APQ_GPIO_PINS(36);
218DECLARE_APQ_GPIO_PINS(37);
219DECLARE_APQ_GPIO_PINS(38);
220DECLARE_APQ_GPIO_PINS(39);
221DECLARE_APQ_GPIO_PINS(40);
222DECLARE_APQ_GPIO_PINS(41);
223DECLARE_APQ_GPIO_PINS(42);
224DECLARE_APQ_GPIO_PINS(43);
225DECLARE_APQ_GPIO_PINS(44);
226DECLARE_APQ_GPIO_PINS(45);
227DECLARE_APQ_GPIO_PINS(46);
228DECLARE_APQ_GPIO_PINS(47);
229DECLARE_APQ_GPIO_PINS(48);
230DECLARE_APQ_GPIO_PINS(49);
231DECLARE_APQ_GPIO_PINS(50);
232DECLARE_APQ_GPIO_PINS(51);
233DECLARE_APQ_GPIO_PINS(52);
234DECLARE_APQ_GPIO_PINS(53);
235DECLARE_APQ_GPIO_PINS(54);
236DECLARE_APQ_GPIO_PINS(55);
237DECLARE_APQ_GPIO_PINS(56);
238DECLARE_APQ_GPIO_PINS(57);
239DECLARE_APQ_GPIO_PINS(58);
240DECLARE_APQ_GPIO_PINS(59);
241DECLARE_APQ_GPIO_PINS(60);
242DECLARE_APQ_GPIO_PINS(61);
243DECLARE_APQ_GPIO_PINS(62);
244DECLARE_APQ_GPIO_PINS(63);
245DECLARE_APQ_GPIO_PINS(64);
246DECLARE_APQ_GPIO_PINS(65);
247DECLARE_APQ_GPIO_PINS(66);
248DECLARE_APQ_GPIO_PINS(67);
249DECLARE_APQ_GPIO_PINS(68);
250DECLARE_APQ_GPIO_PINS(69);
251DECLARE_APQ_GPIO_PINS(70);
252DECLARE_APQ_GPIO_PINS(71);
253DECLARE_APQ_GPIO_PINS(72);
254DECLARE_APQ_GPIO_PINS(73);
255DECLARE_APQ_GPIO_PINS(74);
256DECLARE_APQ_GPIO_PINS(75);
257DECLARE_APQ_GPIO_PINS(76);
258DECLARE_APQ_GPIO_PINS(77);
259DECLARE_APQ_GPIO_PINS(78);
260DECLARE_APQ_GPIO_PINS(79);
261DECLARE_APQ_GPIO_PINS(80);
262DECLARE_APQ_GPIO_PINS(81);
263DECLARE_APQ_GPIO_PINS(82);
264DECLARE_APQ_GPIO_PINS(83);
265DECLARE_APQ_GPIO_PINS(84);
266DECLARE_APQ_GPIO_PINS(85);
267DECLARE_APQ_GPIO_PINS(86);
268DECLARE_APQ_GPIO_PINS(87);
269DECLARE_APQ_GPIO_PINS(88);
270DECLARE_APQ_GPIO_PINS(89);
271DECLARE_APQ_GPIO_PINS(90);
272DECLARE_APQ_GPIO_PINS(91);
273DECLARE_APQ_GPIO_PINS(92);
274DECLARE_APQ_GPIO_PINS(93);
275DECLARE_APQ_GPIO_PINS(94);
276DECLARE_APQ_GPIO_PINS(95);
277DECLARE_APQ_GPIO_PINS(96);
278DECLARE_APQ_GPIO_PINS(97);
279DECLARE_APQ_GPIO_PINS(98);
280DECLARE_APQ_GPIO_PINS(99);
281DECLARE_APQ_GPIO_PINS(100);
282DECLARE_APQ_GPIO_PINS(101);
283DECLARE_APQ_GPIO_PINS(102);
284DECLARE_APQ_GPIO_PINS(103);
285DECLARE_APQ_GPIO_PINS(104);
286DECLARE_APQ_GPIO_PINS(105);
287DECLARE_APQ_GPIO_PINS(106);
288DECLARE_APQ_GPIO_PINS(107);
289DECLARE_APQ_GPIO_PINS(108);
290DECLARE_APQ_GPIO_PINS(109);
291DECLARE_APQ_GPIO_PINS(110);
292DECLARE_APQ_GPIO_PINS(111);
293DECLARE_APQ_GPIO_PINS(112);
294DECLARE_APQ_GPIO_PINS(113);
295DECLARE_APQ_GPIO_PINS(114);
296DECLARE_APQ_GPIO_PINS(115);
297DECLARE_APQ_GPIO_PINS(116);
298DECLARE_APQ_GPIO_PINS(117);
299DECLARE_APQ_GPIO_PINS(118);
300DECLARE_APQ_GPIO_PINS(119);
301DECLARE_APQ_GPIO_PINS(120);
302DECLARE_APQ_GPIO_PINS(121);
303DECLARE_APQ_GPIO_PINS(122);
304DECLARE_APQ_GPIO_PINS(123);
305DECLARE_APQ_GPIO_PINS(124);
306DECLARE_APQ_GPIO_PINS(125);
307DECLARE_APQ_GPIO_PINS(126);
308DECLARE_APQ_GPIO_PINS(127);
309DECLARE_APQ_GPIO_PINS(128);
310DECLARE_APQ_GPIO_PINS(129);
311DECLARE_APQ_GPIO_PINS(130);
312DECLARE_APQ_GPIO_PINS(131);
313DECLARE_APQ_GPIO_PINS(132);
314DECLARE_APQ_GPIO_PINS(133);
315DECLARE_APQ_GPIO_PINS(134);
316DECLARE_APQ_GPIO_PINS(135);
317DECLARE_APQ_GPIO_PINS(136);
318DECLARE_APQ_GPIO_PINS(137);
319DECLARE_APQ_GPIO_PINS(138);
320DECLARE_APQ_GPIO_PINS(139);
321DECLARE_APQ_GPIO_PINS(140);
322DECLARE_APQ_GPIO_PINS(141);
323DECLARE_APQ_GPIO_PINS(142);
324DECLARE_APQ_GPIO_PINS(143);
325DECLARE_APQ_GPIO_PINS(144);
326DECLARE_APQ_GPIO_PINS(145);
327DECLARE_APQ_GPIO_PINS(146);
328
329static const unsigned int sdc1_clk_pins[] = { 147 };
330static const unsigned int sdc1_cmd_pins[] = { 148 };
331static const unsigned int sdc1_data_pins[] = { 149 };
332static const unsigned int sdc2_clk_pins[] = { 150 };
333static const unsigned int sdc2_cmd_pins[] = { 151 };
334static const unsigned int sdc2_data_pins[] = { 152 };
335
336#define FUNCTION(fname) \
337 [APQ_MUX_##fname] = { \
338 .name = #fname, \
339 .groups = fname##_groups, \
340 .ngroups = ARRAY_SIZE(fname##_groups), \
341 }
342
343#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \
344 { \
345 .name = "gpio" #id, \
346 .pins = gpio##id##_pins, \
347 .npins = ARRAY_SIZE(gpio##id##_pins), \
348 .funcs = (int[]){ \
349 APQ_MUX_gpio, \
350 APQ_MUX_##f1, \
351 APQ_MUX_##f2, \
352 APQ_MUX_##f3, \
353 APQ_MUX_##f4, \
354 APQ_MUX_##f5, \
355 APQ_MUX_##f6, \
356 APQ_MUX_##f7 \
357 }, \
358 .nfuncs = 8, \
359 .ctl_reg = 0x1000 + 0x10 * id, \
360 .io_reg = 0x1004 + 0x10 * id, \
361 .intr_cfg_reg = 0x1008 + 0x10 * id, \
362 .intr_status_reg = 0x100c + 0x10 * id, \
363 .intr_target_reg = 0x1008 + 0x10 * id, \
364 .mux_bit = 2, \
365 .pull_bit = 0, \
366 .drv_bit = 6, \
367 .oe_bit = 9, \
368 .in_bit = 0, \
369 .out_bit = 1, \
370 .intr_enable_bit = 0, \
371 .intr_status_bit = 0, \
372 .intr_ack_high = 0, \
373 .intr_target_bit = 5, \
374 .intr_target_kpss_val = 3, \
375 .intr_raw_status_bit = 4, \
376 .intr_polarity_bit = 1, \
377 .intr_detection_bit = 2, \
378 .intr_detection_width = 2, \
379 }
380
381#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
382 { \
383 .name = #pg_name, \
384 .pins = pg_name##_pins, \
385 .npins = ARRAY_SIZE(pg_name##_pins), \
386 .ctl_reg = ctl, \
387 .io_reg = 0, \
388 .intr_cfg_reg = 0, \
389 .intr_status_reg = 0, \
390 .intr_target_reg = 0, \
391 .mux_bit = -1, \
392 .pull_bit = pull, \
393 .drv_bit = drv, \
394 .oe_bit = -1, \
395 .in_bit = -1, \
396 .out_bit = -1, \
397 .intr_enable_bit = -1, \
398 .intr_status_bit = -1, \
399 .intr_target_bit = -1, \
400 .intr_target_kpss_val = -1, \
401 .intr_raw_status_bit = -1, \
402 .intr_polarity_bit = -1, \
403 .intr_detection_bit = -1, \
404 .intr_detection_width = -1, \
405 }
406
407enum apq8084_functions {
408 APQ_MUX_adsp_ext,
409 APQ_MUX_audio_ref,
410 APQ_MUX_blsp_i2c1,
411 APQ_MUX_blsp_i2c2,
412 APQ_MUX_blsp_i2c3,
413 APQ_MUX_blsp_i2c4,
414 APQ_MUX_blsp_i2c5,
415 APQ_MUX_blsp_i2c6,
416 APQ_MUX_blsp_i2c7,
417 APQ_MUX_blsp_i2c8,
418 APQ_MUX_blsp_i2c9,
419 APQ_MUX_blsp_i2c10,
420 APQ_MUX_blsp_i2c11,
421 APQ_MUX_blsp_i2c12,
422 APQ_MUX_blsp_spi1,
423 APQ_MUX_blsp_spi1_cs1,
424 APQ_MUX_blsp_spi1_cs2,
425 APQ_MUX_blsp_spi1_cs3,
426 APQ_MUX_blsp_spi2,
427 APQ_MUX_blsp_spi3,
428 APQ_MUX_blsp_spi3_cs1,
429 APQ_MUX_blsp_spi3_cs2,
430 APQ_MUX_blsp_spi3_cs3,
431 APQ_MUX_blsp_spi4,
432 APQ_MUX_blsp_spi5,
433 APQ_MUX_blsp_spi6,
434 APQ_MUX_blsp_spi7,
435 APQ_MUX_blsp_spi8,
436 APQ_MUX_blsp_spi9,
437 APQ_MUX_blsp_spi10,
438 APQ_MUX_blsp_spi10_cs1,
439 APQ_MUX_blsp_spi10_cs2,
440 APQ_MUX_blsp_spi10_cs3,
441 APQ_MUX_blsp_spi11,
442 APQ_MUX_blsp_spi12,
443 APQ_MUX_blsp_uart1,
444 APQ_MUX_blsp_uart2,
445 APQ_MUX_blsp_uart3,
446 APQ_MUX_blsp_uart4,
447 APQ_MUX_blsp_uart5,
448 APQ_MUX_blsp_uart6,
449 APQ_MUX_blsp_uart7,
450 APQ_MUX_blsp_uart8,
451 APQ_MUX_blsp_uart9,
452 APQ_MUX_blsp_uart10,
453 APQ_MUX_blsp_uart11,
454 APQ_MUX_blsp_uart12,
455 APQ_MUX_blsp_uim1,
456 APQ_MUX_blsp_uim2,
457 APQ_MUX_blsp_uim3,
458 APQ_MUX_blsp_uim4,
459 APQ_MUX_blsp_uim5,
460 APQ_MUX_blsp_uim6,
461 APQ_MUX_blsp_uim7,
462 APQ_MUX_blsp_uim8,
463 APQ_MUX_blsp_uim9,
464 APQ_MUX_blsp_uim10,
465 APQ_MUX_blsp_uim11,
466 APQ_MUX_blsp_uim12,
467 APQ_MUX_cam_mclk0,
468 APQ_MUX_cam_mclk1,
469 APQ_MUX_cam_mclk2,
470 APQ_MUX_cam_mclk3,
471 APQ_MUX_cci_async,
472 APQ_MUX_cci_async_in0,
473 APQ_MUX_cci_i2c0,
474 APQ_MUX_cci_i2c1,
475 APQ_MUX_cci_timer0,
476 APQ_MUX_cci_timer1,
477 APQ_MUX_cci_timer2,
478 APQ_MUX_cci_timer3,
479 APQ_MUX_cci_timer4,
480 APQ_MUX_edp_hpd,
481 APQ_MUX_gcc_gp1,
482 APQ_MUX_gcc_gp2,
483 APQ_MUX_gcc_gp3,
484 APQ_MUX_gcc_obt,
485 APQ_MUX_gcc_vtt,
486 APQ_MUX_gp_mn,
487 APQ_MUX_gp_pdm0,
488 APQ_MUX_gp_pdm1,
489 APQ_MUX_gp_pdm2,
490 APQ_MUX_gp0_clk,
491 APQ_MUX_gp1_clk,
492 APQ_MUX_gpio,
493 APQ_MUX_hdmi_cec,
494 APQ_MUX_hdmi_ddc,
495 APQ_MUX_hdmi_dtest,
496 APQ_MUX_hdmi_hpd,
497 APQ_MUX_hdmi_rcv,
498 APQ_MUX_hsic,
499 APQ_MUX_ldo_en,
500 APQ_MUX_ldo_update,
501 APQ_MUX_mdp_vsync,
502 APQ_MUX_pci_e0,
503 APQ_MUX_pci_e0_n,
504 APQ_MUX_pci_e0_rst,
505 APQ_MUX_pci_e1,
506 APQ_MUX_pci_e1_rst,
507 APQ_MUX_pci_e1_rst_n,
508 APQ_MUX_pci_e1_clkreq_n,
509 APQ_MUX_pri_mi2s,
510 APQ_MUX_qua_mi2s,
511 APQ_MUX_sata_act,
512 APQ_MUX_sata_devsleep,
513 APQ_MUX_sata_devsleep_n,
514 APQ_MUX_sd_write,
515 APQ_MUX_sdc_emmc_mode,
516 APQ_MUX_sdc3,
517 APQ_MUX_sdc4,
518 APQ_MUX_sec_mi2s,
519 APQ_MUX_slimbus,
520 APQ_MUX_spdif_tx,
521 APQ_MUX_spkr_i2s,
522 APQ_MUX_spkr_i2s_ws,
523 APQ_MUX_spss_geni,
524 APQ_MUX_ter_mi2s,
525 APQ_MUX_tsif1,
526 APQ_MUX_tsif2,
527 APQ_MUX_uim,
528 APQ_MUX_uim_batt_alarm,
529 APQ_MUX_NA,
530};
531
532static const char * const gpio_groups[] = {
533 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
534 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
535 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
536 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
537 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
538 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
539 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
540 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
541 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
542 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
543 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
544 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
545 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
546 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
547 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
548 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
549 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
550 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
551 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
552 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
553 "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
554 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146"
555};
556
557static const char * const adsp_ext_groups[] = {
558 "gpio34"
559};
560static const char * const audio_ref_groups[] = {
561 "gpio100"
562};
563static const char * const blsp_i2c1_groups[] = {
564 "gpio2", "gpio3"
565};
566static const char * const blsp_i2c2_groups[] = {
567 "gpio6", "gpio7"
568};
569static const char * const blsp_i2c3_groups[] = {
570 "gpio10", "gpio11"
571};
572static const char * const blsp_i2c4_groups[] = {
573 "gpio29", "gpio30"
574};
575static const char * const blsp_i2c5_groups[] = {
576 "gpio41", "gpio42"
577};
578static const char * const blsp_i2c6_groups[] = {
579 "gpio45", "gpio46"
580};
581static const char * const blsp_i2c7_groups[] = {
582 "gpio132", "gpio133"
583};
584static const char * const blsp_i2c8_groups[] = {
585 "gpio53", "gpio54"
586};
587static const char * const blsp_i2c9_groups[] = {
588 "gpio57", "gpio58"
589};
590static const char * const blsp_i2c10_groups[] = {
591 "gpio61", "gpio62"
592};
593static const char * const blsp_i2c11_groups[] = {
594 "gpio65", "gpio66"
595};
596static const char * const blsp_i2c12_groups[] = {
597 "gpio49", "gpio50"
598};
599static const char * const blsp_spi1_groups[] = {
600 "gpio0", "gpio1", "gpio2", "gpio3"
601};
602static const char * const blsp_spi2_groups[] = {
603 "gpio4", "gpio5", "gpio6", "gpio7"
604};
605static const char * const blsp_spi3_groups[] = {
606 "gpio8", "gpio9", "gpio10", "gpio11"
607};
608static const char * const blsp_spi4_groups[] = {
609 "gpio27", "gpio28", "gpio29", "gpio30"
610};
611static const char * const blsp_spi5_groups[] = {
612 "gpio39", "gpio40", "gpio41", "gpio42"
613};
614static const char * const blsp_spi6_groups[] = {
615 "gpio43", "gpio44", "gpio45", "gpio46"
616};
617static const char * const blsp_spi7_groups[] = {
618 "gpio130", "gpio131", "gpio132", "gpio133"
619};
620static const char * const blsp_spi8_groups[] = {
621 "gpio51", "gpio52", "gpio53", "gpio54"
622};
623static const char * const blsp_spi9_groups[] = {
624 "gpio55", "gpio56", "gpio57", "gpio58"
625};
626static const char * const blsp_spi10_groups[] = {
627 "gpio59", "gpio60", "gpio61", "gpio62"
628};
629static const char * const blsp_spi11_groups[] = {
630 "gpio63", "gpio64", "gpio65", "gpio66"
631};
632static const char * const blsp_spi12_groups[] = {
633 "gpio47", "gpio48", "gpio49", "gpio50"
634};
635static const char * const blsp_uart1_groups[] = {
636 "gpio0", "gpio1", "gpio2", "gpio3"
637};
638static const char * const blsp_uart2_groups[] = {
639 "gpio4", "gpio5", "gpio6", "gpio7"
640};
641static const char * const blsp_uart3_groups[] = {
642 "gpio8"
643};
644static const char * const blsp_uart4_groups[] = {
645 "gpio27", "gpio28", "gpio29", "gpio30"
646};
647static const char * const blsp_uart5_groups[] = {
648 "gpio39", "gpio40", "gpio41", "gpio42"
649};
650static const char * const blsp_uart6_groups[] = {
651 "gpio43", "gpio44", "gpio45", "gpio46"
652};
653static const char * const blsp_uart7_groups[] = {
654 "gpio130", "gpio131", "gpio132", "gpio133"
655};
656static const char * const blsp_uart8_groups[] = {
657 "gpio51", "gpio52", "gpio53", "gpio54"
658};
659static const char * const blsp_uart9_groups[] = {
660 "gpio55", "gpio56", "gpio57", "gpio58"
661};
662static const char * const blsp_uart10_groups[] = {
663 "gpio59", "gpio60", "gpio61", "gpio62"
664};
665static const char * const blsp_uart11_groups[] = {
666 "gpio63", "gpio64", "gpio65", "gpio66"
667};
668static const char * const blsp_uart12_groups[] = {
669 "gpio47", "gpio48", "gpio49", "gpio50"
670};
671static const char * const blsp_uim1_groups[] = {
672 "gpio0", "gpio1"
673};
674static const char * const blsp_uim2_groups[] = {
675 "gpio4", "gpio5"
676};
677static const char * const blsp_uim3_groups[] = {
678 "gpio8", "gpio9"
679};
680static const char * const blsp_uim4_groups[] = {
681 "gpio27", "gpio28"
682};
683static const char * const blsp_uim5_groups[] = {
684 "gpio39", "gpio40"
685};
686static const char * const blsp_uim6_groups[] = {
687 "gpio43", "gpio44"
688};
689static const char * const blsp_uim7_groups[] = {
690 "gpio130", "gpio131"
691};
692static const char * const blsp_uim8_groups[] = {
693 "gpio51", "gpio52"
694};
695static const char * const blsp_uim9_groups[] = {
696 "gpio55", "gpio56"
697};
698static const char * const blsp_uim10_groups[] = {
699 "gpio59", "gpio60"
700};
701static const char * const blsp_uim11_groups[] = {
702 "gpio63", "gpio64"
703};
704static const char * const blsp_uim12_groups[] = {
705 "gpio47", "gpio48"
706};
707static const char * const blsp_spi1_cs1_groups[] = {
708 "gpio116"
709};
710static const char * const blsp_spi1_cs2_groups[] = {
711 "gpio117"
712};
713static const char * const blsp_spi1_cs3_groups[] = {
714 "gpio118"
715};
716static const char * const blsp_spi3_cs1_groups[] = {
717 "gpio67"
718};
719static const char * const blsp_spi3_cs2_groups[] = {
720 "gpio71"
721};
722static const char * const blsp_spi3_cs3_groups[] = {
723 "gpio72"
724};
725static const char * const blsp_spi10_cs1_groups[] = {
726 "gpio106"
727};
728static const char * const blsp_spi10_cs2_groups[] = {
729 "gpio111"
730};
731static const char * const blsp_spi10_cs3_groups[] = {
732 "gpio128"
733};
734static const char * const cam_mclk0_groups[] = {
735 "gpio15"
736};
737static const char * const cam_mclk1_groups[] = {
738 "gpio16"
739};
740static const char * const cam_mclk2_groups[] = {
741 "gpio17"
742};
743static const char * const cam_mclk3_groups[] = {
744 "gpio18"
745};
746static const char * const cci_async_groups[] = {
747 "gpio26", "gpio119"
748};
749static const char * const cci_async_in0_groups[] = {
750 "gpio120"
751};
752static const char * const cci_i2c0_groups[] = {
753 "gpio19", "gpio20"
754};
755static const char * const cci_i2c1_groups[] = {
756 "gpio21", "gpio22"
757};
758static const char * const cci_timer0_groups[] = {
759 "gpio23"
760};
761static const char * const cci_timer1_groups[] = {
762 "gpio24"
763};
764static const char * const cci_timer2_groups[] = {
765 "gpio25"
766};
767static const char * const cci_timer3_groups[] = {
768 "gpio26"
769};
770static const char * const cci_timer4_groups[] = {
771 "gpio119"
772};
773static const char * const edp_hpd_groups[] = {
774 "gpio103"
775};
776static const char * const gcc_gp1_groups[] = {
777 "gpio37"
778};
779static const char * const gcc_gp2_groups[] = {
780 "gpio38"
781};
782static const char * const gcc_gp3_groups[] = {
783 "gpio86"
784};
785static const char * const gcc_obt_groups[] = {
786 "gpio127"
787};
788static const char * const gcc_vtt_groups[] = {
789 "gpio126"
790};
791static const char * const gp_mn_groups[] = {
792 "gpio29"
793};
794static const char * const gp_pdm0_groups[] = {
795 "gpio48", "gpio83"
796};
797static const char * const gp_pdm1_groups[] = {
798 "gpio84", "gpio101"
799};
800static const char * const gp_pdm2_groups[] = {
801 "gpio85", "gpio110"
802};
803static const char * const gp0_clk_groups[] = {
804 "gpio25"
805};
806static const char * const gp1_clk_groups[] = {
807 "gpio26"
808};
809static const char * const hdmi_cec_groups[] = {
810 "gpio31"
811};
812static const char * const hdmi_ddc_groups[] = {
813 "gpio32", "gpio33"
814};
815static const char * const hdmi_dtest_groups[] = {
816 "gpio123"
817};
818static const char * const hdmi_hpd_groups[] = {
819 "gpio34"
820};
821static const char * const hdmi_rcv_groups[] = {
822 "gpio125"
823};
824static const char * const hsic_groups[] = {
825 "gpio134", "gpio135"
826};
827static const char * const ldo_en_groups[] = {
828 "gpio124"
829};
830static const char * const ldo_update_groups[] = {
831 "gpio125"
832};
833static const char * const mdp_vsync_groups[] = {
834 "gpio12", "gpio13", "gpio14"
835};
836static const char * const pci_e0_groups[] = {
837 "gpio68", "gpio70"
838};
839static const char * const pci_e0_n_groups[] = {
840 "gpio68", "gpio70"
841};
842static const char * const pci_e0_rst_groups[] = {
843 "gpio70"
844};
845static const char * const pci_e1_groups[] = {
846 "gpio140"
847};
848static const char * const pci_e1_rst_groups[] = {
849 "gpio140"
850};
851static const char * const pci_e1_rst_n_groups[] = {
852 "gpio140"
853};
854static const char * const pci_e1_clkreq_n_groups[] = {
855 "gpio141"
856};
857static const char * const pri_mi2s_groups[] = {
858 "gpio76", "gpio77", "gpio78", "gpio79", "gpio80"
859};
860static const char * const qua_mi2s_groups[] = {
861 "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97"
862};
863static const char * const sata_act_groups[] = {
864 "gpio129"
865};
866static const char * const sata_devsleep_groups[] = {
867 "gpio119"
868};
869static const char * const sata_devsleep_n_groups[] = {
870 "gpio119"
871};
872static const char * const sd_write_groups[] = {
873 "gpio75"
874};
875static const char * const sdc_emmc_mode_groups[] = {
876 "gpio146"
877};
878static const char * const sdc3_groups[] = {
879 "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", "gpio72"
880};
881static const char * const sdc4_groups[] = {
882 "gpio82", "gpio83", "gpio84", "gpio85", "gpio86",
883 "gpio91", "gpio95", "gpio96", "gpio97", "gpio101"
884};
885static const char * const sec_mi2s_groups[] = {
886 "gpio81", "gpio82", "gpio83", "gpio84", "gpio85"
887};
888static const char * const slimbus_groups[] = {
889 "gpio98", "gpio99"
890};
891static const char * const spdif_tx_groups[] = {
892 "gpio124", "gpio136", "gpio142"
893};
894static const char * const spkr_i2s_groups[] = {
895 "gpio98", "gpio99", "gpio100"
896};
897static const char * const spkr_i2s_ws_groups[] = {
898 "gpio104"
899};
900static const char * const spss_geni_groups[] = {
901 "gpio8", "gpio9"
902};
903static const char * const ter_mi2s_groups[] = {
904 "gpio86", "gpio87", "gpio88", "gpio89", "gpio90"
905};
906static const char * const tsif1_groups[] = {
907 "gpio82", "gpio83", "gpio84", "gpio85", "gpio86"
908};
909static const char * const tsif2_groups[] = {
910 "gpio91", "gpio95", "gpio96", "gpio97", "gpio101"
911};
912static const char * const uim_groups[] = {
913 "gpio130", "gpio131", "gpio132", "gpio133"
914};
915static const char * const uim_batt_alarm_groups[] = {
916 "gpio102"
917};
918static const struct msm_function apq8084_functions[] = {
919 FUNCTION(adsp_ext),
920 FUNCTION(audio_ref),
921 FUNCTION(blsp_i2c1),
922 FUNCTION(blsp_i2c2),
923 FUNCTION(blsp_i2c3),
924 FUNCTION(blsp_i2c4),
925 FUNCTION(blsp_i2c5),
926 FUNCTION(blsp_i2c6),
927 FUNCTION(blsp_i2c7),
928 FUNCTION(blsp_i2c8),
929 FUNCTION(blsp_i2c9),
930 FUNCTION(blsp_i2c10),
931 FUNCTION(blsp_i2c11),
932 FUNCTION(blsp_i2c12),
933 FUNCTION(blsp_spi1),
934 FUNCTION(blsp_spi1_cs1),
935 FUNCTION(blsp_spi1_cs2),
936 FUNCTION(blsp_spi1_cs3),
937 FUNCTION(blsp_spi2),
938 FUNCTION(blsp_spi3),
939 FUNCTION(blsp_spi3_cs1),
940 FUNCTION(blsp_spi3_cs2),
941 FUNCTION(blsp_spi3_cs3),
942 FUNCTION(blsp_spi4),
943 FUNCTION(blsp_spi5),
944 FUNCTION(blsp_spi6),
945 FUNCTION(blsp_spi7),
946 FUNCTION(blsp_spi8),
947 FUNCTION(blsp_spi9),
948 FUNCTION(blsp_spi10),
949 FUNCTION(blsp_spi10_cs1),
950 FUNCTION(blsp_spi10_cs2),
951 FUNCTION(blsp_spi10_cs3),
952 FUNCTION(blsp_spi11),
953 FUNCTION(blsp_spi12),
954 FUNCTION(blsp_uart1),
955 FUNCTION(blsp_uart2),
956 FUNCTION(blsp_uart3),
957 FUNCTION(blsp_uart4),
958 FUNCTION(blsp_uart5),
959 FUNCTION(blsp_uart6),
960 FUNCTION(blsp_uart7),
961 FUNCTION(blsp_uart8),
962 FUNCTION(blsp_uart9),
963 FUNCTION(blsp_uart10),
964 FUNCTION(blsp_uart11),
965 FUNCTION(blsp_uart12),
966 FUNCTION(blsp_uim1),
967 FUNCTION(blsp_uim2),
968 FUNCTION(blsp_uim3),
969 FUNCTION(blsp_uim4),
970 FUNCTION(blsp_uim5),
971 FUNCTION(blsp_uim6),
972 FUNCTION(blsp_uim7),
973 FUNCTION(blsp_uim8),
974 FUNCTION(blsp_uim9),
975 FUNCTION(blsp_uim10),
976 FUNCTION(blsp_uim11),
977 FUNCTION(blsp_uim12),
978 FUNCTION(cam_mclk0),
979 FUNCTION(cam_mclk1),
980 FUNCTION(cam_mclk2),
981 FUNCTION(cam_mclk3),
982 FUNCTION(cci_async),
983 FUNCTION(cci_async_in0),
984 FUNCTION(cci_i2c0),
985 FUNCTION(cci_i2c1),
986 FUNCTION(cci_timer0),
987 FUNCTION(cci_timer1),
988 FUNCTION(cci_timer2),
989 FUNCTION(cci_timer3),
990 FUNCTION(cci_timer4),
991 FUNCTION(edp_hpd),
992 FUNCTION(gcc_gp1),
993 FUNCTION(gcc_gp2),
994 FUNCTION(gcc_gp3),
995 FUNCTION(gcc_obt),
996 FUNCTION(gcc_vtt),
997 FUNCTION(gp_mn),
998 FUNCTION(gp_pdm0),
999 FUNCTION(gp_pdm1),
1000 FUNCTION(gp_pdm2),
1001 FUNCTION(gp0_clk),
1002 FUNCTION(gp1_clk),
1003 FUNCTION(gpio),
1004 FUNCTION(hdmi_cec),
1005 FUNCTION(hdmi_ddc),
1006 FUNCTION(hdmi_dtest),
1007 FUNCTION(hdmi_hpd),
1008 FUNCTION(hdmi_rcv),
1009 FUNCTION(hsic),
1010 FUNCTION(ldo_en),
1011 FUNCTION(ldo_update),
1012 FUNCTION(mdp_vsync),
1013 FUNCTION(pci_e0),
1014 FUNCTION(pci_e0_n),
1015 FUNCTION(pci_e0_rst),
1016 FUNCTION(pci_e1),
1017 FUNCTION(pci_e1_rst),
1018 FUNCTION(pci_e1_rst_n),
1019 FUNCTION(pci_e1_clkreq_n),
1020 FUNCTION(pri_mi2s),
1021 FUNCTION(qua_mi2s),
1022 FUNCTION(sata_act),
1023 FUNCTION(sata_devsleep),
1024 FUNCTION(sata_devsleep_n),
1025 FUNCTION(sd_write),
1026 FUNCTION(sdc_emmc_mode),
1027 FUNCTION(sdc3),
1028 FUNCTION(sdc4),
1029 FUNCTION(sec_mi2s),
1030 FUNCTION(slimbus),
1031 FUNCTION(spdif_tx),
1032 FUNCTION(spkr_i2s),
1033 FUNCTION(spkr_i2s_ws),
1034 FUNCTION(spss_geni),
1035 FUNCTION(ter_mi2s),
1036 FUNCTION(tsif1),
1037 FUNCTION(tsif2),
1038 FUNCTION(uim),
1039 FUNCTION(uim_batt_alarm),
1040};
1041
1042static const struct msm_pingroup apq8084_groups[] = {
1043 PINGROUP(0, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA),
1044 PINGROUP(1, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA),
1045 PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA),
1046 PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA),
1047 PINGROUP(4, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA),
1048 PINGROUP(5, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA),
1049 PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA),
1050 PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA),
1051 PINGROUP(8, blsp_spi3, blsp_uart3, blsp_uim3, spss_geni, NA, NA, NA),
1052 PINGROUP(9, blsp_spi3, blsp_uim3, blsp_uart3, spss_geni, NA, NA, NA),
1053 PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA),
1054 PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA),
1055 PINGROUP(12, mdp_vsync, NA, NA, NA, NA, NA, NA),
1056 PINGROUP(13, mdp_vsync, NA, NA, NA, NA, NA, NA),
1057 PINGROUP(14, mdp_vsync, NA, NA, NA, NA, NA, NA),
1058 PINGROUP(15, cam_mclk0, NA, NA, NA, NA, NA, NA),
1059 PINGROUP(16, cam_mclk1, NA, NA, NA, NA, NA, NA),
1060 PINGROUP(17, cam_mclk2, NA, NA, NA, NA, NA, NA),
1061 PINGROUP(18, cam_mclk3, NA, NA, NA, NA, NA, NA),
1062 PINGROUP(19, cci_i2c0, NA, NA, NA, NA, NA, NA),
1063 PINGROUP(20, cci_i2c0, NA, NA, NA, NA, NA, NA),
1064 PINGROUP(21, cci_i2c1, NA, NA, NA, NA, NA, NA),
1065 PINGROUP(22, cci_i2c1, NA, NA, NA, NA, NA, NA),
1066 PINGROUP(23, cci_timer0, NA, NA, NA, NA, NA, NA),
1067 PINGROUP(24, cci_timer1, NA, NA, NA, NA, NA, NA),
1068 PINGROUP(25, cci_timer2, gp0_clk, NA, NA, NA, NA, NA),
1069 PINGROUP(26, cci_timer3, cci_async, gp1_clk, NA, NA, NA, NA),
1070 PINGROUP(27, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA, NA),
1071 PINGROUP(28, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA, NA),
1072 PINGROUP(29, blsp_spi4, blsp_uart4, blsp_i2c4, gp_mn, NA, NA, NA),
1073 PINGROUP(30, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA, NA),
1074 PINGROUP(31, hdmi_cec, NA, NA, NA, NA, NA, NA),
1075 PINGROUP(32, hdmi_ddc, NA, NA, NA, NA, NA, NA),
1076 PINGROUP(33, hdmi_ddc, NA, NA, NA, NA, NA, NA),
1077 PINGROUP(34, hdmi_hpd, NA, adsp_ext, NA, NA, NA, NA),
1078 PINGROUP(35, NA, NA, NA, NA, NA, NA, NA),
1079 PINGROUP(36, NA, NA, NA, NA, NA, NA, NA),
1080 PINGROUP(37, gcc_gp1, NA, NA, NA, NA, NA, NA),
1081 PINGROUP(38, gcc_gp2, NA, NA, NA, NA, NA, NA),
1082 PINGROUP(39, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA),
1083 PINGROUP(40, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA),
1084 PINGROUP(41, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA),
1085 PINGROUP(42, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA),
1086 PINGROUP(43, blsp_spi6, blsp_uart6, blsp_uim6, NA, NA, NA, NA),
1087 PINGROUP(44, blsp_spi6, blsp_uart6, blsp_uim6, NA, NA, NA, NA),
1088 PINGROUP(45, blsp_spi6, blsp_uart6, blsp_i2c6, NA, NA, NA, NA),
1089 PINGROUP(46, blsp_spi6, blsp_uart6, blsp_i2c6, NA, NA, NA, NA),
1090 PINGROUP(47, blsp_spi12, blsp_uart12, blsp_uim12, NA, NA, NA, NA),
1091 PINGROUP(48, blsp_spi12, blsp_uart12, blsp_uim12, gp_pdm0, NA, NA, NA),
1092 PINGROUP(49, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA),
1093 PINGROUP(50, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA),
1094 PINGROUP(51, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA),
1095 PINGROUP(52, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA),
1096 PINGROUP(53, blsp_spi8, blsp_uart8, blsp_i2c8, NA, NA, NA, NA),
1097 PINGROUP(54, blsp_spi8, blsp_uart8, blsp_i2c8, NA, NA, NA, NA),
1098 PINGROUP(55, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA, NA),
1099 PINGROUP(56, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA, NA),
1100 PINGROUP(57, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA, NA),
1101 PINGROUP(58, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA, NA),
1102 PINGROUP(59, blsp_spi10, blsp_uart10, blsp_uim10, NA, NA, NA, NA),
1103 PINGROUP(60, blsp_spi10, blsp_uart10, blsp_uim10, NA, NA, NA, NA),
1104 PINGROUP(61, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA),
1105 PINGROUP(62, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA),
1106 PINGROUP(63, blsp_spi11, blsp_uart11, blsp_uim11, NA, NA, NA, NA),
1107 PINGROUP(64, blsp_spi11, blsp_uart11, blsp_uim11, NA, NA, NA, NA),
1108 PINGROUP(65, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA),
1109 PINGROUP(66, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA),
1110 PINGROUP(67, sdc3, blsp_spi3_cs1, NA, NA, NA, NA, NA),
1111 PINGROUP(68, sdc3, pci_e0, NA, NA, NA, NA, NA),
1112 PINGROUP(69, sdc3, NA, NA, NA, NA, NA, NA),
1113 PINGROUP(70, sdc3, pci_e0_n, pci_e0, NA, NA, NA, NA),
1114 PINGROUP(71, sdc3, blsp_spi3_cs2, NA, NA, NA, NA, NA),
1115 PINGROUP(72, sdc3, blsp_spi3_cs3, NA, NA, NA, NA, NA),
1116 PINGROUP(73, NA, NA, NA, NA, NA, NA, NA),
1117 PINGROUP(74, NA, NA, NA, NA, NA, NA, NA),
1118 PINGROUP(75, sd_write, NA, NA, NA, NA, NA, NA),
1119 PINGROUP(76, pri_mi2s, NA, NA, NA, NA, NA, NA),
1120 PINGROUP(77, pri_mi2s, NA, NA, NA, NA, NA, NA),
1121 PINGROUP(78, pri_mi2s, NA, NA, NA, NA, NA, NA),
1122 PINGROUP(79, pri_mi2s, NA, NA, NA, NA, NA, NA),
1123 PINGROUP(80, pri_mi2s, NA, NA, NA, NA, NA, NA),
1124 PINGROUP(81, sec_mi2s, NA, NA, NA, NA, NA, NA),
1125 PINGROUP(82, sec_mi2s, sdc4, tsif1, NA, NA, NA, NA),
1126 PINGROUP(83, sec_mi2s, sdc4, tsif1, NA, NA, NA, gp_pdm0),
1127 PINGROUP(84, sec_mi2s, sdc4, tsif1, NA, NA, NA, gp_pdm1),
1128 PINGROUP(85, sec_mi2s, sdc4, tsif1, NA, gp_pdm2, NA, NA),
1129 PINGROUP(86, ter_mi2s, sdc4, tsif1, NA, NA, NA, gcc_gp3),
1130 PINGROUP(87, ter_mi2s, NA, NA, NA, NA, NA, NA),
1131 PINGROUP(88, ter_mi2s, NA, NA, NA, NA, NA, NA),
1132 PINGROUP(89, ter_mi2s, NA, NA, NA, NA, NA, NA),
1133 PINGROUP(90, ter_mi2s, NA, NA, NA, NA, NA, NA),
1134 PINGROUP(91, qua_mi2s, sdc4, tsif2, NA, NA, NA, NA),
1135 PINGROUP(92, qua_mi2s, NA, NA, NA, NA, NA, NA),
1136 PINGROUP(93, qua_mi2s, NA, NA, NA, NA, NA, NA),
1137 PINGROUP(94, qua_mi2s, NA, NA, NA, NA, NA, NA),
1138 PINGROUP(95, qua_mi2s, sdc4, tsif2, NA, NA, NA, gcc_gp1),
1139 PINGROUP(96, qua_mi2s, sdc4, tsif2, NA, NA, NA, gcc_gp2),
1140 PINGROUP(97, qua_mi2s, sdc4, tsif2, NA, gcc_gp3, NA, NA),
1141 PINGROUP(98, slimbus, spkr_i2s, NA, NA, NA, NA, NA),
1142 PINGROUP(99, slimbus, spkr_i2s, NA, NA, NA, NA, NA),
1143 PINGROUP(100, audio_ref, spkr_i2s, NA, NA, NA, NA, NA),
1144 PINGROUP(101, sdc4, tsif2, gp_pdm1, NA, NA, NA, NA),
1145 PINGROUP(102, uim_batt_alarm, NA, NA, NA, NA, NA, NA),
1146 PINGROUP(103, edp_hpd, NA, NA, NA, NA, NA, NA),
1147 PINGROUP(104, spkr_i2s, NA, NA, NA, NA, NA, NA),
1148 PINGROUP(105, NA, NA, NA, NA, NA, NA, NA),
1149 PINGROUP(106, blsp_spi10_cs1, NA, NA, NA, NA, NA, NA),
1150 PINGROUP(107, NA, NA, NA, NA, NA, NA, NA),
1151 PINGROUP(108, NA, NA, NA, NA, NA, NA, NA),
1152 PINGROUP(109, NA, NA, NA, NA, NA, NA, NA),
1153 PINGROUP(110, gp_pdm2, NA, NA, NA, NA, NA, NA),
1154 PINGROUP(111, blsp_spi10_cs2, NA, NA, NA, NA, NA, NA),
1155 PINGROUP(112, NA, NA, NA, NA, NA, NA, NA),
1156 PINGROUP(113, NA, NA, NA, NA, NA, NA, NA),
1157 PINGROUP(114, NA, NA, NA, NA, NA, NA, NA),
1158 PINGROUP(115, NA, NA, NA, NA, NA, NA, NA),
1159 PINGROUP(116, blsp_spi1_cs1, NA, NA, NA, NA, NA, NA),
1160 PINGROUP(117, blsp_spi1_cs2, NA, NA, NA, NA, NA, NA),
1161 PINGROUP(118, blsp_spi1_cs3, NA, NA, NA, NA, NA, NA),
1162 PINGROUP(119, cci_timer4, cci_async, sata_devsleep, sata_devsleep_n, NA, NA, NA),
1163 PINGROUP(120, cci_async, NA, NA, NA, NA, NA, NA),
1164 PINGROUP(121, NA, NA, NA, NA, NA, NA, NA),
1165 PINGROUP(122, NA, NA, NA, NA, NA, NA, NA),
1166 PINGROUP(123, hdmi_dtest, NA, NA, NA, NA, NA, NA),
1167 PINGROUP(124, spdif_tx, ldo_en, NA, NA, NA, NA, NA),
1168 PINGROUP(125, ldo_update, hdmi_rcv, NA, NA, NA, NA, NA),
1169 PINGROUP(126, gcc_vtt, NA, NA, NA, NA, NA, NA),
1170 PINGROUP(127, gcc_obt, NA, NA, NA, NA, NA, NA),
1171 PINGROUP(128, blsp_spi10_cs3, NA, NA, NA, NA, NA, NA),
1172 PINGROUP(129, sata_act, NA, NA, NA, NA, NA, NA),
1173 PINGROUP(130, uim, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA),
1174 PINGROUP(131, uim, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA),
1175 PINGROUP(132, uim, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA),
1176 PINGROUP(133, uim, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA),
1177 PINGROUP(134, hsic, NA, NA, NA, NA, NA, NA),
1178 PINGROUP(135, hsic, NA, NA, NA, NA, NA, NA),
1179 PINGROUP(136, spdif_tx, NA, NA, NA, NA, NA, NA),
1180 PINGROUP(137, NA, NA, NA, NA, NA, NA, NA),
1181 PINGROUP(138, NA, NA, NA, NA, NA, NA, NA),
1182 PINGROUP(139, NA, NA, NA, NA, NA, NA, NA),
1183 PINGROUP(140, pci_e1_rst_n, pci_e1_rst, NA, NA, NA, NA, NA),
1184 PINGROUP(141, pci_e1_clkreq_n, NA, NA, NA, NA, NA, NA),
1185 PINGROUP(142, spdif_tx, NA, NA, NA, NA, NA, NA),
1186 PINGROUP(143, NA, NA, NA, NA, NA, NA, NA),
1187 PINGROUP(144, NA, NA, NA, NA, NA, NA, NA),
1188 PINGROUP(145, NA, NA, NA, NA, NA, NA, NA),
1189 PINGROUP(146, sdc_emmc_mode, NA, NA, NA, NA, NA, NA),
1190
1191 SDC_PINGROUP(sdc1_clk, 0x2044, 13, 6),
1192 SDC_PINGROUP(sdc1_cmd, 0x2044, 11, 3),
1193 SDC_PINGROUP(sdc1_data, 0x2044, 9, 0),
1194 SDC_PINGROUP(sdc2_clk, 0x2048, 14, 6),
1195 SDC_PINGROUP(sdc2_cmd, 0x2048, 11, 3),
1196 SDC_PINGROUP(sdc2_data, 0x2048, 9, 0),
1197};
1198
1199#define NUM_GPIO_PINGROUPS 147
1200
1201static const struct msm_pinctrl_soc_data apq8084_pinctrl = {
1202 .pins = apq8084_pins,
1203 .npins = ARRAY_SIZE(apq8084_pins),
1204 .functions = apq8084_functions,
1205 .nfunctions = ARRAY_SIZE(apq8084_functions),
1206 .groups = apq8084_groups,
1207 .ngroups = ARRAY_SIZE(apq8084_groups),
1208 .ngpios = NUM_GPIO_PINGROUPS,
1209};
1210
1211static int apq8084_pinctrl_probe(struct platform_device *pdev)
1212{
1213 return msm_pinctrl_probe(pdev, &apq8084_pinctrl);
1214}
1215
1216static const struct of_device_id apq8084_pinctrl_of_match[] = {
1217 { .compatible = "qcom,apq8084-pinctrl", },
1218 { },
1219};
1220
1221static struct platform_driver apq8084_pinctrl_driver = {
1222 .driver = {
1223 .name = "apq8084-pinctrl",
1224 .owner = THIS_MODULE,
1225 .of_match_table = apq8084_pinctrl_of_match,
1226 },
1227 .probe = apq8084_pinctrl_probe,
1228 .remove = msm_pinctrl_remove,
1229};
1230
1231static int __init apq8084_pinctrl_init(void)
1232{
1233 return platform_driver_register(&apq8084_pinctrl_driver);
1234}
1235arch_initcall(apq8084_pinctrl_init);
1236
1237static void __exit apq8084_pinctrl_exit(void)
1238{
1239 platform_driver_unregister(&apq8084_pinctrl_driver);
1240}
1241module_exit(apq8084_pinctrl_exit);
1242
1243MODULE_DESCRIPTION("Qualcomm APQ8084 pinctrl driver");
1244MODULE_LICENSE("GPL v2");
1245MODULE_DEVICE_TABLE(of, apq8084_pinctrl_of_match);
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8064.c b/drivers/pinctrl/qcom/pinctrl-ipq8064.c
index 767cf1120b20..81f49a9b4dbe 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq8064.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c
@@ -211,6 +211,7 @@ static const unsigned int sdc3_data_pins[] = { 71 };
211 .intr_status_bit = 0, \ 211 .intr_status_bit = 0, \
212 .intr_ack_high = 1, \ 212 .intr_ack_high = 1, \
213 .intr_target_bit = 0, \ 213 .intr_target_bit = 0, \
214 .intr_target_kpss_val = 4, \
214 .intr_raw_status_bit = 3, \ 215 .intr_raw_status_bit = 3, \
215 .intr_polarity_bit = 1, \ 216 .intr_polarity_bit = 1, \
216 .intr_detection_bit = 2, \ 217 .intr_detection_bit = 2, \
@@ -236,6 +237,7 @@ static const unsigned int sdc3_data_pins[] = { 71 };
236 .intr_enable_bit = -1, \ 237 .intr_enable_bit = -1, \
237 .intr_status_bit = -1, \ 238 .intr_status_bit = -1, \
238 .intr_target_bit = -1, \ 239 .intr_target_bit = -1, \
240 .intr_target_kpss_val = -1, \
239 .intr_raw_status_bit = -1, \ 241 .intr_raw_status_bit = -1, \
240 .intr_polarity_bit = -1, \ 242 .intr_polarity_bit = -1, \
241 .intr_detection_bit = -1, \ 243 .intr_detection_bit = -1, \
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 2738108caff2..d30dddd21323 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -12,6 +12,7 @@
12 * GNU General Public License for more details. 12 * GNU General Public License for more details.
13 */ 13 */
14 14
15#include <linux/delay.h>
15#include <linux/err.h> 16#include <linux/err.h>
16#include <linux/io.h> 17#include <linux/io.h>
17#include <linux/module.h> 18#include <linux/module.h>
@@ -26,6 +27,7 @@
26#include <linux/gpio.h> 27#include <linux/gpio.h>
27#include <linux/interrupt.h> 28#include <linux/interrupt.h>
28#include <linux/spinlock.h> 29#include <linux/spinlock.h>
30#include <linux/reboot.h>
29 31
30#include "../core.h" 32#include "../core.h"
31#include "../pinconf.h" 33#include "../pinconf.h"
@@ -33,12 +35,14 @@
33#include "../pinctrl-utils.h" 35#include "../pinctrl-utils.h"
34 36
35#define MAX_NR_GPIO 300 37#define MAX_NR_GPIO 300
38#define PS_HOLD_OFFSET 0x820
36 39
37/** 40/**
38 * struct msm_pinctrl - state for a pinctrl-msm device 41 * struct msm_pinctrl - state for a pinctrl-msm device
39 * @dev: device handle. 42 * @dev: device handle.
40 * @pctrl: pinctrl handle. 43 * @pctrl: pinctrl handle.
41 * @chip: gpiochip handle. 44 * @chip: gpiochip handle.
45 * @restart_nb: restart notifier block.
42 * @irq: parent irq for the TLMM irq_chip. 46 * @irq: parent irq for the TLMM irq_chip.
43 * @lock: Spinlock to protect register resources as well 47 * @lock: Spinlock to protect register resources as well
44 * as msm_pinctrl data structures. 48 * as msm_pinctrl data structures.
@@ -52,6 +56,7 @@ struct msm_pinctrl {
52 struct device *dev; 56 struct device *dev;
53 struct pinctrl_dev *pctrl; 57 struct pinctrl_dev *pctrl;
54 struct gpio_chip chip; 58 struct gpio_chip chip;
59 struct notifier_block restart_nb;
55 int irq; 60 int irq;
56 61
57 spinlock_t lock; 62 spinlock_t lock;
@@ -130,9 +135,9 @@ static int msm_get_function_groups(struct pinctrl_dev *pctldev,
130 return 0; 135 return 0;
131} 136}
132 137
133static int msm_pinmux_enable(struct pinctrl_dev *pctldev, 138static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
134 unsigned function, 139 unsigned function,
135 unsigned group) 140 unsigned group)
136{ 141{
137 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 142 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
138 const struct msm_pingroup *g; 143 const struct msm_pingroup *g;
@@ -166,7 +171,7 @@ static const struct pinmux_ops msm_pinmux_ops = {
166 .get_functions_count = msm_get_functions_count, 171 .get_functions_count = msm_get_functions_count,
167 .get_function_name = msm_get_function_name, 172 .get_function_name = msm_get_function_name,
168 .get_function_groups = msm_get_function_groups, 173 .get_function_groups = msm_get_function_groups,
169 .enable = msm_pinmux_enable, 174 .set_mux = msm_pinmux_set_mux,
170}; 175};
171 176
172static int msm_config_reg(struct msm_pinctrl *pctrl, 177static int msm_config_reg(struct msm_pinctrl *pctrl,
@@ -649,8 +654,6 @@ static void msm_gpio_irq_ack(struct irq_data *d)
649 spin_unlock_irqrestore(&pctrl->lock, flags); 654 spin_unlock_irqrestore(&pctrl->lock, flags);
650} 655}
651 656
652#define INTR_TARGET_PROC_APPS 4
653
654static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) 657static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
655{ 658{
656 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 659 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
@@ -674,7 +677,7 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
674 /* Route interrupts to application cpu */ 677 /* Route interrupts to application cpu */
675 val = readl(pctrl->regs + g->intr_target_reg); 678 val = readl(pctrl->regs + g->intr_target_reg);
676 val &= ~(7 << g->intr_target_bit); 679 val &= ~(7 << g->intr_target_bit);
677 val |= INTR_TARGET_PROC_APPS << g->intr_target_bit; 680 val |= g->intr_target_kpss_val << g->intr_target_bit;
678 writel(val, pctrl->regs + g->intr_target_reg); 681 writel(val, pctrl->regs + g->intr_target_reg);
679 682
680 /* Update configuration for gpio. 683 /* Update configuration for gpio.
@@ -829,6 +832,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
829 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio); 832 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio);
830 if (ret) { 833 if (ret) {
831 dev_err(pctrl->dev, "Failed to add pin range\n"); 834 dev_err(pctrl->dev, "Failed to add pin range\n");
835 gpiochip_remove(&pctrl->chip);
832 return ret; 836 return ret;
833 } 837 }
834 838
@@ -839,6 +843,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
839 IRQ_TYPE_NONE); 843 IRQ_TYPE_NONE);
840 if (ret) { 844 if (ret) {
841 dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n"); 845 dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n");
846 gpiochip_remove(&pctrl->chip);
842 return -ENOSYS; 847 return -ENOSYS;
843 } 848 }
844 849
@@ -848,6 +853,32 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
848 return 0; 853 return 0;
849} 854}
850 855
856static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action,
857 void *data)
858{
859 struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb);
860
861 writel(0, pctrl->regs + PS_HOLD_OFFSET);
862 mdelay(1000);
863 return NOTIFY_DONE;
864}
865
866static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
867{
868 int i = 0;
869 const struct msm_function *func = pctrl->soc->functions;
870
871 for (; i <= pctrl->soc->nfunctions; i++)
872 if (!strcmp(func[i].name, "ps_hold")) {
873 pctrl->restart_nb.notifier_call = msm_ps_hold_restart;
874 pctrl->restart_nb.priority = 128;
875 if (register_restart_handler(&pctrl->restart_nb))
876 dev_err(pctrl->dev,
877 "failed to setup restart handler.\n");
878 break;
879 }
880}
881
851int msm_pinctrl_probe(struct platform_device *pdev, 882int msm_pinctrl_probe(struct platform_device *pdev,
852 const struct msm_pinctrl_soc_data *soc_data) 883 const struct msm_pinctrl_soc_data *soc_data)
853{ 884{
@@ -871,6 +902,8 @@ int msm_pinctrl_probe(struct platform_device *pdev,
871 if (IS_ERR(pctrl->regs)) 902 if (IS_ERR(pctrl->regs))
872 return PTR_ERR(pctrl->regs); 903 return PTR_ERR(pctrl->regs);
873 904
905 msm_pinctrl_setup_pm_reset(pctrl);
906
874 pctrl->irq = platform_get_irq(pdev, 0); 907 pctrl->irq = platform_get_irq(pdev, 0);
875 if (pctrl->irq < 0) { 908 if (pctrl->irq < 0) {
876 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n"); 909 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n");
@@ -913,6 +946,8 @@ int msm_pinctrl_remove(struct platform_device *pdev)
913 946
914 pinctrl_unregister(pctrl->pctrl); 947 pinctrl_unregister(pctrl->pctrl);
915 948
949 unregister_restart_handler(&pctrl->restart_nb);
950
916 return 0; 951 return 0;
917} 952}
918EXPORT_SYMBOL(msm_pinctrl_remove); 953EXPORT_SYMBOL(msm_pinctrl_remove);
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h
index 7b2a227a590a..b952c4b4a8e9 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.h
+++ b/drivers/pinctrl/qcom/pinctrl-msm.h
@@ -53,6 +53,8 @@ struct msm_function {
53 * @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt 53 * @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt
54 * status. 54 * status.
55 * @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing. 55 * @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing.
56 * @intr_target_kpss_val: Value in @intr_target_bit for specifying that the interrupt from
57 * this gpio should get routed to the KPSS processor.
56 * @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit. 58 * @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit.
57 * @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt. 59 * @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt.
58 * @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type. 60 * @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type.
@@ -88,6 +90,7 @@ struct msm_pingroup {
88 unsigned intr_ack_high:1; 90 unsigned intr_ack_high:1;
89 91
90 unsigned intr_target_bit:5; 92 unsigned intr_target_bit:5;
93 unsigned intr_target_kpss_val:5;
91 unsigned intr_raw_status_bit:5; 94 unsigned intr_raw_status_bit:5;
92 unsigned intr_polarity_bit:5; 95 unsigned intr_polarity_bit:5;
93 unsigned intr_detection_bit:5; 96 unsigned intr_detection_bit:5;
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8960.c b/drivers/pinctrl/qcom/pinctrl-msm8960.c
index 35047036a053..2ab21ce5575a 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm8960.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm8960.c
@@ -384,6 +384,7 @@ static const unsigned int sdc3_data_pins[] = { 157 };
384 .intr_status_bit = 0, \ 384 .intr_status_bit = 0, \
385 .intr_ack_high = 1, \ 385 .intr_ack_high = 1, \
386 .intr_target_bit = 0, \ 386 .intr_target_bit = 0, \
387 .intr_target_kpss_val = 4, \
387 .intr_raw_status_bit = 3, \ 388 .intr_raw_status_bit = 3, \
388 .intr_polarity_bit = 1, \ 389 .intr_polarity_bit = 1, \
389 .intr_detection_bit = 2, \ 390 .intr_detection_bit = 2, \
@@ -409,6 +410,7 @@ static const unsigned int sdc3_data_pins[] = { 157 };
409 .intr_enable_bit = -1, \ 410 .intr_enable_bit = -1, \
410 .intr_status_bit = -1, \ 411 .intr_status_bit = -1, \
411 .intr_target_bit = -1, \ 412 .intr_target_bit = -1, \
413 .intr_target_kpss_val = -1, \
412 .intr_raw_status_bit = -1, \ 414 .intr_raw_status_bit = -1, \
413 .intr_polarity_bit = -1, \ 415 .intr_polarity_bit = -1, \
414 .intr_detection_bit = -1, \ 416 .intr_detection_bit = -1, \
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8x74.c b/drivers/pinctrl/qcom/pinctrl-msm8x74.c
index 8c9720154d1e..3c858384d041 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm8x74.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm8x74.c
@@ -366,6 +366,7 @@ static const unsigned int sdc2_data_pins[] = { 151 };
366 .intr_enable_bit = 0, \ 366 .intr_enable_bit = 0, \
367 .intr_status_bit = 0, \ 367 .intr_status_bit = 0, \
368 .intr_target_bit = 5, \ 368 .intr_target_bit = 5, \
369 .intr_target_kpss_val = 4, \
369 .intr_raw_status_bit = 4, \ 370 .intr_raw_status_bit = 4, \
370 .intr_polarity_bit = 1, \ 371 .intr_polarity_bit = 1, \
371 .intr_detection_bit = 2, \ 372 .intr_detection_bit = 2, \
@@ -391,6 +392,7 @@ static const unsigned int sdc2_data_pins[] = { 151 };
391 .intr_enable_bit = -1, \ 392 .intr_enable_bit = -1, \
392 .intr_status_bit = -1, \ 393 .intr_status_bit = -1, \
393 .intr_target_bit = -1, \ 394 .intr_target_bit = -1, \
395 .intr_target_kpss_val = -1, \
394 .intr_raw_status_bit = -1, \ 396 .intr_raw_status_bit = -1, \
395 .intr_polarity_bit = -1, \ 397 .intr_polarity_bit = -1, \
396 .intr_detection_bit = -1, \ 398 .intr_detection_bit = -1, \
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos5440.c b/drivers/pinctrl/samsung/pinctrl-exynos5440.c
index 603da2f9dd95..b995ec2c5d16 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos5440.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos5440.c
@@ -364,8 +364,9 @@ static void exynos5440_pinmux_setup(struct pinctrl_dev *pctldev, unsigned select
364} 364}
365 365
366/* enable a specified pinmux by writing to registers */ 366/* enable a specified pinmux by writing to registers */
367static int exynos5440_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector, 367static int exynos5440_pinmux_set_mux(struct pinctrl_dev *pctldev,
368 unsigned group) 368 unsigned selector,
369 unsigned group)
369{ 370{
370 exynos5440_pinmux_setup(pctldev, selector, group, true); 371 exynos5440_pinmux_setup(pctldev, selector, group, true);
371 return 0; 372 return 0;
@@ -387,7 +388,7 @@ static const struct pinmux_ops exynos5440_pinmux_ops = {
387 .get_functions_count = exynos5440_get_functions_count, 388 .get_functions_count = exynos5440_get_functions_count,
388 .get_function_name = exynos5440_pinmux_get_fname, 389 .get_function_name = exynos5440_pinmux_get_fname,
389 .get_function_groups = exynos5440_pinmux_get_groups, 390 .get_function_groups = exynos5440_pinmux_get_groups,
390 .enable = exynos5440_pinmux_enable, 391 .set_mux = exynos5440_pinmux_set_mux,
391 .gpio_set_direction = exynos5440_pinmux_gpio_set_direction, 392 .gpio_set_direction = exynos5440_pinmux_gpio_set_direction,
392}; 393};
393 394
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index b07406da333c..4a47691c32b1 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -401,8 +401,9 @@ static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
401} 401}
402 402
403/* enable a specified pinmux by writing to registers */ 403/* enable a specified pinmux by writing to registers */
404static int samsung_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector, 404static int samsung_pinmux_set_mux(struct pinctrl_dev *pctldev,
405 unsigned group) 405 unsigned selector,
406 unsigned group)
406{ 407{
407 samsung_pinmux_setup(pctldev, selector, group, true); 408 samsung_pinmux_setup(pctldev, selector, group, true);
408 return 0; 409 return 0;
@@ -413,7 +414,7 @@ static const struct pinmux_ops samsung_pinmux_ops = {
413 .get_functions_count = samsung_get_functions_count, 414 .get_functions_count = samsung_get_functions_count,
414 .get_function_name = samsung_pinmux_get_fname, 415 .get_function_name = samsung_pinmux_get_fname,
415 .get_function_groups = samsung_pinmux_get_groups, 416 .get_function_groups = samsung_pinmux_get_groups,
416 .enable = samsung_pinmux_enable, 417 .set_mux = samsung_pinmux_set_mux,
417}; 418};
418 419
419/* set or get the pin config settings for a specified pin */ 420/* set or get the pin config settings for a specified pin */
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index b9b464d0578c..6572c233f73d 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -542,7 +542,7 @@ static int sh_pfc_probe(struct platform_device *pdev)
542 */ 542 */
543 ret = sh_pfc_register_pinctrl(pfc); 543 ret = sh_pfc_register_pinctrl(pfc);
544 if (unlikely(ret != 0)) 544 if (unlikely(ret != 0))
545 goto error; 545 return ret;
546 546
547#ifdef CONFIG_GPIO_SH_PFC 547#ifdef CONFIG_GPIO_SH_PFC
548 /* 548 /*
@@ -564,11 +564,6 @@ static int sh_pfc_probe(struct platform_device *pdev)
564 dev_info(pfc->dev, "%s support registered\n", info->name); 564 dev_info(pfc->dev, "%s support registered\n", info->name);
565 565
566 return 0; 566 return 0;
567
568error:
569 if (info->ops && info->ops->exit)
570 info->ops->exit(pfc);
571 return ret;
572} 567}
573 568
574static int sh_pfc_remove(struct platform_device *pdev) 569static int sh_pfc_remove(struct platform_device *pdev)
@@ -580,9 +575,6 @@ static int sh_pfc_remove(struct platform_device *pdev)
580#endif 575#endif
581 sh_pfc_unregister_pinctrl(pfc); 576 sh_pfc_unregister_pinctrl(pfc);
582 577
583 if (pfc->info->ops && pfc->info->ops->exit)
584 pfc->info->ops->exit(pfc);
585
586 return 0; 578 return 0;
587} 579}
588 580
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index b7b0e6ccf305..3daaa5241c47 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -33,7 +33,6 @@ struct sh_pfc_pin_range {
33struct sh_pfc { 33struct sh_pfc {
34 struct device *dev; 34 struct device *dev;
35 const struct sh_pfc_soc_info *info; 35 const struct sh_pfc_soc_info *info;
36 void *soc_data;
37 spinlock_t lock; 36 spinlock_t lock;
38 37
39 unsigned int num_windows; 38 unsigned int num_windows;
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index ce9fb7aa8ba3..280a56f97786 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -2717,14 +2717,14 @@ static void r8a73a4_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
2717 iowrite8(value, addr); 2717 iowrite8(value, addr);
2718} 2718}
2719 2719
2720static const struct sh_pfc_soc_operations r8a73a4_pinmux_ops = { 2720static const struct sh_pfc_soc_operations r8a73a4_pfc_ops = {
2721 .get_bias = r8a73a4_pinmux_get_bias, 2721 .get_bias = r8a73a4_pinmux_get_bias,
2722 .set_bias = r8a73a4_pinmux_set_bias, 2722 .set_bias = r8a73a4_pinmux_set_bias,
2723}; 2723};
2724 2724
2725const struct sh_pfc_soc_info r8a73a4_pinmux_info = { 2725const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
2726 .name = "r8a73a4_pfc", 2726 .name = "r8a73a4_pfc",
2727 .ops = &r8a73a4_pinmux_ops, 2727 .ops = &r8a73a4_pfc_ops,
2728 2728
2729 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 2729 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2730 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 2730 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index e4c1ef477053..b486e9d20cc2 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -3752,14 +3752,14 @@ static void r8a7740_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3752 iowrite8(value, addr); 3752 iowrite8(value, addr);
3753} 3753}
3754 3754
3755static const struct sh_pfc_soc_operations r8a7740_pinmux_ops = { 3755static const struct sh_pfc_soc_operations r8a7740_pfc_ops = {
3756 .get_bias = r8a7740_pinmux_get_bias, 3756 .get_bias = r8a7740_pinmux_get_bias,
3757 .set_bias = r8a7740_pinmux_set_bias, 3757 .set_bias = r8a7740_pinmux_set_bias,
3758}; 3758};
3759 3759
3760const struct sh_pfc_soc_info r8a7740_pinmux_info = { 3760const struct sh_pfc_soc_info r8a7740_pinmux_info = {
3761 .name = "r8a7740_pfc", 3761 .name = "r8a7740_pfc",
3762 .ops = &r8a7740_pinmux_ops, 3762 .ops = &r8a7740_pfc_ops,
3763 3763
3764 .input = { PINMUX_INPUT_BEGIN, 3764 .input = { PINMUX_INPUT_BEGIN,
3765 PINMUX_INPUT_END }, 3765 PINMUX_INPUT_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index d9158b3b2919..8211f66a2f68 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -2614,14 +2614,14 @@ static void sh7372_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
2614 iowrite8(value, addr); 2614 iowrite8(value, addr);
2615} 2615}
2616 2616
2617static const struct sh_pfc_soc_operations sh7372_pinmux_ops = { 2617static const struct sh_pfc_soc_operations sh7372_pfc_ops = {
2618 .get_bias = sh7372_pinmux_get_bias, 2618 .get_bias = sh7372_pinmux_get_bias,
2619 .set_bias = sh7372_pinmux_set_bias, 2619 .set_bias = sh7372_pinmux_set_bias,
2620}; 2620};
2621 2621
2622const struct sh_pfc_soc_info sh7372_pinmux_info = { 2622const struct sh_pfc_soc_info sh7372_pinmux_info = {
2623 .name = "sh7372_pfc", 2623 .name = "sh7372_pfc",
2624 .ops = &sh7372_pinmux_ops, 2624 .ops = &sh7372_pfc_ops,
2625 2625
2626 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 2626 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2627 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 2627 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 0bd8f4401b42..d2efbfb776ac 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -3824,39 +3824,28 @@ static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3824 * SoC information 3824 * SoC information
3825 */ 3825 */
3826 3826
3827struct sh73a0_pinmux_data {
3828 struct regulator_dev *vccq_mc0;
3829};
3830
3831static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc) 3827static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc)
3832{ 3828{
3833 struct sh73a0_pinmux_data *data;
3834 struct regulator_config cfg = { }; 3829 struct regulator_config cfg = { };
3830 struct regulator_dev *vccq;
3835 int ret; 3831 int ret;
3836 3832
3837 data = devm_kzalloc(pfc->dev, sizeof(*data), GFP_KERNEL);
3838 if (data == NULL)
3839 return -ENOMEM;
3840
3841 cfg.dev = pfc->dev; 3833 cfg.dev = pfc->dev;
3842 cfg.init_data = &sh73a0_vccq_mc0_init_data; 3834 cfg.init_data = &sh73a0_vccq_mc0_init_data;
3843 cfg.driver_data = pfc; 3835 cfg.driver_data = pfc;
3844 3836
3845 data->vccq_mc0 = devm_regulator_register(pfc->dev, 3837 vccq = devm_regulator_register(pfc->dev, &sh73a0_vccq_mc0_desc, &cfg);
3846 &sh73a0_vccq_mc0_desc, &cfg); 3838 if (IS_ERR(vccq)) {
3847 if (IS_ERR(data->vccq_mc0)) { 3839 ret = PTR_ERR(vccq);
3848 ret = PTR_ERR(data->vccq_mc0);
3849 dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n", 3840 dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n",
3850 ret); 3841 ret);
3851 return ret; 3842 return ret;
3852 } 3843 }
3853 3844
3854 pfc->soc_data = data;
3855
3856 return 0; 3845 return 0;
3857} 3846}
3858 3847
3859static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = { 3848static const struct sh_pfc_soc_operations sh73a0_pfc_ops = {
3860 .init = sh73a0_pinmux_soc_init, 3849 .init = sh73a0_pinmux_soc_init,
3861 .get_bias = sh73a0_pinmux_get_bias, 3850 .get_bias = sh73a0_pinmux_get_bias,
3862 .set_bias = sh73a0_pinmux_set_bias, 3851 .set_bias = sh73a0_pinmux_set_bias,
@@ -3864,7 +3853,7 @@ static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = {
3864 3853
3865const struct sh_pfc_soc_info sh73a0_pinmux_info = { 3854const struct sh_pfc_soc_info sh73a0_pinmux_info = {
3866 .name = "sh73a0_pfc", 3855 .name = "sh73a0_pfc",
3867 .ops = &sh73a0_pinmux_ops, 3856 .ops = &sh73a0_pfc_ops,
3868 3857
3869 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 3858 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
3870 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 3859 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index 11db3ee39d40..910deaefa0ac 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -312,8 +312,8 @@ static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev,
312 return 0; 312 return 0;
313} 313}
314 314
315static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector, 315static int sh_pfc_func_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
316 unsigned group) 316 unsigned group)
317{ 317{
318 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 318 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
319 struct sh_pfc *pfc = pmx->pfc; 319 struct sh_pfc *pfc = pmx->pfc;
@@ -442,7 +442,7 @@ static const struct pinmux_ops sh_pfc_pinmux_ops = {
442 .get_functions_count = sh_pfc_get_functions_count, 442 .get_functions_count = sh_pfc_get_functions_count,
443 .get_function_name = sh_pfc_get_function_name, 443 .get_function_name = sh_pfc_get_function_name,
444 .get_function_groups = sh_pfc_get_function_groups, 444 .get_function_groups = sh_pfc_get_function_groups,
445 .enable = sh_pfc_func_enable, 445 .set_mux = sh_pfc_func_set_mux,
446 .gpio_request_enable = sh_pfc_gpio_request_enable, 446 .gpio_request_enable = sh_pfc_gpio_request_enable,
447 .gpio_disable_free = sh_pfc_gpio_disable_free, 447 .gpio_disable_free = sh_pfc_gpio_disable_free,
448 .gpio_set_direction = sh_pfc_gpio_set_direction, 448 .gpio_set_direction = sh_pfc_gpio_set_direction,
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index d482c40b012a..5b7283182c1e 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -116,7 +116,6 @@ struct sh_pfc;
116 116
117struct sh_pfc_soc_operations { 117struct sh_pfc_soc_operations {
118 int (*init)(struct sh_pfc *pfc); 118 int (*init)(struct sh_pfc *pfc);
119 void (*exit)(struct sh_pfc *pfc);
120 unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin); 119 unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
121 void (*set_bias)(struct sh_pfc *pfc, unsigned int pin, 120 void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
122 unsigned int bias); 121 unsigned int bias);
diff --git a/drivers/pinctrl/sirf/pinctrl-atlas6.c b/drivers/pinctrl/sirf/pinctrl-atlas6.c
index c4dd3d5cf9c3..45f8391ddb34 100644
--- a/drivers/pinctrl/sirf/pinctrl-atlas6.c
+++ b/drivers/pinctrl/sirf/pinctrl-atlas6.c
@@ -134,8 +134,9 @@ static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
134 .mask = BIT(30) | BIT(31), 134 .mask = BIT(30) | BIT(31),
135 }, { 135 }, {
136 .group = 2, 136 .group = 2,
137 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | 137 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
138 BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | 138 BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) |
139 BIT(16) | BIT(17) | BIT(18) | BIT(19) |
139 BIT(20) | BIT(21) | BIT(22) | BIT(31), 140 BIT(20) | BIT(21) | BIT(22) | BIT(31),
140 }, 141 },
141}; 142};
@@ -148,14 +149,15 @@ static const struct sirfsoc_padmux lcd_16bits_padmux = {
148 .funcval = 0, 149 .funcval = 0,
149}; 150};
150 151
151static const unsigned lcd_16bits_pins[] = { 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, 152static const unsigned lcd_16bits_pins[] = { 62, 63, 65, 70, 71, 72, 73, 74, 75,
152 84, 85, 86, 95 }; 153 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95 };
153 154
154static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = { 155static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
155 { 156 {
156 .group = 2, 157 .group = 2,
157 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | 158 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
158 BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | 159 BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) |
160 BIT(16) | BIT(17) | BIT(18) | BIT(19) |
159 BIT(20) | BIT(21) | BIT(22) | BIT(31), 161 BIT(20) | BIT(21) | BIT(22) | BIT(31),
160 }, { 162 }, {
161 .group = 1, 163 .group = 1,
@@ -174,21 +176,23 @@ static const struct sirfsoc_padmux lcd_18bits_padmux = {
174 .funcval = 0, 176 .funcval = 0,
175}; 177};
176 178
177static const unsigned lcd_18bits_pins[] = { 16, 17, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, 179static const unsigned lcd_18bits_pins[] = { 16, 17, 62, 63, 65, 70, 71, 72, 73,
178 84, 85, 86, 95 }; 180 74, 75, 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95 };
179 181
180static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = { 182static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
181 { 183 {
182 .group = 2, 184 .group = 2,
183 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | 185 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
184 BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | 186 BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) |
187 BIT(16) | BIT(17) | BIT(18) | BIT(19) |
185 BIT(20) | BIT(21) | BIT(22) | BIT(31), 188 BIT(20) | BIT(21) | BIT(22) | BIT(31),
186 }, { 189 }, {
187 .group = 1, 190 .group = 1,
188 .mask = BIT(30) | BIT(31), 191 .mask = BIT(30) | BIT(31),
189 }, { 192 }, {
190 .group = 0, 193 .group = 0,
191 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23), 194 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) |
195 BIT(21) | BIT(22) | BIT(23),
192 }, 196 },
193}; 197};
194 198
@@ -200,14 +204,16 @@ static const struct sirfsoc_padmux lcd_24bits_padmux = {
200 .funcval = 0, 204 .funcval = 0,
201}; 205};
202 206
203static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 207static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 62,
204 80, 81, 82, 83, 84, 85, 86, 95}; 208 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, 84,
209 85, 86, 95};
205 210
206static const struct sirfsoc_muxmask lcdrom_muxmask[] = { 211static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
207 { 212 {
208 .group = 2, 213 .group = 2,
209 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | 214 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) |
210 BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | 215 BIT(11) | BIT(12) | BIT(13) | BIT(15) | BIT(16) |
216 BIT(17) | BIT(18) | BIT(19) |
211 BIT(20) | BIT(21) | BIT(22) | BIT(31), 217 BIT(20) | BIT(21) | BIT(22) | BIT(31),
212 }, { 218 }, {
213 .group = 1, 219 .group = 1,
@@ -226,8 +232,8 @@ static const struct sirfsoc_padmux lcdrom_padmux = {
226 .funcval = BIT(4), 232 .funcval = BIT(4),
227}; 233};
228 234
229static const unsigned lcdrom_pins[] = { 8, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, 235static const unsigned lcdrom_pins[] = { 8, 62, 63, 65, 70, 71, 72, 73, 74, 75,
230 84, 85, 86, 95}; 236 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95};
231 237
232static const struct sirfsoc_muxmask uart0_muxmask[] = { 238static const struct sirfsoc_muxmask uart0_muxmask[] = {
233 { 239 {
@@ -371,11 +377,42 @@ static const struct sirfsoc_padmux cko1_padmux = {
371 377
372static const unsigned cko1_pins[] = { 42 }; 378static const unsigned cko1_pins[] = { 42 };
373 379
374static const struct sirfsoc_muxmask i2s_muxmask[] = { 380static const struct sirfsoc_muxmask i2s_mclk_muxmask[] = {
375 { 381 {
376 .group = 1, 382 .group = 1,
377 .mask = BIT(10), 383 .mask = BIT(10),
378 }, { 384 },
385};
386
387static const struct sirfsoc_padmux i2s_mclk_padmux = {
388 .muxmask_counts = ARRAY_SIZE(i2s_mclk_muxmask),
389 .muxmask = i2s_mclk_muxmask,
390 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
391 .funcmask = BIT(3),
392 .funcval = BIT(3),
393};
394
395static const unsigned i2s_mclk_pins[] = { 42 };
396
397static const struct sirfsoc_muxmask i2s_ext_clk_input_muxmask[] = {
398 {
399 .group = 1,
400 .mask = BIT(19),
401 },
402};
403
404static const struct sirfsoc_padmux i2s_ext_clk_input_padmux = {
405 .muxmask_counts = ARRAY_SIZE(i2s_ext_clk_input_muxmask),
406 .muxmask = i2s_ext_clk_input_muxmask,
407 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
408 .funcmask = BIT(2),
409 .funcval = BIT(2),
410};
411
412static const unsigned i2s_ext_clk_input_pins[] = { 51 };
413
414static const struct sirfsoc_muxmask i2s_muxmask[] = {
415 {
379 .group = 3, 416 .group = 3,
380 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5), 417 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
381 }, 418 },
@@ -385,17 +422,12 @@ static const struct sirfsoc_padmux i2s_padmux = {
385 .muxmask_counts = ARRAY_SIZE(i2s_muxmask), 422 .muxmask_counts = ARRAY_SIZE(i2s_muxmask),
386 .muxmask = i2s_muxmask, 423 .muxmask = i2s_muxmask,
387 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 424 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
388 .funcmask = BIT(3),
389 .funcval = BIT(3),
390}; 425};
391 426
392static const unsigned i2s_pins[] = { 42, 98, 99, 100, 101 }; 427static const unsigned i2s_pins[] = { 98, 99, 100, 101 };
393 428
394static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = { 429static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = {
395 { 430 {
396 .group = 1,
397 .mask = BIT(10),
398 }, {
399 .group = 3, 431 .group = 3,
400 .mask = BIT(2) | BIT(3) | BIT(4), 432 .mask = BIT(2) | BIT(3) | BIT(4),
401 }, 433 },
@@ -405,17 +437,12 @@ static const struct sirfsoc_padmux i2s_no_din_padmux = {
405 .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask), 437 .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
406 .muxmask = i2s_no_din_muxmask, 438 .muxmask = i2s_no_din_muxmask,
407 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 439 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
408 .funcmask = BIT(3),
409 .funcval = BIT(3),
410}; 440};
411 441
412static const unsigned i2s_no_din_pins[] = { 42, 98, 99, 100 }; 442static const unsigned i2s_no_din_pins[] = { 98, 99, 100 };
413 443
414static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = { 444static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = {
415 { 445 {
416 .group = 1,
417 .mask = BIT(10) | BIT(20) | BIT(23),
418 }, {
419 .group = 3, 446 .group = 3,
420 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5), 447 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
421 }, 448 },
@@ -425,11 +452,11 @@ static const struct sirfsoc_padmux i2s_6chn_padmux = {
425 .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask), 452 .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
426 .muxmask = i2s_6chn_muxmask, 453 .muxmask = i2s_6chn_muxmask,
427 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 454 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
428 .funcmask = BIT(1) | BIT(3) | BIT(9), 455 .funcmask = BIT(1) | BIT(9),
429 .funcval = BIT(1) | BIT(3) | BIT(9), 456 .funcval = BIT(1) | BIT(9),
430}; 457};
431 458
432static const unsigned i2s_6chn_pins[] = { 42, 52, 55, 98, 99, 100, 101 }; 459static const unsigned i2s_6chn_pins[] = { 52, 55, 98, 99, 100, 101 };
433 460
434static const struct sirfsoc_muxmask ac97_muxmask[] = { 461static const struct sirfsoc_muxmask ac97_muxmask[] = {
435 { 462 {
@@ -716,7 +743,8 @@ static const struct sirfsoc_padmux vip_padmux = {
716 .funcval = BIT(18), 743 .funcval = BIT(18),
717}; 744};
718 745
719static const unsigned vip_pins[] = { 36, 37, 38, 40, 41, 56, 57, 58, 59, 60, 61 }; 746static const unsigned vip_pins[] = { 36, 37, 38, 40, 41, 56, 57, 58, 59,
747 60, 61 };
720 748
721static const struct sirfsoc_muxmask vip_noupli_muxmask[] = { 749static const struct sirfsoc_muxmask vip_noupli_muxmask[] = {
722 { 750 {
@@ -737,7 +765,8 @@ static const struct sirfsoc_padmux vip_noupli_padmux = {
737 .funcval = BIT(15), 765 .funcval = BIT(15),
738}; 766};
739 767
740static const unsigned vip_noupli_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 87, 88, 89 }; 768static const unsigned vip_noupli_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23,
769 87, 88, 89 };
741 770
742static const struct sirfsoc_muxmask i2c0_muxmask[] = { 771static const struct sirfsoc_muxmask i2c0_muxmask[] = {
743 { 772 {
@@ -876,7 +905,8 @@ static const struct sirfsoc_padmux usb0_upli_drvbus_padmux = {
876 .funcval = 0, 905 .funcval = 0,
877}; 906};
878 907
879static const unsigned usb0_upli_drvbus_pins[] = { 36, 37, 38, 39, 40, 41, 56, 57, 58, 59, 60, 61 }; 908static const unsigned usb0_upli_drvbus_pins[] = { 36, 37, 38, 39, 40,
909 41, 56, 57, 58, 59, 60, 61 };
880 910
881static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = { 911static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
882 { 912 {
@@ -968,6 +998,8 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
968 SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins), 998 SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
969 SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins), 999 SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
970 SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins), 1000 SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
1001 SIRFSOC_PIN_GROUP("i2smclkgrp", i2s_mclk_pins),
1002 SIRFSOC_PIN_GROUP("i2s_ext_clk_inputgrp", i2s_ext_clk_input_pins),
971 SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins), 1003 SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
972 SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins), 1004 SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
973 SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins), 1005 SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins),
@@ -1017,8 +1049,11 @@ static const char * const sdmmc2_nowpgrp[] = { "sdmmc2_nowpgrp" };
1017static const char * const usb0_upli_drvbusgrp[] = { "usb0_upli_drvbusgrp" }; 1049static const char * const usb0_upli_drvbusgrp[] = { "usb0_upli_drvbusgrp" };
1018static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" }; 1050static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
1019static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" }; 1051static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
1020static const char * const uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" }; 1052static const char * const
1053 uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
1021static const char * const pulse_countgrp[] = { "pulse_countgrp" }; 1054static const char * const pulse_countgrp[] = { "pulse_countgrp" };
1055static const char * const i2smclkgrp[] = { "i2smclkgrp" };
1056static const char * const i2s_ext_clk_inputgrp[] = { "i2s_ext_clk_inputgrp" };
1022static const char * const i2sgrp[] = { "i2sgrp" }; 1057static const char * const i2sgrp[] = { "i2sgrp" };
1023static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" }; 1058static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
1024static const char * const i2s_6chngrp[] = { "i2s_6chngrp" }; 1059static const char * const i2s_6chngrp[] = { "i2s_6chngrp" };
@@ -1038,7 +1073,8 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
1038 uart0_nostreamctrl_padmux), 1073 uart0_nostreamctrl_padmux),
1039 SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux), 1074 SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
1040 SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux), 1075 SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
1041 SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux), 1076 SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl",
1077 uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
1042 SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux), 1078 SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
1043 SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl", 1079 SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
1044 usp0_uart_nostreamctrl_grp, 1080 usp0_uart_nostreamctrl_grp,
@@ -1068,12 +1104,19 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
1068 SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux), 1104 SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux),
1069 SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux), 1105 SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
1070 SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux), 1106 SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
1071 SIRFSOC_PMX_FUNCTION("sdmmc2_nowp", sdmmc2_nowpgrp, sdmmc2_nowp_padmux), 1107 SIRFSOC_PMX_FUNCTION("sdmmc2_nowp",
1072 SIRFSOC_PMX_FUNCTION("usb0_upli_drvbus", usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux), 1108 sdmmc2_nowpgrp, sdmmc2_nowp_padmux),
1073 SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux), 1109 SIRFSOC_PMX_FUNCTION("usb0_upli_drvbus",
1110 usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux),
1111 SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus",
1112 usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
1074 SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux), 1113 SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
1075 SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", uart1_route_io_usb1grp, uart1_route_io_usb1_padmux), 1114 SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1",
1115 uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
1076 SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux), 1116 SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
1117 SIRFSOC_PMX_FUNCTION("i2s_mclk", i2smclkgrp, i2s_mclk_padmux),
1118 SIRFSOC_PMX_FUNCTION("i2s_ext_clk_input", i2s_ext_clk_inputgrp,
1119 i2s_ext_clk_input_padmux),
1077 SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux), 1120 SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
1078 SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux), 1121 SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
1079 SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux), 1122 SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux),
diff --git a/drivers/pinctrl/sirf/pinctrl-prima2.c b/drivers/pinctrl/sirf/pinctrl-prima2.c
index 8aa76f0776d7..357678ee28e3 100644
--- a/drivers/pinctrl/sirf/pinctrl-prima2.c
+++ b/drivers/pinctrl/sirf/pinctrl-prima2.c
@@ -135,8 +135,9 @@ static const struct pinctrl_pin_desc sirfsoc_pads[] = {
135static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = { 135static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
136 { 136 {
137 .group = 3, 137 .group = 3,
138 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | 138 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
139 BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | 139 BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
140 BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
140 BIT(17) | BIT(18), 141 BIT(17) | BIT(18),
141 }, { 142 }, {
142 .group = 2, 143 .group = 2,
@@ -152,14 +153,15 @@ static const struct sirfsoc_padmux lcd_16bits_padmux = {
152 .funcval = 0, 153 .funcval = 0,
153}; 154};
154 155
155static const unsigned lcd_16bits_pins[] = { 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 156static const unsigned lcd_16bits_pins[] = { 95, 96, 97, 98, 99, 100, 101, 102,
156 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 }; 157 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
157 158
158static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = { 159static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
159 { 160 {
160 .group = 3, 161 .group = 3,
161 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | 162 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
162 BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | 163 BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
164 BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
163 BIT(17) | BIT(18), 165 BIT(17) | BIT(18),
164 }, { 166 }, {
165 .group = 2, 167 .group = 2,
@@ -178,21 +180,23 @@ static const struct sirfsoc_padmux lcd_18bits_padmux = {
178 .funcval = 0, 180 .funcval = 0,
179}; 181};
180 182
181static const unsigned lcd_18bits_pins[] = { 16, 17, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 183static const unsigned lcd_18bits_pins[] = { 16, 17, 95, 96, 97, 98, 99, 100,
182 105, 106, 107, 108, 109, 110, 111, 112, 113, 114}; 184 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114};
183 185
184static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = { 186static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
185 { 187 {
186 .group = 3, 188 .group = 3,
187 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | 189 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
188 BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | 190 BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
191 BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
189 BIT(17) | BIT(18), 192 BIT(17) | BIT(18),
190 }, { 193 }, {
191 .group = 2, 194 .group = 2,
192 .mask = BIT(31), 195 .mask = BIT(31),
193 }, { 196 }, {
194 .group = 0, 197 .group = 0,
195 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23), 198 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) |
199 BIT(21) | BIT(22) | BIT(23),
196 }, 200 },
197}; 201};
198 202
@@ -204,14 +208,16 @@ static const struct sirfsoc_padmux lcd_24bits_padmux = {
204 .funcval = 0, 208 .funcval = 0,
205}; 209};
206 210
207static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 211static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23,
208 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 }; 212 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109,
213 110, 111, 112, 113, 114 };
209 214
210static const struct sirfsoc_muxmask lcdrom_muxmask[] = { 215static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
211 { 216 {
212 .group = 3, 217 .group = 3,
213 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | 218 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
214 BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) | 219 BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
220 BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
215 BIT(17) | BIT(18), 221 BIT(17) | BIT(18),
216 }, { 222 }, {
217 .group = 2, 223 .group = 2,
@@ -230,8 +236,8 @@ static const struct sirfsoc_padmux lcdrom_padmux = {
230 .funcval = BIT(4), 236 .funcval = BIT(4),
231}; 237};
232 238
233static const unsigned lcdrom_pins[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 239static const unsigned lcdrom_pins[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102,
234 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 }; 240 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
235 241
236static const struct sirfsoc_muxmask uart0_muxmask[] = { 242static const struct sirfsoc_muxmask uart0_muxmask[] = {
237 { 243 {
@@ -380,12 +386,44 @@ static const struct sirfsoc_padmux cko1_padmux = {
380 386
381static const unsigned cko1_pins[] = { 42 }; 387static const unsigned cko1_pins[] = { 42 };
382 388
389static const struct sirfsoc_muxmask i2s_mclk_muxmask[] = {
390 {
391 .group = 1,
392 .mask = BIT(10),
393 },
394};
395
396static const struct sirfsoc_padmux i2s_mclk_padmux = {
397 .muxmask_counts = ARRAY_SIZE(i2s_mclk_muxmask),
398 .muxmask = i2s_mclk_muxmask,
399 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
400 .funcmask = BIT(3),
401 .funcval = BIT(3),
402};
403
404static const unsigned i2s_mclk_pins[] = { 42 };
405
406static const struct sirfsoc_muxmask i2s_ext_clk_input_muxmask[] = {
407 {
408 .group = 1,
409 .mask = BIT(19),
410 },
411};
412
413static const struct sirfsoc_padmux i2s_ext_clk_input_padmux = {
414 .muxmask_counts = ARRAY_SIZE(i2s_ext_clk_input_muxmask),
415 .muxmask = i2s_ext_clk_input_muxmask,
416 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
417 .funcmask = BIT(2),
418 .funcval = BIT(2),
419};
420
421static const unsigned i2s_ext_clk_input_pins[] = { 51 };
422
383static const struct sirfsoc_muxmask i2s_muxmask[] = { 423static const struct sirfsoc_muxmask i2s_muxmask[] = {
384 { 424 {
385 .group = 1, 425 .group = 1,
386 .mask = 426 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
387 BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(19)
388 | BIT(23) | BIT(28),
389 }, 427 },
390}; 428};
391 429
@@ -393,11 +431,42 @@ static const struct sirfsoc_padmux i2s_padmux = {
393 .muxmask_counts = ARRAY_SIZE(i2s_muxmask), 431 .muxmask_counts = ARRAY_SIZE(i2s_muxmask),
394 .muxmask = i2s_muxmask, 432 .muxmask = i2s_muxmask,
395 .ctrlreg = SIRFSOC_RSC_PIN_MUX, 433 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
396 .funcmask = BIT(3) | BIT(9),
397 .funcval = BIT(3),
398}; 434};
399 435
400static const unsigned i2s_pins[] = { 42, 43, 44, 45, 46, 51, 55, 60 }; 436static const unsigned i2s_pins[] = { 43, 44, 45, 46 };
437
438static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = {
439 {
440 .group = 1,
441 .mask = BIT(11) | BIT(12) | BIT(14),
442 },
443};
444
445static const struct sirfsoc_padmux i2s_no_din_padmux = {
446 .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
447 .muxmask = i2s_no_din_muxmask,
448 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
449};
450
451static const unsigned i2s_no_din_pins[] = { 43, 44, 46 };
452
453static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = {
454 {
455 .group = 1,
456 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14)
457 | BIT(23) | BIT(28),
458 },
459};
460
461static const struct sirfsoc_padmux i2s_6chn_padmux = {
462 .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
463 .muxmask = i2s_6chn_muxmask,
464 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
465 .funcmask = BIT(1) | BIT(9),
466 .funcval = BIT(1) | BIT(9),
467};
468
469static const unsigned i2s_6chn_pins[] = { 43, 44, 45, 46, 55, 60 };
401 470
402static const struct sirfsoc_muxmask ac97_muxmask[] = { 471static const struct sirfsoc_muxmask ac97_muxmask[] = {
403 { 472 {
@@ -685,7 +754,8 @@ static const struct sirfsoc_padmux vip_padmux = {
685 .funcval = 0, 754 .funcval = 0,
686}; 755};
687 756
688static const unsigned vip_pins[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 }; 757static const unsigned vip_pins[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87,
758 88, 89 };
689 759
690static const struct sirfsoc_muxmask i2c0_muxmask[] = { 760static const struct sirfsoc_muxmask i2c0_muxmask[] = {
691 { 761 {
@@ -735,7 +805,8 @@ static const struct sirfsoc_padmux viprom_padmux = {
735 .funcval = BIT(0), 805 .funcval = BIT(0),
736}; 806};
737 807
738static const unsigned viprom_pins[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 }; 808static const unsigned viprom_pins[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86,
809 87, 88, 89 };
739 810
740static const struct sirfsoc_muxmask pwm0_muxmask[] = { 811static const struct sirfsoc_muxmask pwm0_muxmask[] = {
741 { 812 {
@@ -918,7 +989,11 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
918 SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins), 989 SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
919 SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins), 990 SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
920 SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins), 991 SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
992 SIRFSOC_PIN_GROUP("i2smclkgrp", i2s_mclk_pins),
993 SIRFSOC_PIN_GROUP("i2s_ext_clk_inputgrp", i2s_ext_clk_input_pins),
921 SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins), 994 SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
995 SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
996 SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins),
922 SIRFSOC_PIN_GROUP("ac97grp", ac97_pins), 997 SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
923 SIRFSOC_PIN_GROUP("nandgrp", nand_pins), 998 SIRFSOC_PIN_GROUP("nandgrp", nand_pins),
924 SIRFSOC_PIN_GROUP("spi0grp", spi0_pins), 999 SIRFSOC_PIN_GROUP("spi0grp", spi0_pins),
@@ -936,16 +1011,19 @@ static const char * const uart1grp[] = { "uart1grp" };
936static const char * const uart2grp[] = { "uart2grp" }; 1011static const char * const uart2grp[] = { "uart2grp" };
937static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" }; 1012static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
938static const char * const usp0grp[] = { "usp0grp" }; 1013static const char * const usp0grp[] = { "usp0grp" };
939static const char * const usp0_uart_nostreamctrl_grp[] = 1014static const char * const usp0_uart_nostreamctrl_grp[] = {
940 { "usp0_uart_nostreamctrl_grp" }; 1015 "usp0_uart_nostreamctrl_grp"
1016};
941static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" }; 1017static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" };
942static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" }; 1018static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" };
943static const char * const usp1grp[] = { "usp1grp" }; 1019static const char * const usp1grp[] = { "usp1grp" };
944static const char * const usp1_uart_nostreamctrl_grp[] = 1020static const char * const usp1_uart_nostreamctrl_grp[] = {
945 { "usp1_uart_nostreamctrl_grp" }; 1021 "usp1_uart_nostreamctrl_grp"
1022};
946static const char * const usp2grp[] = { "usp2grp" }; 1023static const char * const usp2grp[] = { "usp2grp" };
947static const char * const usp2_uart_nostreamctrl_grp[] = 1024static const char * const usp2_uart_nostreamctrl_grp[] = {
948 { "usp2_uart_nostreamctrl_grp" }; 1025 "usp2_uart_nostreamctrl_grp"
1026};
949static const char * const i2c0grp[] = { "i2c0grp" }; 1027static const char * const i2c0grp[] = { "i2c0grp" };
950static const char * const i2c1grp[] = { "i2c1grp" }; 1028static const char * const i2c1grp[] = { "i2c1grp" };
951static const char * const pwm0grp[] = { "pwm0grp" }; 1029static const char * const pwm0grp[] = { "pwm0grp" };
@@ -966,9 +1044,14 @@ static const char * const sdmmc5grp[] = { "sdmmc5grp" };
966static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" }; 1044static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" };
967static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" }; 1045static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
968static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" }; 1046static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
969static const char * const uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" }; 1047static const char * const
1048 uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
970static const char * const pulse_countgrp[] = { "pulse_countgrp" }; 1049static const char * const pulse_countgrp[] = { "pulse_countgrp" };
1050static const char * const i2smclkgrp[] = { "i2smclkgrp" };
1051static const char * const i2s_ext_clk_inputgrp[] = { "i2s_ext_clk_inputgrp" };
971static const char * const i2sgrp[] = { "i2sgrp" }; 1052static const char * const i2sgrp[] = { "i2sgrp" };
1053static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
1054static const char * const i2s_6chngrp[] = { "i2s_6chngrp" };
972static const char * const ac97grp[] = { "ac97grp" }; 1055static const char * const ac97grp[] = { "ac97grp" };
973static const char * const nandgrp[] = { "nandgrp" }; 1056static const char * const nandgrp[] = { "nandgrp" };
974static const char * const spi0grp[] = { "spi0grp" }; 1057static const char * const spi0grp[] = { "spi0grp" };
@@ -981,15 +1064,19 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
981 SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux), 1064 SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
982 SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux), 1065 SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
983 SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux), 1066 SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
984 SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl", uart0_nostreamctrlgrp, uart0_nostreamctrl_padmux), 1067 SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl",
1068 uart0_nostreamctrlgrp, uart0_nostreamctrl_padmux),
985 SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux), 1069 SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
986 SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux), 1070 SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
987 SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux), 1071 SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl",
1072 uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
988 SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux), 1073 SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
989 SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl", 1074 SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
990 usp0_uart_nostreamctrl_grp, usp0_uart_nostreamctrl_padmux), 1075 usp0_uart_nostreamctrl_grp, usp0_uart_nostreamctrl_padmux),
991 SIRFSOC_PMX_FUNCTION("usp0_only_utfs", usp0_only_utfs_grp, usp0_only_utfs_padmux), 1076 SIRFSOC_PMX_FUNCTION("usp0_only_utfs",
992 SIRFSOC_PMX_FUNCTION("usp0_only_urfs", usp0_only_urfs_grp, usp0_only_urfs_padmux), 1077 usp0_only_utfs_grp, usp0_only_utfs_padmux),
1078 SIRFSOC_PMX_FUNCTION("usp0_only_urfs",
1079 usp0_only_urfs_grp, usp0_only_urfs_padmux),
993 SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux), 1080 SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
994 SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl", 1081 SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl",
995 usp1_uart_nostreamctrl_grp, usp1_uart_nostreamctrl_padmux), 1082 usp1_uart_nostreamctrl_grp, usp1_uart_nostreamctrl_padmux),
@@ -1013,12 +1100,20 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
1013 SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux), 1100 SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
1014 SIRFSOC_PMX_FUNCTION("sdmmc4", sdmmc4grp, sdmmc4_padmux), 1101 SIRFSOC_PMX_FUNCTION("sdmmc4", sdmmc4grp, sdmmc4_padmux),
1015 SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux), 1102 SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
1016 SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus", usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux), 1103 SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus",
1017 SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux), 1104 usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux),
1105 SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus",
1106 usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
1018 SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux), 1107 SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
1019 SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", uart1_route_io_usb1grp, uart1_route_io_usb1_padmux), 1108 SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1",
1109 uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
1020 SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux), 1110 SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
1111 SIRFSOC_PMX_FUNCTION("i2s_mclk", i2smclkgrp, i2s_mclk_padmux),
1112 SIRFSOC_PMX_FUNCTION("i2s_ext_clk_input", i2s_ext_clk_inputgrp,
1113 i2s_ext_clk_input_padmux),
1021 SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux), 1114 SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
1115 SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
1116 SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux),
1022 SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux), 1117 SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
1023 SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux), 1118 SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux),
1024 SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux), 1119 SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux),
diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c
index 4c1d7c68666d..b713bd59ffbb 100644
--- a/drivers/pinctrl/sirf/pinctrl-sirf.c
+++ b/drivers/pinctrl/sirf/pinctrl-sirf.c
@@ -58,17 +58,18 @@ static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
58 return sirfsoc_pin_groups[selector].name; 58 return sirfsoc_pin_groups[selector].name;
59} 59}
60 60
61static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, 61static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev,
62 const unsigned **pins, 62 unsigned selector,
63 unsigned *num_pins) 63 const unsigned **pins,
64 unsigned *num_pins)
64{ 65{
65 *pins = sirfsoc_pin_groups[selector].pins; 66 *pins = sirfsoc_pin_groups[selector].pins;
66 *num_pins = sirfsoc_pin_groups[selector].num_pins; 67 *num_pins = sirfsoc_pin_groups[selector].num_pins;
67 return 0; 68 return 0;
68} 69}
69 70
70static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 71static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev,
71 unsigned offset) 72 struct seq_file *s, unsigned offset)
72{ 73{
73 seq_printf(s, " " DRIVER_NAME); 74 seq_printf(s, " " DRIVER_NAME);
74} 75}
@@ -138,22 +139,25 @@ static struct pinctrl_ops sirfsoc_pctrl_ops = {
138static struct sirfsoc_pmx_func *sirfsoc_pmx_functions; 139static struct sirfsoc_pmx_func *sirfsoc_pmx_functions;
139static int sirfsoc_pmxfunc_cnt; 140static int sirfsoc_pmxfunc_cnt;
140 141
141static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector, 142static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx,
142 bool enable) 143 unsigned selector, bool enable)
143{ 144{
144 int i; 145 int i;
145 const struct sirfsoc_padmux *mux = sirfsoc_pmx_functions[selector].padmux; 146 const struct sirfsoc_padmux *mux =
147 sirfsoc_pmx_functions[selector].padmux;
146 const struct sirfsoc_muxmask *mask = mux->muxmask; 148 const struct sirfsoc_muxmask *mask = mux->muxmask;
147 149
148 for (i = 0; i < mux->muxmask_counts; i++) { 150 for (i = 0; i < mux->muxmask_counts; i++) {
149 u32 muxval; 151 u32 muxval;
150 if (!spmx->is_marco) { 152 if (!spmx->is_marco) {
151 muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group)); 153 muxval = readl(spmx->gpio_virtbase +
154 SIRFSOC_GPIO_PAD_EN(mask[i].group));
152 if (enable) 155 if (enable)
153 muxval = muxval & ~mask[i].mask; 156 muxval = muxval & ~mask[i].mask;
154 else 157 else
155 muxval = muxval | mask[i].mask; 158 muxval = muxval | mask[i].mask;
156 writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group)); 159 writel(muxval, spmx->gpio_virtbase +
160 SIRFSOC_GPIO_PAD_EN(mask[i].group));
157 } else { 161 } else {
158 if (enable) 162 if (enable)
159 writel(mask[i].mask, spmx->gpio_virtbase + 163 writel(mask[i].mask, spmx->gpio_virtbase +
@@ -175,8 +179,9 @@ static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector
175 } 179 }
176} 180}
177 181
178static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector, 182static int sirfsoc_pinmux_set_mux(struct pinctrl_dev *pmxdev,
179 unsigned group) 183 unsigned selector,
184 unsigned group)
180{ 185{
181 struct sirfsoc_pmx *spmx; 186 struct sirfsoc_pmx *spmx;
182 187
@@ -197,9 +202,10 @@ static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
197 return sirfsoc_pmx_functions[selector].name; 202 return sirfsoc_pmx_functions[selector].name;
198} 203}
199 204
200static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector, 205static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev,
201 const char * const **groups, 206 unsigned selector,
202 unsigned * const num_groups) 207 const char * const **groups,
208 unsigned * const num_groups)
203{ 209{
204 *groups = sirfsoc_pmx_functions[selector].groups; 210 *groups = sirfsoc_pmx_functions[selector].groups;
205 *num_groups = sirfsoc_pmx_functions[selector].num_groups; 211 *num_groups = sirfsoc_pmx_functions[selector].num_groups;
@@ -218,9 +224,11 @@ static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
218 spmx = pinctrl_dev_get_drvdata(pmxdev); 224 spmx = pinctrl_dev_get_drvdata(pmxdev);
219 225
220 if (!spmx->is_marco) { 226 if (!spmx->is_marco) {
221 muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group)); 227 muxval = readl(spmx->gpio_virtbase +
228 SIRFSOC_GPIO_PAD_EN(group));
222 muxval = muxval | (1 << (offset - range->pin_base)); 229 muxval = muxval | (1 << (offset - range->pin_base));
223 writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group)); 230 writel(muxval, spmx->gpio_virtbase +
231 SIRFSOC_GPIO_PAD_EN(group));
224 } else { 232 } else {
225 writel(1 << (offset - range->pin_base), spmx->gpio_virtbase + 233 writel(1 << (offset - range->pin_base), spmx->gpio_virtbase +
226 SIRFSOC_GPIO_PAD_EN(group)); 234 SIRFSOC_GPIO_PAD_EN(group));
@@ -230,7 +238,7 @@ static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
230} 238}
231 239
232static struct pinmux_ops sirfsoc_pinmux_ops = { 240static struct pinmux_ops sirfsoc_pinmux_ops = {
233 .enable = sirfsoc_pinmux_enable, 241 .set_mux = sirfsoc_pinmux_set_mux,
234 .get_functions_count = sirfsoc_pinmux_get_funcs_count, 242 .get_functions_count = sirfsoc_pinmux_get_funcs_count,
235 .get_function_name = sirfsoc_pinmux_get_func_name, 243 .get_function_name = sirfsoc_pinmux_get_func_name,
236 .get_function_groups = sirfsoc_pinmux_get_groups, 244 .get_function_groups = sirfsoc_pinmux_get_groups,
@@ -518,24 +526,29 @@ static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
518 case IRQ_TYPE_NONE: 526 case IRQ_TYPE_NONE:
519 break; 527 break;
520 case IRQ_TYPE_EDGE_RISING: 528 case IRQ_TYPE_EDGE_RISING:
521 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; 529 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK |
530 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
522 val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK; 531 val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
523 break; 532 break;
524 case IRQ_TYPE_EDGE_FALLING: 533 case IRQ_TYPE_EDGE_FALLING:
525 val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; 534 val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
526 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; 535 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
536 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
527 break; 537 break;
528 case IRQ_TYPE_EDGE_BOTH: 538 case IRQ_TYPE_EDGE_BOTH:
529 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_LOW_MASK | 539 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK |
530 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK; 540 SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
541 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
531 break; 542 break;
532 case IRQ_TYPE_LEVEL_LOW: 543 case IRQ_TYPE_LEVEL_LOW:
533 val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); 544 val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK |
545 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
534 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK; 546 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
535 break; 547 break;
536 case IRQ_TYPE_LEVEL_HIGH: 548 case IRQ_TYPE_LEVEL_HIGH:
537 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK; 549 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
538 val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK); 550 val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
551 SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
539 break; 552 break;
540 } 553 }
541 554
@@ -694,7 +707,8 @@ static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_chip *sgpio,
694 spin_unlock_irqrestore(&bank->lock, flags); 707 spin_unlock_irqrestore(&bank->lock, flags);
695} 708}
696 709
697static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value) 710static int sirfsoc_gpio_direction_output(struct gpio_chip *chip,
711 unsigned gpio, int value)
698{ 712{
699 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip); 713 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
700 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio); 714 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
@@ -839,7 +853,7 @@ static int sirfsoc_gpio_probe(struct device_node *np)
839 if (err) { 853 if (err) {
840 dev_err(&pdev->dev, 854 dev_err(&pdev->dev,
841 "could not connect irqchip to gpiochip\n"); 855 "could not connect irqchip to gpiochip\n");
842 goto out; 856 goto out_banks;
843 } 857 }
844 858
845 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { 859 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
@@ -898,8 +912,8 @@ static int __init sirfsoc_gpio_init(void)
898} 912}
899subsys_initcall(sirfsoc_gpio_init); 913subsys_initcall(sirfsoc_gpio_init);
900 914
901MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, " 915MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>");
902 "Yuping Luo <yuping.luo@csr.com>, " 916MODULE_AUTHOR("Yuping Luo <yuping.luo@csr.com>");
903 "Barry Song <baohua.song@csr.com>"); 917MODULE_AUTHOR("Barry Song <baohua.song@csr.com>");
904MODULE_DESCRIPTION("SIRFSOC pin control driver"); 918MODULE_DESCRIPTION("SIRFSOC pin control driver");
905MODULE_LICENSE("GPL"); 919MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/spear/pinctrl-spear.c b/drivers/pinctrl/spear/pinctrl-spear.c
index f72cc4e192bd..abdb05ac43dc 100644
--- a/drivers/pinctrl/spear/pinctrl-spear.c
+++ b/drivers/pinctrl/spear/pinctrl-spear.c
@@ -268,7 +268,7 @@ static int spear_pinctrl_endisable(struct pinctrl_dev *pctldev,
268 return 0; 268 return 0;
269} 269}
270 270
271static int spear_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function, 271static int spear_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned function,
272 unsigned group) 272 unsigned group)
273{ 273{
274 return spear_pinctrl_endisable(pctldev, function, group, true); 274 return spear_pinctrl_endisable(pctldev, function, group, true);
@@ -338,7 +338,7 @@ static const struct pinmux_ops spear_pinmux_ops = {
338 .get_functions_count = spear_pinctrl_get_funcs_count, 338 .get_functions_count = spear_pinctrl_get_funcs_count,
339 .get_function_name = spear_pinctrl_get_func_name, 339 .get_function_name = spear_pinctrl_get_func_name,
340 .get_function_groups = spear_pinctrl_get_func_groups, 340 .get_function_groups = spear_pinctrl_get_func_groups,
341 .enable = spear_pinctrl_enable, 341 .set_mux = spear_pinctrl_set_mux,
342 .gpio_request_enable = gpio_request_enable, 342 .gpio_request_enable = gpio_request_enable,
343 .gpio_disable_free = gpio_disable_free, 343 .gpio_disable_free = gpio_disable_free,
344}; 344};
diff --git a/drivers/pinctrl/spear/pinctrl-spear1310.c b/drivers/pinctrl/spear/pinctrl-spear1310.c
index 1a8bbfec60ca..6d57d43ab640 100644
--- a/drivers/pinctrl/spear/pinctrl-spear1310.c
+++ b/drivers/pinctrl/spear/pinctrl-spear1310.c
@@ -2692,7 +2692,7 @@ static struct spear_pinctrl_machdata spear1310_machdata = {
2692 .modes_supported = false, 2692 .modes_supported = false,
2693}; 2693};
2694 2694
2695static struct of_device_id spear1310_pinctrl_of_match[] = { 2695static const struct of_device_id spear1310_pinctrl_of_match[] = {
2696 { 2696 {
2697 .compatible = "st,spear1310-pinmux", 2697 .compatible = "st,spear1310-pinmux",
2698 }, 2698 },
diff --git a/drivers/pinctrl/spear/pinctrl-spear1340.c b/drivers/pinctrl/spear/pinctrl-spear1340.c
index 873966e2b99f..d243e43e7f6d 100644
--- a/drivers/pinctrl/spear/pinctrl-spear1340.c
+++ b/drivers/pinctrl/spear/pinctrl-spear1340.c
@@ -2008,7 +2008,7 @@ static struct spear_pinctrl_machdata spear1340_machdata = {
2008 .modes_supported = false, 2008 .modes_supported = false,
2009}; 2009};
2010 2010
2011static struct of_device_id spear1340_pinctrl_of_match[] = { 2011static const struct of_device_id spear1340_pinctrl_of_match[] = {
2012 { 2012 {
2013 .compatible = "st,spear1340-pinmux", 2013 .compatible = "st,spear1340-pinmux",
2014 }, 2014 },
diff --git a/drivers/pinctrl/spear/pinctrl-spear300.c b/drivers/pinctrl/spear/pinctrl-spear300.c
index 4777c0d0e730..9db83e9ee18c 100644
--- a/drivers/pinctrl/spear/pinctrl-spear300.c
+++ b/drivers/pinctrl/spear/pinctrl-spear300.c
@@ -646,7 +646,7 @@ static struct spear_function *spear300_functions[] = {
646 &gpio1_function, 646 &gpio1_function,
647}; 647};
648 648
649static struct of_device_id spear300_pinctrl_of_match[] = { 649static const struct of_device_id spear300_pinctrl_of_match[] = {
650 { 650 {
651 .compatible = "st,spear300-pinmux", 651 .compatible = "st,spear300-pinmux",
652 }, 652 },
diff --git a/drivers/pinctrl/spear/pinctrl-spear310.c b/drivers/pinctrl/spear/pinctrl-spear310.c
index ed1d3608f486..db775a414b7a 100644
--- a/drivers/pinctrl/spear/pinctrl-spear310.c
+++ b/drivers/pinctrl/spear/pinctrl-spear310.c
@@ -371,7 +371,7 @@ static struct spear_function *spear310_functions[] = {
371 &tdm_function, 371 &tdm_function,
372}; 372};
373 373
374static struct of_device_id spear310_pinctrl_of_match[] = { 374static const struct of_device_id spear310_pinctrl_of_match[] = {
375 { 375 {
376 .compatible = "st,spear310-pinmux", 376 .compatible = "st,spear310-pinmux",
377 }, 377 },
diff --git a/drivers/pinctrl/spear/pinctrl-spear320.c b/drivers/pinctrl/spear/pinctrl-spear320.c
index b8e290a8c8c9..80fbd68e17bc 100644
--- a/drivers/pinctrl/spear/pinctrl-spear320.c
+++ b/drivers/pinctrl/spear/pinctrl-spear320.c
@@ -3410,7 +3410,7 @@ static struct spear_function *spear320_functions[] = {
3410 &i2c2_function, 3410 &i2c2_function,
3411}; 3411};
3412 3412
3413static struct of_device_id spear320_pinctrl_of_match[] = { 3413static const struct of_device_id spear320_pinctrl_of_match[] = {
3414 { 3414 {
3415 .compatible = "st,spear320-pinmux", 3415 .compatible = "st,spear320-pinmux",
3416 }, 3416 },
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 3df66e366c87..ef9d804e55de 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -393,9 +393,9 @@ static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
393 spin_unlock_irqrestore(&pctl->lock, flags); 393 spin_unlock_irqrestore(&pctl->lock, flags);
394} 394}
395 395
396static int sunxi_pmx_enable(struct pinctrl_dev *pctldev, 396static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev,
397 unsigned function, 397 unsigned function,
398 unsigned group) 398 unsigned group)
399{ 399{
400 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 400 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
401 struct sunxi_pinctrl_group *g = pctl->groups + group; 401 struct sunxi_pinctrl_group *g = pctl->groups + group;
@@ -441,7 +441,7 @@ static const struct pinmux_ops sunxi_pmx_ops = {
441 .get_functions_count = sunxi_pmx_get_funcs_cnt, 441 .get_functions_count = sunxi_pmx_get_funcs_cnt,
442 .get_function_name = sunxi_pmx_get_func_name, 442 .get_function_name = sunxi_pmx_get_func_name,
443 .get_function_groups = sunxi_pmx_get_func_groups, 443 .get_function_groups = sunxi_pmx_get_func_groups,
444 .enable = sunxi_pmx_enable, 444 .set_mux = sunxi_pmx_set_mux,
445 .gpio_set_direction = sunxi_pmx_gpio_set_direction, 445 .gpio_set_direction = sunxi_pmx_gpio_set_direction,
446}; 446};
447 447
diff --git a/drivers/pinctrl/vt8500/pinctrl-wmt.c b/drivers/pinctrl/vt8500/pinctrl-wmt.c
index 8cea355f9a81..d055d63309e4 100644
--- a/drivers/pinctrl/vt8500/pinctrl-wmt.c
+++ b/drivers/pinctrl/vt8500/pinctrl-wmt.c
@@ -131,9 +131,9 @@ static int wmt_set_pinmux(struct wmt_pinctrl_data *data, unsigned func,
131 return 0; 131 return 0;
132} 132}
133 133
134static int wmt_pmx_enable(struct pinctrl_dev *pctldev, 134static int wmt_pmx_set_mux(struct pinctrl_dev *pctldev,
135 unsigned func_selector, 135 unsigned func_selector,
136 unsigned group_selector) 136 unsigned group_selector)
137{ 137{
138 struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev); 138 struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
139 u32 pinnum = data->pins[group_selector].number; 139 u32 pinnum = data->pins[group_selector].number;
@@ -168,7 +168,7 @@ static struct pinmux_ops wmt_pinmux_ops = {
168 .get_functions_count = wmt_pmx_get_functions_count, 168 .get_functions_count = wmt_pmx_get_functions_count,
169 .get_function_name = wmt_pmx_get_function_name, 169 .get_function_name = wmt_pmx_get_function_name,
170 .get_function_groups = wmt_pmx_get_function_groups, 170 .get_function_groups = wmt_pmx_get_function_groups,
171 .enable = wmt_pmx_enable, 171 .set_mux = wmt_pmx_set_mux,
172 .gpio_disable_free = wmt_pmx_gpio_disable_free, 172 .gpio_disable_free = wmt_pmx_gpio_disable_free,
173 .gpio_set_direction = wmt_pmx_gpio_set_direction, 173 .gpio_set_direction = wmt_pmx_gpio_set_direction,
174}; 174};
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-25 03:45:22 -0500