Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS updates from Ralf Baechle:

 - Improvements to the tlb_dump code
 - KVM fixes
 - Add support for appended DTB
 - Minor improvements to the R12000 support
 - Minor improvements to the R12000 support
 - Various platform improvments for BCM47xx
 - The usual pile of minor cleanups
 - A number of BPF fixes and improvments
 - Some improvments to the support for R3000 and DECstations
 - Some improvments to the ATH79 platform support
 - A major patchset for the JZ4740 SOC adding support for the CI20 platform
 - Add support for the Pistachio SOC
 - Minor BMIPS/BCM63xx platform support improvments.
 - Avoid "SYNC 0" as memory barrier when unlocking spinlocks
 - Add support for the XWR-1750 board.
 - Paul's __cpuinit/__cpuinitdata cleanups.
 - New Malta CPU board support large memory so enable ZONE_DMA32.

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (131 commits)
  MIPS: spinlock: Adjust arch_spin_lock back-off time
  MIPS: asmmacro: Ensure 64-bit FP registers are used with MSA
  MIPS: BCM47xx: Simplify handling SPROM revisions
  MIPS: Cobalt Don't use module_init in non-modular MTD registration.
  MIPS: BCM47xx: Move NVRAM driver to the drivers/firmware/
  MIPS: use for_each_sg()
  MIPS: BCM47xx: Don't select BCMA_HOST_PCI
  MIPS: BCM47xx: Add helper variable for storing NVRAM length
  MIPS: IRQ/IP27: Move IRQ allocation API to platform code.
  MIPS: Replace smp_mb with release barrier function in unlocks.
  MIPS: i8259: DT support
  MIPS: Malta: Basic DT plumbing
  MIPS: include errno.h for ENODEV in mips-cm.h
  MIPS: Define GCR_GIC_STATUS register fields
  MIPS: BPF: Introduce BPF ASM helpers
  MIPS: BPF: Use BPF register names to describe the ABI
  MIPS: BPF: Move register definition to the BPF header
  MIPS: net: BPF: Replace RSIZE with SZREG
  MIPS: BPF: Free up some callee-saved registers
  MIPS: Xtalk: Update xwidget.h with known Xtalk device numbers
  ...

3 files changed, 214 insertions, 0 deletions

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 487d057431cc..c0e6ede3e27d 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -267,6 +267,13 @@ config PHY_EXYNOS5_USBDRD
           This driver provides PHY interface for USB 3.0 DRD controller
           present on Exynos5 SoC series.
 
+config PHY_PISTACHIO_USB
+        tristate "IMG Pistachio USB2.0 PHY driver"
+        depends on MACH_PISTACHIO
+        select GENERIC_PHY
+        help
+          Enable this to support the USB2.0 PHY on the IMG Pistachio SoC.
+
 config PHY_QCOM_APQ8064_SATA
         tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
         depends on ARCH_QCOM
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 42f58e95aff0..f344e1b2e825 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -44,3 +44,4 @@ obj-$(CONFIG_PHY_QCOM_UFS) 	+= phy-qcom-ufs-qmp-20nm.o
 obj-$(CONFIG_PHY_QCOM_UFS)      += phy-qcom-ufs-qmp-14nm.o
 obj-$(CONFIG_PHY_TUSB1210)              += phy-tusb1210.o
 obj-$(CONFIG_PHY_BRCMSTB_SATA)          += phy-brcmstb-sata.o
+obj-$(CONFIG_PHY_PISTACHIO_USB)         += phy-pistachio-usb.o
diff --git a/drivers/phy/phy-pistachio-usb.c b/drivers/phy/phy-pistachio-usb.c
new file mode 100644
index 000000000000..c6db35e6bb63
--- /dev/null
+++ b/drivers/phy/phy-pistachio-usb.c
@@ -0,0 +1,206 @@
+/*
+ * IMG Pistachio USB PHY driver
+ *
+ * Copyright (C) 2015 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/phy/phy-pistachio-usb.h>
+
+#define USB_PHY_CONTROL1                                0x04
+#define USB_PHY_CONTROL1_FSEL_SHIFT                     2
+#define USB_PHY_CONTROL1_FSEL_MASK                      0x7
+
+#define USB_PHY_STRAP_CONTROL                           0x10
+#define USB_PHY_STRAP_CONTROL_REFCLK_SHIFT              4
+#define USB_PHY_STRAP_CONTROL_REFCLK_MASK               0x3
+
+#define USB_PHY_STATUS                                  0x14
+#define USB_PHY_STATUS_RX_PHY_CLK                       BIT(9)
+#define USB_PHY_STATUS_RX_UTMI_CLK                      BIT(8)
+#define USB_PHY_STATUS_VBUS_FAULT                       BIT(7)
+
+struct pistachio_usb_phy {
+        struct device *dev;
+        struct regmap *cr_top;
+        struct clk *phy_clk;
+        unsigned int refclk;
+};
+
+static const unsigned long fsel_rate_map[] = {
+        9600000,
+        10000000,
+        12000000,
+        19200000,
+        20000000,
+        24000000,
+        0,
+        50000000,
+};
+
+static int pistachio_usb_phy_power_on(struct phy *phy)
+{
+        struct pistachio_usb_phy *p_phy = phy_get_drvdata(phy);
+        unsigned long timeout, rate;
+        unsigned int i;
+        int ret;
+
+        ret = clk_prepare_enable(p_phy->phy_clk);
+        if (ret < 0) {
+                dev_err(p_phy->dev, "Failed to enable PHY clock: %d\n", ret);
+                return ret;
+        }
+
+        regmap_update_bits(p_phy->cr_top, USB_PHY_STRAP_CONTROL,
+                           USB_PHY_STRAP_CONTROL_REFCLK_MASK <<
+                           USB_PHY_STRAP_CONTROL_REFCLK_SHIFT,
+                           p_phy->refclk << USB_PHY_STRAP_CONTROL_REFCLK_SHIFT);
+
+        rate = clk_get_rate(p_phy->phy_clk);
+        if (p_phy->refclk == REFCLK_XO_CRYSTAL && rate != 12000000) {
+                dev_err(p_phy->dev, "Unsupported rate for XO crystal: %ld\n",
+                        rate);
+                ret = -EINVAL;
+                goto disable_clk;
+        }
+
+        for (i = 0; i < ARRAY_SIZE(fsel_rate_map); i++) {
+                if (rate == fsel_rate_map[i])
+                        break;
+        }
+        if (i == ARRAY_SIZE(fsel_rate_map)) {
+                dev_err(p_phy->dev, "Unsupported clock rate: %lu\n", rate);
+                ret = -EINVAL;
+                goto disable_clk;
+        }
+
+        regmap_update_bits(p_phy->cr_top, USB_PHY_CONTROL1,
+                           USB_PHY_CONTROL1_FSEL_MASK <<
+                           USB_PHY_CONTROL1_FSEL_SHIFT,
+                           i << USB_PHY_CONTROL1_FSEL_SHIFT);
+
+        timeout = jiffies + msecs_to_jiffies(200);
+        while (time_before(jiffies, timeout)) {
+                unsigned int val;
+
+                regmap_read(p_phy->cr_top, USB_PHY_STATUS, &val);
+                if (val & USB_PHY_STATUS_VBUS_FAULT) {
+                        dev_err(p_phy->dev, "VBUS fault detected\n");
+                        ret = -EIO;
+                        goto disable_clk;
+                }
+                if ((val & USB_PHY_STATUS_RX_PHY_CLK) &&
+                    (val & USB_PHY_STATUS_RX_UTMI_CLK))
+                        return 0;
+                usleep_range(1000, 1500);
+        }
+
+        dev_err(p_phy->dev, "Timed out waiting for PHY to power on\n");
+        ret = -ETIMEDOUT;
+
+disable_clk:
+        clk_disable_unprepare(p_phy->phy_clk);
+        return ret;
+}
+
+static int pistachio_usb_phy_power_off(struct phy *phy)
+{
+        struct pistachio_usb_phy *p_phy = phy_get_drvdata(phy);
+
+        clk_disable_unprepare(p_phy->phy_clk);
+
+        return 0;
+}
+
+static const struct phy_ops pistachio_usb_phy_ops = {
+        .power_on = pistachio_usb_phy_power_on,
+        .power_off = pistachio_usb_phy_power_off,
+        .owner = THIS_MODULE,
+};
+
+static int pistachio_usb_phy_probe(struct platform_device *pdev)
+{
+        struct pistachio_usb_phy *p_phy;
+        struct phy_provider *provider;
+        struct phy *phy;
+        int ret;
+
+        p_phy = devm_kzalloc(&pdev->dev, sizeof(*p_phy), GFP_KERNEL);
+        if (!p_phy)
+                return -ENOMEM;
+        p_phy->dev = &pdev->dev;
+        platform_set_drvdata(pdev, p_phy);
+
+        p_phy->cr_top = syscon_regmap_lookup_by_phandle(p_phy->dev->of_node,
+                                                        "img,cr-top");
+        if (IS_ERR(p_phy->cr_top)) {
+                dev_err(p_phy->dev, "Failed to get CR_TOP registers: %ld\n",
+                        PTR_ERR(p_phy->cr_top));
+                return PTR_ERR(p_phy->cr_top);
+        }
+
+        p_phy->phy_clk = devm_clk_get(p_phy->dev, "usb_phy");
+        if (IS_ERR(p_phy->phy_clk)) {
+                dev_err(p_phy->dev, "Failed to get usb_phy clock: %ld\n",
+                        PTR_ERR(p_phy->phy_clk));
+                return PTR_ERR(p_phy->phy_clk);
+        }
+
+        ret = of_property_read_u32(p_phy->dev->of_node, "img,refclk",
+                                   &p_phy->refclk);
+        if (ret < 0) {
+                dev_err(p_phy->dev, "No reference clock selector specified\n");
+                return ret;
+        }
+
+        phy = devm_phy_create(p_phy->dev, NULL, &pistachio_usb_phy_ops);
+        if (IS_ERR(phy)) {
+                dev_err(p_phy->dev, "Failed to create PHY: %ld\n",
+                        PTR_ERR(phy));
+                return PTR_ERR(phy);
+        }
+        phy_set_drvdata(phy, p_phy);
+
+        provider = devm_of_phy_provider_register(p_phy->dev,
+                                                 of_phy_simple_xlate);
+        if (IS_ERR(provider)) {
+                dev_err(p_phy->dev, "Failed to register PHY provider: %ld\n",
+                        PTR_ERR(provider));
+                return PTR_ERR(provider);
+        }
+
+        return 0;
+}
+
+static const struct of_device_id pistachio_usb_phy_of_match[] = {
+        { .compatible = "img,pistachio-usb-phy", },
+        { },
+};
+MODULE_DEVICE_TABLE(of, pistachio_usb_phy_of_match);
+
+static struct platform_driver pistachio_usb_phy_driver = {
+        .probe          = pistachio_usb_phy_probe,
+        .driver         = {
+                .name   = "pistachio-usb-phy",
+                .of_match_table = pistachio_usb_phy_of_match,
+        },
+};
+module_platform_driver(pistachio_usb_phy_driver);
+
+MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
+MODULE_DESCRIPTION("IMG Pistachio USB2.0 PHY driver");
+MODULE_LICENSE("GPL v2");