Merge tag 'usb-5.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb

Pull USB/PHY updates from Greg KH:
 "Here is the big set of USB and PHY driver patches for 5.2-rc1

  There is the usual set of:

   - USB gadget updates

   - PHY driver updates and additions

   - USB serial driver updates and fixes

   - typec updates and new chips supported

   - mtu3 driver updates

   - xhci driver updates

   - other tiny driver updates

  Nothing really interesting, just constant forward progress.

  All of these have been in linux-next for a while with no reported
  issues. The usb-gadget and usb-serial trees were merged a bit "late",
  but both of them had been in linux-next before they got merged here
  last Friday"

* tag 'usb-5.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (206 commits)
  USB: serial: f81232: implement break control
  USB: serial: f81232: add high baud rate support
  USB: serial: f81232: clear overrun flag
  USB: serial: f81232: fix interrupt worker not stop
  usb: dwc3: Rename DWC3_DCTL_LPM_ERRATA
  usb: dwc3: Fix default lpm_nyet_threshold value
  usb: dwc3: debug: Print GET_STATUS(device) tracepoint
  usb: dwc3: Do core validation early on probe
  usb: dwc3: gadget: Set lpm_capable
  usb: gadget: atmel: tie wake lock to running clock
  usb: gadget: atmel: support USB suspend
  usb: gadget: atmel_usba_udc: simplify setting of interrupt-enabled mask
  dwc2: gadget: Fix completed transfer size calculation in DDMA
  usb: dwc2: Set lpm mode parameters depend on HW configuration
  usb: dwc2: Fix channel disable flow
  usb: dwc2: Set actual frame number for completed ISOC transfer
  usb: gadget: do not use __constant_cpu_to_le16
  usb: dwc2: gadget: Increase descriptors count for ISOC's
  usb: introduce usb_ep_type_string() function
  usb: dwc3: move synchronize_irq() out of the spinlock protected block
  ...

1 files changed, 165 insertions, 57 deletions

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 08d6f6f7f039..cd91b4179b10 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -242,6 +242,88 @@ static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
         QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
 };
 
+static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
+        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
+};
+
+static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
+        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
+        QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
+        QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
+        QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
+};
+
+static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
+        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
+        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
+        QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
+        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
+        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
+        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
+        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
+        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
+        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
+        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
+        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+        QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
+        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
+        QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
+};
+
+static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
+        QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
+        QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
+        QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
+        QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
+        QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
+        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
+        QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
+        QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
+        QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
+        QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
+};
+
 static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
@@ -897,6 +979,7 @@ struct qmp_phy {
  * @init_count: phy common block initialization count
  * @phy_initialized: indicate if PHY has been initialized
  * @mode: current PHY mode
+ * @ufs_reset: optional UFS PHY reset handle
  */
 struct qcom_qmp {
         struct device *dev;
@@ -914,6 +997,8 @@ struct qcom_qmp {
         int init_count;
         bool phy_initialized;
         enum phy_mode mode;
+
+        struct reset_control *ufs_reset;
 };
 
 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
@@ -1146,6 +1231,31 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
         .no_pcs_sw_reset        = true,
 };
 
+static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
+        .type                   = PHY_TYPE_PCIE,
+        .nlanes                 = 1,
+
+        .serdes_tbl             = msm8998_pcie_serdes_tbl,
+        .serdes_tbl_num         = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
+        .tx_tbl                 = msm8998_pcie_tx_tbl,
+        .tx_tbl_num             = ARRAY_SIZE(msm8998_pcie_tx_tbl),
+        .rx_tbl                 = msm8998_pcie_rx_tbl,
+        .rx_tbl_num             = ARRAY_SIZE(msm8998_pcie_rx_tbl),
+        .pcs_tbl                = msm8998_pcie_pcs_tbl,
+        .pcs_tbl_num            = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
+        .clk_list               = msm8996_phy_clk_l,
+        .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
+        .reset_list             = ipq8074_pciephy_reset_l,
+        .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
+        .vreg_list              = qmp_phy_vreg_l,
+        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
+        .regs                   = pciephy_regs_layout,
+
+        .start_ctrl             = SERDES_START | PCS_START,
+        .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
+        .mask_com_pcs_ready     = PCS_READY,
+};
+
 static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
         .type                   = PHY_TYPE_USB3,
         .nlanes                 = 1,
@@ -1314,6 +1424,7 @@ static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp)
                 return 0;
         }
 
+        reset_control_assert(qmp->ufs_reset);
         if (cfg->has_phy_com_ctrl) {
                 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
                              SERDES_START | PCS_START);
@@ -1335,8 +1446,7 @@ static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp)
         return 0;
 }
 
-/* PHY Initialization */
-static int qcom_qmp_phy_init(struct phy *phy)
+static int qcom_qmp_phy_enable(struct phy *phy)
 {
         struct qmp_phy *qphy = phy_get_drvdata(phy);
         struct qcom_qmp *qmp = qphy->qmp;
@@ -1351,6 +1461,33 @@ static int qcom_qmp_phy_init(struct phy *phy)
 
         dev_vdbg(qmp->dev, "Initializing QMP phy\n");
 
+        if (cfg->no_pcs_sw_reset) {
+                /*
+                 * Get UFS reset, which is delayed until now to avoid a
+                 * circular dependency where UFS needs its PHY, but the PHY
+                 * needs this UFS reset.
+                 */
+                if (!qmp->ufs_reset) {
+                        qmp->ufs_reset =
+                                devm_reset_control_get_exclusive(qmp->dev,
+                                                                 "ufsphy");
+
+                        if (IS_ERR(qmp->ufs_reset)) {
+                                ret = PTR_ERR(qmp->ufs_reset);
+                                dev_err(qmp->dev,
+                                        "failed to get UFS reset: %d\n",
+                                        ret);
+
+                                qmp->ufs_reset = NULL;
+                                return ret;
+                        }
+                }
+
+                ret = reset_control_assert(qmp->ufs_reset);
+                if (ret)
+                        goto err_lane_rst;
+        }
+
         ret = qcom_qmp_phy_com_init(qphy);
         if (ret)
                 return ret;
@@ -1383,14 +1520,9 @@ static int qcom_qmp_phy_init(struct phy *phy)
                                        cfg->rx_tbl, cfg->rx_tbl_num);
 
         qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
-
-        /*
-         * UFS PHY requires the deassert of software reset before serdes start.
-         * For UFS PHYs that do not have software reset control bits, defer
-         * starting serdes until the power on callback.
-         */
-        if ((cfg->type == PHY_TYPE_UFS) && cfg->no_pcs_sw_reset)
-                goto out;
+        ret = reset_control_deassert(qmp->ufs_reset);
+        if (ret)
+                goto err_lane_rst;
 
         /*
          * Pull out PHY from POWER DOWN state.
@@ -1403,7 +1535,9 @@ static int qcom_qmp_phy_init(struct phy *phy)
                 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
 
         /* Pull PHY out of reset state */
-        qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
+        if (!cfg->no_pcs_sw_reset)
+                qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
+
         if (cfg->has_phy_dp_com_ctrl)
                 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
 
@@ -1420,11 +1554,10 @@ static int qcom_qmp_phy_init(struct phy *phy)
                 goto err_pcs_ready;
         }
         qmp->phy_initialized = true;
-
-out:
-        return ret;
+        return 0;
 
 err_pcs_ready:
+        reset_control_assert(qmp->ufs_reset);
         clk_disable_unprepare(qphy->pipe_clk);
 err_clk_enable:
         if (cfg->has_lane_rst)
@@ -1435,7 +1568,7 @@ err_lane_rst:
         return ret;
 }
 
-static int qcom_qmp_phy_exit(struct phy *phy)
+static int qcom_qmp_phy_disable(struct phy *phy)
 {
         struct qmp_phy *qphy = phy_get_drvdata(phy);
         struct qcom_qmp *qmp = qphy->qmp;
@@ -1463,44 +1596,6 @@ static int qcom_qmp_phy_exit(struct phy *phy)
         return 0;
 }
 
-static int qcom_qmp_phy_poweron(struct phy *phy)
-{
-        struct qmp_phy *qphy = phy_get_drvdata(phy);
-        struct qcom_qmp *qmp = qphy->qmp;
-        const struct qmp_phy_cfg *cfg = qmp->cfg;
-        void __iomem *pcs = qphy->pcs;
-        void __iomem *status;
-        unsigned int mask, val;
-        int ret = 0;
-
-        if (cfg->type != PHY_TYPE_UFS)
-                return 0;
-
-        /*
-         * For UFS PHY that has not software reset control, serdes start
-         * should only happen when UFS driver explicitly calls phy_power_on
-         * after it deasserts software reset.
-         */
-        if (cfg->no_pcs_sw_reset && !qmp->phy_initialized &&
-            (qmp->init_count != 0)) {
-                /* start SerDes and Phy-Coding-Sublayer */
-                qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-
-                status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
-                mask = cfg->mask_pcs_ready;
-
-                ret = readl_poll_timeout(status, val, !(val & mask), 1,
-                                         PHY_INIT_COMPLETE_TIMEOUT);
-                if (ret) {
-                        dev_err(qmp->dev, "phy initialization timed-out\n");
-                        return ret;
-                }
-                qmp->phy_initialized = true;
-        }
-
-        return ret;
-}
-
 static int qcom_qmp_phy_set_mode(struct phy *phy,
                                  enum phy_mode mode, int submode)
 {
@@ -1750,9 +1845,15 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
 }
 
 static const struct phy_ops qcom_qmp_phy_gen_ops = {
-        .init           = qcom_qmp_phy_init,
-        .exit           = qcom_qmp_phy_exit,
-        .power_on       = qcom_qmp_phy_poweron,
+        .init           = qcom_qmp_phy_enable,
+        .exit           = qcom_qmp_phy_disable,
+        .set_mode       = qcom_qmp_phy_set_mode,
+        .owner          = THIS_MODULE,
+};
+
+static const struct phy_ops qcom_qmp_ufs_ops = {
+        .power_on       = qcom_qmp_phy_enable,
+        .power_off      = qcom_qmp_phy_disable,
         .set_mode       = qcom_qmp_phy_set_mode,
         .owner          = THIS_MODULE,
 };
@@ -1763,6 +1864,7 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id)
         struct qcom_qmp *qmp = dev_get_drvdata(dev);
         struct phy *generic_phy;
         struct qmp_phy *qphy;
+        const struct phy_ops *ops = &qcom_qmp_phy_gen_ops;
         char prop_name[MAX_PROP_NAME];
         int ret;
 
@@ -1849,7 +1951,10 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id)
                 }
         }
 
-        generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_gen_ops);
+        if (qmp->cfg->type == PHY_TYPE_UFS)
+                ops = &qcom_qmp_ufs_ops;
+
+        generic_phy = devm_phy_create(dev, np, ops);
         if (IS_ERR(generic_phy)) {
                 ret = PTR_ERR(generic_phy);
                 dev_err(dev, "failed to create qphy %d\n", ret);
@@ -1873,6 +1978,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
                 .compatible = "qcom,msm8996-qmp-usb3-phy",
                 .data = &msm8996_usb3phy_cfg,
         }, {
+                .compatible = "qcom,msm8998-qmp-pcie-phy",
+                .data = &msm8998_pciephy_cfg,
+        }, {
                 .compatible = "qcom,msm8998-qmp-ufs-phy",
                 .data = &sdm845_ufsphy_cfg,
         }, {