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authorMarek Szyprowski <m.szyprowski@samsung.com>2016-03-23 07:09:18 -0400
committerKishon Vijay Abraham I <kishon@ti.com>2016-04-30 10:42:30 -0400
commit71f5c63c07e5be7abdce40891778ffbf3cec04f0 (patch)
treed396f737d05479f97e6c41392b6f180e4a30eb07 /drivers/phy/phy-exynos-mipi-video.c
parent97a3042f76164330f7ac5dbe7434f63f92d6f09d (diff)
phy: exynos-mipi-video: Add support for Exynos 5420 and 5433 SoCs
This patch adds support for MIPI DPHYs found in Exynos5420-compatible (5420, 5422 and 5800) and Exynos5433 SoCs. Those SoCs differs from earlier by different offset of MIPI DPHY registers in PMU controllers (Exynos 5420-compatible case) or by moving MIPI DPHY reset registers to separate system register controllers (Exynos 5433 case). In both case also additional 5th PHY (MIPI CSIS 2) has been added. Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'drivers/phy/phy-exynos-mipi-video.c')
-rw-r--r--drivers/phy/phy-exynos-mipi-video.c129
1 files changed, 128 insertions, 1 deletions
diff --git a/drivers/phy/phy-exynos-mipi-video.c b/drivers/phy/phy-exynos-mipi-video.c
index 3cb69e005f18..cc093ebfda94 100644
--- a/drivers/phy/phy-exynos-mipi-video.c
+++ b/drivers/phy/phy-exynos-mipi-video.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY driver 2 * Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY driver
3 * 3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 4 * Copyright (C) 2013,2016 Samsung Electronics Co., Ltd.
5 * Author: Sylwester Nawrocki <s.nawrocki@samsung.com> 5 * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
@@ -13,6 +13,7 @@
13#include <linux/io.h> 13#include <linux/io.h>
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/mfd/syscon/exynos4-pmu.h> 15#include <linux/mfd/syscon/exynos4-pmu.h>
16#include <linux/mfd/syscon/exynos5-pmu.h>
16#include <linux/module.h> 17#include <linux/module.h>
17#include <linux/of.h> 18#include <linux/of.h>
18#include <linux/of_address.h> 19#include <linux/of_address.h>
@@ -28,11 +29,15 @@ enum exynos_mipi_phy_id {
28 EXYNOS_MIPI_PHY_ID_DSIM0, 29 EXYNOS_MIPI_PHY_ID_DSIM0,
29 EXYNOS_MIPI_PHY_ID_CSIS1, 30 EXYNOS_MIPI_PHY_ID_CSIS1,
30 EXYNOS_MIPI_PHY_ID_DSIM1, 31 EXYNOS_MIPI_PHY_ID_DSIM1,
32 EXYNOS_MIPI_PHY_ID_CSIS2,
31 EXYNOS_MIPI_PHYS_NUM 33 EXYNOS_MIPI_PHYS_NUM
32}; 34};
33 35
34enum exynos_mipi_phy_regmap_id { 36enum exynos_mipi_phy_regmap_id {
35 EXYNOS_MIPI_REGMAP_PMU, 37 EXYNOS_MIPI_REGMAP_PMU,
38 EXYNOS_MIPI_REGMAP_DISP,
39 EXYNOS_MIPI_REGMAP_CAM0,
40 EXYNOS_MIPI_REGMAP_CAM1,
36 EXYNOS_MIPI_REGMAPS_NUM 41 EXYNOS_MIPI_REGMAPS_NUM
37}; 42};
38 43
@@ -96,6 +101,122 @@ static const struct mipi_phy_device_desc s5pv210_mipi_phy = {
96 }, 101 },
97}; 102};
98 103
104static const struct mipi_phy_device_desc exynos5420_mipi_phy = {
105 .num_regmaps = 1,
106 .regmap_names = {"syscon"},
107 .num_phys = 5,
108 .phys = {
109 {
110 /* EXYNOS_MIPI_PHY_ID_CSIS0 */
111 .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
112 .enable_val = EXYNOS5_PHY_ENABLE,
113 .enable_reg = EXYNOS5420_MIPI_PHY0_CONTROL,
114 .enable_map = EXYNOS_MIPI_REGMAP_PMU,
115 .resetn_val = EXYNOS5_MIPI_PHY_S_RESETN,
116 .resetn_reg = EXYNOS5420_MIPI_PHY0_CONTROL,
117 .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
118 }, {
119 /* EXYNOS_MIPI_PHY_ID_DSIM0 */
120 .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
121 .enable_val = EXYNOS5_PHY_ENABLE,
122 .enable_reg = EXYNOS5420_MIPI_PHY0_CONTROL,
123 .enable_map = EXYNOS_MIPI_REGMAP_PMU,
124 .resetn_val = EXYNOS5_MIPI_PHY_M_RESETN,
125 .resetn_reg = EXYNOS5420_MIPI_PHY0_CONTROL,
126 .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
127 }, {
128 /* EXYNOS_MIPI_PHY_ID_CSIS1 */
129 .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM1,
130 .enable_val = EXYNOS5_PHY_ENABLE,
131 .enable_reg = EXYNOS5420_MIPI_PHY1_CONTROL,
132 .enable_map = EXYNOS_MIPI_REGMAP_PMU,
133 .resetn_val = EXYNOS5_MIPI_PHY_S_RESETN,
134 .resetn_reg = EXYNOS5420_MIPI_PHY1_CONTROL,
135 .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
136 }, {
137 /* EXYNOS_MIPI_PHY_ID_DSIM1 */
138 .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS1,
139 .enable_val = EXYNOS5_PHY_ENABLE,
140 .enable_reg = EXYNOS5420_MIPI_PHY1_CONTROL,
141 .enable_map = EXYNOS_MIPI_REGMAP_PMU,
142 .resetn_val = EXYNOS5_MIPI_PHY_M_RESETN,
143 .resetn_reg = EXYNOS5420_MIPI_PHY1_CONTROL,
144 .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
145 }, {
146 /* EXYNOS_MIPI_PHY_ID_CSIS2 */
147 .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
148 .enable_val = EXYNOS5_PHY_ENABLE,
149 .enable_reg = EXYNOS5420_MIPI_PHY2_CONTROL,
150 .enable_map = EXYNOS_MIPI_REGMAP_PMU,
151 .resetn_val = EXYNOS5_MIPI_PHY_S_RESETN,
152 .resetn_reg = EXYNOS5420_MIPI_PHY2_CONTROL,
153 .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
154 },
155 },
156};
157
158#define EXYNOS5433_SYSREG_DISP_MIPI_PHY 0x100C
159#define EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON 0x1014
160#define EXYNOS5433_SYSREG_CAM1_MIPI_DPHY_CON 0x1020
161
162static const struct mipi_phy_device_desc exynos5433_mipi_phy = {
163 .num_regmaps = 4,
164 .regmap_names = {
165 "samsung,pmu-syscon",
166 "samsung,disp-sysreg",
167 "samsung,cam0-sysreg",
168 "samsung,cam1-sysreg"
169 },
170 .num_phys = 5,
171 .phys = {
172 {
173 /* EXYNOS_MIPI_PHY_ID_CSIS0 */
174 .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
175 .enable_val = EXYNOS5_PHY_ENABLE,
176 .enable_reg = EXYNOS5433_MIPI_PHY0_CONTROL,
177 .enable_map = EXYNOS_MIPI_REGMAP_PMU,
178 .resetn_val = BIT(0),
179 .resetn_reg = EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON,
180 .resetn_map = EXYNOS_MIPI_REGMAP_CAM0,
181 }, {
182 /* EXYNOS_MIPI_PHY_ID_DSIM0 */
183 .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
184 .enable_val = EXYNOS5_PHY_ENABLE,
185 .enable_reg = EXYNOS5433_MIPI_PHY0_CONTROL,
186 .enable_map = EXYNOS_MIPI_REGMAP_PMU,
187 .resetn_val = BIT(0),
188 .resetn_reg = EXYNOS5433_SYSREG_DISP_MIPI_PHY,
189 .resetn_map = EXYNOS_MIPI_REGMAP_DISP,
190 }, {
191 /* EXYNOS_MIPI_PHY_ID_CSIS1 */
192 .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
193 .enable_val = EXYNOS5_PHY_ENABLE,
194 .enable_reg = EXYNOS5433_MIPI_PHY1_CONTROL,
195 .enable_map = EXYNOS_MIPI_REGMAP_PMU,
196 .resetn_val = BIT(1),
197 .resetn_reg = EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON,
198 .resetn_map = EXYNOS_MIPI_REGMAP_CAM0,
199 }, {
200 /* EXYNOS_MIPI_PHY_ID_DSIM1 */
201 .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
202 .enable_val = EXYNOS5_PHY_ENABLE,
203 .enable_reg = EXYNOS5433_MIPI_PHY1_CONTROL,
204 .enable_map = EXYNOS_MIPI_REGMAP_PMU,
205 .resetn_val = BIT(1),
206 .resetn_reg = EXYNOS5433_SYSREG_DISP_MIPI_PHY,
207 .resetn_map = EXYNOS_MIPI_REGMAP_DISP,
208 }, {
209 /* EXYNOS_MIPI_PHY_ID_CSIS2 */
210 .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
211 .enable_val = EXYNOS5_PHY_ENABLE,
212 .enable_reg = EXYNOS5433_MIPI_PHY2_CONTROL,
213 .enable_map = EXYNOS_MIPI_REGMAP_PMU,
214 .resetn_val = BIT(0),
215 .resetn_reg = EXYNOS5433_SYSREG_CAM1_MIPI_DPHY_CON,
216 .resetn_map = EXYNOS_MIPI_REGMAP_CAM1,
217 },
218 },
219};
99 220
100struct exynos_mipi_video_phy { 221struct exynos_mipi_video_phy {
101 struct regmap *regmaps[EXYNOS_MIPI_REGMAPS_NUM]; 222 struct regmap *regmaps[EXYNOS_MIPI_REGMAPS_NUM];
@@ -241,6 +362,12 @@ static const struct of_device_id exynos_mipi_video_phy_of_match[] = {
241 { 362 {
242 .compatible = "samsung,s5pv210-mipi-video-phy", 363 .compatible = "samsung,s5pv210-mipi-video-phy",
243 .data = &s5pv210_mipi_phy, 364 .data = &s5pv210_mipi_phy,
365 }, {
366 .compatible = "samsung,exynos5420-mipi-video-phy",
367 .data = &exynos5420_mipi_phy,
368 }, {
369 .compatible = "samsung,exynos5433-mipi-video-phy",
370 .data = &exynos5433_mipi_phy,
244 }, 371 },
245 { /* sentinel */ }, 372 { /* sentinel */ },
246}; 373};