PCI: rockchip: Mark RC as common clock architecture

The default value of common clock configuration is zero indicating
Rockchip's RC is using asynchronous clock architecture but actually we are
using common clock.  This will confuse some EP drivers if they need some
different settings referring to this value.

Set the Common Clock Configuration bit in the Link Control Register.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

1 files changed, 6 insertions, 0 deletions

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 36f5eeb530f5..b296808ccc71 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -141,6 +141,7 @@
 #define   PCIE_RC_CONFIG_DCR_CPLS_SHIFT         26
 #define PCIE_RC_CONFIG_LCS              (PCIE_RC_CONFIG_BASE + 0xd0)
 #define   PCIE_RC_CONFIG_LCS_RETRAIN_LINK       BIT(5)
+#define   PCIE_RC_CONFIG_LCS_CCC                BIT(6)
 #define   PCIE_RC_CONFIG_LCS_LBMIE              BIT(10)
 #define   PCIE_RC_CONFIG_LCS_LABIE              BIT(11)
 #define   PCIE_RC_CONFIG_LCS_LBMS               BIT(30)
@@ -577,6 +578,11 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
 
         rockchip_pcie_set_power_limit(rockchip);
 
+        /* Set RC's clock architecture as common clock */
+        status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
+        status |= PCIE_RC_CONFIG_LCS_CCC;
+        rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
+
         /* Enable Gen1 training */
         rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
                             PCIE_CLIENT_CONFIG);