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authorThierry Reding <treding@nvidia.com>2016-11-25 05:57:14 -0500
committerBjorn Helgaas <helgaas@kernel.org>2016-12-07 13:06:33 -0500
commit76245ca2dfa848bf044acccb5f0d1c07f6e42411 (patch)
tree117b6ebf9e8a6f94704b1d5d43e82465017a8689 /drivers/pci
parent528925c4394f69744b88fc6506640fa8b6e6b56b (diff)
PCI: tegra: Implement PCA enable workaround
Tegra210's PCIe controller has a bug that requires the PCA (performance counter) feature to be enabled. If this isn't done, accesses to device configuration space will hang the chip for tens of seconds. Implement the workaround. Based on commit 514e19138af2 ("pci: tegra: implement PCA enable workaround") from U-Boot by Stephen Warren <swarren@nvidia.com>. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/host/pci-tegra.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index d5206fa53353..4bfaac6d3582 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -188,6 +188,9 @@
188#define RP_VEND_XP 0x00000f00 188#define RP_VEND_XP 0x00000f00
189#define RP_VEND_XP_DL_UP (1 << 30) 189#define RP_VEND_XP_DL_UP (1 << 30)
190 190
191#define RP_VEND_CTL2 0x00000fa8
192#define RP_VEND_CTL2_PCA_ENABLE (1 << 7)
193
191#define RP_PRIV_MISC 0x00000fe0 194#define RP_PRIV_MISC 0x00000fe0
192#define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xe << 0) 195#define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xe << 0)
193#define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xf << 0) 196#define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xf << 0)
@@ -252,6 +255,7 @@ struct tegra_pcie_soc {
252 bool has_intr_prsnt_sense; 255 bool has_intr_prsnt_sense;
253 bool has_cml_clk; 256 bool has_cml_clk;
254 bool has_gen2; 257 bool has_gen2;
258 bool force_pca_enable;
255}; 259};
256 260
257static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip) 261static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip)
@@ -556,6 +560,12 @@ static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
556 afi_writel(port->pcie, value, ctrl); 560 afi_writel(port->pcie, value, ctrl);
557 561
558 tegra_pcie_port_reset(port); 562 tegra_pcie_port_reset(port);
563
564 if (soc->force_pca_enable) {
565 value = readl(port->base + RP_VEND_CTL2);
566 value |= RP_VEND_CTL2_PCA_ENABLE;
567 writel(value, port->base + RP_VEND_CTL2);
568 }
559} 569}
560 570
561static void tegra_pcie_port_disable(struct tegra_pcie_port *port) 571static void tegra_pcie_port_disable(struct tegra_pcie_port *port)
@@ -2046,6 +2056,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
2046 .has_intr_prsnt_sense = false, 2056 .has_intr_prsnt_sense = false,
2047 .has_cml_clk = false, 2057 .has_cml_clk = false,
2048 .has_gen2 = false, 2058 .has_gen2 = false,
2059 .force_pca_enable = false,
2049}; 2060};
2050 2061
2051static const struct tegra_pcie_soc tegra30_pcie = { 2062static const struct tegra_pcie_soc tegra30_pcie = {
@@ -2060,6 +2071,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
2060 .has_intr_prsnt_sense = true, 2071 .has_intr_prsnt_sense = true,
2061 .has_cml_clk = true, 2072 .has_cml_clk = true,
2062 .has_gen2 = false, 2073 .has_gen2 = false,
2074 .force_pca_enable = false,
2063}; 2075};
2064 2076
2065static const struct tegra_pcie_soc tegra124_pcie = { 2077static const struct tegra_pcie_soc tegra124_pcie = {
@@ -2073,6 +2085,7 @@ static const struct tegra_pcie_soc tegra124_pcie = {
2073 .has_intr_prsnt_sense = true, 2085 .has_intr_prsnt_sense = true,
2074 .has_cml_clk = true, 2086 .has_cml_clk = true,
2075 .has_gen2 = true, 2087 .has_gen2 = true,
2088 .force_pca_enable = false,
2076}; 2089};
2077 2090
2078static const struct of_device_id tegra_pcie_of_match[] = { 2091static const struct of_device_id tegra_pcie_of_match[] = {