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authorBjorn Helgaas <bhelgaas@google.com>2016-10-12 12:14:58 -0400
committerBjorn Helgaas <bhelgaas@google.com>2016-10-12 12:14:58 -0400
commit22c7e1d4b48f61138a9e81270beaf73e98099adf (patch)
treefc570fe0b5031dee9b315903c44afb890f92c617 /drivers/pci
parentdd5bba52d3efe13ea43ca95d72f2ed2cd3f1e612 (diff)
parent4c9441d1e64c0ce224771d0985fabd75690a6d53 (diff)
Merge branch 'pci/host-designware' into next
* pci/host-designware: PCI: designware-plat: Remove unused platform data PCI: designware-plat: Add local struct device pointers PCI: designware-plat: Remove redundant dw_plat_pcie.mem_base PCI: designware: Swap order of dw_pcie_writel_unroll() reg/val arguments PCI: designware: Uninline register accessors PCI: designware: Export dw_pcie_readl_rc(), dw_pcie_writel_rc() PCI: designware: Swap order of dw_pcie_writel_rc() reg/val arguments PCI: designware: Simplify pcie_host_ops.readl_rc() and .writel_rc() interfaces PCI: designware: Simplify dw_pcie_readl_unroll(), dw_pcie_writel_unroll() PCI: designware: Rename dw_pcie_valid_config() to dw_pcie_valid_device()
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/host/pci-exynos.c10
-rw-r--r--drivers/pci/host/pcie-designware-plat.c25
-rw-r--r--drivers/pci/host/pcie-designware.c102
-rw-r--r--drivers/pci/host/pcie-designware.h7
4 files changed, 67 insertions, 77 deletions
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index 2e2d7f00b9e8..f559b494f300 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -425,22 +425,20 @@ static void exynos_pcie_enable_interrupts(struct pcie_port *pp)
425 exynos_pcie_msi_init(pp); 425 exynos_pcie_msi_init(pp);
426} 426}
427 427
428static inline u32 exynos_pcie_readl_rc(struct pcie_port *pp, 428static inline u32 exynos_pcie_readl_rc(struct pcie_port *pp, u32 reg)
429 void __iomem *dbi_base)
430{ 429{
431 u32 val; 430 u32 val;
432 431
433 exynos_pcie_sideband_dbi_r_mode(pp, true); 432 exynos_pcie_sideband_dbi_r_mode(pp, true);
434 val = readl(dbi_base); 433 val = readl(pp->dbi_base + reg);
435 exynos_pcie_sideband_dbi_r_mode(pp, false); 434 exynos_pcie_sideband_dbi_r_mode(pp, false);
436 return val; 435 return val;
437} 436}
438 437
439static inline void exynos_pcie_writel_rc(struct pcie_port *pp, 438static inline void exynos_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val)
440 u32 val, void __iomem *dbi_base)
441{ 439{
442 exynos_pcie_sideband_dbi_w_mode(pp, true); 440 exynos_pcie_sideband_dbi_w_mode(pp, true);
443 writel(val, dbi_base); 441 writel(val, pp->dbi_base + reg);
444 exynos_pcie_sideband_dbi_w_mode(pp, false); 442 exynos_pcie_sideband_dbi_w_mode(pp, false);
445} 443}
446 444
diff --git a/drivers/pci/host/pcie-designware-plat.c b/drivers/pci/host/pcie-designware-plat.c
index 17da005497a5..537f58a664fa 100644
--- a/drivers/pci/host/pcie-designware-plat.c
+++ b/drivers/pci/host/pcie-designware-plat.c
@@ -25,8 +25,7 @@
25#include "pcie-designware.h" 25#include "pcie-designware.h"
26 26
27struct dw_plat_pcie { 27struct dw_plat_pcie {
28 void __iomem *mem_base; 28 struct pcie_port pp; /* pp.dbi_base is DT 0th resource */
29 struct pcie_port pp;
30}; 29};
31 30
32static irqreturn_t dw_plat_pcie_msi_irq_handler(int irq, void *arg) 31static irqreturn_t dw_plat_pcie_msi_irq_handler(int irq, void *arg)
@@ -52,6 +51,7 @@ static struct pcie_host_ops dw_plat_pcie_host_ops = {
52static int dw_plat_add_pcie_port(struct pcie_port *pp, 51static int dw_plat_add_pcie_port(struct pcie_port *pp,
53 struct platform_device *pdev) 52 struct platform_device *pdev)
54{ 53{
54 struct device *dev = pp->dev;
55 int ret; 55 int ret;
56 56
57 pp->irq = platform_get_irq(pdev, 1); 57 pp->irq = platform_get_irq(pdev, 1);
@@ -63,11 +63,11 @@ static int dw_plat_add_pcie_port(struct pcie_port *pp,
63 if (pp->msi_irq < 0) 63 if (pp->msi_irq < 0)
64 return pp->msi_irq; 64 return pp->msi_irq;
65 65
66 ret = devm_request_irq(&pdev->dev, pp->msi_irq, 66 ret = devm_request_irq(dev, pp->msi_irq,
67 dw_plat_pcie_msi_irq_handler, 67 dw_plat_pcie_msi_irq_handler,
68 IRQF_SHARED, "dw-plat-pcie-msi", pp); 68 IRQF_SHARED, "dw-plat-pcie-msi", pp);
69 if (ret) { 69 if (ret) {
70 dev_err(&pdev->dev, "failed to request MSI IRQ\n"); 70 dev_err(dev, "failed to request MSI IRQ\n");
71 return ret; 71 return ret;
72 } 72 }
73 } 73 }
@@ -77,7 +77,7 @@ static int dw_plat_add_pcie_port(struct pcie_port *pp,
77 77
78 ret = dw_pcie_host_init(pp); 78 ret = dw_pcie_host_init(pp);
79 if (ret) { 79 if (ret) {
80 dev_err(&pdev->dev, "failed to initialize host\n"); 80 dev_err(dev, "failed to initialize host\n");
81 return ret; 81 return ret;
82 } 82 }
83 83
@@ -86,31 +86,28 @@ static int dw_plat_add_pcie_port(struct pcie_port *pp,
86 86
87static int dw_plat_pcie_probe(struct platform_device *pdev) 87static int dw_plat_pcie_probe(struct platform_device *pdev)
88{ 88{
89 struct device *dev = &pdev->dev;
89 struct dw_plat_pcie *dw_plat_pcie; 90 struct dw_plat_pcie *dw_plat_pcie;
90 struct pcie_port *pp; 91 struct pcie_port *pp;
91 struct resource *res; /* Resource from DT */ 92 struct resource *res; /* Resource from DT */
92 int ret; 93 int ret;
93 94
94 dw_plat_pcie = devm_kzalloc(&pdev->dev, sizeof(*dw_plat_pcie), 95 dw_plat_pcie = devm_kzalloc(dev, sizeof(*dw_plat_pcie), GFP_KERNEL);
95 GFP_KERNEL);
96 if (!dw_plat_pcie) 96 if (!dw_plat_pcie)
97 return -ENOMEM; 97 return -ENOMEM;
98 98
99 pp = &dw_plat_pcie->pp; 99 pp = &dw_plat_pcie->pp;
100 pp->dev = &pdev->dev; 100 pp->dev = dev;
101 101
102 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 102 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
103 dw_plat_pcie->mem_base = devm_ioremap_resource(&pdev->dev, res); 103 pp->dbi_base = devm_ioremap_resource(dev, res);
104 if (IS_ERR(dw_plat_pcie->mem_base)) 104 if (IS_ERR(pp->dbi_base))
105 return PTR_ERR(dw_plat_pcie->mem_base); 105 return PTR_ERR(pp->dbi_base);
106
107 pp->dbi_base = dw_plat_pcie->mem_base;
108 106
109 ret = dw_plat_add_pcie_port(pp, pdev); 107 ret = dw_plat_add_pcie_port(pp, pdev);
110 if (ret < 0) 108 if (ret < 0)
111 return ret; 109 return ret;
112 110
113 platform_set_drvdata(pdev, dw_plat_pcie);
114 return 0; 111 return 0;
115} 112}
116 113
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 74da71ea544a..035f50c03281 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -141,41 +141,35 @@ int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val)
141 return PCIBIOS_SUCCESSFUL; 141 return PCIBIOS_SUCCESSFUL;
142} 142}
143 143
144static inline u32 dw_pcie_readl_rc(struct pcie_port *pp, u32 reg) 144u32 dw_pcie_readl_rc(struct pcie_port *pp, u32 reg)
145{ 145{
146 if (pp->ops->readl_rc) 146 if (pp->ops->readl_rc)
147 return pp->ops->readl_rc(pp, pp->dbi_base + reg); 147 return pp->ops->readl_rc(pp, reg);
148 148
149 return readl(pp->dbi_base + reg); 149 return readl(pp->dbi_base + reg);
150} 150}
151 151
152static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg) 152void dw_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val)
153{ 153{
154 if (pp->ops->writel_rc) 154 if (pp->ops->writel_rc)
155 pp->ops->writel_rc(pp, val, pp->dbi_base + reg); 155 pp->ops->writel_rc(pp, reg, val);
156 else 156 else
157 writel(val, pp->dbi_base + reg); 157 writel(val, pp->dbi_base + reg);
158} 158}
159 159
160static inline u32 dw_pcie_readl_unroll(struct pcie_port *pp, u32 index, u32 reg) 160static u32 dw_pcie_readl_unroll(struct pcie_port *pp, u32 index, u32 reg)
161{ 161{
162 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); 162 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
163 163
164 if (pp->ops->readl_rc) 164 return dw_pcie_readl_rc(pp, offset + reg);
165 return pp->ops->readl_rc(pp, pp->dbi_base + offset + reg);
166
167 return readl(pp->dbi_base + offset + reg);
168} 165}
169 166
170static inline void dw_pcie_writel_unroll(struct pcie_port *pp, u32 index, 167static void dw_pcie_writel_unroll(struct pcie_port *pp, u32 index, u32 reg,
171 u32 val, u32 reg) 168 u32 val)
172{ 169{
173 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); 170 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
174 171
175 if (pp->ops->writel_rc) 172 dw_pcie_writel_rc(pp, offset + reg, val);
176 pp->ops->writel_rc(pp, val, pp->dbi_base + offset + reg);
177 else
178 writel(val, pp->dbi_base + offset + reg);
179} 173}
180 174
181static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, 175static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
@@ -202,35 +196,35 @@ static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
202 u32 retries, val; 196 u32 retries, val;
203 197
204 if (pp->iatu_unroll_enabled) { 198 if (pp->iatu_unroll_enabled) {
205 dw_pcie_writel_unroll(pp, index, 199 dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_LOWER_BASE,
206 lower_32_bits(cpu_addr), PCIE_ATU_UNR_LOWER_BASE); 200 lower_32_bits(cpu_addr));
207 dw_pcie_writel_unroll(pp, index, 201 dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_UPPER_BASE,
208 upper_32_bits(cpu_addr), PCIE_ATU_UNR_UPPER_BASE); 202 upper_32_bits(cpu_addr));
209 dw_pcie_writel_unroll(pp, index, 203 dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_LIMIT,
210 lower_32_bits(cpu_addr + size - 1), PCIE_ATU_UNR_LIMIT); 204 lower_32_bits(cpu_addr + size - 1));
211 dw_pcie_writel_unroll(pp, index, 205 dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_LOWER_TARGET,
212 lower_32_bits(pci_addr), PCIE_ATU_UNR_LOWER_TARGET); 206 lower_32_bits(pci_addr));
213 dw_pcie_writel_unroll(pp, index, 207 dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_UPPER_TARGET,
214 upper_32_bits(pci_addr), PCIE_ATU_UNR_UPPER_TARGET); 208 upper_32_bits(pci_addr));
215 dw_pcie_writel_unroll(pp, index, 209 dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_REGION_CTRL1,
216 type, PCIE_ATU_UNR_REGION_CTRL1); 210 type);
217 dw_pcie_writel_unroll(pp, index, 211 dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_REGION_CTRL2,
218 PCIE_ATU_ENABLE, PCIE_ATU_UNR_REGION_CTRL2); 212 PCIE_ATU_ENABLE);
219 } else { 213 } else {
220 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index, 214 dw_pcie_writel_rc(pp, PCIE_ATU_VIEWPORT,
221 PCIE_ATU_VIEWPORT); 215 PCIE_ATU_REGION_OUTBOUND | index);
222 dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr), 216 dw_pcie_writel_rc(pp, PCIE_ATU_LOWER_BASE,
223 PCIE_ATU_LOWER_BASE); 217 lower_32_bits(cpu_addr));
224 dw_pcie_writel_rc(pp, upper_32_bits(cpu_addr), 218 dw_pcie_writel_rc(pp, PCIE_ATU_UPPER_BASE,
225 PCIE_ATU_UPPER_BASE); 219 upper_32_bits(cpu_addr));
226 dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr + size - 1), 220 dw_pcie_writel_rc(pp, PCIE_ATU_LIMIT,
227 PCIE_ATU_LIMIT); 221 lower_32_bits(cpu_addr + size - 1));
228 dw_pcie_writel_rc(pp, lower_32_bits(pci_addr), 222 dw_pcie_writel_rc(pp, PCIE_ATU_LOWER_TARGET,
229 PCIE_ATU_LOWER_TARGET); 223 lower_32_bits(pci_addr));
230 dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), 224 dw_pcie_writel_rc(pp, PCIE_ATU_UPPER_TARGET,
231 PCIE_ATU_UPPER_TARGET); 225 upper_32_bits(pci_addr));
232 dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1); 226 dw_pcie_writel_rc(pp, PCIE_ATU_CR1, type);
233 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); 227 dw_pcie_writel_rc(pp, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
234 } 228 }
235 229
236 /* 230 /*
@@ -760,8 +754,8 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
760 return ret; 754 return ret;
761} 755}
762 756
763static int dw_pcie_valid_config(struct pcie_port *pp, 757static int dw_pcie_valid_device(struct pcie_port *pp, struct pci_bus *bus,
764 struct pci_bus *bus, int dev) 758 int dev)
765{ 759{
766 /* If there is no link, then there is no device */ 760 /* If there is no link, then there is no device */
767 if (bus->number != pp->root_bus_nr) { 761 if (bus->number != pp->root_bus_nr) {
@@ -781,7 +775,7 @@ static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
781{ 775{
782 struct pcie_port *pp = bus->sysdata; 776 struct pcie_port *pp = bus->sysdata;
783 777
784 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) { 778 if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn))) {
785 *val = 0xffffffff; 779 *val = 0xffffffff;
786 return PCIBIOS_DEVICE_NOT_FOUND; 780 return PCIBIOS_DEVICE_NOT_FOUND;
787 } 781 }
@@ -797,7 +791,7 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
797{ 791{
798 struct pcie_port *pp = bus->sysdata; 792 struct pcie_port *pp = bus->sysdata;
799 793
800 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) 794 if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn)))
801 return PCIBIOS_DEVICE_NOT_FOUND; 795 return PCIBIOS_DEVICE_NOT_FOUND;
802 796
803 if (bus->number == pp->root_bus_nr) 797 if (bus->number == pp->root_bus_nr)
@@ -835,7 +829,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
835 dev_err(pp->dev, "num-lanes %u: invalid value\n", pp->lanes); 829 dev_err(pp->dev, "num-lanes %u: invalid value\n", pp->lanes);
836 return; 830 return;
837 } 831 }
838 dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL); 832 dw_pcie_writel_rc(pp, PCIE_PORT_LINK_CONTROL, val);
839 833
840 /* set link width speed control register */ 834 /* set link width speed control register */
841 val = dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL); 835 val = dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL);
@@ -854,30 +848,30 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
854 val |= PORT_LOGIC_LINK_WIDTH_8_LANES; 848 val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
855 break; 849 break;
856 } 850 }
857 dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL); 851 dw_pcie_writel_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
858 852
859 /* setup RC BARs */ 853 /* setup RC BARs */
860 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0); 854 dw_pcie_writel_rc(pp, PCI_BASE_ADDRESS_0, 0x00000004);
861 dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1); 855 dw_pcie_writel_rc(pp, PCI_BASE_ADDRESS_1, 0x00000000);
862 856
863 /* setup interrupt pins */ 857 /* setup interrupt pins */
864 val = dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE); 858 val = dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE);
865 val &= 0xffff00ff; 859 val &= 0xffff00ff;
866 val |= 0x00000100; 860 val |= 0x00000100;
867 dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE); 861 dw_pcie_writel_rc(pp, PCI_INTERRUPT_LINE, val);
868 862
869 /* setup bus numbers */ 863 /* setup bus numbers */
870 val = dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS); 864 val = dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS);
871 val &= 0xff000000; 865 val &= 0xff000000;
872 val |= 0x00010100; 866 val |= 0x00010100;
873 dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS); 867 dw_pcie_writel_rc(pp, PCI_PRIMARY_BUS, val);
874 868
875 /* setup command register */ 869 /* setup command register */
876 val = dw_pcie_readl_rc(pp, PCI_COMMAND); 870 val = dw_pcie_readl_rc(pp, PCI_COMMAND);
877 val &= 0xffff0000; 871 val &= 0xffff0000;
878 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 872 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
879 PCI_COMMAND_MASTER | PCI_COMMAND_SERR; 873 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
880 dw_pcie_writel_rc(pp, val, PCI_COMMAND); 874 dw_pcie_writel_rc(pp, PCI_COMMAND, val);
881 875
882 /* 876 /*
883 * If the platform provides ->rd_other_conf, it means the platform 877 * If the platform provides ->rd_other_conf, it means the platform
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index c8e5bc647f49..a567ea288ee2 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -54,9 +54,8 @@ struct pcie_port {
54}; 54};
55 55
56struct pcie_host_ops { 56struct pcie_host_ops {
57 u32 (*readl_rc)(struct pcie_port *pp, void __iomem *dbi_base); 57 u32 (*readl_rc)(struct pcie_port *pp, u32 reg);
58 void (*writel_rc)(struct pcie_port *pp, 58 void (*writel_rc)(struct pcie_port *pp, u32 reg, u32 val);
59 u32 val, void __iomem *dbi_base);
60 int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val); 59 int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
61 int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val); 60 int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
62 int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus, 61 int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
@@ -73,6 +72,8 @@ struct pcie_host_ops {
73 int (*msi_host_init)(struct pcie_port *pp, struct msi_controller *chip); 72 int (*msi_host_init)(struct pcie_port *pp, struct msi_controller *chip);
74}; 73};
75 74
75u32 dw_pcie_readl_rc(struct pcie_port *pp, u32 reg);
76void dw_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val);
76int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val); 77int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val);
77int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val); 78int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val);
78irqreturn_t dw_handle_msi_irq(struct pcie_port *pp); 79irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-16 09:40:16 -0400