diff options
author | Bogicevic Sasa <brutallesale@gmail.com> | 2015-12-27 16:21:11 -0500 |
---|---|---|
committer | Bjorn Helgaas <bhelgaas@google.com> | 2016-01-08 11:35:24 -0500 |
commit | ff3ce480e8b59fbc0f459476fe1b5451464592a5 (patch) | |
tree | 46500e2528f05508dd8923306368df2855680491 /drivers/pci/hotplug/ibmphp_hpc.c | |
parent | 1d1e8cdc823b9c0ed9b51dffef59b874b0aac808 (diff) |
PCI: Fix all whitespace issues
Fix all whitespace issues (missing or needed whitespace) in all files in
drivers/pci. Code is compiled with allyesconfig before and after code
changes and objects are recorded and checked with objdiff and they are not
changed after this commit.
Signed-off-by: Bogicevic Sasa <brutallesale@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci/hotplug/ibmphp_hpc.c')
-rw-r--r-- | drivers/pci/hotplug/ibmphp_hpc.c | 386 |
1 files changed, 193 insertions, 193 deletions
diff --git a/drivers/pci/hotplug/ibmphp_hpc.c b/drivers/pci/hotplug/ibmphp_hpc.c index 220876715a08..035425adb24e 100644 --- a/drivers/pci/hotplug/ibmphp_hpc.c +++ b/drivers/pci/hotplug/ibmphp_hpc.c | |||
@@ -40,7 +40,7 @@ | |||
40 | #include "ibmphp.h" | 40 | #include "ibmphp.h" |
41 | 41 | ||
42 | static int to_debug = 0; | 42 | static int to_debug = 0; |
43 | #define debug_polling(fmt, arg...) do { if (to_debug) debug (fmt, arg); } while (0) | 43 | #define debug_polling(fmt, arg...) do { if (to_debug) debug(fmt, arg); } while (0) |
44 | 44 | ||
45 | //---------------------------------------------------------------------------- | 45 | //---------------------------------------------------------------------------- |
46 | // timeout values | 46 | // timeout values |
@@ -110,16 +110,16 @@ static struct task_struct *ibmphp_poll_thread; | |||
110 | //---------------------------------------------------------------------------- | 110 | //---------------------------------------------------------------------------- |
111 | // local function prototypes | 111 | // local function prototypes |
112 | //---------------------------------------------------------------------------- | 112 | //---------------------------------------------------------------------------- |
113 | static u8 i2c_ctrl_read (struct controller *, void __iomem *, u8); | 113 | static u8 i2c_ctrl_read(struct controller *, void __iomem *, u8); |
114 | static u8 i2c_ctrl_write (struct controller *, void __iomem *, u8, u8); | 114 | static u8 i2c_ctrl_write(struct controller *, void __iomem *, u8, u8); |
115 | static u8 hpc_writecmdtoindex (u8, u8); | 115 | static u8 hpc_writecmdtoindex(u8, u8); |
116 | static u8 hpc_readcmdtoindex (u8, u8); | 116 | static u8 hpc_readcmdtoindex(u8, u8); |
117 | static void get_hpc_access (void); | 117 | static void get_hpc_access(void); |
118 | static void free_hpc_access (void); | 118 | static void free_hpc_access(void); |
119 | static int poll_hpc(void *data); | 119 | static int poll_hpc(void *data); |
120 | static int process_changeinstatus (struct slot *, struct slot *); | 120 | static int process_changeinstatus(struct slot *, struct slot *); |
121 | static int process_changeinlatch (u8, u8, struct controller *); | 121 | static int process_changeinlatch(u8, u8, struct controller *); |
122 | static int hpc_wait_ctlr_notworking (int, struct controller *, void __iomem *, u8 *); | 122 | static int hpc_wait_ctlr_notworking(int, struct controller *, void __iomem *, u8 *); |
123 | //---------------------------------------------------------------------------- | 123 | //---------------------------------------------------------------------------- |
124 | 124 | ||
125 | 125 | ||
@@ -128,16 +128,16 @@ static int hpc_wait_ctlr_notworking (int, struct controller *, void __iomem *, u | |||
128 | * | 128 | * |
129 | * Action: initialize semaphores and variables | 129 | * Action: initialize semaphores and variables |
130 | *---------------------------------------------------------------------*/ | 130 | *---------------------------------------------------------------------*/ |
131 | void __init ibmphp_hpc_initvars (void) | 131 | void __init ibmphp_hpc_initvars(void) |
132 | { | 132 | { |
133 | debug ("%s - Entry\n", __func__); | 133 | debug("%s - Entry\n", __func__); |
134 | 134 | ||
135 | mutex_init(&sem_hpcaccess); | 135 | mutex_init(&sem_hpcaccess); |
136 | sema_init(&semOperations, 1); | 136 | sema_init(&semOperations, 1); |
137 | sema_init(&sem_exit, 0); | 137 | sema_init(&sem_exit, 0); |
138 | to_debug = 0; | 138 | to_debug = 0; |
139 | 139 | ||
140 | debug ("%s - Exit\n", __func__); | 140 | debug("%s - Exit\n", __func__); |
141 | } | 141 | } |
142 | 142 | ||
143 | /*---------------------------------------------------------------------- | 143 | /*---------------------------------------------------------------------- |
@@ -146,7 +146,7 @@ void __init ibmphp_hpc_initvars (void) | |||
146 | * Action: read from HPC over I2C | 146 | * Action: read from HPC over I2C |
147 | * | 147 | * |
148 | *---------------------------------------------------------------------*/ | 148 | *---------------------------------------------------------------------*/ |
149 | static u8 i2c_ctrl_read (struct controller *ctlr_ptr, void __iomem *WPGBbar, u8 index) | 149 | static u8 i2c_ctrl_read(struct controller *ctlr_ptr, void __iomem *WPGBbar, u8 index) |
150 | { | 150 | { |
151 | u8 status; | 151 | u8 status; |
152 | int i; | 152 | int i; |
@@ -155,7 +155,7 @@ static u8 i2c_ctrl_read (struct controller *ctlr_ptr, void __iomem *WPGBbar, u8 | |||
155 | unsigned long ultemp; | 155 | unsigned long ultemp; |
156 | unsigned long data; // actual data HILO format | 156 | unsigned long data; // actual data HILO format |
157 | 157 | ||
158 | debug_polling ("%s - Entry WPGBbar[%p] index[%x] \n", __func__, WPGBbar, index); | 158 | debug_polling("%s - Entry WPGBbar[%p] index[%x] \n", __func__, WPGBbar, index); |
159 | 159 | ||
160 | //-------------------------------------------------------------------- | 160 | //-------------------------------------------------------------------- |
161 | // READ - step 1 | 161 | // READ - step 1 |
@@ -178,28 +178,28 @@ static u8 i2c_ctrl_read (struct controller *ctlr_ptr, void __iomem *WPGBbar, u8 | |||
178 | ultemp = ultemp << 8; | 178 | ultemp = ultemp << 8; |
179 | data |= ultemp; | 179 | data |= ultemp; |
180 | } else { | 180 | } else { |
181 | err ("this controller type is not supported \n"); | 181 | err("this controller type is not supported \n"); |
182 | return HPC_ERROR; | 182 | return HPC_ERROR; |
183 | } | 183 | } |
184 | 184 | ||
185 | wpg_data = swab32 (data); // swap data before writing | 185 | wpg_data = swab32(data); // swap data before writing |
186 | wpg_addr = WPGBbar + WPG_I2CMOSUP_OFFSET; | 186 | wpg_addr = WPGBbar + WPG_I2CMOSUP_OFFSET; |
187 | writel (wpg_data, wpg_addr); | 187 | writel(wpg_data, wpg_addr); |
188 | 188 | ||
189 | //-------------------------------------------------------------------- | 189 | //-------------------------------------------------------------------- |
190 | // READ - step 2 : clear the message buffer | 190 | // READ - step 2 : clear the message buffer |
191 | data = 0x00000000; | 191 | data = 0x00000000; |
192 | wpg_data = swab32 (data); | 192 | wpg_data = swab32(data); |
193 | wpg_addr = WPGBbar + WPG_I2CMBUFL_OFFSET; | 193 | wpg_addr = WPGBbar + WPG_I2CMBUFL_OFFSET; |
194 | writel (wpg_data, wpg_addr); | 194 | writel(wpg_data, wpg_addr); |
195 | 195 | ||
196 | //-------------------------------------------------------------------- | 196 | //-------------------------------------------------------------------- |
197 | // READ - step 3 : issue start operation, I2C master control bit 30:ON | 197 | // READ - step 3 : issue start operation, I2C master control bit 30:ON |
198 | // 2020 : [20] OR operation at [20] offset 0x20 | 198 | // 2020 : [20] OR operation at [20] offset 0x20 |
199 | data = WPG_I2CMCNTL_STARTOP_MASK; | 199 | data = WPG_I2CMCNTL_STARTOP_MASK; |
200 | wpg_data = swab32 (data); | 200 | wpg_data = swab32(data); |
201 | wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET + WPG_I2C_OR; | 201 | wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET + WPG_I2C_OR; |
202 | writel (wpg_data, wpg_addr); | 202 | writel(wpg_data, wpg_addr); |
203 | 203 | ||
204 | //-------------------------------------------------------------------- | 204 | //-------------------------------------------------------------------- |
205 | // READ - step 4 : wait until start operation bit clears | 205 | // READ - step 4 : wait until start operation bit clears |
@@ -207,14 +207,14 @@ static u8 i2c_ctrl_read (struct controller *ctlr_ptr, void __iomem *WPGBbar, u8 | |||
207 | while (i) { | 207 | while (i) { |
208 | msleep(10); | 208 | msleep(10); |
209 | wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET; | 209 | wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET; |
210 | wpg_data = readl (wpg_addr); | 210 | wpg_data = readl(wpg_addr); |
211 | data = swab32 (wpg_data); | 211 | data = swab32(wpg_data); |
212 | if (!(data & WPG_I2CMCNTL_STARTOP_MASK)) | 212 | if (!(data & WPG_I2CMCNTL_STARTOP_MASK)) |
213 | break; | 213 | break; |
214 | i--; | 214 | i--; |
215 | } | 215 | } |
216 | if (i == 0) { | 216 | if (i == 0) { |
217 | debug ("%s - Error : WPG timeout\n", __func__); | 217 | debug("%s - Error : WPG timeout\n", __func__); |
218 | return HPC_ERROR; | 218 | return HPC_ERROR; |
219 | } | 219 | } |
220 | //-------------------------------------------------------------------- | 220 | //-------------------------------------------------------------------- |
@@ -223,26 +223,26 @@ static u8 i2c_ctrl_read (struct controller *ctlr_ptr, void __iomem *WPGBbar, u8 | |||
223 | while (i) { | 223 | while (i) { |
224 | msleep(10); | 224 | msleep(10); |
225 | wpg_addr = WPGBbar + WPG_I2CSTAT_OFFSET; | 225 | wpg_addr = WPGBbar + WPG_I2CSTAT_OFFSET; |
226 | wpg_data = readl (wpg_addr); | 226 | wpg_data = readl(wpg_addr); |
227 | data = swab32 (wpg_data); | 227 | data = swab32(wpg_data); |
228 | if (HPC_I2CSTATUS_CHECK (data)) | 228 | if (HPC_I2CSTATUS_CHECK(data)) |
229 | break; | 229 | break; |
230 | i--; | 230 | i--; |
231 | } | 231 | } |
232 | if (i == 0) { | 232 | if (i == 0) { |
233 | debug ("ctrl_read - Exit Error:I2C timeout\n"); | 233 | debug("ctrl_read - Exit Error:I2C timeout\n"); |
234 | return HPC_ERROR; | 234 | return HPC_ERROR; |
235 | } | 235 | } |
236 | 236 | ||
237 | //-------------------------------------------------------------------- | 237 | //-------------------------------------------------------------------- |
238 | // READ - step 6 : get DATA | 238 | // READ - step 6 : get DATA |
239 | wpg_addr = WPGBbar + WPG_I2CMBUFL_OFFSET; | 239 | wpg_addr = WPGBbar + WPG_I2CMBUFL_OFFSET; |
240 | wpg_data = readl (wpg_addr); | 240 | wpg_data = readl(wpg_addr); |
241 | data = swab32 (wpg_data); | 241 | data = swab32(wpg_data); |
242 | 242 | ||
243 | status = (u8) data; | 243 | status = (u8) data; |
244 | 244 | ||
245 | debug_polling ("%s - Exit index[%x] status[%x]\n", __func__, index, status); | 245 | debug_polling("%s - Exit index[%x] status[%x]\n", __func__, index, status); |
246 | 246 | ||
247 | return (status); | 247 | return (status); |
248 | } | 248 | } |
@@ -254,7 +254,7 @@ static u8 i2c_ctrl_read (struct controller *ctlr_ptr, void __iomem *WPGBbar, u8 | |||
254 | * | 254 | * |
255 | * Return 0 or error codes | 255 | * Return 0 or error codes |
256 | *---------------------------------------------------------------------*/ | 256 | *---------------------------------------------------------------------*/ |
257 | static u8 i2c_ctrl_write (struct controller *ctlr_ptr, void __iomem *WPGBbar, u8 index, u8 cmd) | 257 | static u8 i2c_ctrl_write(struct controller *ctlr_ptr, void __iomem *WPGBbar, u8 index, u8 cmd) |
258 | { | 258 | { |
259 | u8 rc; | 259 | u8 rc; |
260 | void __iomem *wpg_addr; // base addr + offset | 260 | void __iomem *wpg_addr; // base addr + offset |
@@ -263,7 +263,7 @@ static u8 i2c_ctrl_write (struct controller *ctlr_ptr, void __iomem *WPGBbar, u8 | |||
263 | unsigned long data; // actual data HILO format | 263 | unsigned long data; // actual data HILO format |
264 | int i; | 264 | int i; |
265 | 265 | ||
266 | debug_polling ("%s - Entry WPGBbar[%p] index[%x] cmd[%x]\n", __func__, WPGBbar, index, cmd); | 266 | debug_polling("%s - Entry WPGBbar[%p] index[%x] cmd[%x]\n", __func__, WPGBbar, index, cmd); |
267 | 267 | ||
268 | rc = 0; | 268 | rc = 0; |
269 | //-------------------------------------------------------------------- | 269 | //-------------------------------------------------------------------- |
@@ -289,28 +289,28 @@ static u8 i2c_ctrl_write (struct controller *ctlr_ptr, void __iomem *WPGBbar, u8 | |||
289 | ultemp = ultemp << 8; | 289 | ultemp = ultemp << 8; |
290 | data |= ultemp; | 290 | data |= ultemp; |
291 | } else { | 291 | } else { |
292 | err ("this controller type is not supported \n"); | 292 | err("this controller type is not supported \n"); |
293 | return HPC_ERROR; | 293 | return HPC_ERROR; |
294 | } | 294 | } |
295 | 295 | ||
296 | wpg_data = swab32 (data); // swap data before writing | 296 | wpg_data = swab32(data); // swap data before writing |
297 | wpg_addr = WPGBbar + WPG_I2CMOSUP_OFFSET; | 297 | wpg_addr = WPGBbar + WPG_I2CMOSUP_OFFSET; |
298 | writel (wpg_data, wpg_addr); | 298 | writel(wpg_data, wpg_addr); |
299 | 299 | ||
300 | //-------------------------------------------------------------------- | 300 | //-------------------------------------------------------------------- |
301 | // WRITE - step 2 : clear the message buffer | 301 | // WRITE - step 2 : clear the message buffer |
302 | data = 0x00000000 | (unsigned long)cmd; | 302 | data = 0x00000000 | (unsigned long)cmd; |
303 | wpg_data = swab32 (data); | 303 | wpg_data = swab32(data); |
304 | wpg_addr = WPGBbar + WPG_I2CMBUFL_OFFSET; | 304 | wpg_addr = WPGBbar + WPG_I2CMBUFL_OFFSET; |
305 | writel (wpg_data, wpg_addr); | 305 | writel(wpg_data, wpg_addr); |
306 | 306 | ||
307 | //-------------------------------------------------------------------- | 307 | //-------------------------------------------------------------------- |
308 | // WRITE - step 3 : issue start operation,I2C master control bit 30:ON | 308 | // WRITE - step 3 : issue start operation,I2C master control bit 30:ON |
309 | // 2020 : [20] OR operation at [20] offset 0x20 | 309 | // 2020 : [20] OR operation at [20] offset 0x20 |
310 | data = WPG_I2CMCNTL_STARTOP_MASK; | 310 | data = WPG_I2CMCNTL_STARTOP_MASK; |
311 | wpg_data = swab32 (data); | 311 | wpg_data = swab32(data); |
312 | wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET + WPG_I2C_OR; | 312 | wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET + WPG_I2C_OR; |
313 | writel (wpg_data, wpg_addr); | 313 | writel(wpg_data, wpg_addr); |
314 | 314 | ||
315 | //-------------------------------------------------------------------- | 315 | //-------------------------------------------------------------------- |
316 | // WRITE - step 4 : wait until start operation bit clears | 316 | // WRITE - step 4 : wait until start operation bit clears |
@@ -318,14 +318,14 @@ static u8 i2c_ctrl_write (struct controller *ctlr_ptr, void __iomem *WPGBbar, u8 | |||
318 | while (i) { | 318 | while (i) { |
319 | msleep(10); | 319 | msleep(10); |
320 | wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET; | 320 | wpg_addr = WPGBbar + WPG_I2CMCNTL_OFFSET; |
321 | wpg_data = readl (wpg_addr); | 321 | wpg_data = readl(wpg_addr); |
322 | data = swab32 (wpg_data); | 322 | data = swab32(wpg_data); |
323 | if (!(data & WPG_I2CMCNTL_STARTOP_MASK)) | 323 | if (!(data & WPG_I2CMCNTL_STARTOP_MASK)) |
324 | break; | 324 | break; |
325 | i--; | 325 | i--; |
326 | } | 326 | } |
327 | if (i == 0) { | 327 | if (i == 0) { |
328 | debug ("%s - Exit Error:WPG timeout\n", __func__); | 328 | debug("%s - Exit Error:WPG timeout\n", __func__); |
329 | rc = HPC_ERROR; | 329 | rc = HPC_ERROR; |
330 | } | 330 | } |
331 | 331 | ||
@@ -335,25 +335,25 @@ static u8 i2c_ctrl_write (struct controller *ctlr_ptr, void __iomem *WPGBbar, u8 | |||
335 | while (i) { | 335 | while (i) { |
336 | msleep(10); | 336 | msleep(10); |
337 | wpg_addr = WPGBbar + WPG_I2CSTAT_OFFSET; | 337 | wpg_addr = WPGBbar + WPG_I2CSTAT_OFFSET; |
338 | wpg_data = readl (wpg_addr); | 338 | wpg_data = readl(wpg_addr); |
339 | data = swab32 (wpg_data); | 339 | data = swab32(wpg_data); |
340 | if (HPC_I2CSTATUS_CHECK (data)) | 340 | if (HPC_I2CSTATUS_CHECK(data)) |
341 | break; | 341 | break; |
342 | i--; | 342 | i--; |
343 | } | 343 | } |
344 | if (i == 0) { | 344 | if (i == 0) { |
345 | debug ("ctrl_read - Error : I2C timeout\n"); | 345 | debug("ctrl_read - Error : I2C timeout\n"); |
346 | rc = HPC_ERROR; | 346 | rc = HPC_ERROR; |
347 | } | 347 | } |
348 | 348 | ||
349 | debug_polling ("%s Exit rc[%x]\n", __func__, rc); | 349 | debug_polling("%s Exit rc[%x]\n", __func__, rc); |
350 | return (rc); | 350 | return (rc); |
351 | } | 351 | } |
352 | 352 | ||
353 | //------------------------------------------------------------ | 353 | //------------------------------------------------------------ |
354 | // Read from ISA type HPC | 354 | // Read from ISA type HPC |
355 | //------------------------------------------------------------ | 355 | //------------------------------------------------------------ |
356 | static u8 isa_ctrl_read (struct controller *ctlr_ptr, u8 offset) | 356 | static u8 isa_ctrl_read(struct controller *ctlr_ptr, u8 offset) |
357 | { | 357 | { |
358 | u16 start_address; | 358 | u16 start_address; |
359 | u16 end_address; | 359 | u16 end_address; |
@@ -361,56 +361,56 @@ static u8 isa_ctrl_read (struct controller *ctlr_ptr, u8 offset) | |||
361 | 361 | ||
362 | start_address = ctlr_ptr->u.isa_ctlr.io_start; | 362 | start_address = ctlr_ptr->u.isa_ctlr.io_start; |
363 | end_address = ctlr_ptr->u.isa_ctlr.io_end; | 363 | end_address = ctlr_ptr->u.isa_ctlr.io_end; |
364 | data = inb (start_address + offset); | 364 | data = inb(start_address + offset); |
365 | return data; | 365 | return data; |
366 | } | 366 | } |
367 | 367 | ||
368 | //-------------------------------------------------------------- | 368 | //-------------------------------------------------------------- |
369 | // Write to ISA type HPC | 369 | // Write to ISA type HPC |
370 | //-------------------------------------------------------------- | 370 | //-------------------------------------------------------------- |
371 | static void isa_ctrl_write (struct controller *ctlr_ptr, u8 offset, u8 data) | 371 | static void isa_ctrl_write(struct controller *ctlr_ptr, u8 offset, u8 data) |
372 | { | 372 | { |
373 | u16 start_address; | 373 | u16 start_address; |
374 | u16 port_address; | 374 | u16 port_address; |
375 | 375 | ||
376 | start_address = ctlr_ptr->u.isa_ctlr.io_start; | 376 | start_address = ctlr_ptr->u.isa_ctlr.io_start; |
377 | port_address = start_address + (u16) offset; | 377 | port_address = start_address + (u16) offset; |
378 | outb (data, port_address); | 378 | outb(data, port_address); |
379 | } | 379 | } |
380 | 380 | ||
381 | static u8 pci_ctrl_read (struct controller *ctrl, u8 offset) | 381 | static u8 pci_ctrl_read(struct controller *ctrl, u8 offset) |
382 | { | 382 | { |
383 | u8 data = 0x00; | 383 | u8 data = 0x00; |
384 | debug ("inside pci_ctrl_read\n"); | 384 | debug("inside pci_ctrl_read\n"); |
385 | if (ctrl->ctrl_dev) | 385 | if (ctrl->ctrl_dev) |
386 | pci_read_config_byte (ctrl->ctrl_dev, HPC_PCI_OFFSET + offset, &data); | 386 | pci_read_config_byte(ctrl->ctrl_dev, HPC_PCI_OFFSET + offset, &data); |
387 | return data; | 387 | return data; |
388 | } | 388 | } |
389 | 389 | ||
390 | static u8 pci_ctrl_write (struct controller *ctrl, u8 offset, u8 data) | 390 | static u8 pci_ctrl_write(struct controller *ctrl, u8 offset, u8 data) |
391 | { | 391 | { |
392 | u8 rc = -ENODEV; | 392 | u8 rc = -ENODEV; |
393 | debug ("inside pci_ctrl_write\n"); | 393 | debug("inside pci_ctrl_write\n"); |
394 | if (ctrl->ctrl_dev) { | 394 | if (ctrl->ctrl_dev) { |
395 | pci_write_config_byte (ctrl->ctrl_dev, HPC_PCI_OFFSET + offset, data); | 395 | pci_write_config_byte(ctrl->ctrl_dev, HPC_PCI_OFFSET + offset, data); |
396 | rc = 0; | 396 | rc = 0; |
397 | } | 397 | } |
398 | return rc; | 398 | return rc; |
399 | } | 399 | } |
400 | 400 | ||
401 | static u8 ctrl_read (struct controller *ctlr, void __iomem *base, u8 offset) | 401 | static u8 ctrl_read(struct controller *ctlr, void __iomem *base, u8 offset) |
402 | { | 402 | { |
403 | u8 rc; | 403 | u8 rc; |
404 | switch (ctlr->ctlr_type) { | 404 | switch (ctlr->ctlr_type) { |
405 | case 0: | 405 | case 0: |
406 | rc = isa_ctrl_read (ctlr, offset); | 406 | rc = isa_ctrl_read(ctlr, offset); |
407 | break; | 407 | break; |
408 | case 1: | 408 | case 1: |
409 | rc = pci_ctrl_read (ctlr, offset); | 409 | rc = pci_ctrl_read(ctlr, offset); |
410 | break; | 410 | break; |
411 | case 2: | 411 | case 2: |
412 | case 4: | 412 | case 4: |
413 | rc = i2c_ctrl_read (ctlr, base, offset); | 413 | rc = i2c_ctrl_read(ctlr, base, offset); |
414 | break; | 414 | break; |
415 | default: | 415 | default: |
416 | return -ENODEV; | 416 | return -ENODEV; |
@@ -418,7 +418,7 @@ static u8 ctrl_read (struct controller *ctlr, void __iomem *base, u8 offset) | |||
418 | return rc; | 418 | return rc; |
419 | } | 419 | } |
420 | 420 | ||
421 | static u8 ctrl_write (struct controller *ctlr, void __iomem *base, u8 offset, u8 data) | 421 | static u8 ctrl_write(struct controller *ctlr, void __iomem *base, u8 offset, u8 data) |
422 | { | 422 | { |
423 | u8 rc = 0; | 423 | u8 rc = 0; |
424 | switch (ctlr->ctlr_type) { | 424 | switch (ctlr->ctlr_type) { |
@@ -426,7 +426,7 @@ static u8 ctrl_write (struct controller *ctlr, void __iomem *base, u8 offset, u8 | |||
426 | isa_ctrl_write(ctlr, offset, data); | 426 | isa_ctrl_write(ctlr, offset, data); |
427 | break; | 427 | break; |
428 | case 1: | 428 | case 1: |
429 | rc = pci_ctrl_write (ctlr, offset, data); | 429 | rc = pci_ctrl_write(ctlr, offset, data); |
430 | break; | 430 | break; |
431 | case 2: | 431 | case 2: |
432 | case 4: | 432 | case 4: |
@@ -444,7 +444,7 @@ static u8 ctrl_write (struct controller *ctlr, void __iomem *base, u8 offset, u8 | |||
444 | * | 444 | * |
445 | * Return index, HPC_ERROR | 445 | * Return index, HPC_ERROR |
446 | *---------------------------------------------------------------------*/ | 446 | *---------------------------------------------------------------------*/ |
447 | static u8 hpc_writecmdtoindex (u8 cmd, u8 index) | 447 | static u8 hpc_writecmdtoindex(u8 cmd, u8 index) |
448 | { | 448 | { |
449 | u8 rc; | 449 | u8 rc; |
450 | 450 | ||
@@ -476,7 +476,7 @@ static u8 hpc_writecmdtoindex (u8 cmd, u8 index) | |||
476 | break; | 476 | break; |
477 | 477 | ||
478 | default: | 478 | default: |
479 | err ("hpc_writecmdtoindex - Error invalid cmd[%x]\n", cmd); | 479 | err("hpc_writecmdtoindex - Error invalid cmd[%x]\n", cmd); |
480 | rc = HPC_ERROR; | 480 | rc = HPC_ERROR; |
481 | } | 481 | } |
482 | 482 | ||
@@ -490,7 +490,7 @@ static u8 hpc_writecmdtoindex (u8 cmd, u8 index) | |||
490 | * | 490 | * |
491 | * Return index, HPC_ERROR | 491 | * Return index, HPC_ERROR |
492 | *---------------------------------------------------------------------*/ | 492 | *---------------------------------------------------------------------*/ |
493 | static u8 hpc_readcmdtoindex (u8 cmd, u8 index) | 493 | static u8 hpc_readcmdtoindex(u8 cmd, u8 index) |
494 | { | 494 | { |
495 | u8 rc; | 495 | u8 rc; |
496 | 496 | ||
@@ -533,7 +533,7 @@ static u8 hpc_readcmdtoindex (u8 cmd, u8 index) | |||
533 | * | 533 | * |
534 | * Return 0 or error codes | 534 | * Return 0 or error codes |
535 | *---------------------------------------------------------------------*/ | 535 | *---------------------------------------------------------------------*/ |
536 | int ibmphp_hpc_readslot (struct slot *pslot, u8 cmd, u8 *pstatus) | 536 | int ibmphp_hpc_readslot(struct slot *pslot, u8 cmd, u8 *pstatus) |
537 | { | 537 | { |
538 | void __iomem *wpg_bbar = NULL; | 538 | void __iomem *wpg_bbar = NULL; |
539 | struct controller *ctlr_ptr; | 539 | struct controller *ctlr_ptr; |
@@ -542,69 +542,69 @@ int ibmphp_hpc_readslot (struct slot *pslot, u8 cmd, u8 *pstatus) | |||
542 | int rc = 0; | 542 | int rc = 0; |
543 | int busindex; | 543 | int busindex; |
544 | 544 | ||
545 | debug_polling ("%s - Entry pslot[%p] cmd[%x] pstatus[%p]\n", __func__, pslot, cmd, pstatus); | 545 | debug_polling("%s - Entry pslot[%p] cmd[%x] pstatus[%p]\n", __func__, pslot, cmd, pstatus); |
546 | 546 | ||
547 | if ((pslot == NULL) | 547 | if ((pslot == NULL) |
548 | || ((pstatus == NULL) && (cmd != READ_ALLSTAT) && (cmd != READ_BUSSTATUS))) { | 548 | || ((pstatus == NULL) && (cmd != READ_ALLSTAT) && (cmd != READ_BUSSTATUS))) { |
549 | rc = -EINVAL; | 549 | rc = -EINVAL; |
550 | err ("%s - Error invalid pointer, rc[%d]\n", __func__, rc); | 550 | err("%s - Error invalid pointer, rc[%d]\n", __func__, rc); |
551 | return rc; | 551 | return rc; |
552 | } | 552 | } |
553 | 553 | ||
554 | if (cmd == READ_BUSSTATUS) { | 554 | if (cmd == READ_BUSSTATUS) { |
555 | busindex = ibmphp_get_bus_index (pslot->bus); | 555 | busindex = ibmphp_get_bus_index(pslot->bus); |
556 | if (busindex < 0) { | 556 | if (busindex < 0) { |
557 | rc = -EINVAL; | 557 | rc = -EINVAL; |
558 | err ("%s - Exit Error:invalid bus, rc[%d]\n", __func__, rc); | 558 | err("%s - Exit Error:invalid bus, rc[%d]\n", __func__, rc); |
559 | return rc; | 559 | return rc; |
560 | } else | 560 | } else |
561 | index = (u8) busindex; | 561 | index = (u8) busindex; |
562 | } else | 562 | } else |
563 | index = pslot->ctlr_index; | 563 | index = pslot->ctlr_index; |
564 | 564 | ||
565 | index = hpc_readcmdtoindex (cmd, index); | 565 | index = hpc_readcmdtoindex(cmd, index); |
566 | 566 | ||
567 | if (index == HPC_ERROR) { | 567 | if (index == HPC_ERROR) { |
568 | rc = -EINVAL; | 568 | rc = -EINVAL; |
569 | err ("%s - Exit Error:invalid index, rc[%d]\n", __func__, rc); | 569 | err("%s - Exit Error:invalid index, rc[%d]\n", __func__, rc); |
570 | return rc; | 570 | return rc; |
571 | } | 571 | } |
572 | 572 | ||
573 | ctlr_ptr = pslot->ctrl; | 573 | ctlr_ptr = pslot->ctrl; |
574 | 574 | ||
575 | get_hpc_access (); | 575 | get_hpc_access(); |
576 | 576 | ||
577 | //-------------------------------------------------------------------- | 577 | //-------------------------------------------------------------------- |
578 | // map physical address to logical address | 578 | // map physical address to logical address |
579 | //-------------------------------------------------------------------- | 579 | //-------------------------------------------------------------------- |
580 | if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4)) | 580 | if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4)) |
581 | wpg_bbar = ioremap (ctlr_ptr->u.wpeg_ctlr.wpegbbar, WPG_I2C_IOREMAP_SIZE); | 581 | wpg_bbar = ioremap(ctlr_ptr->u.wpeg_ctlr.wpegbbar, WPG_I2C_IOREMAP_SIZE); |
582 | 582 | ||
583 | //-------------------------------------------------------------------- | 583 | //-------------------------------------------------------------------- |
584 | // check controller status before reading | 584 | // check controller status before reading |
585 | //-------------------------------------------------------------------- | 585 | //-------------------------------------------------------------------- |
586 | rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar, &status); | 586 | rc = hpc_wait_ctlr_notworking(HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar, &status); |
587 | if (!rc) { | 587 | if (!rc) { |
588 | switch (cmd) { | 588 | switch (cmd) { |
589 | case READ_ALLSTAT: | 589 | case READ_ALLSTAT: |
590 | // update the slot structure | 590 | // update the slot structure |
591 | pslot->ctrl->status = status; | 591 | pslot->ctrl->status = status; |
592 | pslot->status = ctrl_read (ctlr_ptr, wpg_bbar, index); | 592 | pslot->status = ctrl_read(ctlr_ptr, wpg_bbar, index); |
593 | rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar, | 593 | rc = hpc_wait_ctlr_notworking(HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar, |
594 | &status); | 594 | &status); |
595 | if (!rc) | 595 | if (!rc) |
596 | pslot->ext_status = ctrl_read (ctlr_ptr, wpg_bbar, index + WPG_1ST_EXTSLOT_INDEX); | 596 | pslot->ext_status = ctrl_read(ctlr_ptr, wpg_bbar, index + WPG_1ST_EXTSLOT_INDEX); |
597 | 597 | ||
598 | break; | 598 | break; |
599 | 599 | ||
600 | case READ_SLOTSTATUS: | 600 | case READ_SLOTSTATUS: |
601 | // DO NOT update the slot structure | 601 | // DO NOT update the slot structure |
602 | *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, index); | 602 | *pstatus = ctrl_read(ctlr_ptr, wpg_bbar, index); |
603 | break; | 603 | break; |
604 | 604 | ||
605 | case READ_EXTSLOTSTATUS: | 605 | case READ_EXTSLOTSTATUS: |
606 | // DO NOT update the slot structure | 606 | // DO NOT update the slot structure |
607 | *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, index); | 607 | *pstatus = ctrl_read(ctlr_ptr, wpg_bbar, index); |
608 | break; | 608 | break; |
609 | 609 | ||
610 | case READ_CTLRSTATUS: | 610 | case READ_CTLRSTATUS: |
@@ -613,36 +613,36 @@ int ibmphp_hpc_readslot (struct slot *pslot, u8 cmd, u8 *pstatus) | |||
613 | break; | 613 | break; |
614 | 614 | ||
615 | case READ_BUSSTATUS: | 615 | case READ_BUSSTATUS: |
616 | pslot->busstatus = ctrl_read (ctlr_ptr, wpg_bbar, index); | 616 | pslot->busstatus = ctrl_read(ctlr_ptr, wpg_bbar, index); |
617 | break; | 617 | break; |
618 | case READ_REVLEVEL: | 618 | case READ_REVLEVEL: |
619 | *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, index); | 619 | *pstatus = ctrl_read(ctlr_ptr, wpg_bbar, index); |
620 | break; | 620 | break; |
621 | case READ_HPCOPTIONS: | 621 | case READ_HPCOPTIONS: |
622 | *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, index); | 622 | *pstatus = ctrl_read(ctlr_ptr, wpg_bbar, index); |
623 | break; | 623 | break; |
624 | case READ_SLOTLATCHLOWREG: | 624 | case READ_SLOTLATCHLOWREG: |
625 | // DO NOT update the slot structure | 625 | // DO NOT update the slot structure |
626 | *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, index); | 626 | *pstatus = ctrl_read(ctlr_ptr, wpg_bbar, index); |
627 | break; | 627 | break; |
628 | 628 | ||
629 | // Not used | 629 | // Not used |
630 | case READ_ALLSLOT: | 630 | case READ_ALLSLOT: |
631 | list_for_each (pslotlist, &ibmphp_slot_head) { | 631 | list_for_each(pslotlist, &ibmphp_slot_head) { |
632 | pslot = list_entry (pslotlist, struct slot, ibm_slot_list); | 632 | pslot = list_entry(pslotlist, struct slot, ibm_slot_list); |
633 | index = pslot->ctlr_index; | 633 | index = pslot->ctlr_index; |
634 | rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, ctlr_ptr, | 634 | rc = hpc_wait_ctlr_notworking(HPC_CTLR_WORKING_TOUT, ctlr_ptr, |
635 | wpg_bbar, &status); | 635 | wpg_bbar, &status); |
636 | if (!rc) { | 636 | if (!rc) { |
637 | pslot->status = ctrl_read (ctlr_ptr, wpg_bbar, index); | 637 | pslot->status = ctrl_read(ctlr_ptr, wpg_bbar, index); |
638 | rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, | 638 | rc = hpc_wait_ctlr_notworking(HPC_CTLR_WORKING_TOUT, |
639 | ctlr_ptr, wpg_bbar, &status); | 639 | ctlr_ptr, wpg_bbar, &status); |
640 | if (!rc) | 640 | if (!rc) |
641 | pslot->ext_status = | 641 | pslot->ext_status = |
642 | ctrl_read (ctlr_ptr, wpg_bbar, | 642 | ctrl_read(ctlr_ptr, wpg_bbar, |
643 | index + WPG_1ST_EXTSLOT_INDEX); | 643 | index + WPG_1ST_EXTSLOT_INDEX); |
644 | } else { | 644 | } else { |
645 | err ("%s - Error ctrl_read failed\n", __func__); | 645 | err("%s - Error ctrl_read failed\n", __func__); |
646 | rc = -EINVAL; | 646 | rc = -EINVAL; |
647 | break; | 647 | break; |
648 | } | 648 | } |
@@ -659,11 +659,11 @@ int ibmphp_hpc_readslot (struct slot *pslot, u8 cmd, u8 *pstatus) | |||
659 | 659 | ||
660 | // remove physical to logical address mapping | 660 | // remove physical to logical address mapping |
661 | if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4)) | 661 | if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4)) |
662 | iounmap (wpg_bbar); | 662 | iounmap(wpg_bbar); |
663 | 663 | ||
664 | free_hpc_access (); | 664 | free_hpc_access(); |
665 | 665 | ||
666 | debug_polling ("%s - Exit rc[%d]\n", __func__, rc); | 666 | debug_polling("%s - Exit rc[%d]\n", __func__, rc); |
667 | return rc; | 667 | return rc; |
668 | } | 668 | } |
669 | 669 | ||
@@ -672,7 +672,7 @@ int ibmphp_hpc_readslot (struct slot *pslot, u8 cmd, u8 *pstatus) | |||
672 | * | 672 | * |
673 | * Action: issue a WRITE command to HPC | 673 | * Action: issue a WRITE command to HPC |
674 | *---------------------------------------------------------------------*/ | 674 | *---------------------------------------------------------------------*/ |
675 | int ibmphp_hpc_writeslot (struct slot *pslot, u8 cmd) | 675 | int ibmphp_hpc_writeslot(struct slot *pslot, u8 cmd) |
676 | { | 676 | { |
677 | void __iomem *wpg_bbar = NULL; | 677 | void __iomem *wpg_bbar = NULL; |
678 | struct controller *ctlr_ptr; | 678 | struct controller *ctlr_ptr; |
@@ -682,55 +682,55 @@ int ibmphp_hpc_writeslot (struct slot *pslot, u8 cmd) | |||
682 | int rc = 0; | 682 | int rc = 0; |
683 | int timeout; | 683 | int timeout; |
684 | 684 | ||
685 | debug_polling ("%s - Entry pslot[%p] cmd[%x]\n", __func__, pslot, cmd); | 685 | debug_polling("%s - Entry pslot[%p] cmd[%x]\n", __func__, pslot, cmd); |
686 | if (pslot == NULL) { | 686 | if (pslot == NULL) { |
687 | rc = -EINVAL; | 687 | rc = -EINVAL; |
688 | err ("%s - Error Exit rc[%d]\n", __func__, rc); | 688 | err("%s - Error Exit rc[%d]\n", __func__, rc); |
689 | return rc; | 689 | return rc; |
690 | } | 690 | } |
691 | 691 | ||
692 | if ((cmd == HPC_BUS_33CONVMODE) || (cmd == HPC_BUS_66CONVMODE) || | 692 | if ((cmd == HPC_BUS_33CONVMODE) || (cmd == HPC_BUS_66CONVMODE) || |
693 | (cmd == HPC_BUS_66PCIXMODE) || (cmd == HPC_BUS_100PCIXMODE) || | 693 | (cmd == HPC_BUS_66PCIXMODE) || (cmd == HPC_BUS_100PCIXMODE) || |
694 | (cmd == HPC_BUS_133PCIXMODE)) { | 694 | (cmd == HPC_BUS_133PCIXMODE)) { |
695 | busindex = ibmphp_get_bus_index (pslot->bus); | 695 | busindex = ibmphp_get_bus_index(pslot->bus); |
696 | if (busindex < 0) { | 696 | if (busindex < 0) { |
697 | rc = -EINVAL; | 697 | rc = -EINVAL; |
698 | err ("%s - Exit Error:invalid bus, rc[%d]\n", __func__, rc); | 698 | err("%s - Exit Error:invalid bus, rc[%d]\n", __func__, rc); |
699 | return rc; | 699 | return rc; |
700 | } else | 700 | } else |
701 | index = (u8) busindex; | 701 | index = (u8) busindex; |
702 | } else | 702 | } else |
703 | index = pslot->ctlr_index; | 703 | index = pslot->ctlr_index; |
704 | 704 | ||
705 | index = hpc_writecmdtoindex (cmd, index); | 705 | index = hpc_writecmdtoindex(cmd, index); |
706 | 706 | ||
707 | if (index == HPC_ERROR) { | 707 | if (index == HPC_ERROR) { |
708 | rc = -EINVAL; | 708 | rc = -EINVAL; |
709 | err ("%s - Error Exit rc[%d]\n", __func__, rc); | 709 | err("%s - Error Exit rc[%d]\n", __func__, rc); |
710 | return rc; | 710 | return rc; |
711 | } | 711 | } |
712 | 712 | ||
713 | ctlr_ptr = pslot->ctrl; | 713 | ctlr_ptr = pslot->ctrl; |
714 | 714 | ||
715 | get_hpc_access (); | 715 | get_hpc_access(); |
716 | 716 | ||
717 | //-------------------------------------------------------------------- | 717 | //-------------------------------------------------------------------- |
718 | // map physical address to logical address | 718 | // map physical address to logical address |
719 | //-------------------------------------------------------------------- | 719 | //-------------------------------------------------------------------- |
720 | if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4)) { | 720 | if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4)) { |
721 | wpg_bbar = ioremap (ctlr_ptr->u.wpeg_ctlr.wpegbbar, WPG_I2C_IOREMAP_SIZE); | 721 | wpg_bbar = ioremap(ctlr_ptr->u.wpeg_ctlr.wpegbbar, WPG_I2C_IOREMAP_SIZE); |
722 | 722 | ||
723 | debug ("%s - ctlr id[%x] physical[%lx] logical[%lx] i2c[%x]\n", __func__, | 723 | debug("%s - ctlr id[%x] physical[%lx] logical[%lx] i2c[%x]\n", __func__, |
724 | ctlr_ptr->ctlr_id, (ulong) (ctlr_ptr->u.wpeg_ctlr.wpegbbar), (ulong) wpg_bbar, | 724 | ctlr_ptr->ctlr_id, (ulong) (ctlr_ptr->u.wpeg_ctlr.wpegbbar), (ulong) wpg_bbar, |
725 | ctlr_ptr->u.wpeg_ctlr.i2c_addr); | 725 | ctlr_ptr->u.wpeg_ctlr.i2c_addr); |
726 | } | 726 | } |
727 | //-------------------------------------------------------------------- | 727 | //-------------------------------------------------------------------- |
728 | // check controller status before writing | 728 | // check controller status before writing |
729 | //-------------------------------------------------------------------- | 729 | //-------------------------------------------------------------------- |
730 | rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar, &status); | 730 | rc = hpc_wait_ctlr_notworking(HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar, &status); |
731 | if (!rc) { | 731 | if (!rc) { |
732 | 732 | ||
733 | ctrl_write (ctlr_ptr, wpg_bbar, index, cmd); | 733 | ctrl_write(ctlr_ptr, wpg_bbar, index, cmd); |
734 | 734 | ||
735 | //-------------------------------------------------------------------- | 735 | //-------------------------------------------------------------------- |
736 | // check controller is still not working on the command | 736 | // check controller is still not working on the command |
@@ -738,11 +738,11 @@ int ibmphp_hpc_writeslot (struct slot *pslot, u8 cmd) | |||
738 | timeout = CMD_COMPLETE_TOUT_SEC; | 738 | timeout = CMD_COMPLETE_TOUT_SEC; |
739 | done = 0; | 739 | done = 0; |
740 | while (!done) { | 740 | while (!done) { |
741 | rc = hpc_wait_ctlr_notworking (HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar, | 741 | rc = hpc_wait_ctlr_notworking(HPC_CTLR_WORKING_TOUT, ctlr_ptr, wpg_bbar, |
742 | &status); | 742 | &status); |
743 | if (!rc) { | 743 | if (!rc) { |
744 | if (NEEDTOCHECK_CMDSTATUS (cmd)) { | 744 | if (NEEDTOCHECK_CMDSTATUS(cmd)) { |
745 | if (CTLR_FINISHED (status) == HPC_CTLR_FINISHED_YES) | 745 | if (CTLR_FINISHED(status) == HPC_CTLR_FINISHED_YES) |
746 | done = 1; | 746 | done = 1; |
747 | } else | 747 | } else |
748 | done = 1; | 748 | done = 1; |
@@ -751,7 +751,7 @@ int ibmphp_hpc_writeslot (struct slot *pslot, u8 cmd) | |||
751 | msleep(1000); | 751 | msleep(1000); |
752 | if (timeout < 1) { | 752 | if (timeout < 1) { |
753 | done = 1; | 753 | done = 1; |
754 | err ("%s - Error command complete timeout\n", __func__); | 754 | err("%s - Error command complete timeout\n", __func__); |
755 | rc = -EFAULT; | 755 | rc = -EFAULT; |
756 | } else | 756 | } else |
757 | timeout--; | 757 | timeout--; |
@@ -763,10 +763,10 @@ int ibmphp_hpc_writeslot (struct slot *pslot, u8 cmd) | |||
763 | 763 | ||
764 | // remove physical to logical address mapping | 764 | // remove physical to logical address mapping |
765 | if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4)) | 765 | if ((ctlr_ptr->ctlr_type == 2) || (ctlr_ptr->ctlr_type == 4)) |
766 | iounmap (wpg_bbar); | 766 | iounmap(wpg_bbar); |
767 | free_hpc_access (); | 767 | free_hpc_access(); |
768 | 768 | ||
769 | debug_polling ("%s - Exit rc[%d]\n", __func__, rc); | 769 | debug_polling("%s - Exit rc[%d]\n", __func__, rc); |
770 | return rc; | 770 | return rc; |
771 | } | 771 | } |
772 | 772 | ||
@@ -775,7 +775,7 @@ int ibmphp_hpc_writeslot (struct slot *pslot, u8 cmd) | |||
775 | * | 775 | * |
776 | * Action: make sure only one process can access HPC at one time | 776 | * Action: make sure only one process can access HPC at one time |
777 | *---------------------------------------------------------------------*/ | 777 | *---------------------------------------------------------------------*/ |
778 | static void get_hpc_access (void) | 778 | static void get_hpc_access(void) |
779 | { | 779 | { |
780 | mutex_lock(&sem_hpcaccess); | 780 | mutex_lock(&sem_hpcaccess); |
781 | } | 781 | } |
@@ -783,7 +783,7 @@ static void get_hpc_access (void) | |||
783 | /*---------------------------------------------------------------------- | 783 | /*---------------------------------------------------------------------- |
784 | * Name: free_hpc_access() | 784 | * Name: free_hpc_access() |
785 | *---------------------------------------------------------------------*/ | 785 | *---------------------------------------------------------------------*/ |
786 | void free_hpc_access (void) | 786 | void free_hpc_access(void) |
787 | { | 787 | { |
788 | mutex_unlock(&sem_hpcaccess); | 788 | mutex_unlock(&sem_hpcaccess); |
789 | } | 789 | } |
@@ -793,21 +793,21 @@ void free_hpc_access (void) | |||
793 | * | 793 | * |
794 | * Action: make sure only one process can change the data structure | 794 | * Action: make sure only one process can change the data structure |
795 | *---------------------------------------------------------------------*/ | 795 | *---------------------------------------------------------------------*/ |
796 | void ibmphp_lock_operations (void) | 796 | void ibmphp_lock_operations(void) |
797 | { | 797 | { |
798 | down (&semOperations); | 798 | down(&semOperations); |
799 | to_debug = 1; | 799 | to_debug = 1; |
800 | } | 800 | } |
801 | 801 | ||
802 | /*---------------------------------------------------------------------- | 802 | /*---------------------------------------------------------------------- |
803 | * Name: ibmphp_unlock_operations() | 803 | * Name: ibmphp_unlock_operations() |
804 | *---------------------------------------------------------------------*/ | 804 | *---------------------------------------------------------------------*/ |
805 | void ibmphp_unlock_operations (void) | 805 | void ibmphp_unlock_operations(void) |
806 | { | 806 | { |
807 | debug ("%s - Entry\n", __func__); | 807 | debug("%s - Entry\n", __func__); |
808 | up (&semOperations); | 808 | up(&semOperations); |
809 | to_debug = 0; | 809 | to_debug = 0; |
810 | debug ("%s - Exit\n", __func__); | 810 | debug("%s - Exit\n", __func__); |
811 | } | 811 | } |
812 | 812 | ||
813 | /*---------------------------------------------------------------------- | 813 | /*---------------------------------------------------------------------- |
@@ -828,28 +828,28 @@ static int poll_hpc(void *data) | |||
828 | int poll_count = 0; | 828 | int poll_count = 0; |
829 | u8 ctrl_count = 0x00; | 829 | u8 ctrl_count = 0x00; |
830 | 830 | ||
831 | debug ("%s - Entry\n", __func__); | 831 | debug("%s - Entry\n", __func__); |
832 | 832 | ||
833 | while (!kthread_should_stop()) { | 833 | while (!kthread_should_stop()) { |
834 | /* try to get the lock to do some kind of hardware access */ | 834 | /* try to get the lock to do some kind of hardware access */ |
835 | down (&semOperations); | 835 | down(&semOperations); |
836 | 836 | ||
837 | switch (poll_state) { | 837 | switch (poll_state) { |
838 | case POLL_LATCH_REGISTER: | 838 | case POLL_LATCH_REGISTER: |
839 | oldlatchlow = curlatchlow; | 839 | oldlatchlow = curlatchlow; |
840 | ctrl_count = 0x00; | 840 | ctrl_count = 0x00; |
841 | list_for_each (pslotlist, &ibmphp_slot_head) { | 841 | list_for_each(pslotlist, &ibmphp_slot_head) { |
842 | if (ctrl_count >= ibmphp_get_total_controllers()) | 842 | if (ctrl_count >= ibmphp_get_total_controllers()) |
843 | break; | 843 | break; |
844 | pslot = list_entry (pslotlist, struct slot, ibm_slot_list); | 844 | pslot = list_entry(pslotlist, struct slot, ibm_slot_list); |
845 | if (pslot->ctrl->ctlr_relative_id == ctrl_count) { | 845 | if (pslot->ctrl->ctlr_relative_id == ctrl_count) { |
846 | ctrl_count++; | 846 | ctrl_count++; |
847 | if (READ_SLOT_LATCH (pslot->ctrl)) { | 847 | if (READ_SLOT_LATCH(pslot->ctrl)) { |
848 | rc = ibmphp_hpc_readslot (pslot, | 848 | rc = ibmphp_hpc_readslot(pslot, |
849 | READ_SLOTLATCHLOWREG, | 849 | READ_SLOTLATCHLOWREG, |
850 | &curlatchlow); | 850 | &curlatchlow); |
851 | if (oldlatchlow != curlatchlow) | 851 | if (oldlatchlow != curlatchlow) |
852 | process_changeinlatch (oldlatchlow, | 852 | process_changeinlatch(oldlatchlow, |
853 | curlatchlow, | 853 | curlatchlow, |
854 | pslot->ctrl); | 854 | pslot->ctrl); |
855 | } | 855 | } |
@@ -859,25 +859,25 @@ static int poll_hpc(void *data) | |||
859 | poll_state = POLL_SLEEP; | 859 | poll_state = POLL_SLEEP; |
860 | break; | 860 | break; |
861 | case POLL_SLOTS: | 861 | case POLL_SLOTS: |
862 | list_for_each (pslotlist, &ibmphp_slot_head) { | 862 | list_for_each(pslotlist, &ibmphp_slot_head) { |
863 | pslot = list_entry (pslotlist, struct slot, ibm_slot_list); | 863 | pslot = list_entry(pslotlist, struct slot, ibm_slot_list); |
864 | // make a copy of the old status | 864 | // make a copy of the old status |
865 | memcpy ((void *) &myslot, (void *) pslot, | 865 | memcpy((void *) &myslot, (void *) pslot, |
866 | sizeof (struct slot)); | 866 | sizeof(struct slot)); |
867 | rc = ibmphp_hpc_readslot (pslot, READ_ALLSTAT, NULL); | 867 | rc = ibmphp_hpc_readslot(pslot, READ_ALLSTAT, NULL); |
868 | if ((myslot.status != pslot->status) | 868 | if ((myslot.status != pslot->status) |
869 | || (myslot.ext_status != pslot->ext_status)) | 869 | || (myslot.ext_status != pslot->ext_status)) |
870 | process_changeinstatus (pslot, &myslot); | 870 | process_changeinstatus(pslot, &myslot); |
871 | } | 871 | } |
872 | ctrl_count = 0x00; | 872 | ctrl_count = 0x00; |
873 | list_for_each (pslotlist, &ibmphp_slot_head) { | 873 | list_for_each(pslotlist, &ibmphp_slot_head) { |
874 | if (ctrl_count >= ibmphp_get_total_controllers()) | 874 | if (ctrl_count >= ibmphp_get_total_controllers()) |
875 | break; | 875 | break; |
876 | pslot = list_entry (pslotlist, struct slot, ibm_slot_list); | 876 | pslot = list_entry(pslotlist, struct slot, ibm_slot_list); |
877 | if (pslot->ctrl->ctlr_relative_id == ctrl_count) { | 877 | if (pslot->ctrl->ctlr_relative_id == ctrl_count) { |
878 | ctrl_count++; | 878 | ctrl_count++; |
879 | if (READ_SLOT_LATCH (pslot->ctrl)) | 879 | if (READ_SLOT_LATCH(pslot->ctrl)) |
880 | rc = ibmphp_hpc_readslot (pslot, | 880 | rc = ibmphp_hpc_readslot(pslot, |
881 | READ_SLOTLATCHLOWREG, | 881 | READ_SLOTLATCHLOWREG, |
882 | &curlatchlow); | 882 | &curlatchlow); |
883 | } | 883 | } |
@@ -887,13 +887,13 @@ static int poll_hpc(void *data) | |||
887 | break; | 887 | break; |
888 | case POLL_SLEEP: | 888 | case POLL_SLEEP: |
889 | /* don't sleep with a lock on the hardware */ | 889 | /* don't sleep with a lock on the hardware */ |
890 | up (&semOperations); | 890 | up(&semOperations); |
891 | msleep(POLL_INTERVAL_SEC * 1000); | 891 | msleep(POLL_INTERVAL_SEC * 1000); |
892 | 892 | ||
893 | if (kthread_should_stop()) | 893 | if (kthread_should_stop()) |
894 | goto out_sleep; | 894 | goto out_sleep; |
895 | 895 | ||
896 | down (&semOperations); | 896 | down(&semOperations); |
897 | 897 | ||
898 | if (poll_count >= POLL_LATCH_CNT) { | 898 | if (poll_count >= POLL_LATCH_CNT) { |
899 | poll_count = 0; | 899 | poll_count = 0; |
@@ -903,13 +903,13 @@ static int poll_hpc(void *data) | |||
903 | break; | 903 | break; |
904 | } | 904 | } |
905 | /* give up the hardware semaphore */ | 905 | /* give up the hardware semaphore */ |
906 | up (&semOperations); | 906 | up(&semOperations); |
907 | /* sleep for a short time just for good measure */ | 907 | /* sleep for a short time just for good measure */ |
908 | out_sleep: | 908 | out_sleep: |
909 | msleep(100); | 909 | msleep(100); |
910 | } | 910 | } |
911 | up (&sem_exit); | 911 | up(&sem_exit); |
912 | debug ("%s - Exit\n", __func__); | 912 | debug("%s - Exit\n", __func__); |
913 | return 0; | 913 | return 0; |
914 | } | 914 | } |
915 | 915 | ||
@@ -929,14 +929,14 @@ out_sleep: | |||
929 | * | 929 | * |
930 | * Notes: | 930 | * Notes: |
931 | *---------------------------------------------------------------------*/ | 931 | *---------------------------------------------------------------------*/ |
932 | static int process_changeinstatus (struct slot *pslot, struct slot *poldslot) | 932 | static int process_changeinstatus(struct slot *pslot, struct slot *poldslot) |
933 | { | 933 | { |
934 | u8 status; | 934 | u8 status; |
935 | int rc = 0; | 935 | int rc = 0; |
936 | u8 disable = 0; | 936 | u8 disable = 0; |
937 | u8 update = 0; | 937 | u8 update = 0; |
938 | 938 | ||
939 | debug ("process_changeinstatus - Entry pslot[%p], poldslot[%p]\n", pslot, poldslot); | 939 | debug("process_changeinstatus - Entry pslot[%p], poldslot[%p]\n", pslot, poldslot); |
940 | 940 | ||
941 | // bit 0 - HPC_SLOT_POWER | 941 | // bit 0 - HPC_SLOT_POWER |
942 | if ((pslot->status & 0x01) != (poldslot->status & 0x01)) | 942 | if ((pslot->status & 0x01) != (poldslot->status & 0x01)) |
@@ -958,7 +958,7 @@ static int process_changeinstatus (struct slot *pslot, struct slot *poldslot) | |||
958 | // bit 5 - HPC_SLOT_PWRGD | 958 | // bit 5 - HPC_SLOT_PWRGD |
959 | if ((pslot->status & 0x20) != (poldslot->status & 0x20)) | 959 | if ((pslot->status & 0x20) != (poldslot->status & 0x20)) |
960 | // OFF -> ON: ignore, ON -> OFF: disable slot | 960 | // OFF -> ON: ignore, ON -> OFF: disable slot |
961 | if ((poldslot->status & 0x20) && (SLOT_CONNECT (poldslot->status) == HPC_SLOT_CONNECTED) && (SLOT_PRESENT (poldslot->status))) | 961 | if ((poldslot->status & 0x20) && (SLOT_CONNECT(poldslot->status) == HPC_SLOT_CONNECTED) && (SLOT_PRESENT(poldslot->status))) |
962 | disable = 1; | 962 | disable = 1; |
963 | 963 | ||
964 | // bit 6 - HPC_SLOT_BUS_SPEED | 964 | // bit 6 - HPC_SLOT_BUS_SPEED |
@@ -969,20 +969,20 @@ static int process_changeinstatus (struct slot *pslot, struct slot *poldslot) | |||
969 | update = 1; | 969 | update = 1; |
970 | // OPEN -> CLOSE | 970 | // OPEN -> CLOSE |
971 | if (pslot->status & 0x80) { | 971 | if (pslot->status & 0x80) { |
972 | if (SLOT_PWRGD (pslot->status)) { | 972 | if (SLOT_PWRGD(pslot->status)) { |
973 | // power goes on and off after closing latch | 973 | // power goes on and off after closing latch |
974 | // check again to make sure power is still ON | 974 | // check again to make sure power is still ON |
975 | msleep(1000); | 975 | msleep(1000); |
976 | rc = ibmphp_hpc_readslot (pslot, READ_SLOTSTATUS, &status); | 976 | rc = ibmphp_hpc_readslot(pslot, READ_SLOTSTATUS, &status); |
977 | if (SLOT_PWRGD (status)) | 977 | if (SLOT_PWRGD(status)) |
978 | update = 1; | 978 | update = 1; |
979 | else // overwrite power in pslot to OFF | 979 | else // overwrite power in pslot to OFF |
980 | pslot->status &= ~HPC_SLOT_POWER; | 980 | pslot->status &= ~HPC_SLOT_POWER; |
981 | } | 981 | } |
982 | } | 982 | } |
983 | // CLOSE -> OPEN | 983 | // CLOSE -> OPEN |
984 | else if ((SLOT_PWRGD (poldslot->status) == HPC_SLOT_PWRGD_GOOD) | 984 | else if ((SLOT_PWRGD(poldslot->status) == HPC_SLOT_PWRGD_GOOD) |
985 | && (SLOT_CONNECT (poldslot->status) == HPC_SLOT_CONNECTED) && (SLOT_PRESENT (poldslot->status))) { | 985 | && (SLOT_CONNECT(poldslot->status) == HPC_SLOT_CONNECTED) && (SLOT_PRESENT(poldslot->status))) { |
986 | disable = 1; | 986 | disable = 1; |
987 | } | 987 | } |
988 | // else - ignore | 988 | // else - ignore |
@@ -992,15 +992,15 @@ static int process_changeinstatus (struct slot *pslot, struct slot *poldslot) | |||
992 | update = 1; | 992 | update = 1; |
993 | 993 | ||
994 | if (disable) { | 994 | if (disable) { |
995 | debug ("process_changeinstatus - disable slot\n"); | 995 | debug("process_changeinstatus - disable slot\n"); |
996 | pslot->flag = 0; | 996 | pslot->flag = 0; |
997 | rc = ibmphp_do_disable_slot (pslot); | 997 | rc = ibmphp_do_disable_slot(pslot); |
998 | } | 998 | } |
999 | 999 | ||
1000 | if (update || disable) | 1000 | if (update || disable) |
1001 | ibmphp_update_slot_info (pslot); | 1001 | ibmphp_update_slot_info(pslot); |
1002 | 1002 | ||
1003 | debug ("%s - Exit rc[%d] disable[%x] update[%x]\n", __func__, rc, disable, update); | 1003 | debug("%s - Exit rc[%d] disable[%x] update[%x]\n", __func__, rc, disable, update); |
1004 | 1004 | ||
1005 | return rc; | 1005 | return rc; |
1006 | } | 1006 | } |
@@ -1015,32 +1015,32 @@ static int process_changeinstatus (struct slot *pslot, struct slot *poldslot) | |||
1015 | * Return 0 or error codes | 1015 | * Return 0 or error codes |
1016 | * Value: | 1016 | * Value: |
1017 | *---------------------------------------------------------------------*/ | 1017 | *---------------------------------------------------------------------*/ |
1018 | static int process_changeinlatch (u8 old, u8 new, struct controller *ctrl) | 1018 | static int process_changeinlatch(u8 old, u8 new, struct controller *ctrl) |
1019 | { | 1019 | { |
1020 | struct slot myslot, *pslot; | 1020 | struct slot myslot, *pslot; |
1021 | u8 i; | 1021 | u8 i; |
1022 | u8 mask; | 1022 | u8 mask; |
1023 | int rc = 0; | 1023 | int rc = 0; |
1024 | 1024 | ||
1025 | debug ("%s - Entry old[%x], new[%x]\n", __func__, old, new); | 1025 | debug("%s - Entry old[%x], new[%x]\n", __func__, old, new); |
1026 | // bit 0 reserved, 0 is LSB, check bit 1-6 for 6 slots | 1026 | // bit 0 reserved, 0 is LSB, check bit 1-6 for 6 slots |
1027 | 1027 | ||
1028 | for (i = ctrl->starting_slot_num; i <= ctrl->ending_slot_num; i++) { | 1028 | for (i = ctrl->starting_slot_num; i <= ctrl->ending_slot_num; i++) { |
1029 | mask = 0x01 << i; | 1029 | mask = 0x01 << i; |
1030 | if ((mask & old) != (mask & new)) { | 1030 | if ((mask & old) != (mask & new)) { |
1031 | pslot = ibmphp_get_slot_from_physical_num (i); | 1031 | pslot = ibmphp_get_slot_from_physical_num(i); |
1032 | if (pslot) { | 1032 | if (pslot) { |
1033 | memcpy ((void *) &myslot, (void *) pslot, sizeof (struct slot)); | 1033 | memcpy((void *) &myslot, (void *) pslot, sizeof(struct slot)); |
1034 | rc = ibmphp_hpc_readslot (pslot, READ_ALLSTAT, NULL); | 1034 | rc = ibmphp_hpc_readslot(pslot, READ_ALLSTAT, NULL); |
1035 | debug ("%s - call process_changeinstatus for slot[%d]\n", __func__, i); | 1035 | debug("%s - call process_changeinstatus for slot[%d]\n", __func__, i); |
1036 | process_changeinstatus (pslot, &myslot); | 1036 | process_changeinstatus(pslot, &myslot); |
1037 | } else { | 1037 | } else { |
1038 | rc = -EINVAL; | 1038 | rc = -EINVAL; |
1039 | err ("%s - Error bad pointer for slot[%d]\n", __func__, i); | 1039 | err("%s - Error bad pointer for slot[%d]\n", __func__, i); |
1040 | } | 1040 | } |
1041 | } | 1041 | } |
1042 | } | 1042 | } |
1043 | debug ("%s - Exit rc[%d]\n", __func__, rc); | 1043 | debug("%s - Exit rc[%d]\n", __func__, rc); |
1044 | return rc; | 1044 | return rc; |
1045 | } | 1045 | } |
1046 | 1046 | ||
@@ -1049,13 +1049,13 @@ static int process_changeinlatch (u8 old, u8 new, struct controller *ctrl) | |||
1049 | * | 1049 | * |
1050 | * Action: start polling thread | 1050 | * Action: start polling thread |
1051 | *---------------------------------------------------------------------*/ | 1051 | *---------------------------------------------------------------------*/ |
1052 | int __init ibmphp_hpc_start_poll_thread (void) | 1052 | int __init ibmphp_hpc_start_poll_thread(void) |
1053 | { | 1053 | { |
1054 | debug ("%s - Entry\n", __func__); | 1054 | debug("%s - Entry\n", __func__); |
1055 | 1055 | ||
1056 | ibmphp_poll_thread = kthread_run(poll_hpc, NULL, "hpc_poll"); | 1056 | ibmphp_poll_thread = kthread_run(poll_hpc, NULL, "hpc_poll"); |
1057 | if (IS_ERR(ibmphp_poll_thread)) { | 1057 | if (IS_ERR(ibmphp_poll_thread)) { |
1058 | err ("%s - Error, thread not started\n", __func__); | 1058 | err("%s - Error, thread not started\n", __func__); |
1059 | return PTR_ERR(ibmphp_poll_thread); | 1059 | return PTR_ERR(ibmphp_poll_thread); |
1060 | } | 1060 | } |
1061 | return 0; | 1061 | return 0; |
@@ -1066,30 +1066,30 @@ int __init ibmphp_hpc_start_poll_thread (void) | |||
1066 | * | 1066 | * |
1067 | * Action: stop polling thread and cleanup | 1067 | * Action: stop polling thread and cleanup |
1068 | *---------------------------------------------------------------------*/ | 1068 | *---------------------------------------------------------------------*/ |
1069 | void __exit ibmphp_hpc_stop_poll_thread (void) | 1069 | void __exit ibmphp_hpc_stop_poll_thread(void) |
1070 | { | 1070 | { |
1071 | debug ("%s - Entry\n", __func__); | 1071 | debug("%s - Entry\n", __func__); |
1072 | 1072 | ||
1073 | kthread_stop(ibmphp_poll_thread); | 1073 | kthread_stop(ibmphp_poll_thread); |
1074 | debug ("before locking operations \n"); | 1074 | debug("before locking operations\n"); |
1075 | ibmphp_lock_operations (); | 1075 | ibmphp_lock_operations(); |
1076 | debug ("after locking operations \n"); | 1076 | debug("after locking operations\n"); |
1077 | 1077 | ||
1078 | // wait for poll thread to exit | 1078 | // wait for poll thread to exit |
1079 | debug ("before sem_exit down \n"); | 1079 | debug("before sem_exit down\n"); |
1080 | down (&sem_exit); | 1080 | down(&sem_exit); |
1081 | debug ("after sem_exit down \n"); | 1081 | debug("after sem_exit down\n"); |
1082 | 1082 | ||
1083 | // cleanup | 1083 | // cleanup |
1084 | debug ("before free_hpc_access \n"); | 1084 | debug("before free_hpc_access\n"); |
1085 | free_hpc_access (); | 1085 | free_hpc_access(); |
1086 | debug ("after free_hpc_access \n"); | 1086 | debug("after free_hpc_access\n"); |
1087 | ibmphp_unlock_operations (); | 1087 | ibmphp_unlock_operations(); |
1088 | debug ("after unlock operations \n"); | 1088 | debug("after unlock operations\n"); |
1089 | up (&sem_exit); | 1089 | up(&sem_exit); |
1090 | debug ("after sem exit up\n"); | 1090 | debug("after sem exit up\n"); |
1091 | 1091 | ||
1092 | debug ("%s - Exit\n", __func__); | 1092 | debug("%s - Exit\n", __func__); |
1093 | } | 1093 | } |
1094 | 1094 | ||
1095 | /*---------------------------------------------------------------------- | 1095 | /*---------------------------------------------------------------------- |
@@ -1100,32 +1100,32 @@ void __exit ibmphp_hpc_stop_poll_thread (void) | |||
1100 | * Return 0, HPC_ERROR | 1100 | * Return 0, HPC_ERROR |
1101 | * Value: | 1101 | * Value: |
1102 | *---------------------------------------------------------------------*/ | 1102 | *---------------------------------------------------------------------*/ |
1103 | static int hpc_wait_ctlr_notworking (int timeout, struct controller *ctlr_ptr, void __iomem *wpg_bbar, | 1103 | static int hpc_wait_ctlr_notworking(int timeout, struct controller *ctlr_ptr, void __iomem *wpg_bbar, |
1104 | u8 *pstatus) | 1104 | u8 *pstatus) |
1105 | { | 1105 | { |
1106 | int rc = 0; | 1106 | int rc = 0; |
1107 | u8 done = 0; | 1107 | u8 done = 0; |
1108 | 1108 | ||
1109 | debug_polling ("hpc_wait_ctlr_notworking - Entry timeout[%d]\n", timeout); | 1109 | debug_polling("hpc_wait_ctlr_notworking - Entry timeout[%d]\n", timeout); |
1110 | 1110 | ||
1111 | while (!done) { | 1111 | while (!done) { |
1112 | *pstatus = ctrl_read (ctlr_ptr, wpg_bbar, WPG_CTLR_INDEX); | 1112 | *pstatus = ctrl_read(ctlr_ptr, wpg_bbar, WPG_CTLR_INDEX); |
1113 | if (*pstatus == HPC_ERROR) { | 1113 | if (*pstatus == HPC_ERROR) { |
1114 | rc = HPC_ERROR; | 1114 | rc = HPC_ERROR; |
1115 | done = 1; | 1115 | done = 1; |
1116 | } | 1116 | } |
1117 | if (CTLR_WORKING (*pstatus) == HPC_CTLR_WORKING_NO) | 1117 | if (CTLR_WORKING(*pstatus) == HPC_CTLR_WORKING_NO) |
1118 | done = 1; | 1118 | done = 1; |
1119 | if (!done) { | 1119 | if (!done) { |
1120 | msleep(1000); | 1120 | msleep(1000); |
1121 | if (timeout < 1) { | 1121 | if (timeout < 1) { |
1122 | done = 1; | 1122 | done = 1; |
1123 | err ("HPCreadslot - Error ctlr timeout\n"); | 1123 | err("HPCreadslot - Error ctlr timeout\n"); |
1124 | rc = HPC_ERROR; | 1124 | rc = HPC_ERROR; |
1125 | } else | 1125 | } else |
1126 | timeout--; | 1126 | timeout--; |
1127 | } | 1127 | } |
1128 | } | 1128 | } |
1129 | debug_polling ("hpc_wait_ctlr_notworking - Exit rc[%x] status[%x]\n", rc, *pstatus); | 1129 | debug_polling("hpc_wait_ctlr_notworking - Exit rc[%x] status[%x]\n", rc, *pstatus); |
1130 | return rc; | 1130 | return rc; |
1131 | } | 1131 | } |