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authorBjorn Helgaas <bhelgaas@google.com>2018-08-15 15:59:09 -0400
committerBjorn Helgaas <bhelgaas@google.com>2018-08-15 15:59:09 -0400
commitce342a1aa8c61fe3315b782f6cf4f34d5babce13 (patch)
treeb03a7d93cb3b9c10c563cb6a8c57164a4ecc69b4 /drivers/pci/controller/pci-aardvark.c
parent0d56768651fc63691552ea59abc4b2ad07a74241 (diff)
parentc8e144f8ab00e6c4a070a932ef9c57db09aa41cf (diff)
Merge branch 'remotes/lorenzo/pci/aardvark'
- Remove Aardvark outbound window configuration (Evan Wang) - Fix Aardvark bridge window sizing issue (Zachary Zhang) - Convert Aardvark to use pci_host_probe() to reduce code duplication (Thomas Petazzoni) * remotes/lorenzo/pci/aardvark: PCI: aardvark: Convert to use pci_host_probe() PCI: aardvark: Size bridges before resources allocation PCI: aardvark: Remove PCIe outbound window configuration PCI: aardvark: Introduce an advk_pcie_valid_device() helper # Conflicts: # drivers/pci/controller/pci-aardvark.c
Diffstat (limited to 'drivers/pci/controller/pci-aardvark.c')
-rw-r--r--drivers/pci/controller/pci-aardvark.c79
1 files changed, 12 insertions, 67 deletions
diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index 0fae816fba39..6b4555ff2548 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -111,24 +111,6 @@
111#define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C) 111#define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C)
112#define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C) 112#define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C)
113 113
114/* PCIe window configuration */
115#define OB_WIN_BASE_ADDR 0x4c00
116#define OB_WIN_BLOCK_SIZE 0x20
117#define OB_WIN_REG_ADDR(win, offset) (OB_WIN_BASE_ADDR + \
118 OB_WIN_BLOCK_SIZE * (win) + \
119 (offset))
120#define OB_WIN_MATCH_LS(win) OB_WIN_REG_ADDR(win, 0x00)
121#define OB_WIN_MATCH_MS(win) OB_WIN_REG_ADDR(win, 0x04)
122#define OB_WIN_REMAP_LS(win) OB_WIN_REG_ADDR(win, 0x08)
123#define OB_WIN_REMAP_MS(win) OB_WIN_REG_ADDR(win, 0x0c)
124#define OB_WIN_MASK_LS(win) OB_WIN_REG_ADDR(win, 0x10)
125#define OB_WIN_MASK_MS(win) OB_WIN_REG_ADDR(win, 0x14)
126#define OB_WIN_ACTIONS(win) OB_WIN_REG_ADDR(win, 0x18)
127
128/* PCIe window types */
129#define OB_PCIE_MEM 0x0
130#define OB_PCIE_IO 0x4
131
132/* LMI registers base address and register offsets */ 114/* LMI registers base address and register offsets */
133#define LMI_BASE_ADDR 0x6000 115#define LMI_BASE_ADDR 0x6000
134#define CFG_REG (LMI_BASE_ADDR + 0x0) 116#define CFG_REG (LMI_BASE_ADDR + 0x0)
@@ -247,34 +229,9 @@ static int advk_pcie_wait_for_link(struct advk_pcie *pcie)
247 return -ETIMEDOUT; 229 return -ETIMEDOUT;
248} 230}
249 231
250/*
251 * Set PCIe address window register which could be used for memory
252 * mapping.
253 */
254static void advk_pcie_set_ob_win(struct advk_pcie *pcie,
255 u32 win_num, u32 match_ms,
256 u32 match_ls, u32 mask_ms,
257 u32 mask_ls, u32 remap_ms,
258 u32 remap_ls, u32 action)
259{
260 advk_writel(pcie, match_ls, OB_WIN_MATCH_LS(win_num));
261 advk_writel(pcie, match_ms, OB_WIN_MATCH_MS(win_num));
262 advk_writel(pcie, mask_ms, OB_WIN_MASK_MS(win_num));
263 advk_writel(pcie, mask_ls, OB_WIN_MASK_LS(win_num));
264 advk_writel(pcie, remap_ms, OB_WIN_REMAP_MS(win_num));
265 advk_writel(pcie, remap_ls, OB_WIN_REMAP_LS(win_num));
266 advk_writel(pcie, action, OB_WIN_ACTIONS(win_num));
267 advk_writel(pcie, match_ls | BIT(0), OB_WIN_MATCH_LS(win_num));
268}
269
270static void advk_pcie_setup_hw(struct advk_pcie *pcie) 232static void advk_pcie_setup_hw(struct advk_pcie *pcie)
271{ 233{
272 u32 reg; 234 u32 reg;
273 int i;
274
275 /* Point PCIe unit MBUS decode windows to DRAM space */
276 for (i = 0; i < 8; i++)
277 advk_pcie_set_ob_win(pcie, i, 0, 0, 0, 0, 0, 0, 0);
278 235
279 /* Set to Direct mode */ 236 /* Set to Direct mode */
280 reg = advk_readl(pcie, CTRL_CONFIG_REG); 237 reg = advk_readl(pcie, CTRL_CONFIG_REG);
@@ -433,6 +390,15 @@ static int advk_pcie_wait_pio(struct advk_pcie *pcie)
433 return -ETIMEDOUT; 390 return -ETIMEDOUT;
434} 391}
435 392
393static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus,
394 int devfn)
395{
396 if ((bus->number == pcie->root_bus_nr) && PCI_SLOT(devfn) != 0)
397 return false;
398
399 return true;
400}
401
436static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn, 402static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
437 int where, int size, u32 *val) 403 int where, int size, u32 *val)
438{ 404{
@@ -440,7 +406,7 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
440 u32 reg; 406 u32 reg;
441 int ret; 407 int ret;
442 408
443 if ((bus->number == pcie->root_bus_nr) && PCI_SLOT(devfn) != 0) { 409 if (!advk_pcie_valid_device(pcie, bus, devfn)) {
444 *val = 0xffffffff; 410 *val = 0xffffffff;
445 return PCIBIOS_DEVICE_NOT_FOUND; 411 return PCIBIOS_DEVICE_NOT_FOUND;
446 } 412 }
@@ -494,7 +460,7 @@ static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
494 int offset; 460 int offset;
495 int ret; 461 int ret;
496 462
497 if ((bus->number == pcie->root_bus_nr) && PCI_SLOT(devfn) != 0) 463 if (!advk_pcie_valid_device(pcie, bus, devfn))
498 return PCIBIOS_DEVICE_NOT_FOUND; 464 return PCIBIOS_DEVICE_NOT_FOUND;
499 465
500 if (where % size) 466 if (where % size)
@@ -843,12 +809,6 @@ static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie)
843 809
844 switch (resource_type(res)) { 810 switch (resource_type(res)) {
845 case IORESOURCE_IO: 811 case IORESOURCE_IO:
846 advk_pcie_set_ob_win(pcie, 1,
847 upper_32_bits(res->start),
848 lower_32_bits(res->start),
849 0, 0xF8000000, 0,
850 lower_32_bits(res->start),
851 OB_PCIE_IO);
852 err = devm_pci_remap_iospace(dev, res, iobase); 812 err = devm_pci_remap_iospace(dev, res, iobase);
853 if (err) { 813 if (err) {
854 dev_warn(dev, "error %d: failed to map resource %pR\n", 814 dev_warn(dev, "error %d: failed to map resource %pR\n",
@@ -857,12 +817,6 @@ static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie)
857 } 817 }
858 break; 818 break;
859 case IORESOURCE_MEM: 819 case IORESOURCE_MEM:
860 advk_pcie_set_ob_win(pcie, 0,
861 upper_32_bits(res->start),
862 lower_32_bits(res->start),
863 0x0, 0xF8000000, 0,
864 lower_32_bits(res->start),
865 (2 << 20) | OB_PCIE_MEM);
866 res_valid |= !(res->flags & IORESOURCE_PREFETCH); 820 res_valid |= !(res->flags & IORESOURCE_PREFETCH);
867 break; 821 break;
868 case IORESOURCE_BUS: 822 case IORESOURCE_BUS:
@@ -889,7 +843,6 @@ static int advk_pcie_probe(struct platform_device *pdev)
889 struct device *dev = &pdev->dev; 843 struct device *dev = &pdev->dev;
890 struct advk_pcie *pcie; 844 struct advk_pcie *pcie;
891 struct resource *res; 845 struct resource *res;
892 struct pci_bus *bus, *child;
893 struct pci_host_bridge *bridge; 846 struct pci_host_bridge *bridge;
894 int ret, irq; 847 int ret, irq;
895 848
@@ -943,21 +896,13 @@ static int advk_pcie_probe(struct platform_device *pdev)
943 bridge->map_irq = of_irq_parse_and_map_pci; 896 bridge->map_irq = of_irq_parse_and_map_pci;
944 bridge->swizzle_irq = pci_common_swizzle; 897 bridge->swizzle_irq = pci_common_swizzle;
945 898
946 ret = pci_scan_root_bus_bridge(bridge); 899 ret = pci_host_probe(bridge);
947 if (ret < 0) { 900 if (ret < 0) {
948 advk_pcie_remove_msi_irq_domain(pcie); 901 advk_pcie_remove_msi_irq_domain(pcie);
949 advk_pcie_remove_irq_domain(pcie); 902 advk_pcie_remove_irq_domain(pcie);
950 return ret; 903 return ret;
951 } 904 }
952 905
953 bus = bridge->bus;
954
955 pci_bus_assign_resources(bus);
956
957 list_for_each_entry(child, &bus->children, node)
958 pcie_bus_configure_settings(child);
959
960 pci_bus_add_devices(bus);
961 return 0; 906 return 0;
962} 907}
963 908