diff options
author | Kishon Vijay Abraham I <kishon@ti.com> | 2018-10-17 03:41:09 -0400 |
---|---|---|
committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2018-10-17 04:58:46 -0400 |
commit | f9127db9fbadd079c6b88974001cb036057c8afc (patch) | |
tree | 2d6f8ac458042c5d27dc2889ea7c8eb584dcc5af /drivers/pci/controller/dwc | |
parent | e75043ad9792596916ed0e1910b44f34b181c3b7 (diff) |
PCI: keystone: Cleanup set_dbi_mode() and get_dbi_mode()
No functional change. Use BIT() macro for DBI_CS2 and cleanup
set_dbi_mode() and get_dbi_mode().
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Diffstat (limited to 'drivers/pci/controller/dwc')
-rw-r--r-- | drivers/pci/controller/dwc/pci-keystone.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 3576a184b9eb..2decbaec81a3 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c | |||
@@ -40,7 +40,7 @@ | |||
40 | #define LTSSM_EN_VAL BIT(0) | 40 | #define LTSSM_EN_VAL BIT(0) |
41 | #define LTSSM_STATE_MASK 0x1f | 41 | #define LTSSM_STATE_MASK 0x1f |
42 | #define LTSSM_STATE_L0 0x11 | 42 | #define LTSSM_STATE_L0 0x11 |
43 | #define DBI_CS2_EN_VAL 0x20 | 43 | #define DBI_CS2 BIT(5) |
44 | #define OB_XLAT_EN_VAL BIT(1) | 44 | #define OB_XLAT_EN_VAL BIT(1) |
45 | 45 | ||
46 | /* Application registers */ | 46 | /* Application registers */ |
@@ -315,11 +315,12 @@ static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie) | |||
315 | u32 val; | 315 | u32 val; |
316 | 316 | ||
317 | val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); | 317 | val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); |
318 | ks_pcie_app_writel(ks_pcie, CMD_STATUS, DBI_CS2_EN_VAL | val); | 318 | val |= DBI_CS2; |
319 | ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); | ||
319 | 320 | ||
320 | do { | 321 | do { |
321 | val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); | 322 | val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); |
322 | } while (!(val & DBI_CS2_EN_VAL)); | 323 | } while (!(val & DBI_CS2)); |
323 | } | 324 | } |
324 | 325 | ||
325 | /** | 326 | /** |
@@ -333,11 +334,12 @@ static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie) | |||
333 | u32 val; | 334 | u32 val; |
334 | 335 | ||
335 | val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); | 336 | val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); |
336 | ks_pcie_app_writel(ks_pcie, CMD_STATUS, ~DBI_CS2_EN_VAL & val); | 337 | val &= ~DBI_CS2; |
338 | ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); | ||
337 | 339 | ||
338 | do { | 340 | do { |
339 | val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); | 341 | val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); |
340 | } while (val & DBI_CS2_EN_VAL); | 342 | } while (val & DBI_CS2); |
341 | } | 343 | } |
342 | 344 | ||
343 | static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) | 345 | static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) |