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authorBaruch Siach <baruch@tkos.co.il>2019-01-31 16:00:18 -0500
committerBjorn Helgaas <bhelgaas@google.com>2019-01-31 16:07:29 -0500
commitf14bcc0add3abecceca1a3fe538c4ec9566893f3 (patch)
treeae61e6110f9bcecc24c77595fc69c51f2066f0a5 /drivers/pci/controller/dwc
parent432dd7064aa1c030a488745917cfa4ebc6c8c060 (diff)
Revert "PCI: armada8k: Add support for gpio controlled reset signal"
Revert commit 3d71746c42 ("PCI: armada8k: Add support for gpio controlled reset signal"). That commit breaks boot on Macchiatobin board when a Mellanox NIC is present in the PCIe slot. It turns out that full reset cycle requires first comphy serdes initialization. Reset signal toggle without comphy initialization makes access to PCI configuration registers stall indefinitely. U-Boot toggles the Macchiatobin PCIe reset line already at boot, after initializing the comphy serdes. So while commit 3d71746c42 ("PCI: armada8k: Add support for gpio controlled reset signal") enables PCIe on platforms that U-Boot does not touch the reset line (like Clearfog GT-8K), it breaks PCIe (and boot) on the Macchiatobin board. Revert commit 3d71746c42 ("PCI: armada8k: Add support for gpio controlled reset signal") entirely to fix the Macchiatobin regression. Reported-by: Sven Auhagen <sven.auhagen@voleatech.de> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Diffstat (limited to 'drivers/pci/controller/dwc')
-rw-r--r--drivers/pci/controller/dwc/pcie-armada8k.c16
1 files changed, 0 insertions, 16 deletions
diff --git a/drivers/pci/controller/dwc/pcie-armada8k.c b/drivers/pci/controller/dwc/pcie-armada8k.c
index b171b6bc15c8..0c389a30ef5d 100644
--- a/drivers/pci/controller/dwc/pcie-armada8k.c
+++ b/drivers/pci/controller/dwc/pcie-armada8k.c
@@ -22,7 +22,6 @@
22#include <linux/resource.h> 22#include <linux/resource.h>
23#include <linux/of_pci.h> 23#include <linux/of_pci.h>
24#include <linux/of_irq.h> 24#include <linux/of_irq.h>
25#include <linux/gpio/consumer.h>
26 25
27#include "pcie-designware.h" 26#include "pcie-designware.h"
28 27
@@ -30,7 +29,6 @@ struct armada8k_pcie {
30 struct dw_pcie *pci; 29 struct dw_pcie *pci;
31 struct clk *clk; 30 struct clk *clk;
32 struct clk *clk_reg; 31 struct clk *clk_reg;
33 struct gpio_desc *reset_gpio;
34}; 32};
35 33
36#define PCIE_VENDOR_REGS_OFFSET 0x8000 34#define PCIE_VENDOR_REGS_OFFSET 0x8000
@@ -139,12 +137,6 @@ static int armada8k_pcie_host_init(struct pcie_port *pp)
139 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 137 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
140 struct armada8k_pcie *pcie = to_armada8k_pcie(pci); 138 struct armada8k_pcie *pcie = to_armada8k_pcie(pci);
141 139
142 if (pcie->reset_gpio) {
143 /* assert and then deassert the reset signal */
144 gpiod_set_value_cansleep(pcie->reset_gpio, 1);
145 msleep(100);
146 gpiod_set_value_cansleep(pcie->reset_gpio, 0);
147 }
148 dw_pcie_setup_rc(pp); 140 dw_pcie_setup_rc(pp);
149 armada8k_pcie_establish_link(pcie); 141 armada8k_pcie_establish_link(pcie);
150 142
@@ -257,14 +249,6 @@ static int armada8k_pcie_probe(struct platform_device *pdev)
257 goto fail_clkreg; 249 goto fail_clkreg;
258 } 250 }
259 251
260 /* Get reset gpio signal and hold asserted (logically high) */
261 pcie->reset_gpio = devm_gpiod_get_optional(dev, "reset",
262 GPIOD_OUT_HIGH);
263 if (IS_ERR(pcie->reset_gpio)) {
264 ret = PTR_ERR(pcie->reset_gpio);
265 goto fail_clkreg;
266 }
267
268 platform_set_drvdata(pdev, pcie); 252 platform_set_drvdata(pdev, pcie);
269 253
270 ret = armada8k_add_pcie_port(pcie, pdev); 254 ret = armada8k_add_pcie_port(pcie, pdev);