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authorKishon Vijay Abraham I <kishon@ti.com>2018-10-17 03:40:59 -0400
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2018-10-17 04:43:44 -0400
commitb492aca35c982011500377797d2e85b36fffda22 (patch)
treea4694be94d578a2d440a63e8e629c9611b491c33 /drivers/pci/controller/dwc
parent1f79f98f0575521df1a3921f30948b6cd8317ee4 (diff)
PCI: keystone: Merge pci-keystone-dw.c and pci-keystone.c
No functional change. Having two different files for keystone PCI driver doesn't serve any purpose. Merge pci-keystone-dw.c and pci-keystone.c into a single pci-keystone.c file and remove pci-keystone.h. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Diffstat (limited to 'drivers/pci/controller/dwc')
-rw-r--r--drivers/pci/controller/dwc/Makefile2
-rw-r--r--drivers/pci/controller/dwc/pci-keystone-dw.c483
-rw-r--r--drivers/pci/controller/dwc/pci-keystone.c489
-rw-r--r--drivers/pci/controller/dwc/pci-keystone.h56
4 files changed, 489 insertions, 541 deletions
diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
index 5d2ce72c7a52..fcf91eacfc63 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -7,7 +7,7 @@ obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
7obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o 7obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
8obj-$(CONFIG_PCI_IMX6) += pci-imx6.o 8obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
9obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o 9obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
10obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone-dw.o pci-keystone.o 10obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o
11obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o 11obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
12obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o 12obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
13obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o 13obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
diff --git a/drivers/pci/controller/dwc/pci-keystone-dw.c b/drivers/pci/controller/dwc/pci-keystone-dw.c
deleted file mode 100644
index 4bd6c6e2b177..000000000000
--- a/drivers/pci/controller/dwc/pci-keystone-dw.c
+++ /dev/null
@@ -1,483 +0,0 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * DesignWare application register space functions for Keystone PCI controller
4 *
5 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
6 * http://www.ti.com
7 *
8 * Author: Murali Karicheri <m-karicheri2@ti.com>
9 */
10
11#include <linux/irq.h>
12#include <linux/irqdomain.h>
13#include <linux/irqreturn.h>
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/of_pci.h>
17#include <linux/pci.h>
18#include <linux/platform_device.h>
19
20#include "pcie-designware.h"
21#include "pci-keystone.h"
22
23/* Application register defines */
24#define LTSSM_EN_VAL 1
25#define LTSSM_STATE_MASK 0x1f
26#define LTSSM_STATE_L0 0x11
27#define DBI_CS2_EN_VAL 0x20
28#define OB_XLAT_EN_VAL 2
29
30/* Application registers */
31#define CMD_STATUS 0x004
32#define CFG_SETUP 0x008
33#define OB_SIZE 0x030
34#define CFG_PCIM_WIN_SZ_IDX 3
35#define CFG_PCIM_WIN_CNT 32
36#define SPACE0_REMOTE_CFG_OFFSET 0x1000
37#define OB_OFFSET_INDEX(n) (0x200 + (8 * n))
38#define OB_OFFSET_HI(n) (0x204 + (8 * n))
39
40/* IRQ register defines */
41#define IRQ_EOI 0x050
42#define IRQ_STATUS 0x184
43#define IRQ_ENABLE_SET 0x188
44#define IRQ_ENABLE_CLR 0x18c
45
46#define MSI_IRQ 0x054
47#define MSI0_IRQ_STATUS 0x104
48#define MSI0_IRQ_ENABLE_SET 0x108
49#define MSI0_IRQ_ENABLE_CLR 0x10c
50#define IRQ_STATUS 0x184
51#define MSI_IRQ_OFFSET 4
52
53/* Error IRQ bits */
54#define ERR_AER BIT(5) /* ECRC error */
55#define ERR_AXI BIT(4) /* AXI tag lookup fatal error */
56#define ERR_CORR BIT(3) /* Correctable error */
57#define ERR_NONFATAL BIT(2) /* Non-fatal error */
58#define ERR_FATAL BIT(1) /* Fatal error */
59#define ERR_SYS BIT(0) /* System (fatal, non-fatal, or correctable) */
60#define ERR_IRQ_ALL (ERR_AER | ERR_AXI | ERR_CORR | \
61 ERR_NONFATAL | ERR_FATAL | ERR_SYS)
62#define ERR_FATAL_IRQ (ERR_FATAL | ERR_AXI)
63#define ERR_IRQ_STATUS_RAW 0x1c0
64#define ERR_IRQ_STATUS 0x1c4
65#define ERR_IRQ_ENABLE_SET 0x1c8
66#define ERR_IRQ_ENABLE_CLR 0x1cc
67
68/* Config space registers */
69#define DEBUG0 0x728
70
71#define to_keystone_pcie(x) dev_get_drvdata((x)->dev)
72
73static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset,
74 u32 *bit_pos)
75{
76 *reg_offset = offset % 8;
77 *bit_pos = offset >> 3;
78}
79
80phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp)
81{
82 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
83 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
84
85 return ks_pcie->app.start + MSI_IRQ;
86}
87
88static u32 ks_dw_app_readl(struct keystone_pcie *ks_pcie, u32 offset)
89{
90 return readl(ks_pcie->va_app_base + offset);
91}
92
93static void ks_dw_app_writel(struct keystone_pcie *ks_pcie, u32 offset, u32 val)
94{
95 writel(val, ks_pcie->va_app_base + offset);
96}
97
98void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset)
99{
100 struct dw_pcie *pci = ks_pcie->pci;
101 struct pcie_port *pp = &pci->pp;
102 struct device *dev = pci->dev;
103 u32 pending, vector;
104 int src, virq;
105
106 pending = ks_dw_app_readl(ks_pcie, MSI0_IRQ_STATUS + (offset << 4));
107
108 /*
109 * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit
110 * shows 1, 9, 17, 25 and so forth
111 */
112 for (src = 0; src < 4; src++) {
113 if (BIT(src) & pending) {
114 vector = offset + (src << 3);
115 virq = irq_linear_revmap(pp->irq_domain, vector);
116 dev_dbg(dev, "irq: bit %d, vector %d, virq %d\n",
117 src, vector, virq);
118 generic_handle_irq(virq);
119 }
120 }
121}
122
123void ks_dw_pcie_msi_irq_ack(int irq, struct pcie_port *pp)
124{
125 u32 reg_offset, bit_pos;
126 struct keystone_pcie *ks_pcie;
127 struct dw_pcie *pci;
128
129 pci = to_dw_pcie_from_pp(pp);
130 ks_pcie = to_keystone_pcie(pci);
131 update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
132
133 ks_dw_app_writel(ks_pcie, MSI0_IRQ_STATUS + (reg_offset << 4),
134 BIT(bit_pos));
135 ks_dw_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET);
136}
137
138void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
139{
140 u32 reg_offset, bit_pos;
141 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
142 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
143
144 update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
145 ks_dw_app_writel(ks_pcie, MSI0_IRQ_ENABLE_SET + (reg_offset << 4),
146 BIT(bit_pos));
147}
148
149void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
150{
151 u32 reg_offset, bit_pos;
152 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
153 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
154
155 update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
156 ks_dw_app_writel(ks_pcie, MSI0_IRQ_ENABLE_CLR + (reg_offset << 4),
157 BIT(bit_pos));
158}
159
160int ks_dw_pcie_msi_host_init(struct pcie_port *pp)
161{
162 return dw_pcie_allocate_domains(pp);
163}
164
165void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie)
166{
167 int i;
168
169 for (i = 0; i < PCI_NUM_INTX; i++)
170 ks_dw_app_writel(ks_pcie, IRQ_ENABLE_SET + (i << 4), 0x1);
171}
172
173void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset)
174{
175 struct dw_pcie *pci = ks_pcie->pci;
176 struct device *dev = pci->dev;
177 u32 pending;
178 int virq;
179
180 pending = ks_dw_app_readl(ks_pcie, IRQ_STATUS + (offset << 4));
181
182 if (BIT(0) & pending) {
183 virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset);
184 dev_dbg(dev, ": irq: irq_offset %d, virq %d\n", offset, virq);
185 generic_handle_irq(virq);
186 }
187
188 /* EOI the INTx interrupt */
189 ks_dw_app_writel(ks_pcie, IRQ_EOI, offset);
190}
191
192void ks_dw_pcie_enable_error_irq(struct keystone_pcie *ks_pcie)
193{
194 ks_dw_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL);
195}
196
197irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *ks_pcie)
198{
199 u32 status;
200
201 status = ks_dw_app_readl(ks_pcie, ERR_IRQ_STATUS_RAW) & ERR_IRQ_ALL;
202 if (!status)
203 return IRQ_NONE;
204
205 if (status & ERR_FATAL_IRQ)
206 dev_err(ks_pcie->pci->dev, "fatal error (status %#010x)\n",
207 status);
208
209 /* Ack the IRQ; status bits are RW1C */
210 ks_dw_app_writel(ks_pcie, ERR_IRQ_STATUS, status);
211 return IRQ_HANDLED;
212}
213
214static void ks_dw_pcie_ack_legacy_irq(struct irq_data *d)
215{
216}
217
218static void ks_dw_pcie_mask_legacy_irq(struct irq_data *d)
219{
220}
221
222static void ks_dw_pcie_unmask_legacy_irq(struct irq_data *d)
223{
224}
225
226static struct irq_chip ks_dw_pcie_legacy_irq_chip = {
227 .name = "Keystone-PCI-Legacy-IRQ",
228 .irq_ack = ks_dw_pcie_ack_legacy_irq,
229 .irq_mask = ks_dw_pcie_mask_legacy_irq,
230 .irq_unmask = ks_dw_pcie_unmask_legacy_irq,
231};
232
233static int ks_dw_pcie_init_legacy_irq_map(struct irq_domain *d,
234 unsigned int irq, irq_hw_number_t hw_irq)
235{
236 irq_set_chip_and_handler(irq, &ks_dw_pcie_legacy_irq_chip,
237 handle_level_irq);
238 irq_set_chip_data(irq, d->host_data);
239
240 return 0;
241}
242
243static const struct irq_domain_ops ks_dw_pcie_legacy_irq_domain_ops = {
244 .map = ks_dw_pcie_init_legacy_irq_map,
245 .xlate = irq_domain_xlate_onetwocell,
246};
247
248/**
249 * ks_dw_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask
250 * registers
251 *
252 * Since modification of dbi_cs2 involves different clock domain, read the
253 * status back to ensure the transition is complete.
254 */
255static void ks_dw_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie)
256{
257 u32 val;
258
259 val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
260 ks_dw_app_writel(ks_pcie, CMD_STATUS, DBI_CS2_EN_VAL | val);
261
262 do {
263 val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
264 } while (!(val & DBI_CS2_EN_VAL));
265}
266
267/**
268 * ks_dw_pcie_clear_dbi_mode() - Disable DBI mode
269 *
270 * Since modification of dbi_cs2 involves different clock domain, read the
271 * status back to ensure the transition is complete.
272 */
273static void ks_dw_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie)
274{
275 u32 val;
276
277 val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
278 ks_dw_app_writel(ks_pcie, CMD_STATUS, ~DBI_CS2_EN_VAL & val);
279
280 do {
281 val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
282 } while (val & DBI_CS2_EN_VAL);
283}
284
285void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
286{
287 struct dw_pcie *pci = ks_pcie->pci;
288 struct pcie_port *pp = &pci->pp;
289 u32 start = pp->mem->start, end = pp->mem->end;
290 int i, tr_size;
291 u32 val;
292
293 /* Disable BARs for inbound access */
294 ks_dw_pcie_set_dbi_mode(ks_pcie);
295 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
296 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0);
297 ks_dw_pcie_clear_dbi_mode(ks_pcie);
298
299 /* Set outbound translation size per window division */
300 ks_dw_app_writel(ks_pcie, OB_SIZE, CFG_PCIM_WIN_SZ_IDX & 0x7);
301
302 tr_size = (1 << (CFG_PCIM_WIN_SZ_IDX & 0x7)) * SZ_1M;
303
304 /* Using Direct 1:1 mapping of RC <-> PCI memory space */
305 for (i = 0; (i < CFG_PCIM_WIN_CNT) && (start < end); i++) {
306 ks_dw_app_writel(ks_pcie, OB_OFFSET_INDEX(i), start | 1);
307 ks_dw_app_writel(ks_pcie, OB_OFFSET_HI(i), 0);
308 start += tr_size;
309 }
310
311 /* Enable OB translation */
312 val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
313 ks_dw_app_writel(ks_pcie, CMD_STATUS, OB_XLAT_EN_VAL | val);
314}
315
316/**
317 * ks_pcie_cfg_setup() - Set up configuration space address for a device
318 *
319 * @ks_pcie: ptr to keystone_pcie structure
320 * @bus: Bus number the device is residing on
321 * @devfn: device, function number info
322 *
323 * Forms and returns the address of configuration space mapped in PCIESS
324 * address space 0. Also configures CFG_SETUP for remote configuration space
325 * access.
326 *
327 * The address space has two regions to access configuration - local and remote.
328 * We access local region for bus 0 (as RC is attached on bus 0) and remote
329 * region for others with TYPE 1 access when bus > 1. As for device on bus = 1,
330 * we will do TYPE 0 access as it will be on our secondary bus (logical).
331 * CFG_SETUP is needed only for remote configuration access.
332 */
333static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *ks_pcie, u8 bus,
334 unsigned int devfn)
335{
336 u8 device = PCI_SLOT(devfn), function = PCI_FUNC(devfn);
337 struct dw_pcie *pci = ks_pcie->pci;
338 struct pcie_port *pp = &pci->pp;
339 u32 regval;
340
341 if (bus == 0)
342 return pci->dbi_base;
343
344 regval = (bus << 16) | (device << 8) | function;
345
346 /*
347 * Since Bus#1 will be a virtual bus, we need to have TYPE0
348 * access only.
349 * TYPE 1
350 */
351 if (bus != 1)
352 regval |= BIT(24);
353
354 ks_dw_app_writel(ks_pcie, CFG_SETUP, regval);
355 return pp->va_cfg0_base;
356}
357
358int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
359 unsigned int devfn, int where, int size, u32 *val)
360{
361 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
362 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
363 u8 bus_num = bus->number;
364 void __iomem *addr;
365
366 addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);
367
368 return dw_pcie_read(addr + where, size, val);
369}
370
371int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
372 unsigned int devfn, int where, int size, u32 val)
373{
374 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
375 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
376 u8 bus_num = bus->number;
377 void __iomem *addr;
378
379 addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);
380
381 return dw_pcie_write(addr + where, size, val);
382}
383
384/**
385 * ks_dw_pcie_v3_65_scan_bus() - keystone scan_bus post initialization
386 *
387 * This sets BAR0 to enable inbound access for MSI_IRQ register
388 */
389void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
390{
391 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
392 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
393
394 /* Configure and set up BAR0 */
395 ks_dw_pcie_set_dbi_mode(ks_pcie);
396
397 /* Enable BAR0 */
398 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1);
399 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1);
400
401 ks_dw_pcie_clear_dbi_mode(ks_pcie);
402
403 /*
404 * For BAR0, just setting bus address for inbound writes (MSI) should
405 * be sufficient. Use physical address to avoid any conflicts.
406 */
407 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
408}
409
410/**
411 * ks_dw_pcie_link_up() - Check if link up
412 */
413int ks_dw_pcie_link_up(struct dw_pcie *pci)
414{
415 u32 val;
416
417 val = dw_pcie_readl_dbi(pci, DEBUG0);
418 return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0;
419}
420
421void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie)
422{
423 u32 val;
424
425 /* Disable Link training */
426 val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
427 val &= ~LTSSM_EN_VAL;
428 ks_dw_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val);
429
430 /* Initiate Link Training */
431 val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
432 ks_dw_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val);
433}
434
435/**
436 * ks_dw_pcie_host_init() - initialize host for v3_65 dw hardware
437 *
438 * Ioremap the register resources, initialize legacy irq domain
439 * and call dw_pcie_v3_65_host_init() API to initialize the Keystone
440 * PCI host controller.
441 */
442int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie)
443{
444 struct dw_pcie *pci = ks_pcie->pci;
445 struct pcie_port *pp = &pci->pp;
446 struct device *dev = pci->dev;
447 struct platform_device *pdev = to_platform_device(dev);
448 struct resource *res;
449
450 /* Index 0 is the config reg. space address */
451 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
452 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res);
453 if (IS_ERR(pci->dbi_base))
454 return PTR_ERR(pci->dbi_base);
455
456 /*
457 * We set these same and is used in pcie rd/wr_other_conf
458 * functions
459 */
460 pp->va_cfg0_base = pci->dbi_base + SPACE0_REMOTE_CFG_OFFSET;
461 pp->va_cfg1_base = pp->va_cfg0_base;
462
463 /* Index 1 is the application reg. space address */
464 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
465 ks_pcie->va_app_base = devm_ioremap_resource(dev, res);
466 if (IS_ERR(ks_pcie->va_app_base))
467 return PTR_ERR(ks_pcie->va_app_base);
468
469 ks_pcie->app = *res;
470
471 /* Create legacy IRQ domain */
472 ks_pcie->legacy_irq_domain =
473 irq_domain_add_linear(ks_pcie->legacy_intc_np,
474 PCI_NUM_INTX,
475 &ks_dw_pcie_legacy_irq_domain_ops,
476 NULL);
477 if (!ks_pcie->legacy_irq_domain) {
478 dev_err(dev, "Failed to add irq domain for legacy irqs\n");
479 return -EINVAL;
480 }
481
482 return dw_pcie_host_init(pp);
483}
diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
index f87ade2de711..337464d15775 100644
--- a/drivers/pci/controller/dwc/pci-keystone.c
+++ b/drivers/pci/controller/dwc/pci-keystone.c
@@ -25,13 +25,62 @@
25#include <linux/signal.h> 25#include <linux/signal.h>
26 26
27#include "pcie-designware.h" 27#include "pcie-designware.h"
28#include "pci-keystone.h"
29 28
30#define DRIVER_NAME "keystone-pcie" 29#define DRIVER_NAME "keystone-pcie"
31 30
32/* DEV_STAT_CTRL */ 31/* DEV_STAT_CTRL */
33#define PCIE_CAP_BASE 0x70 32#define PCIE_CAP_BASE 0x70
34 33
34/* Application register defines */
35#define LTSSM_EN_VAL BIT(0)
36#define LTSSM_STATE_MASK 0x1f
37#define LTSSM_STATE_L0 0x11
38#define DBI_CS2_EN_VAL 0x20
39#define OB_XLAT_EN_VAL 2
40
41/* Application registers */
42#define CMD_STATUS 0x004
43#define CFG_SETUP 0x008
44#define OB_SIZE 0x030
45#define CFG_PCIM_WIN_SZ_IDX 3
46#define CFG_PCIM_WIN_CNT 32
47#define SPACE0_REMOTE_CFG_OFFSET 0x1000
48#define OB_OFFSET_INDEX(n) (0x200 + (8 * (n)))
49#define OB_OFFSET_HI(n) (0x204 + (8 * (n)))
50
51/* IRQ register defines */
52#define IRQ_EOI 0x050
53#define IRQ_STATUS 0x184
54#define IRQ_ENABLE_SET 0x188
55#define IRQ_ENABLE_CLR 0x18c
56
57#define MSI_IRQ 0x054
58#define MSI0_IRQ_STATUS 0x104
59#define MSI0_IRQ_ENABLE_SET 0x108
60#define MSI0_IRQ_ENABLE_CLR 0x10c
61#define IRQ_STATUS 0x184
62#define MSI_IRQ_OFFSET 4
63
64/* Error IRQ bits */
65#define ERR_AER BIT(5) /* ECRC error */
66#define ERR_AXI BIT(4) /* AXI tag lookup fatal error */
67#define ERR_CORR BIT(3) /* Correctable error */
68#define ERR_NONFATAL BIT(2) /* Non-fatal error */
69#define ERR_FATAL BIT(1) /* Fatal error */
70#define ERR_SYS BIT(0) /* System (fatal, non-fatal, or correctable) */
71#define ERR_IRQ_ALL (ERR_AER | ERR_AXI | ERR_CORR | \
72 ERR_NONFATAL | ERR_FATAL | ERR_SYS)
73#define ERR_FATAL_IRQ (ERR_FATAL | ERR_AXI)
74#define ERR_IRQ_STATUS_RAW 0x1c0
75#define ERR_IRQ_STATUS 0x1c4
76#define ERR_IRQ_ENABLE_SET 0x1c8
77#define ERR_IRQ_ENABLE_CLR 0x1cc
78
79/* Config space registers */
80#define DEBUG0 0x728
81
82#define MAX_MSI_HOST_IRQS 8
83
35/* PCIE controller device IDs */ 84/* PCIE controller device IDs */
36#define PCIE_RC_K2HK 0xb008 85#define PCIE_RC_K2HK 0xb008
37#define PCIE_RC_K2E 0xb009 86#define PCIE_RC_K2E 0xb009
@@ -40,6 +89,444 @@
40 89
41#define to_keystone_pcie(x) dev_get_drvdata((x)->dev) 90#define to_keystone_pcie(x) dev_get_drvdata((x)->dev)
42 91
92struct keystone_pcie {
93 struct dw_pcie *pci;
94 struct clk *clk;
95 /* PCI Device ID */
96 u32 device_id;
97 int num_legacy_host_irqs;
98 int legacy_host_irqs[PCI_NUM_INTX];
99 struct device_node *legacy_intc_np;
100
101 int num_msi_host_irqs;
102 int msi_host_irqs[MAX_MSI_HOST_IRQS];
103 struct device_node *msi_intc_np;
104 struct irq_domain *legacy_irq_domain;
105 struct device_node *np;
106
107 int error_irq;
108
109 /* Application register space */
110 void __iomem *va_app_base; /* DT 1st resource */
111 struct resource app;
112};
113
114static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset,
115 u32 *bit_pos)
116{
117 *reg_offset = offset % 8;
118 *bit_pos = offset >> 3;
119}
120
121static phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp)
122{
123 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
124 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
125
126 return ks_pcie->app.start + MSI_IRQ;
127}
128
129static u32 ks_dw_app_readl(struct keystone_pcie *ks_pcie, u32 offset)
130{
131 return readl(ks_pcie->va_app_base + offset);
132}
133
134static void ks_dw_app_writel(struct keystone_pcie *ks_pcie, u32 offset, u32 val)
135{
136 writel(val, ks_pcie->va_app_base + offset);
137}
138
139static void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset)
140{
141 struct dw_pcie *pci = ks_pcie->pci;
142 struct pcie_port *pp = &pci->pp;
143 struct device *dev = pci->dev;
144 u32 pending, vector;
145 int src, virq;
146
147 pending = ks_dw_app_readl(ks_pcie, MSI0_IRQ_STATUS + (offset << 4));
148
149 /*
150 * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit
151 * shows 1, 9, 17, 25 and so forth
152 */
153 for (src = 0; src < 4; src++) {
154 if (BIT(src) & pending) {
155 vector = offset + (src << 3);
156 virq = irq_linear_revmap(pp->irq_domain, vector);
157 dev_dbg(dev, "irq: bit %d, vector %d, virq %d\n",
158 src, vector, virq);
159 generic_handle_irq(virq);
160 }
161 }
162}
163
164static void ks_dw_pcie_msi_irq_ack(int irq, struct pcie_port *pp)
165{
166 u32 reg_offset, bit_pos;
167 struct keystone_pcie *ks_pcie;
168 struct dw_pcie *pci;
169
170 pci = to_dw_pcie_from_pp(pp);
171 ks_pcie = to_keystone_pcie(pci);
172 update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
173
174 ks_dw_app_writel(ks_pcie, MSI0_IRQ_STATUS + (reg_offset << 4),
175 BIT(bit_pos));
176 ks_dw_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET);
177}
178
179static void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
180{
181 u32 reg_offset, bit_pos;
182 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
183 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
184
185 update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
186 ks_dw_app_writel(ks_pcie, MSI0_IRQ_ENABLE_SET + (reg_offset << 4),
187 BIT(bit_pos));
188}
189
190static void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
191{
192 u32 reg_offset, bit_pos;
193 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
194 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
195
196 update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
197 ks_dw_app_writel(ks_pcie, MSI0_IRQ_ENABLE_CLR + (reg_offset << 4),
198 BIT(bit_pos));
199}
200
201static int ks_dw_pcie_msi_host_init(struct pcie_port *pp)
202{
203 return dw_pcie_allocate_domains(pp);
204}
205
206static void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie)
207{
208 int i;
209
210 for (i = 0; i < PCI_NUM_INTX; i++)
211 ks_dw_app_writel(ks_pcie, IRQ_ENABLE_SET + (i << 4), 0x1);
212}
213
214static void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie,
215 int offset)
216{
217 struct dw_pcie *pci = ks_pcie->pci;
218 struct device *dev = pci->dev;
219 u32 pending;
220 int virq;
221
222 pending = ks_dw_app_readl(ks_pcie, IRQ_STATUS + (offset << 4));
223
224 if (BIT(0) & pending) {
225 virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset);
226 dev_dbg(dev, ": irq: irq_offset %d, virq %d\n", offset, virq);
227 generic_handle_irq(virq);
228 }
229
230 /* EOI the INTx interrupt */
231 ks_dw_app_writel(ks_pcie, IRQ_EOI, offset);
232}
233
234static void ks_dw_pcie_enable_error_irq(struct keystone_pcie *ks_pcie)
235{
236 ks_dw_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL);
237}
238
239static irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *ks_pcie)
240{
241 u32 status;
242
243 status = ks_dw_app_readl(ks_pcie, ERR_IRQ_STATUS_RAW) & ERR_IRQ_ALL;
244 if (!status)
245 return IRQ_NONE;
246
247 if (status & ERR_FATAL_IRQ)
248 dev_err(ks_pcie->pci->dev, "fatal error (status %#010x)\n",
249 status);
250
251 /* Ack the IRQ; status bits are RW1C */
252 ks_dw_app_writel(ks_pcie, ERR_IRQ_STATUS, status);
253 return IRQ_HANDLED;
254}
255
256static void ks_dw_pcie_ack_legacy_irq(struct irq_data *d)
257{
258}
259
260static void ks_dw_pcie_mask_legacy_irq(struct irq_data *d)
261{
262}
263
264static void ks_dw_pcie_unmask_legacy_irq(struct irq_data *d)
265{
266}
267
268static struct irq_chip ks_dw_pcie_legacy_irq_chip = {
269 .name = "Keystone-PCI-Legacy-IRQ",
270 .irq_ack = ks_dw_pcie_ack_legacy_irq,
271 .irq_mask = ks_dw_pcie_mask_legacy_irq,
272 .irq_unmask = ks_dw_pcie_unmask_legacy_irq,
273};
274
275static int ks_dw_pcie_init_legacy_irq_map(struct irq_domain *d,
276 unsigned int irq,
277 irq_hw_number_t hw_irq)
278{
279 irq_set_chip_and_handler(irq, &ks_dw_pcie_legacy_irq_chip,
280 handle_level_irq);
281 irq_set_chip_data(irq, d->host_data);
282
283 return 0;
284}
285
286static const struct irq_domain_ops ks_dw_pcie_legacy_irq_domain_ops = {
287 .map = ks_dw_pcie_init_legacy_irq_map,
288 .xlate = irq_domain_xlate_onetwocell,
289};
290
291/**
292 * ks_dw_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask
293 * registers
294 *
295 * Since modification of dbi_cs2 involves different clock domain, read the
296 * status back to ensure the transition is complete.
297 */
298static void ks_dw_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie)
299{
300 u32 val;
301
302 val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
303 ks_dw_app_writel(ks_pcie, CMD_STATUS, DBI_CS2_EN_VAL | val);
304
305 do {
306 val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
307 } while (!(val & DBI_CS2_EN_VAL));
308}
309
310/**
311 * ks_dw_pcie_clear_dbi_mode() - Disable DBI mode
312 *
313 * Since modification of dbi_cs2 involves different clock domain, read the
314 * status back to ensure the transition is complete.
315 */
316static void ks_dw_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie)
317{
318 u32 val;
319
320 val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
321 ks_dw_app_writel(ks_pcie, CMD_STATUS, ~DBI_CS2_EN_VAL & val);
322
323 do {
324 val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
325 } while (val & DBI_CS2_EN_VAL);
326}
327
328static void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
329{
330 struct dw_pcie *pci = ks_pcie->pci;
331 struct pcie_port *pp = &pci->pp;
332 u32 start = pp->mem->start, end = pp->mem->end;
333 int i, tr_size;
334 u32 val;
335
336 /* Disable BARs for inbound access */
337 ks_dw_pcie_set_dbi_mode(ks_pcie);
338 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
339 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0);
340 ks_dw_pcie_clear_dbi_mode(ks_pcie);
341
342 /* Set outbound translation size per window division */
343 ks_dw_app_writel(ks_pcie, OB_SIZE, CFG_PCIM_WIN_SZ_IDX & 0x7);
344
345 tr_size = (1 << (CFG_PCIM_WIN_SZ_IDX & 0x7)) * SZ_1M;
346
347 /* Using Direct 1:1 mapping of RC <-> PCI memory space */
348 for (i = 0; (i < CFG_PCIM_WIN_CNT) && (start < end); i++) {
349 ks_dw_app_writel(ks_pcie, OB_OFFSET_INDEX(i), start | 1);
350 ks_dw_app_writel(ks_pcie, OB_OFFSET_HI(i), 0);
351 start += tr_size;
352 }
353
354 /* Enable OB translation */
355 val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
356 ks_dw_app_writel(ks_pcie, CMD_STATUS, OB_XLAT_EN_VAL | val);
357}
358
359/**
360 * ks_pcie_cfg_setup() - Set up configuration space address for a device
361 *
362 * @ks_pcie: ptr to keystone_pcie structure
363 * @bus: Bus number the device is residing on
364 * @devfn: device, function number info
365 *
366 * Forms and returns the address of configuration space mapped in PCIESS
367 * address space 0. Also configures CFG_SETUP for remote configuration space
368 * access.
369 *
370 * The address space has two regions to access configuration - local and remote.
371 * We access local region for bus 0 (as RC is attached on bus 0) and remote
372 * region for others with TYPE 1 access when bus > 1. As for device on bus = 1,
373 * we will do TYPE 0 access as it will be on our secondary bus (logical).
374 * CFG_SETUP is needed only for remote configuration access.
375 */
376static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *ks_pcie, u8 bus,
377 unsigned int devfn)
378{
379 u8 device = PCI_SLOT(devfn), function = PCI_FUNC(devfn);
380 struct dw_pcie *pci = ks_pcie->pci;
381 struct pcie_port *pp = &pci->pp;
382 u32 regval;
383
384 if (bus == 0)
385 return pci->dbi_base;
386
387 regval = (bus << 16) | (device << 8) | function;
388
389 /*
390 * Since Bus#1 will be a virtual bus, we need to have TYPE0
391 * access only.
392 * TYPE 1
393 */
394 if (bus != 1)
395 regval |= BIT(24);
396
397 ks_dw_app_writel(ks_pcie, CFG_SETUP, regval);
398 return pp->va_cfg0_base;
399}
400
401static int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
402 unsigned int devfn, int where, int size,
403 u32 *val)
404{
405 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
406 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
407 u8 bus_num = bus->number;
408 void __iomem *addr;
409
410 addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);
411
412 return dw_pcie_read(addr + where, size, val);
413}
414
415static int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
416 unsigned int devfn, int where, int size,
417 u32 val)
418{
419 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
420 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
421 u8 bus_num = bus->number;
422 void __iomem *addr;
423
424 addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);
425
426 return dw_pcie_write(addr + where, size, val);
427}
428
429/**
430 * ks_dw_pcie_v3_65_scan_bus() - keystone scan_bus post initialization
431 *
432 * This sets BAR0 to enable inbound access for MSI_IRQ register
433 */
434static void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
435{
436 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
437 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
438
439 /* Configure and set up BAR0 */
440 ks_dw_pcie_set_dbi_mode(ks_pcie);
441
442 /* Enable BAR0 */
443 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1);
444 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1);
445
446 ks_dw_pcie_clear_dbi_mode(ks_pcie);
447
448 /*
449 * For BAR0, just setting bus address for inbound writes (MSI) should
450 * be sufficient. Use physical address to avoid any conflicts.
451 */
452 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
453}
454
455/**
456 * ks_dw_pcie_link_up() - Check if link up
457 */
458static int ks_dw_pcie_link_up(struct dw_pcie *pci)
459{
460 u32 val;
461
462 val = dw_pcie_readl_dbi(pci, DEBUG0);
463 return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0;
464}
465
466static void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie)
467{
468 u32 val;
469
470 /* Disable Link training */
471 val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
472 val &= ~LTSSM_EN_VAL;
473 ks_dw_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val);
474
475 /* Initiate Link Training */
476 val = ks_dw_app_readl(ks_pcie, CMD_STATUS);
477 ks_dw_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val);
478}
479
480/**
481 * ks_dw_pcie_host_init() - initialize host for v3_65 dw hardware
482 *
483 * Ioremap the register resources, initialize legacy irq domain
484 * and call dw_pcie_v3_65_host_init() API to initialize the Keystone
485 * PCI host controller.
486 */
487static int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie)
488{
489 struct dw_pcie *pci = ks_pcie->pci;
490 struct pcie_port *pp = &pci->pp;
491 struct device *dev = pci->dev;
492 struct platform_device *pdev = to_platform_device(dev);
493 struct resource *res;
494
495 /* Index 0 is the config reg. space address */
496 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
497 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res);
498 if (IS_ERR(pci->dbi_base))
499 return PTR_ERR(pci->dbi_base);
500
501 /*
502 * We set these same and is used in pcie rd/wr_other_conf
503 * functions
504 */
505 pp->va_cfg0_base = pci->dbi_base + SPACE0_REMOTE_CFG_OFFSET;
506 pp->va_cfg1_base = pp->va_cfg0_base;
507
508 /* Index 1 is the application reg. space address */
509 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
510 ks_pcie->va_app_base = devm_ioremap_resource(dev, res);
511 if (IS_ERR(ks_pcie->va_app_base))
512 return PTR_ERR(ks_pcie->va_app_base);
513
514 ks_pcie->app = *res;
515
516 /* Create legacy IRQ domain */
517 ks_pcie->legacy_irq_domain =
518 irq_domain_add_linear(ks_pcie->legacy_intc_np,
519 PCI_NUM_INTX,
520 &ks_dw_pcie_legacy_irq_domain_ops,
521 NULL);
522 if (!ks_pcie->legacy_irq_domain) {
523 dev_err(dev, "Failed to add irq domain for legacy irqs\n");
524 return -EINVAL;
525 }
526
527 return dw_pcie_host_init(pp);
528}
529
43static void quirk_limit_mrrs(struct pci_dev *dev) 530static void quirk_limit_mrrs(struct pci_dev *dev)
44{ 531{
45 struct pci_bus *bus = dev->bus; 532 struct pci_bus *bus = dev->bus;
diff --git a/drivers/pci/controller/dwc/pci-keystone.h b/drivers/pci/controller/dwc/pci-keystone.h
deleted file mode 100644
index 4eacc263f157..000000000000
--- a/drivers/pci/controller/dwc/pci-keystone.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Keystone PCI Controller's common includes
4 *
5 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
6 * http://www.ti.com
7 *
8 * Author: Murali Karicheri <m-karicheri2@ti.com>
9 */
10
11#define MAX_MSI_HOST_IRQS 8
12
13struct keystone_pcie {
14 struct dw_pcie *pci;
15 struct clk *clk;
16 /* PCI Device ID */
17 u32 device_id;
18 int num_legacy_host_irqs;
19 int legacy_host_irqs[PCI_NUM_INTX];
20 struct device_node *legacy_intc_np;
21
22 int num_msi_host_irqs;
23 int msi_host_irqs[MAX_MSI_HOST_IRQS];
24 struct device_node *msi_intc_np;
25 struct irq_domain *legacy_irq_domain;
26 struct device_node *np;
27
28 int error_irq;
29
30 /* Application register space */
31 void __iomem *va_app_base; /* DT 1st resource */
32 struct resource app;
33};
34
35/* Keystone DW specific MSI controller APIs/definitions */
36void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset);
37phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp);
38
39/* Keystone specific PCI controller APIs */
40void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie);
41void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset);
42void ks_dw_pcie_enable_error_irq(struct keystone_pcie *ks_pcie);
43irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *ks_pcie);
44int ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie);
45int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
46 unsigned int devfn, int where, int size, u32 val);
47int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
48 unsigned int devfn, int where, int size, u32 *val);
49void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie);
50void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie);
51void ks_dw_pcie_msi_irq_ack(int i, struct pcie_port *pp);
52void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq);
53void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq);
54void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp);
55int ks_dw_pcie_msi_host_init(struct pcie_port *pp);
56int ks_dw_pcie_link_up(struct dw_pcie *pci);
generated by cgit v1.2.2 (git 2.25.0) at 2025-06-01 14:15:10 -0400