diff options
author | Gustavo Pimentel <gustavo.pimentel@synopsys.com> | 2019-01-31 13:17:07 -0500 |
---|---|---|
committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2019-02-01 07:36:36 -0500 |
commit | 657722570a555c728c59f17f7825c812c124dc28 (patch) | |
tree | a6c8f6f3420f420e7f78d8b9e815437a4e2b30d7 /drivers/pci/controller/dwc | |
parent | a348d015f0de7a08f88f8089f6f6c4bc5248029b (diff) |
PCI: dwc: Replace bit rotation operation (1 << bit) with BIT(bit)
Replace bit rotation operation (1 << bit) with BIT(bit), which
simplifies code reading.
No functional change is intended.
Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Joao Pinto <jpinto@synopsys.com>
Cc: Jingoo Han <jingoohan1@gmail.com>
Diffstat (limited to 'drivers/pci/controller/dwc')
-rw-r--r-- | drivers/pci/controller/dwc/pcie-designware-host.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index c550c4a7ef89..45ff5e4f8af6 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c | |||
@@ -164,7 +164,7 @@ static void dw_pci_bottom_mask(struct irq_data *d) | |||
164 | res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; | 164 | res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; |
165 | bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; | 165 | bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; |
166 | 166 | ||
167 | pp->irq_mask[ctrl] |= (1 << bit); | 167 | pp->irq_mask[ctrl] |= BIT(bit); |
168 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, | 168 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, |
169 | pp->irq_mask[ctrl]); | 169 | pp->irq_mask[ctrl]); |
170 | } | 170 | } |
@@ -187,7 +187,7 @@ static void dw_pci_bottom_unmask(struct irq_data *d) | |||
187 | res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; | 187 | res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; |
188 | bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; | 188 | bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; |
189 | 189 | ||
190 | pp->irq_mask[ctrl] &= ~(1 << bit); | 190 | pp->irq_mask[ctrl] &= ~BIT(bit); |
191 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, | 191 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, |
192 | pp->irq_mask[ctrl]); | 192 | pp->irq_mask[ctrl]); |
193 | } | 193 | } |
@@ -207,7 +207,7 @@ static void dw_pci_bottom_ack(struct irq_data *d) | |||
207 | 207 | ||
208 | raw_spin_lock_irqsave(&pp->lock, flags); | 208 | raw_spin_lock_irqsave(&pp->lock, flags); |
209 | 209 | ||
210 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + res, 4, 1 << bit); | 210 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + res, 4, BIT(bit)); |
211 | 211 | ||
212 | if (pp->ops->msi_irq_ack) | 212 | if (pp->ops->msi_irq_ack) |
213 | pp->ops->msi_irq_ack(d->hwirq, pp); | 213 | pp->ops->msi_irq_ack(d->hwirq, pp); |