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authorKishon Vijay Abraham I <kishon@ti.com>2018-10-17 03:40:54 -0400
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2018-10-17 04:38:39 -0400
commit148e340c0696369fadbbddc8f4bef801ed247d71 (patch)
tree7f99bb7c0d4f339b83a723eef47865251d1263dd /drivers/pci/controller/dwc
parent7876320f88802b22d4e2daf7eb027dd14175a0f8 (diff)
PCI: keystone: Use quirk to limit MRRS for K2G
PCI controller in K2G also has a limitation that memory read request size (MRRS) must not exceed 256 bytes. Use the quirk to limit MRRS (added for K2HK, K2L and K2E) for K2G as well. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Diffstat (limited to 'drivers/pci/controller/dwc')
-rw-r--r--drivers/pci/controller/dwc/pci-keystone.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
index e88bd221fffe..7d43e10a03b0 100644
--- a/drivers/pci/controller/dwc/pci-keystone.c
+++ b/drivers/pci/controller/dwc/pci-keystone.c
@@ -36,6 +36,7 @@
36#define PCIE_RC_K2HK 0xb008 36#define PCIE_RC_K2HK 0xb008
37#define PCIE_RC_K2E 0xb009 37#define PCIE_RC_K2E 0xb009
38#define PCIE_RC_K2L 0xb00a 38#define PCIE_RC_K2L 0xb00a
39#define PCIE_RC_K2G 0xb00b
39 40
40#define to_keystone_pcie(x) dev_get_drvdata((x)->dev) 41#define to_keystone_pcie(x) dev_get_drvdata((x)->dev)
41 42
@@ -50,6 +51,8 @@ static void quirk_limit_mrrs(struct pci_dev *dev)
50 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, 51 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
51 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2L), 52 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2L),
52 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, 53 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
54 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2G),
55 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
53 { 0, }, 56 { 0, },
54 }; 57 };
55 58