PCI: dwc: Make use of BIT() in constant definitions

Avoid using explicit left shifts and convert various definitions to
use BIT() instead. No functional change intended.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
[lorenzo.pieralisi@arm.com: fixed PORT_LOGIC_SPEED_CHANGE redefinition]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org

1 files changed, 7 insertions, 7 deletions

diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 279000255ad1..070382869685 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -41,7 +41,7 @@
 #define PORT_LOGIC_LTSSM_STATE_L0       0x11
 
 #define PCIE_LINK_WIDTH_SPEED_CONTROL   0x80C
-#define PORT_LOGIC_SPEED_CHANGE         (0x1 << 17)
+#define PORT_LOGIC_SPEED_CHANGE         BIT(17)
 #define PORT_LOGIC_LINK_WIDTH_MASK      (0x1f << 8)
 #define PORT_LOGIC_LINK_WIDTH_1_LANES   (0x1 << 8)
 #define PORT_LOGIC_LINK_WIDTH_2_LANES   (0x2 << 8)
@@ -55,8 +55,8 @@
 #define PCIE_MSI_INTR0_STATUS           0x830
 
 #define PCIE_ATU_VIEWPORT               0x900
-#define PCIE_ATU_REGION_INBOUND         (0x1 << 31)
-#define PCIE_ATU_REGION_OUTBOUND        (0x0 << 31)
+#define PCIE_ATU_REGION_INBOUND         BIT(31)
+#define PCIE_ATU_REGION_OUTBOUND        0
 #define PCIE_ATU_REGION_INDEX2          (0x2 << 0)
 #define PCIE_ATU_REGION_INDEX1          (0x1 << 0)
 #define PCIE_ATU_REGION_INDEX0          (0x0 << 0)
@@ -66,8 +66,8 @@
 #define PCIE_ATU_TYPE_CFG0              (0x4 << 0)
 #define PCIE_ATU_TYPE_CFG1              (0x5 << 0)
 #define PCIE_ATU_CR2                    0x908
-#define PCIE_ATU_ENABLE                 (0x1 << 31)
-#define PCIE_ATU_BAR_MODE_ENABLE        (0x1 << 30)
+#define PCIE_ATU_ENABLE                 BIT(31)
+#define PCIE_ATU_BAR_MODE_ENABLE        BIT(30)
 #define PCIE_ATU_LOWER_BASE             0x90C
 #define PCIE_ATU_UPPER_BASE             0x910
 #define PCIE_ATU_LIMIT                  0x914
@@ -78,7 +78,7 @@
 #define PCIE_ATU_UPPER_TARGET           0x91C
 
 #define PCIE_MISC_CONTROL_1_OFF         0x8BC
-#define PCIE_DBI_RO_WR_EN               (0x1 << 0)
+#define PCIE_DBI_RO_WR_EN               BIT(0)
 
 /*
  * iATU Unroll-specific register definitions
@@ -105,7 +105,7 @@
                 ((region) << 9)
 
 #define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \
-                (((region) << 9) | (0x1 << 8))
+                (((region) << 9) | BIT(8))
 
 #define MAX_MSI_IRQS                    256
 #define MAX_MSI_IRQS_PER_CTRL           32