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authorDave Jiang <dave.jiang@intel.com>2018-01-29 15:22:18 -0500
committerJon Mason <jdmason@kudzu.us>2018-06-11 15:20:59 -0400
commita9065055ed09fe6e59e5bbfd12c8de629c53005d (patch)
tree6b61ed31e30353b798658c49ddffe80c0250fd0d /drivers/ntb
parent29dcea88779c856c7dc92040a0c01233263101d4 (diff)
ntb: intel: header definitions refactor
Break out the generation specific definitions to different headers Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
Diffstat (limited to 'drivers/ntb')
-rw-r--r--drivers/ntb/hw/intel/ntb_hw_gen1.h142
-rw-r--r--drivers/ntb/hw/intel/ntb_hw_gen3.h92
-rw-r--r--drivers/ntb/hw/intel/ntb_hw_intel.c2
-rw-r--r--drivers/ntb/hw/intel/ntb_hw_intel.h143
4 files changed, 237 insertions, 142 deletions
diff --git a/drivers/ntb/hw/intel/ntb_hw_gen1.h b/drivers/ntb/hw/intel/ntb_hw_gen1.h
new file mode 100644
index 000000000000..fa61dcb4e812
--- /dev/null
+++ b/drivers/ntb/hw/intel/ntb_hw_gen1.h
@@ -0,0 +1,142 @@
1/*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright(c) 2012-2017 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * BSD LICENSE
14 *
15 * Copyright(c) 2012-2017 Intel Corporation. All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
19 * are met:
20 *
21 * * Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * * Redistributions in binary form must reproduce the above copy
24 * notice, this list of conditions and the following disclaimer in
25 * the documentation and/or other materials provided with the
26 * distribution.
27 * * Neither the name of Intel Corporation nor the names of its
28 * contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
30 *
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
36 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
37 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 */
43
44#ifndef _NTB_INTEL_GEN1_H_
45#define _NTB_INTEL_GEN1_H_
46
47/* Intel Gen1 Xeon hardware */
48#define XEON_PBAR23LMT_OFFSET 0x0000
49#define XEON_PBAR45LMT_OFFSET 0x0008
50#define XEON_PBAR4LMT_OFFSET 0x0008
51#define XEON_PBAR5LMT_OFFSET 0x000c
52#define XEON_PBAR23XLAT_OFFSET 0x0010
53#define XEON_PBAR45XLAT_OFFSET 0x0018
54#define XEON_PBAR4XLAT_OFFSET 0x0018
55#define XEON_PBAR5XLAT_OFFSET 0x001c
56#define XEON_SBAR23LMT_OFFSET 0x0020
57#define XEON_SBAR45LMT_OFFSET 0x0028
58#define XEON_SBAR4LMT_OFFSET 0x0028
59#define XEON_SBAR5LMT_OFFSET 0x002c
60#define XEON_SBAR23XLAT_OFFSET 0x0030
61#define XEON_SBAR45XLAT_OFFSET 0x0038
62#define XEON_SBAR4XLAT_OFFSET 0x0038
63#define XEON_SBAR5XLAT_OFFSET 0x003c
64#define XEON_SBAR0BASE_OFFSET 0x0040
65#define XEON_SBAR23BASE_OFFSET 0x0048
66#define XEON_SBAR45BASE_OFFSET 0x0050
67#define XEON_SBAR4BASE_OFFSET 0x0050
68#define XEON_SBAR5BASE_OFFSET 0x0054
69#define XEON_SBDF_OFFSET 0x005c
70#define XEON_NTBCNTL_OFFSET 0x0058
71#define XEON_PDOORBELL_OFFSET 0x0060
72#define XEON_PDBMSK_OFFSET 0x0062
73#define XEON_SDOORBELL_OFFSET 0x0064
74#define XEON_SDBMSK_OFFSET 0x0066
75#define XEON_USMEMMISS_OFFSET 0x0070
76#define XEON_SPAD_OFFSET 0x0080
77#define XEON_PBAR23SZ_OFFSET 0x00d0
78#define XEON_PBAR45SZ_OFFSET 0x00d1
79#define XEON_PBAR4SZ_OFFSET 0x00d1
80#define XEON_SBAR23SZ_OFFSET 0x00d2
81#define XEON_SBAR45SZ_OFFSET 0x00d3
82#define XEON_SBAR4SZ_OFFSET 0x00d3
83#define XEON_PPD_OFFSET 0x00d4
84#define XEON_PBAR5SZ_OFFSET 0x00d5
85#define XEON_SBAR5SZ_OFFSET 0x00d6
86#define XEON_WCCNTRL_OFFSET 0x00e0
87#define XEON_UNCERRSTS_OFFSET 0x014c
88#define XEON_CORERRSTS_OFFSET 0x0158
89#define XEON_LINK_STATUS_OFFSET 0x01a2
90#define XEON_SPCICMD_OFFSET 0x0504
91#define XEON_DEVCTRL_OFFSET 0x0598
92#define XEON_DEVSTS_OFFSET 0x059a
93#define XEON_SLINK_STATUS_OFFSET 0x05a2
94#define XEON_B2B_SPAD_OFFSET 0x0100
95#define XEON_B2B_DOORBELL_OFFSET 0x0140
96#define XEON_B2B_XLAT_OFFSETL 0x0144
97#define XEON_B2B_XLAT_OFFSETU 0x0148
98#define XEON_PPD_CONN_MASK 0x03
99#define XEON_PPD_CONN_TRANSPARENT 0x00
100#define XEON_PPD_CONN_B2B 0x01
101#define XEON_PPD_CONN_RP 0x02
102#define XEON_PPD_DEV_MASK 0x10
103#define XEON_PPD_DEV_USD 0x00
104#define XEON_PPD_DEV_DSD 0x10
105#define XEON_PPD_SPLIT_BAR_MASK 0x40
106
107#define XEON_PPD_TOPO_MASK (XEON_PPD_CONN_MASK | XEON_PPD_DEV_MASK)
108#define XEON_PPD_TOPO_PRI_USD (XEON_PPD_CONN_RP | XEON_PPD_DEV_USD)
109#define XEON_PPD_TOPO_PRI_DSD (XEON_PPD_CONN_RP | XEON_PPD_DEV_DSD)
110#define XEON_PPD_TOPO_SEC_USD (XEON_PPD_CONN_TRANSPARENT | XEON_PPD_DEV_USD)
111#define XEON_PPD_TOPO_SEC_DSD (XEON_PPD_CONN_TRANSPARENT | XEON_PPD_DEV_DSD)
112#define XEON_PPD_TOPO_B2B_USD (XEON_PPD_CONN_B2B | XEON_PPD_DEV_USD)
113#define XEON_PPD_TOPO_B2B_DSD (XEON_PPD_CONN_B2B | XEON_PPD_DEV_DSD)
114
115#define XEON_MW_COUNT 2
116#define HSX_SPLIT_BAR_MW_COUNT 3
117#define XEON_DB_COUNT 15
118#define XEON_DB_LINK 15
119#define XEON_DB_LINK_BIT BIT_ULL(XEON_DB_LINK)
120#define XEON_DB_MSIX_VECTOR_COUNT 4
121#define XEON_DB_MSIX_VECTOR_SHIFT 5
122#define XEON_DB_TOTAL_SHIFT 16
123#define XEON_SPAD_COUNT 16
124
125/* Use the following addresses for translation between b2b ntb devices in case
126 * the hardware default values are not reliable. */
127#define XEON_B2B_BAR0_ADDR 0x1000000000000000ull
128#define XEON_B2B_BAR2_ADDR64 0x2000000000000000ull
129#define XEON_B2B_BAR4_ADDR64 0x4000000000000000ull
130#define XEON_B2B_BAR4_ADDR32 0x20000000u
131#define XEON_B2B_BAR5_ADDR32 0x40000000u
132
133/* The peer ntb secondary config space is 32KB fixed size */
134#define XEON_B2B_MIN_SIZE 0x8000
135
136/* flags to indicate hardware errata */
137#define NTB_HWERR_SDOORBELL_LOCKUP BIT_ULL(0)
138#define NTB_HWERR_SB01BASE_LOCKUP BIT_ULL(1)
139#define NTB_HWERR_B2BDOORBELL_BIT14 BIT_ULL(2)
140#define NTB_HWERR_MSIX_VECTOR32_BAD BIT_ULL(3)
141
142#endif
diff --git a/drivers/ntb/hw/intel/ntb_hw_gen3.h b/drivers/ntb/hw/intel/ntb_hw_gen3.h
new file mode 100644
index 000000000000..889453ca2ce6
--- /dev/null
+++ b/drivers/ntb/hw/intel/ntb_hw_gen3.h
@@ -0,0 +1,92 @@
1/*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright(c) 2012-2017 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * BSD LICENSE
14 *
15 * Copyright(c) 2012-2017 Intel Corporation. All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
19 * are met:
20 *
21 * * Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * * Redistributions in binary form must reproduce the above copy
24 * notice, this list of conditions and the following disclaimer in
25 * the documentation and/or other materials provided with the
26 * distribution.
27 * * Neither the name of Intel Corporation nor the names of its
28 * contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
30 *
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
36 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
37 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 */
43
44#ifndef _NTB_INTEL_GEN3_H_
45#define _NTB_INTEL_GEN3_H_
46
47/* Intel Skylake Xeon hardware */
48#define SKX_IMBAR1SZ_OFFSET 0x00d0
49#define SKX_IMBAR2SZ_OFFSET 0x00d1
50#define SKX_EMBAR1SZ_OFFSET 0x00d2
51#define SKX_EMBAR2SZ_OFFSET 0x00d3
52#define SKX_DEVCTRL_OFFSET 0x0098
53#define SKX_DEVSTS_OFFSET 0x009a
54#define SKX_UNCERRSTS_OFFSET 0x014c
55#define SKX_CORERRSTS_OFFSET 0x0158
56#define SKX_LINK_STATUS_OFFSET 0x01a2
57
58#define SKX_NTBCNTL_OFFSET 0x0000
59#define SKX_IMBAR1XBASE_OFFSET 0x0010 /* SBAR2XLAT */
60#define SKX_IMBAR1XLMT_OFFSET 0x0018 /* SBAR2LMT */
61#define SKX_IMBAR2XBASE_OFFSET 0x0020 /* SBAR4XLAT */
62#define SKX_IMBAR2XLMT_OFFSET 0x0028 /* SBAR4LMT */
63#define SKX_IM_INT_STATUS_OFFSET 0x0040
64#define SKX_IM_INT_DISABLE_OFFSET 0x0048
65#define SKX_IM_SPAD_OFFSET 0x0080 /* SPAD */
66#define SKX_USMEMMISS_OFFSET 0x0070
67#define SKX_INTVEC_OFFSET 0x00d0
68#define SKX_IM_DOORBELL_OFFSET 0x0100 /* SDOORBELL0 */
69#define SKX_B2B_SPAD_OFFSET 0x0180 /* B2B SPAD */
70#define SKX_EMBAR0XBASE_OFFSET 0x4008 /* B2B_XLAT */
71#define SKX_EMBAR1XBASE_OFFSET 0x4010 /* PBAR2XLAT */
72#define SKX_EMBAR1XLMT_OFFSET 0x4018 /* PBAR2LMT */
73#define SKX_EMBAR2XBASE_OFFSET 0x4020 /* PBAR4XLAT */
74#define SKX_EMBAR2XLMT_OFFSET 0x4028 /* PBAR4LMT */
75#define SKX_EM_INT_STATUS_OFFSET 0x4040
76#define SKX_EM_INT_DISABLE_OFFSET 0x4048
77#define SKX_EM_SPAD_OFFSET 0x4080 /* remote SPAD */
78#define SKX_EM_DOORBELL_OFFSET 0x4100 /* PDOORBELL0 */
79#define SKX_SPCICMD_OFFSET 0x4504 /* SPCICMD */
80#define SKX_EMBAR0_OFFSET 0x4510 /* SBAR0BASE */
81#define SKX_EMBAR1_OFFSET 0x4518 /* SBAR23BASE */
82#define SKX_EMBAR2_OFFSET 0x4520 /* SBAR45BASE */
83
84#define SKX_DB_COUNT 32
85#define SKX_DB_LINK 32
86#define SKX_DB_LINK_BIT BIT_ULL(SKX_DB_LINK)
87#define SKX_DB_MSIX_VECTOR_COUNT 33
88#define SKX_DB_MSIX_VECTOR_SHIFT 1
89#define SKX_DB_TOTAL_SHIFT 33
90#define SKX_SPAD_COUNT 16
91
92#endif
diff --git a/drivers/ntb/hw/intel/ntb_hw_intel.c b/drivers/ntb/hw/intel/ntb_hw_intel.c
index 156b45cd4a19..44bf2f4eb068 100644
--- a/drivers/ntb/hw/intel/ntb_hw_intel.c
+++ b/drivers/ntb/hw/intel/ntb_hw_intel.c
@@ -60,6 +60,8 @@
60#include <linux/slab.h> 60#include <linux/slab.h>
61#include <linux/ntb.h> 61#include <linux/ntb.h>
62 62
63#include "ntb_hw_gen1.h"
64#include "ntb_hw_gen3.h"
63#include "ntb_hw_intel.h" 65#include "ntb_hw_intel.h"
64 66
65#define NTB_NAME "ntb_hw_intel" 67#define NTB_NAME "ntb_hw_intel"
diff --git a/drivers/ntb/hw/intel/ntb_hw_intel.h b/drivers/ntb/hw/intel/ntb_hw_intel.h
index 4415aa7ea775..bdfa302e0152 100644
--- a/drivers/ntb/hw/intel/ntb_hw_intel.h
+++ b/drivers/ntb/hw/intel/ntb_hw_intel.h
@@ -54,6 +54,7 @@
54#include <linux/ntb.h> 54#include <linux/ntb.h>
55#include <linux/pci.h> 55#include <linux/pci.h>
56 56
57/* PCI device IDs */
57#define PCI_DEVICE_ID_INTEL_NTB_B2B_JSF 0x3725 58#define PCI_DEVICE_ID_INTEL_NTB_B2B_JSF 0x3725
58#define PCI_DEVICE_ID_INTEL_NTB_PS_JSF 0x3726 59#define PCI_DEVICE_ID_INTEL_NTB_PS_JSF 0x3726
59#define PCI_DEVICE_ID_INTEL_NTB_SS_JSF 0x3727 60#define PCI_DEVICE_ID_INTEL_NTB_SS_JSF 0x3727
@@ -71,132 +72,7 @@
71#define PCI_DEVICE_ID_INTEL_NTB_SS_BDX 0x6F0F 72#define PCI_DEVICE_ID_INTEL_NTB_SS_BDX 0x6F0F
72#define PCI_DEVICE_ID_INTEL_NTB_B2B_SKX 0x201C 73#define PCI_DEVICE_ID_INTEL_NTB_B2B_SKX 0x201C
73 74
74/* Intel Xeon hardware */
75
76#define XEON_PBAR23LMT_OFFSET 0x0000
77#define XEON_PBAR45LMT_OFFSET 0x0008
78#define XEON_PBAR4LMT_OFFSET 0x0008
79#define XEON_PBAR5LMT_OFFSET 0x000c
80#define XEON_PBAR23XLAT_OFFSET 0x0010
81#define XEON_PBAR45XLAT_OFFSET 0x0018
82#define XEON_PBAR4XLAT_OFFSET 0x0018
83#define XEON_PBAR5XLAT_OFFSET 0x001c
84#define XEON_SBAR23LMT_OFFSET 0x0020
85#define XEON_SBAR45LMT_OFFSET 0x0028
86#define XEON_SBAR4LMT_OFFSET 0x0028
87#define XEON_SBAR5LMT_OFFSET 0x002c
88#define XEON_SBAR23XLAT_OFFSET 0x0030
89#define XEON_SBAR45XLAT_OFFSET 0x0038
90#define XEON_SBAR4XLAT_OFFSET 0x0038
91#define XEON_SBAR5XLAT_OFFSET 0x003c
92#define XEON_SBAR0BASE_OFFSET 0x0040
93#define XEON_SBAR23BASE_OFFSET 0x0048
94#define XEON_SBAR45BASE_OFFSET 0x0050
95#define XEON_SBAR4BASE_OFFSET 0x0050
96#define XEON_SBAR5BASE_OFFSET 0x0054
97#define XEON_SBDF_OFFSET 0x005c
98#define XEON_NTBCNTL_OFFSET 0x0058
99#define XEON_PDOORBELL_OFFSET 0x0060
100#define XEON_PDBMSK_OFFSET 0x0062
101#define XEON_SDOORBELL_OFFSET 0x0064
102#define XEON_SDBMSK_OFFSET 0x0066
103#define XEON_USMEMMISS_OFFSET 0x0070
104#define XEON_SPAD_OFFSET 0x0080
105#define XEON_PBAR23SZ_OFFSET 0x00d0
106#define XEON_PBAR45SZ_OFFSET 0x00d1
107#define XEON_PBAR4SZ_OFFSET 0x00d1
108#define XEON_SBAR23SZ_OFFSET 0x00d2
109#define XEON_SBAR45SZ_OFFSET 0x00d3
110#define XEON_SBAR4SZ_OFFSET 0x00d3
111#define XEON_PPD_OFFSET 0x00d4
112#define XEON_PBAR5SZ_OFFSET 0x00d5
113#define XEON_SBAR5SZ_OFFSET 0x00d6
114#define XEON_WCCNTRL_OFFSET 0x00e0
115#define XEON_UNCERRSTS_OFFSET 0x014c
116#define XEON_CORERRSTS_OFFSET 0x0158
117#define XEON_LINK_STATUS_OFFSET 0x01a2
118#define XEON_SPCICMD_OFFSET 0x0504
119#define XEON_DEVCTRL_OFFSET 0x0598
120#define XEON_DEVSTS_OFFSET 0x059a
121#define XEON_SLINK_STATUS_OFFSET 0x05a2
122#define XEON_B2B_SPAD_OFFSET 0x0100
123#define XEON_B2B_DOORBELL_OFFSET 0x0140
124#define XEON_B2B_XLAT_OFFSETL 0x0144
125#define XEON_B2B_XLAT_OFFSETU 0x0148
126#define XEON_PPD_CONN_MASK 0x03
127#define XEON_PPD_CONN_TRANSPARENT 0x00
128#define XEON_PPD_CONN_B2B 0x01
129#define XEON_PPD_CONN_RP 0x02
130#define XEON_PPD_DEV_MASK 0x10
131#define XEON_PPD_DEV_USD 0x00
132#define XEON_PPD_DEV_DSD 0x10
133#define XEON_PPD_SPLIT_BAR_MASK 0x40
134
135#define XEON_PPD_TOPO_MASK (XEON_PPD_CONN_MASK | XEON_PPD_DEV_MASK)
136#define XEON_PPD_TOPO_PRI_USD (XEON_PPD_CONN_RP | XEON_PPD_DEV_USD)
137#define XEON_PPD_TOPO_PRI_DSD (XEON_PPD_CONN_RP | XEON_PPD_DEV_DSD)
138#define XEON_PPD_TOPO_SEC_USD (XEON_PPD_CONN_TRANSPARENT | XEON_PPD_DEV_USD)
139#define XEON_PPD_TOPO_SEC_DSD (XEON_PPD_CONN_TRANSPARENT | XEON_PPD_DEV_DSD)
140#define XEON_PPD_TOPO_B2B_USD (XEON_PPD_CONN_B2B | XEON_PPD_DEV_USD)
141#define XEON_PPD_TOPO_B2B_DSD (XEON_PPD_CONN_B2B | XEON_PPD_DEV_DSD)
142
143#define XEON_MW_COUNT 2
144#define HSX_SPLIT_BAR_MW_COUNT 3
145#define XEON_DB_COUNT 15
146#define XEON_DB_LINK 15
147#define XEON_DB_LINK_BIT BIT_ULL(XEON_DB_LINK)
148#define XEON_DB_MSIX_VECTOR_COUNT 4
149#define XEON_DB_MSIX_VECTOR_SHIFT 5
150#define XEON_DB_TOTAL_SHIFT 16
151#define XEON_SPAD_COUNT 16
152
153/* Intel Skylake Xeon hardware */
154#define SKX_IMBAR1SZ_OFFSET 0x00d0
155#define SKX_IMBAR2SZ_OFFSET 0x00d1
156#define SKX_EMBAR1SZ_OFFSET 0x00d2
157#define SKX_EMBAR2SZ_OFFSET 0x00d3
158#define SKX_DEVCTRL_OFFSET 0x0098
159#define SKX_DEVSTS_OFFSET 0x009a
160#define SKX_UNCERRSTS_OFFSET 0x014c
161#define SKX_CORERRSTS_OFFSET 0x0158
162#define SKX_LINK_STATUS_OFFSET 0x01a2
163
164#define SKX_NTBCNTL_OFFSET 0x0000
165#define SKX_IMBAR1XBASE_OFFSET 0x0010 /* SBAR2XLAT */
166#define SKX_IMBAR1XLMT_OFFSET 0x0018 /* SBAR2LMT */
167#define SKX_IMBAR2XBASE_OFFSET 0x0020 /* SBAR4XLAT */
168#define SKX_IMBAR2XLMT_OFFSET 0x0028 /* SBAR4LMT */
169#define SKX_IM_INT_STATUS_OFFSET 0x0040
170#define SKX_IM_INT_DISABLE_OFFSET 0x0048
171#define SKX_IM_SPAD_OFFSET 0x0080 /* SPAD */
172#define SKX_USMEMMISS_OFFSET 0x0070
173#define SKX_INTVEC_OFFSET 0x00d0
174#define SKX_IM_DOORBELL_OFFSET 0x0100 /* SDOORBELL0 */
175#define SKX_B2B_SPAD_OFFSET 0x0180 /* B2B SPAD */
176#define SKX_EMBAR0XBASE_OFFSET 0x4008 /* B2B_XLAT */
177#define SKX_EMBAR1XBASE_OFFSET 0x4010 /* PBAR2XLAT */
178#define SKX_EMBAR1XLMT_OFFSET 0x4018 /* PBAR2LMT */
179#define SKX_EMBAR2XBASE_OFFSET 0x4020 /* PBAR4XLAT */
180#define SKX_EMBAR2XLMT_OFFSET 0x4028 /* PBAR4LMT */
181#define SKX_EM_INT_STATUS_OFFSET 0x4040
182#define SKX_EM_INT_DISABLE_OFFSET 0x4048
183#define SKX_EM_SPAD_OFFSET 0x4080 /* remote SPAD */
184#define SKX_EM_DOORBELL_OFFSET 0x4100 /* PDOORBELL0 */
185#define SKX_SPCICMD_OFFSET 0x4504 /* SPCICMD */
186#define SKX_EMBAR0_OFFSET 0x4510 /* SBAR0BASE */
187#define SKX_EMBAR1_OFFSET 0x4518 /* SBAR23BASE */
188#define SKX_EMBAR2_OFFSET 0x4520 /* SBAR45BASE */
189
190#define SKX_DB_COUNT 32
191#define SKX_DB_LINK 32
192#define SKX_DB_LINK_BIT BIT_ULL(SKX_DB_LINK)
193#define SKX_DB_MSIX_VECTOR_COUNT 33
194#define SKX_DB_MSIX_VECTOR_SHIFT 1
195#define SKX_DB_TOTAL_SHIFT 33
196#define SKX_SPAD_COUNT 16
197
198/* Ntb control and link status */ 75/* Ntb control and link status */
199
200#define NTB_CTL_CFG_LOCK BIT(0) 76#define NTB_CTL_CFG_LOCK BIT(0)
201#define NTB_CTL_DISABLE BIT(1) 77#define NTB_CTL_DISABLE BIT(1)
202#define NTB_CTL_S2P_BAR2_SNOOP BIT(2) 78#define NTB_CTL_S2P_BAR2_SNOOP BIT(2)
@@ -213,23 +89,6 @@
213#define NTB_LNK_STA_SPEED(x) ((x) & NTB_LNK_STA_SPEED_MASK) 89#define NTB_LNK_STA_SPEED(x) ((x) & NTB_LNK_STA_SPEED_MASK)
214#define NTB_LNK_STA_WIDTH(x) (((x) & NTB_LNK_STA_WIDTH_MASK) >> 4) 90#define NTB_LNK_STA_WIDTH(x) (((x) & NTB_LNK_STA_WIDTH_MASK) >> 4)
215 91
216/* Use the following addresses for translation between b2b ntb devices in case
217 * the hardware default values are not reliable. */
218#define XEON_B2B_BAR0_ADDR 0x1000000000000000ull
219#define XEON_B2B_BAR2_ADDR64 0x2000000000000000ull
220#define XEON_B2B_BAR4_ADDR64 0x4000000000000000ull
221#define XEON_B2B_BAR4_ADDR32 0x20000000u
222#define XEON_B2B_BAR5_ADDR32 0x40000000u
223
224/* The peer ntb secondary config space is 32KB fixed size */
225#define XEON_B2B_MIN_SIZE 0x8000
226
227/* flags to indicate hardware errata */
228#define NTB_HWERR_SDOORBELL_LOCKUP BIT_ULL(0)
229#define NTB_HWERR_SB01BASE_LOCKUP BIT_ULL(1)
230#define NTB_HWERR_B2BDOORBELL_BIT14 BIT_ULL(2)
231#define NTB_HWERR_MSIX_VECTOR32_BAD BIT_ULL(3)
232
233/* flags to indicate unsafe api */ 92/* flags to indicate unsafe api */
234#define NTB_UNSAFE_DB BIT_ULL(0) 93#define NTB_UNSAFE_DB BIT_ULL(0)
235#define NTB_UNSAFE_SPAD BIT_ULL(1) 94#define NTB_UNSAFE_SPAD BIT_ULL(1)
generated by cgit v1.2.2 (git 2.25.0) at 2026-05-11 11:44:04 -0400