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authorKalle Valo <kvalo@codeaurora.org>2018-10-14 04:40:41 -0400
committerKalle Valo <kvalo@codeaurora.org>2018-10-14 04:40:41 -0400
commit6bfa6975f1b72e3e65fb27eedabbe8348322f20a (patch)
treef5c753abcf0960ac84d8637962bed894702ec1ea /drivers/net/wireless
parent03ce6f8a677692e4e5d5196b4e337555285b8996 (diff)
parentbbd10586f0df1a3ff6abda39c9542458fdfc5686 (diff)
Merge tag 'mt76-for-kvalo-2018-10-13' of https://github.com/nbd168/wireless
mt76 patches for 4.20 * mt76x0 fixes * mt76x0e improvements (should be usable now) * usb support improvements * more mt76x0/mt76x2 unification work * minor fix for aggregation + powersave clients
Diffstat (limited to 'drivers/net/wireless')
-rw-r--r--drivers/net/wireless/mediatek/mt76/mmio.c1
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76.h9
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x0/dma.h126
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c55
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.h6
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x0/init.c9
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x0/main.c22
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x0/mcu.h3
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x0/mt76x0.h3
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x0/pci.c49
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x0/pci_mcu.c1
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x0/phy.c311
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x0/usb_mcu.c7
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x02.h25
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c33
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h37
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x02_mac.c206
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x02_mac.h31
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x02_mcu.c74
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x02_mcu.h14
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x02_mmio.c2
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x02_phy.c167
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x02_phy.h39
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x02_regs.h4
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x02_txrx.c29
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x02_usb.h8
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x02_usb_core.c20
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x02_usb_mcu.c27
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x02_util.c120
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c80
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.h23
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x2/init.c3
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x2/mcu.c5
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x2/mt76x2.h2
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c18
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x2/pci_mac.c2
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x2/pci_main.c2
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x2/pci_mcu.c6
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c100
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x2/phy.c61
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c11
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x2/usb_mac.c6
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x2/usb_main.c4
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x2/usb_mcu.c18
-rw-r--r--drivers/net/wireless/mediatek/mt76/mt76x2/usb_phy.c32
-rw-r--r--drivers/net/wireless/mediatek/mt76/tx.c3
-rw-r--r--drivers/net/wireless/mediatek/mt76/usb.c1
47 files changed, 879 insertions, 936 deletions
diff --git a/drivers/net/wireless/mediatek/mt76/mmio.c b/drivers/net/wireless/mediatek/mt76/mmio.c
index 30a5d928e655..1d6bbce76041 100644
--- a/drivers/net/wireless/mediatek/mt76/mmio.c
+++ b/drivers/net/wireless/mediatek/mt76/mmio.c
@@ -79,6 +79,7 @@ void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs)
79 .copy = mt76_mmio_copy, 79 .copy = mt76_mmio_copy,
80 .wr_rp = mt76_mmio_wr_rp, 80 .wr_rp = mt76_mmio_wr_rp,
81 .rd_rp = mt76_mmio_rd_rp, 81 .rd_rp = mt76_mmio_rd_rp,
82 .type = MT76_BUS_MMIO,
82 }; 83 };
83 84
84 dev->bus = &mt76_mmio_ops; 85 dev->bus = &mt76_mmio_ops;
diff --git a/drivers/net/wireless/mediatek/mt76/mt76.h b/drivers/net/wireless/mediatek/mt76/mt76.h
index f723a07cab29..3bfa7f5e3513 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76.h
+++ b/drivers/net/wireless/mediatek/mt76/mt76.h
@@ -38,6 +38,11 @@ struct mt76_reg_pair {
38 u32 value; 38 u32 value;
39}; 39};
40 40
41enum mt76_bus_type {
42 MT76_BUS_MMIO,
43 MT76_BUS_USB,
44};
45
41struct mt76_bus_ops { 46struct mt76_bus_ops {
42 u32 (*rr)(struct mt76_dev *dev, u32 offset); 47 u32 (*rr)(struct mt76_dev *dev, u32 offset);
43 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val); 48 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val);
@@ -48,8 +53,12 @@ struct mt76_bus_ops {
48 const struct mt76_reg_pair *rp, int len); 53 const struct mt76_reg_pair *rp, int len);
49 int (*rd_rp)(struct mt76_dev *dev, u32 base, 54 int (*rd_rp)(struct mt76_dev *dev, u32 base,
50 struct mt76_reg_pair *rp, int len); 55 struct mt76_reg_pair *rp, int len);
56 enum mt76_bus_type type;
51}; 57};
52 58
59#define mt76_is_usb(dev) ((dev)->mt76.bus->type == MT76_BUS_USB)
60#define mt76_is_mmio(dev) ((dev)->mt76.bus->type == MT76_BUS_MMIO)
61
53enum mt76_txq_id { 62enum mt76_txq_id {
54 MT_TXQ_VO = IEEE80211_AC_VO, 63 MT_TXQ_VO = IEEE80211_AC_VO,
55 MT_TXQ_VI = IEEE80211_AC_VI, 64 MT_TXQ_VI = IEEE80211_AC_VI,
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x0/dma.h b/drivers/net/wireless/mediatek/mt76/mt76x0/dma.h
deleted file mode 100644
index 891ce1c3461f..000000000000
--- a/drivers/net/wireless/mediatek/mt76/mt76x0/dma.h
+++ /dev/null
@@ -1,126 +0,0 @@
1/*
2 * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
3 * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef __MT76X0U_DMA_H
16#define __MT76X0U_DMA_H
17
18#include <asm/unaligned.h>
19#include <linux/skbuff.h>
20
21#define MT_DMA_HDR_LEN 4
22#define MT_RX_INFO_LEN 4
23#define MT_FCE_INFO_LEN 4
24#define MT_DMA_HDRS (MT_DMA_HDR_LEN + MT_RX_INFO_LEN)
25
26/* Common Tx DMA descriptor fields */
27#define MT_TXD_INFO_LEN GENMASK(15, 0)
28#define MT_TXD_INFO_D_PORT GENMASK(29, 27)
29#define MT_TXD_INFO_TYPE GENMASK(31, 30)
30
31/* Tx DMA MCU command specific flags */
32#define MT_TXD_CMD_SEQ GENMASK(19, 16)
33#define MT_TXD_CMD_TYPE GENMASK(26, 20)
34
35enum mt76_msg_port {
36 WLAN_PORT,
37 CPU_RX_PORT,
38 CPU_TX_PORT,
39 HOST_PORT,
40 VIRTUAL_CPU_RX_PORT,
41 VIRTUAL_CPU_TX_PORT,
42 DISCARD,
43};
44
45enum mt76_info_type {
46 DMA_PACKET,
47 DMA_COMMAND,
48};
49
50/* Tx DMA packet specific flags */
51#define MT_TXD_PKT_INFO_NEXT_VLD BIT(16)
52#define MT_TXD_PKT_INFO_TX_BURST BIT(17)
53#define MT_TXD_PKT_INFO_80211 BIT(19)
54#define MT_TXD_PKT_INFO_TSO BIT(20)
55#define MT_TXD_PKT_INFO_CSO BIT(21)
56#define MT_TXD_PKT_INFO_WIV BIT(24)
57#define MT_TXD_PKT_INFO_QSEL GENMASK(26, 25)
58
59enum mt76_qsel {
60 MT_QSEL_MGMT,
61 MT_QSEL_HCCA,
62 MT_QSEL_EDCA,
63 MT_QSEL_EDCA_2,
64};
65
66
67static inline int mt76x0_dma_skb_wrap(struct sk_buff *skb,
68 enum mt76_msg_port d_port,
69 enum mt76_info_type type, u32 flags)
70{
71 u32 info;
72
73 /* Buffer layout:
74 * | 4B | xfer len | pad | 4B |
75 * | TXINFO | pkt/cmd | zero pad to 4B | zero |
76 *
77 * length field of TXINFO should be set to 'xfer len'.
78 */
79
80 info = flags |
81 FIELD_PREP(MT_TXD_INFO_LEN, round_up(skb->len, 4)) |
82 FIELD_PREP(MT_TXD_INFO_D_PORT, d_port) |
83 FIELD_PREP(MT_TXD_INFO_TYPE, type);
84
85 put_unaligned_le32(info, skb_push(skb, sizeof(info)));
86 return skb_put_padto(skb, round_up(skb->len, 4) + 4);
87}
88
89static inline int
90mt76x0_dma_skb_wrap_pkt(struct sk_buff *skb, enum mt76_qsel qsel, u32 flags)
91{
92 flags |= FIELD_PREP(MT_TXD_PKT_INFO_QSEL, qsel);
93 return mt76x0_dma_skb_wrap(skb, WLAN_PORT, DMA_PACKET, flags);
94}
95
96/* Common Rx DMA descriptor fields */
97#define MT_RXD_INFO_LEN GENMASK(13, 0)
98#define MT_RXD_INFO_PCIE_INTR BIT(24)
99#define MT_RXD_INFO_QSEL GENMASK(26, 25)
100#define MT_RXD_INFO_PORT GENMASK(29, 27)
101#define MT_RXD_INFO_TYPE GENMASK(31, 30)
102
103/* Rx DMA packet specific flags */
104#define MT_RXD_PKT_INFO_UDP_ERR BIT(16)
105#define MT_RXD_PKT_INFO_TCP_ERR BIT(17)
106#define MT_RXD_PKT_INFO_IP_ERR BIT(18)
107#define MT_RXD_PKT_INFO_PKT_80211 BIT(19)
108#define MT_RXD_PKT_INFO_L3L4_DONE BIT(20)
109#define MT_RXD_PKT_INFO_MAC_LEN GENMASK(23, 21)
110
111/* Rx DMA MCU command specific flags */
112#define MT_RXD_CMD_INFO_SELF_GEN BIT(15)
113#define MT_RXD_CMD_INFO_CMD_SEQ GENMASK(19, 16)
114#define MT_RXD_CMD_INFO_EVT_TYPE GENMASK(23, 20)
115
116enum mt76_evt_type {
117 CMD_DONE,
118 CMD_ERROR,
119 CMD_RETRY,
120 EVENT_PWR_RSP,
121 EVENT_WOW_RSP,
122 EVENT_CARRIER_DETECT_RSP,
123 EVENT_DFS_DETECT_RSP,
124};
125
126#endif
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c b/drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c
index 5735038c0e2d..ab4fd6e0f23a 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.c
@@ -31,8 +31,8 @@ mt76x0_efuse_physical_size_check(struct mt76x02_dev *dev)
31 int ret, i; 31 int ret, i;
32 u32 start = 0, end = 0, cnt_free; 32 u32 start = 0, end = 0, cnt_free;
33 33
34 ret = mt76x02_get_efuse_data(&dev->mt76, MT_EE_USAGE_MAP_START, 34 ret = mt76x02_get_efuse_data(dev, MT_EE_USAGE_MAP_START, data,
35 data, sizeof(data), MT_EE_PHYSICAL_READ); 35 sizeof(data), MT_EE_PHYSICAL_READ);
36 if (ret) 36 if (ret)
37 return ret; 37 return ret;
38 38
@@ -55,10 +55,10 @@ mt76x0_efuse_physical_size_check(struct mt76x02_dev *dev)
55 55
56static void mt76x0_set_chip_cap(struct mt76x02_dev *dev) 56static void mt76x0_set_chip_cap(struct mt76x02_dev *dev)
57{ 57{
58 u16 nic_conf0 = mt76x02_eeprom_get(&dev->mt76, MT_EE_NIC_CONF_0); 58 u16 nic_conf0 = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_0);
59 u16 nic_conf1 = mt76x02_eeprom_get(&dev->mt76, MT_EE_NIC_CONF_1); 59 u16 nic_conf1 = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_1);
60 60
61 mt76x02_eeprom_parse_hw_cap(&dev->mt76); 61 mt76x02_eeprom_parse_hw_cap(dev);
62 dev_dbg(dev->mt76.dev, "2GHz %d 5GHz %d\n", 62 dev_dbg(dev->mt76.dev, "2GHz %d 5GHz %d\n",
63 dev->mt76.cap.has_2ghz, dev->mt76.cap.has_5ghz); 63 dev->mt76.cap.has_2ghz, dev->mt76.cap.has_5ghz);
64 64
@@ -86,7 +86,7 @@ static void mt76x0_set_temp_offset(struct mt76x02_dev *dev)
86{ 86{
87 u8 val; 87 u8 val;
88 88
89 val = mt76x02_eeprom_get(&dev->mt76, MT_EE_2G_TARGET_POWER) >> 8; 89 val = mt76x02_eeprom_get(dev, MT_EE_2G_TARGET_POWER) >> 8;
90 if (mt76x02_field_valid(val)) 90 if (mt76x02_field_valid(val))
91 dev->cal.rx.temp_offset = mt76x02_sign_extend(val, 8); 91 dev->cal.rx.temp_offset = mt76x02_sign_extend(val, 8);
92 else 92 else
@@ -98,12 +98,12 @@ static void mt76x0_set_freq_offset(struct mt76x02_dev *dev)
98 struct mt76x02_rx_freq_cal *caldata = &dev->cal.rx; 98 struct mt76x02_rx_freq_cal *caldata = &dev->cal.rx;
99 u8 val; 99 u8 val;
100 100
101 val = mt76x02_eeprom_get(&dev->mt76, MT_EE_FREQ_OFFSET); 101 val = mt76x02_eeprom_get(dev, MT_EE_FREQ_OFFSET);
102 if (!mt76x02_field_valid(val)) 102 if (!mt76x02_field_valid(val))
103 val = 0; 103 val = 0;
104 caldata->freq_offset = val; 104 caldata->freq_offset = val;
105 105
106 val = mt76x02_eeprom_get(&dev->mt76, MT_EE_TSSI_BOUND4) >> 8; 106 val = mt76x02_eeprom_get(dev, MT_EE_TSSI_BOUND4) >> 8;
107 if (!mt76x02_field_valid(val)) 107 if (!mt76x02_field_valid(val))
108 val = 0; 108 val = 0;
109 109
@@ -118,10 +118,8 @@ void mt76x0_read_rx_gain(struct mt76x02_dev *dev)
118 u16 rssi_offset; 118 u16 rssi_offset;
119 int i; 119 int i;
120 120
121 mt76x02_get_rx_gain(&dev->mt76, chan->band, &rssi_offset, 121 mt76x02_get_rx_gain(dev, chan->band, &rssi_offset, &lna_2g, lna_5g);
122 &lna_2g, lna_5g); 122 caldata->lna_gain = mt76x02_get_lna_gain(dev, &lna_2g, lna_5g, chan);
123 caldata->lna_gain = mt76x02_get_lna_gain(&dev->mt76, &lna_2g,
124 lna_5g, chan);
125 123
126 for (i = 0; i < ARRAY_SIZE(caldata->rssi_offset); i++) { 124 for (i = 0; i < ARRAY_SIZE(caldata->rssi_offset); i++) {
127 val = rssi_offset >> (8 * i); 125 val = rssi_offset >> (8 * i);
@@ -132,12 +130,12 @@ void mt76x0_read_rx_gain(struct mt76x02_dev *dev)
132 } 130 }
133} 131}
134 132
135static s8 mt76x0_get_delta(struct mt76_dev *dev) 133static s8 mt76x0_get_delta(struct mt76x02_dev *dev)
136{ 134{
137 struct cfg80211_chan_def *chandef = &dev->chandef; 135 struct cfg80211_chan_def *chandef = &dev->mt76.chandef;
138 u8 val; 136 u8 val;
139 137
140 if (mt76x02_tssi_enabled(dev)) 138 if (mt76x0_tssi_enabled(dev))
141 return 0; 139 return 0;
142 140
143 if (chandef->width == NL80211_CHAN_WIDTH_80) { 141 if (chandef->width == NL80211_CHAN_WIDTH_80) {
@@ -162,54 +160,54 @@ void mt76x0_get_tx_power_per_rate(struct mt76x02_dev *dev)
162 struct ieee80211_channel *chan = dev->mt76.chandef.chan; 160 struct ieee80211_channel *chan = dev->mt76.chandef.chan;
163 bool is_2ghz = chan->band == NL80211_BAND_2GHZ; 161 bool is_2ghz = chan->band == NL80211_BAND_2GHZ;
164 struct mt76_rate_power *t = &dev->mt76.rate_power; 162 struct mt76_rate_power *t = &dev->mt76.rate_power;
165 s8 delta = mt76x0_get_delta(&dev->mt76); 163 s8 delta = mt76x0_get_delta(dev);
166 u16 val, addr; 164 u16 val, addr;
167 165
168 memset(t, 0, sizeof(*t)); 166 memset(t, 0, sizeof(*t));
169 167
170 /* cck 1M, 2M, 5.5M, 11M */ 168 /* cck 1M, 2M, 5.5M, 11M */
171 val = mt76x02_eeprom_get(&dev->mt76, MT_EE_TX_POWER_BYRATE_BASE); 169 val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_BYRATE_BASE);
172 t->cck[0] = t->cck[1] = s6_to_s8(val); 170 t->cck[0] = t->cck[1] = s6_to_s8(val);
173 t->cck[2] = t->cck[3] = s6_to_s8(val >> 8); 171 t->cck[2] = t->cck[3] = s6_to_s8(val >> 8);
174 172
175 /* ofdm 6M, 9M, 12M, 18M */ 173 /* ofdm 6M, 9M, 12M, 18M */
176 addr = is_2ghz ? MT_EE_TX_POWER_BYRATE_BASE + 2 : 0x120; 174 addr = is_2ghz ? MT_EE_TX_POWER_BYRATE_BASE + 2 : 0x120;
177 val = mt76x02_eeprom_get(&dev->mt76, addr); 175 val = mt76x02_eeprom_get(dev, addr);
178 t->ofdm[0] = t->ofdm[1] = s6_to_s8(val); 176 t->ofdm[0] = t->ofdm[1] = s6_to_s8(val);
179 t->ofdm[2] = t->ofdm[3] = s6_to_s8(val >> 8); 177 t->ofdm[2] = t->ofdm[3] = s6_to_s8(val >> 8);
180 178
181 /* ofdm 24M, 36M, 48M, 54M */ 179 /* ofdm 24M, 36M, 48M, 54M */
182 addr = is_2ghz ? MT_EE_TX_POWER_BYRATE_BASE + 4 : 0x122; 180 addr = is_2ghz ? MT_EE_TX_POWER_BYRATE_BASE + 4 : 0x122;
183 val = mt76x02_eeprom_get(&dev->mt76, addr); 181 val = mt76x02_eeprom_get(dev, addr);
184 t->ofdm[4] = t->ofdm[5] = s6_to_s8(val); 182 t->ofdm[4] = t->ofdm[5] = s6_to_s8(val);
185 t->ofdm[6] = t->ofdm[7] = s6_to_s8(val >> 8); 183 t->ofdm[6] = t->ofdm[7] = s6_to_s8(val >> 8);
186 184
187 /* ht-vht mcs 1ss 0, 1, 2, 3 */ 185 /* ht-vht mcs 1ss 0, 1, 2, 3 */
188 addr = is_2ghz ? MT_EE_TX_POWER_BYRATE_BASE + 6 : 0x124; 186 addr = is_2ghz ? MT_EE_TX_POWER_BYRATE_BASE + 6 : 0x124;
189 val = mt76x02_eeprom_get(&dev->mt76, addr); 187 val = mt76x02_eeprom_get(dev, addr);
190 t->ht[0] = t->ht[1] = t->vht[0] = t->vht[1] = s6_to_s8(val); 188 t->ht[0] = t->ht[1] = t->vht[0] = t->vht[1] = s6_to_s8(val);
191 t->ht[2] = t->ht[3] = t->vht[2] = t->vht[3] = s6_to_s8(val >> 8); 189 t->ht[2] = t->ht[3] = t->vht[2] = t->vht[3] = s6_to_s8(val >> 8);
192 190
193 /* ht-vht mcs 1ss 4, 5, 6 */ 191 /* ht-vht mcs 1ss 4, 5, 6 */
194 addr = is_2ghz ? MT_EE_TX_POWER_BYRATE_BASE + 8 : 0x126; 192 addr = is_2ghz ? MT_EE_TX_POWER_BYRATE_BASE + 8 : 0x126;
195 val = mt76x02_eeprom_get(&dev->mt76, addr); 193 val = mt76x02_eeprom_get(dev, addr);
196 t->ht[4] = t->ht[5] = t->vht[4] = t->vht[5] = s6_to_s8(val); 194 t->ht[4] = t->ht[5] = t->vht[4] = t->vht[5] = s6_to_s8(val);
197 t->ht[6] = t->vht[6] = s6_to_s8(val >> 8); 195 t->ht[6] = t->vht[6] = s6_to_s8(val >> 8);
198 196
199 /* ht-vht mcs 1ss 0, 1, 2, 3 stbc */ 197 /* ht-vht mcs 1ss 0, 1, 2, 3 stbc */
200 addr = is_2ghz ? MT_EE_TX_POWER_BYRATE_BASE + 14 : 0xec; 198 addr = is_2ghz ? MT_EE_TX_POWER_BYRATE_BASE + 14 : 0xec;
201 val = mt76x02_eeprom_get(&dev->mt76, addr); 199 val = mt76x02_eeprom_get(dev, addr);
202 t->stbc[0] = t->stbc[1] = s6_to_s8(val); 200 t->stbc[0] = t->stbc[1] = s6_to_s8(val);
203 t->stbc[2] = t->stbc[3] = s6_to_s8(val >> 8); 201 t->stbc[2] = t->stbc[3] = s6_to_s8(val >> 8);
204 202
205 /* ht-vht mcs 1ss 4, 5, 6 stbc */ 203 /* ht-vht mcs 1ss 4, 5, 6 stbc */
206 addr = is_2ghz ? MT_EE_TX_POWER_BYRATE_BASE + 16 : 0xee; 204 addr = is_2ghz ? MT_EE_TX_POWER_BYRATE_BASE + 16 : 0xee;
207 val = mt76x02_eeprom_get(&dev->mt76, addr); 205 val = mt76x02_eeprom_get(dev, addr);
208 t->stbc[4] = t->stbc[5] = s6_to_s8(val); 206 t->stbc[4] = t->stbc[5] = s6_to_s8(val);
209 t->stbc[6] = t->stbc[7] = s6_to_s8(val >> 8); 207 t->stbc[6] = t->stbc[7] = s6_to_s8(val >> 8);
210 208
211 /* vht mcs 8, 9 5GHz */ 209 /* vht mcs 8, 9 5GHz */
212 val = mt76x02_eeprom_get(&dev->mt76, 0x132); 210 val = mt76x02_eeprom_get(dev, 0x132);
213 t->vht[7] = s6_to_s8(val); 211 t->vht[7] = s6_to_s8(val);
214 t->vht[8] = s6_to_s8(val >> 8); 212 t->vht[8] = s6_to_s8(val >> 8);
215 213
@@ -266,7 +264,7 @@ void mt76x0_get_power_info(struct mt76x02_dev *dev, u8 *info)
266 addr = MT_EE_TX_POWER_0_GRP4_TSSI_SLOPE + 2 + offset; 264 addr = MT_EE_TX_POWER_0_GRP4_TSSI_SLOPE + 2 + offset;
267 } 265 }
268 266
269 data = mt76x02_eeprom_get(&dev->mt76, addr); 267 data = mt76x02_eeprom_get(dev, addr);
270 268
271 info[0] = data; 269 info[0] = data;
272 if (!info[0] || info[0] > 0x3f) 270 if (!info[0] || info[0] > 0x3f)
@@ -312,7 +310,7 @@ static int mt76x0_load_eeprom(struct mt76x02_dev *dev)
312 if (found < 0) 310 if (found < 0)
313 return found; 311 return found;
314 312
315 return mt76x02_get_efuse_data(&dev->mt76, 0, dev->mt76.eeprom.data, 313 return mt76x02_get_efuse_data(dev, 0, dev->mt76.eeprom.data,
316 MT76X0_EEPROM_SIZE, MT_EE_READ); 314 MT76X0_EEPROM_SIZE, MT_EE_READ);
317} 315}
318 316
@@ -326,7 +324,7 @@ int mt76x0_eeprom_init(struct mt76x02_dev *dev)
326 if (err < 0) 324 if (err < 0)
327 return err; 325 return err;
328 326
329 data = mt76x02_eeprom_get(&dev->mt76, MT_EE_VERSION); 327 data = mt76x02_eeprom_get(dev, MT_EE_VERSION);
330 version = data >> 8; 328 version = data >> 8;
331 fae = data; 329 fae = data;
332 330
@@ -337,8 +335,7 @@ int mt76x0_eeprom_init(struct mt76x02_dev *dev)
337 dev_info(dev->mt76.dev, "EEPROM ver:%02hhx fae:%02hhx\n", 335 dev_info(dev->mt76.dev, "EEPROM ver:%02hhx fae:%02hhx\n",
338 version, fae); 336 version, fae);
339 337
340 mt76x02_mac_setaddr(&dev->mt76, 338 mt76x02_mac_setaddr(dev, dev->mt76.eeprom.data + MT_EE_MAC_ADDR);
341 dev->mt76.eeprom.data + MT_EE_MAC_ADDR);
342 mt76x0_set_chip_cap(dev); 339 mt76x0_set_chip_cap(dev);
343 mt76x0_set_freq_offset(dev); 340 mt76x0_set_freq_offset(dev);
344 mt76x0_set_temp_offset(dev); 341 mt76x0_set_temp_offset(dev);
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.h b/drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.h
index 40fd4e61769b..ee9ade9f3c8b 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.h
+++ b/drivers/net/wireless/mediatek/mt76/mt76x0/eeprom.h
@@ -37,4 +37,10 @@ static inline s8 s6_to_s8(u32 val)
37 return ret; 37 return ret;
38} 38}
39 39
40static inline bool mt76x0_tssi_enabled(struct mt76x02_dev *dev)
41{
42 return (mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_1) &
43 MT_EE_NIC_CONF_1_TX_ALC_EN);
44}
45
40#endif 46#endif
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x0/init.c b/drivers/net/wireless/mediatek/mt76/mt76x0/init.c
index ee2b8e885608..4a9408801260 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x0/init.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x0/init.c
@@ -138,7 +138,7 @@ static void mt76x0_init_mac_registers(struct mt76x02_dev *dev)
138 138
139 RANDOM_WRITE(dev, common_mac_reg_table); 139 RANDOM_WRITE(dev, common_mac_reg_table);
140 140
141 mt76x02_set_beacon_offsets(&dev->mt76); 141 mt76x02_set_beacon_offsets(dev);
142 142
143 /* Enable PBF and MAC clock SYS_CTRL[11:10] = 0x3 */ 143 /* Enable PBF and MAC clock SYS_CTRL[11:10] = 0x3 */
144 RANDOM_WRITE(dev, mt76x0_mac_reg_table); 144 RANDOM_WRITE(dev, mt76x0_mac_reg_table);
@@ -280,7 +280,7 @@ int mt76x0_init_hardware(struct mt76x02_dev *dev)
280 return -ETIMEDOUT; 280 return -ETIMEDOUT;
281 281
282 mt76x0_reset_csr_bbp(dev); 282 mt76x0_reset_csr_bbp(dev);
283 ret = mt76x02_mcu_function_select(&dev->mt76, Q_SELECT, 1, false); 283 ret = mt76x02_mcu_function_select(dev, Q_SELECT, 1, false);
284 if (ret) 284 if (ret)
285 return ret; 285 return ret;
286 286
@@ -368,7 +368,10 @@ int mt76x0_register_device(struct mt76x02_dev *dev)
368 hw->max_rates = 1; 368 hw->max_rates = 1;
369 hw->max_report_rates = 7; 369 hw->max_report_rates = 7;
370 hw->max_rate_tries = 1; 370 hw->max_rate_tries = 1;
371 hw->extra_tx_headroom = sizeof(struct mt76x02_txwi) + 4 + 2; 371 hw->extra_tx_headroom = 2;
372 if (mt76_is_usb(dev))
373 hw->extra_tx_headroom += sizeof(struct mt76x02_txwi) +
374 MT_DMA_HDR_LEN;
372 375
373 hw->sta_data_size = sizeof(struct mt76x02_sta); 376 hw->sta_data_size = sizeof(struct mt76x02_sta);
374 hw->vif_data_size = sizeof(struct mt76x02_vif); 377 hw->vif_data_size = sizeof(struct mt76x02_vif);
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x0/main.c b/drivers/net/wireless/mediatek/mt76/mt76x0/main.c
index c9cd0254a979..9273d2d2764a 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x0/main.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x0/main.c
@@ -16,6 +16,20 @@
16#include <linux/etherdevice.h> 16#include <linux/etherdevice.h>
17#include "mt76x0.h" 17#include "mt76x0.h"
18 18
19static int
20mt76x0_set_channel(struct mt76x02_dev *dev, struct cfg80211_chan_def *chandef)
21{
22 int ret;
23
24 cancel_delayed_work_sync(&dev->cal_work);
25
26 mt76_set_channel(&dev->mt76);
27 ret = mt76x0_phy_set_channel(dev, chandef);
28 mt76_txq_schedule_all(&dev->mt76);
29
30 return ret;
31}
32
19int mt76x0_config(struct ieee80211_hw *hw, u32 changed) 33int mt76x0_config(struct ieee80211_hw *hw, u32 changed)
20{ 34{
21 struct mt76x02_dev *dev = hw->priv; 35 struct mt76x02_dev *dev = hw->priv;
@@ -25,7 +39,7 @@ int mt76x0_config(struct ieee80211_hw *hw, u32 changed)
25 39
26 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { 40 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
27 ieee80211_stop_queues(hw); 41 ieee80211_stop_queues(hw);
28 ret = mt76x0_phy_set_channel(dev, &hw->conf.chandef); 42 ret = mt76x0_set_channel(dev, &hw->conf.chandef);
29 ieee80211_wake_queues(hw); 43 ieee80211_wake_queues(hw);
30 } 44 }
31 45
@@ -114,8 +128,6 @@ void mt76x0_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
114{ 128{
115 struct mt76x02_dev *dev = hw->priv; 129 struct mt76x02_dev *dev = hw->priv;
116 130
117 cancel_delayed_work_sync(&dev->cal_work);
118 mt76x0_agc_save(dev);
119 set_bit(MT76_SCANNING, &dev->mt76.state); 131 set_bit(MT76_SCANNING, &dev->mt76.state);
120} 132}
121EXPORT_SYMBOL_GPL(mt76x0_sw_scan); 133EXPORT_SYMBOL_GPL(mt76x0_sw_scan);
@@ -125,11 +137,7 @@ void mt76x0_sw_scan_complete(struct ieee80211_hw *hw,
125{ 137{
126 struct mt76x02_dev *dev = hw->priv; 138 struct mt76x02_dev *dev = hw->priv;
127 139
128 mt76x0_agc_restore(dev);
129 clear_bit(MT76_SCANNING, &dev->mt76.state); 140 clear_bit(MT76_SCANNING, &dev->mt76.state);
130
131 ieee80211_queue_delayed_work(dev->mt76.hw, &dev->cal_work,
132 MT_CALIBRATE_INTERVAL);
133} 141}
134EXPORT_SYMBOL_GPL(mt76x0_sw_scan_complete); 142EXPORT_SYMBOL_GPL(mt76x0_sw_scan_complete);
135 143
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x0/mcu.h b/drivers/net/wireless/mediatek/mt76/mt76x0/mcu.h
index b66e70f6cd89..3b34e1d2769f 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x0/mcu.h
+++ b/drivers/net/wireless/mediatek/mt76/mt76x0/mcu.h
@@ -39,6 +39,9 @@ enum mcu_calibrate {
39 MCU_CAL_TXDCOC, 39 MCU_CAL_TXDCOC,
40 MCU_CAL_RX_GROUP_DELAY, 40 MCU_CAL_RX_GROUP_DELAY,
41 MCU_CAL_TX_GROUP_DELAY, 41 MCU_CAL_TX_GROUP_DELAY,
42 MCU_CAL_VCO,
43 MCU_CAL_NO_SIGNAL = 0xfe,
44 MCU_CAL_FULL = 0xff,
42}; 45};
43 46
44int mt76x0e_mcu_init(struct mt76x02_dev *dev); 47int mt76x0e_mcu_init(struct mt76x02_dev *dev);
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x0/mt76x0.h b/drivers/net/wireless/mediatek/mt76/mt76x0/mt76x0.h
index 1bff2be45a13..2187bafaf2e9 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x0/mt76x0.h
+++ b/drivers/net/wireless/mediatek/mt76/mt76x0/mt76x0.h
@@ -66,12 +66,11 @@ int mt76x0_set_rts_threshold(struct ieee80211_hw *hw, u32 value);
66/* PHY */ 66/* PHY */
67void mt76x0_phy_init(struct mt76x02_dev *dev); 67void mt76x0_phy_init(struct mt76x02_dev *dev);
68int mt76x0_wait_bbp_ready(struct mt76x02_dev *dev); 68int mt76x0_wait_bbp_ready(struct mt76x02_dev *dev);
69void mt76x0_agc_save(struct mt76x02_dev *dev);
70void mt76x0_agc_restore(struct mt76x02_dev *dev);
71int mt76x0_phy_set_channel(struct mt76x02_dev *dev, 69int mt76x0_phy_set_channel(struct mt76x02_dev *dev,
72 struct cfg80211_chan_def *chandef); 70 struct cfg80211_chan_def *chandef);
73void mt76x0_phy_recalibrate_after_assoc(struct mt76x02_dev *dev); 71void mt76x0_phy_recalibrate_after_assoc(struct mt76x02_dev *dev);
74void mt76x0_phy_set_txpower(struct mt76x02_dev *dev); 72void mt76x0_phy_set_txpower(struct mt76x02_dev *dev);
73void mt76x0_phy_calibrate(struct mt76x02_dev *dev, bool power_on);
75 74
76/* MAC */ 75/* MAC */
77void mt76x0_mac_work(struct work_struct *work); 76void mt76x0_mac_work(struct work_struct *work);
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x0/pci.c b/drivers/net/wireless/mediatek/mt76/mt76x0/pci.c
index 87997cddf0d6..522c86059bcb 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x0/pci.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x0/pci.c
@@ -28,6 +28,7 @@ static int mt76x0e_start(struct ieee80211_hw *hw)
28 mutex_lock(&dev->mt76.mutex); 28 mutex_lock(&dev->mt76.mutex);
29 29
30 mt76x02_mac_start(dev); 30 mt76x02_mac_start(dev);
31 mt76x0_phy_calibrate(dev, true);
31 ieee80211_queue_delayed_work(dev->mt76.hw, &dev->mac_work, 32 ieee80211_queue_delayed_work(dev->mt76.hw, &dev->mac_work,
32 MT_CALIBRATE_INTERVAL); 33 MT_CALIBRATE_INTERVAL);
33 ieee80211_queue_delayed_work(dev->mt76.hw, &dev->cal_work, 34 ieee80211_queue_delayed_work(dev->mt76.hw, &dev->cal_work,
@@ -71,10 +72,19 @@ static const struct ieee80211_ops mt76x0e_ops = {
71 .tx = mt76x02_tx, 72 .tx = mt76x02_tx,
72 .start = mt76x0e_start, 73 .start = mt76x0e_start,
73 .stop = mt76x0e_stop, 74 .stop = mt76x0e_stop,
74 .config = mt76x0_config,
75 .add_interface = mt76x02_add_interface, 75 .add_interface = mt76x02_add_interface,
76 .remove_interface = mt76x02_remove_interface, 76 .remove_interface = mt76x02_remove_interface,
77 .config = mt76x0_config,
77 .configure_filter = mt76x02_configure_filter, 78 .configure_filter = mt76x02_configure_filter,
79 .sta_add = mt76x02_sta_add,
80 .sta_remove = mt76x02_sta_remove,
81 .set_key = mt76x02_set_key,
82 .conf_tx = mt76x02_conf_tx,
83 .sw_scan_start = mt76x0_sw_scan,
84 .sw_scan_complete = mt76x0_sw_scan_complete,
85 .ampdu_action = mt76x02_ampdu_action,
86 .sta_rate_tbl_update = mt76x02_sta_rate_tbl_update,
87 .wake_tx_queue = mt76_wake_tx_queue,
78}; 88};
79 89
80static int mt76x0e_register_device(struct mt76x02_dev *dev) 90static int mt76x0e_register_device(struct mt76x02_dev *dev)
@@ -102,28 +112,34 @@ static int mt76x0e_register_device(struct mt76x02_dev *dev)
102 u16 val; 112 u16 val;
103 113
104 mt76_clear(dev, MT_COEXCFG0, BIT(0)); 114 mt76_clear(dev, MT_COEXCFG0, BIT(0));
105 val = mt76x02_eeprom_get(&dev->mt76, MT_EE_NIC_CONF_0); 115
106 if (val & MT_EE_NIC_CONF_0_PA_IO_CURRENT) { 116 val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_0);
107 u32 data; 117 if (!(val & MT_EE_NIC_CONF_0_PA_IO_CURRENT))
108 118 mt76_set(dev, MT_XO_CTRL7, 0xc03);
109 /* set external external PA I/O
110 * current to 16mA
111 */
112 data = mt76_rr(dev, 0x11c);
113 val |= 0xc03;
114 mt76_wr(dev, 0x11c, val);
115 }
116 } 119 }
117 120
118 mt76_clear(dev, 0x110, BIT(9)); 121 mt76_clear(dev, 0x110, BIT(9));
119 mt76_set(dev, MT_MAX_LEN_CFG, BIT(13)); 122 mt76_set(dev, MT_MAX_LEN_CFG, BIT(13));
120 123
124 err = mt76x0_register_device(dev);
125 if (err < 0)
126 return err;
127
128 set_bit(MT76_STATE_INITIALIZED, &dev->mt76.state);
129
121 return 0; 130 return 0;
122} 131}
123 132
124static int 133static int
125mt76x0e_probe(struct pci_dev *pdev, const struct pci_device_id *id) 134mt76x0e_probe(struct pci_dev *pdev, const struct pci_device_id *id)
126{ 135{
136 static const struct mt76_driver_ops drv_ops = {
137 .txwi_size = sizeof(struct mt76x02_txwi),
138 .tx_prepare_skb = mt76x02_tx_prepare_skb,
139 .tx_complete_skb = mt76x02_tx_complete_skb,
140 .rx_skb = mt76x02_queue_rx_skb,
141 .rx_poll_complete = mt76x02_rx_poll_complete,
142 };
127 struct mt76x02_dev *dev; 143 struct mt76x02_dev *dev;
128 int ret; 144 int ret;
129 145
@@ -141,7 +157,7 @@ mt76x0e_probe(struct pci_dev *pdev, const struct pci_device_id *id)
141 if (ret) 157 if (ret)
142 return ret; 158 return ret;
143 159
144 dev = mt76x0_alloc_device(&pdev->dev, NULL, &mt76x0e_ops); 160 dev = mt76x0_alloc_device(&pdev->dev, &drv_ops, &mt76x0e_ops);
145 if (!dev) 161 if (!dev)
146 return -ENOMEM; 162 return -ENOMEM;
147 163
@@ -150,6 +166,11 @@ mt76x0e_probe(struct pci_dev *pdev, const struct pci_device_id *id)
150 dev->mt76.rev = mt76_rr(dev, MT_ASIC_VERSION); 166 dev->mt76.rev = mt76_rr(dev, MT_ASIC_VERSION);
151 dev_info(dev->mt76.dev, "ASIC revision: %08x\n", dev->mt76.rev); 167 dev_info(dev->mt76.dev, "ASIC revision: %08x\n", dev->mt76.rev);
152 168
169 ret = devm_request_irq(dev->mt76.dev, pdev->irq, mt76x02_irq_handler,
170 IRQF_SHARED, KBUILD_MODNAME, dev);
171 if (ret)
172 goto error;
173
153 ret = mt76x0e_register_device(dev); 174 ret = mt76x0e_register_device(dev);
154 if (ret < 0) 175 if (ret < 0)
155 goto error; 176 goto error;
@@ -167,7 +188,7 @@ static void mt76x0e_cleanup(struct mt76x02_dev *dev)
167 mt76x0_chip_onoff(dev, false, false); 188 mt76x0_chip_onoff(dev, false, false);
168 mt76x0e_stop_hw(dev); 189 mt76x0e_stop_hw(dev);
169 mt76x02_dma_cleanup(dev); 190 mt76x02_dma_cleanup(dev);
170 mt76x02_mcu_cleanup(&dev->mt76); 191 mt76x02_mcu_cleanup(dev);
171} 192}
172 193
173static void 194static void
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x0/pci_mcu.c b/drivers/net/wireless/mediatek/mt76/mt76x0/pci_mcu.c
index 6c66656c21f4..569861289aa5 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x0/pci_mcu.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x0/pci_mcu.c
@@ -116,6 +116,7 @@ static int mt76x0e_load_firmware(struct mt76x02_dev *dev)
116 goto out; 116 goto out;
117 } 117 }
118 118
119 mt76x02_set_ethtool_fwver(dev, hdr);
119 dev_dbg(dev->mt76.dev, "Firmware running!\n"); 120 dev_dbg(dev->mt76.dev, "Firmware running!\n");
120 121
121out: 122out:
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x0/phy.c b/drivers/net/wireless/mediatek/mt76/mt76x0/phy.c
index 4850a2db18d7..cf024950e0ed 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x0/phy.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x0/phy.c
@@ -14,6 +14,9 @@
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 */ 15 */
16 16
17#include <linux/kernel.h>
18#include <linux/etherdevice.h>
19
17#include "mt76x0.h" 20#include "mt76x0.h"
18#include "mcu.h" 21#include "mcu.h"
19#include "eeprom.h" 22#include "eeprom.h"
@@ -23,8 +26,6 @@
23#include "initvals_phy.h" 26#include "initvals_phy.h"
24#include "../mt76x02_phy.h" 27#include "../mt76x02_phy.h"
25 28
26#include <linux/etherdevice.h>
27
28static int 29static int
29mt76x0_rf_csr_wr(struct mt76x02_dev *dev, u32 offset, u8 value) 30mt76x0_rf_csr_wr(struct mt76x02_dev *dev, u32 offset, u8 value)
30{ 31{
@@ -37,7 +38,7 @@ mt76x0_rf_csr_wr(struct mt76x02_dev *dev, u32 offset, u8 value)
37 bank = MT_RF_BANK(offset); 38 bank = MT_RF_BANK(offset);
38 reg = MT_RF_REG(offset); 39 reg = MT_RF_REG(offset);
39 40
40 if (WARN_ON_ONCE(reg > 64) || WARN_ON_ONCE(bank) > 8) 41 if (WARN_ON_ONCE(reg > 127) || WARN_ON_ONCE(bank > 8))
41 return -EINVAL; 42 return -EINVAL;
42 43
43 mutex_lock(&dev->phy_mutex); 44 mutex_lock(&dev->phy_mutex);
@@ -76,7 +77,7 @@ static int mt76x0_rf_csr_rr(struct mt76x02_dev *dev, u32 offset)
76 bank = MT_RF_BANK(offset); 77 bank = MT_RF_BANK(offset);
77 reg = MT_RF_REG(offset); 78 reg = MT_RF_REG(offset);
78 79
79 if (WARN_ON_ONCE(reg > 64) || WARN_ON_ONCE(bank) > 8) 80 if (WARN_ON_ONCE(reg > 127) || WARN_ON_ONCE(bank > 8))
80 return -EINVAL; 81 return -EINVAL;
81 82
82 mutex_lock(&dev->phy_mutex); 83 mutex_lock(&dev->phy_mutex);
@@ -111,15 +112,16 @@ out:
111static int 112static int
112rf_wr(struct mt76x02_dev *dev, u32 offset, u8 val) 113rf_wr(struct mt76x02_dev *dev, u32 offset, u8 val)
113{ 114{
114 if (test_bit(MT76_STATE_MCU_RUNNING, &dev->mt76.state)) { 115 if (mt76_is_usb(dev)) {
115 struct mt76_reg_pair pair = { 116 struct mt76_reg_pair pair = {
116 .reg = offset, 117 .reg = offset,
117 .value = val, 118 .value = val,
118 }; 119 };
119 120
121 WARN_ON_ONCE(!test_bit(MT76_STATE_MCU_RUNNING,
122 &dev->mt76.state));
120 return mt76_wr_rp(dev, MT_MCU_MEMMAP_RF, &pair, 1); 123 return mt76_wr_rp(dev, MT_MCU_MEMMAP_RF, &pair, 1);
121 } else { 124 } else {
122 WARN_ON_ONCE(1);
123 return mt76x0_rf_csr_wr(dev, offset, val); 125 return mt76x0_rf_csr_wr(dev, offset, val);
124 } 126 }
125} 127}
@@ -130,15 +132,16 @@ rf_rr(struct mt76x02_dev *dev, u32 offset)
130 int ret; 132 int ret;
131 u32 val; 133 u32 val;
132 134
133 if (test_bit(MT76_STATE_MCU_RUNNING, &dev->mt76.state)) { 135 if (mt76_is_usb(dev)) {
134 struct mt76_reg_pair pair = { 136 struct mt76_reg_pair pair = {
135 .reg = offset, 137 .reg = offset,
136 }; 138 };
137 139
140 WARN_ON_ONCE(!test_bit(MT76_STATE_MCU_RUNNING,
141 &dev->mt76.state));
138 ret = mt76_rd_rp(dev, MT_MCU_MEMMAP_RF, &pair, 1); 142 ret = mt76_rd_rp(dev, MT_MCU_MEMMAP_RF, &pair, 1);
139 val = pair.value; 143 val = pair.value;
140 } else { 144 } else {
141 WARN_ON_ONCE(1);
142 ret = val = mt76x0_rf_csr_rr(dev, offset); 145 ret = val = mt76x0_rf_csr_rr(dev, offset);
143 } 146 }
144 147
@@ -175,9 +178,22 @@ rf_clear(struct mt76x02_dev *dev, u32 offset, u8 mask)
175} 178}
176#endif 179#endif
177 180
178#define RF_RANDOM_WRITE(dev, tab) \ 181static void
179 mt76_wr_rp(dev, MT_MCU_MEMMAP_RF, \ 182mt76x0_rf_csr_wr_rp(struct mt76x02_dev *dev, const struct mt76_reg_pair *data,
180 tab, ARRAY_SIZE(tab)) 183 int n)
184{
185 while (n-- > 0) {
186 mt76x0_rf_csr_wr(dev, data->reg, data->value);
187 data++;
188 }
189}
190
191#define RF_RANDOM_WRITE(dev, tab) do { \
192 if (mt76_is_mmio(dev)) \
193 mt76x0_rf_csr_wr_rp(dev, tab, ARRAY_SIZE(tab)); \
194 else \
195 mt76_wr_rp(dev, MT_MCU_MEMMAP_RF, tab, ARRAY_SIZE(tab));\
196} while (0)
181 197
182int mt76x0_wait_bbp_ready(struct mt76x02_dev *dev) 198int mt76x0_wait_bbp_ready(struct mt76x02_dev *dev)
183{ 199{
@@ -186,7 +202,6 @@ int mt76x0_wait_bbp_ready(struct mt76x02_dev *dev)
186 202
187 do { 203 do {
188 val = mt76_rr(dev, MT_BBP(CORE, 0)); 204 val = mt76_rr(dev, MT_BBP(CORE, 0));
189 printk("BBP version %08x\n", val);
190 if (val && ~val) 205 if (val && ~val)
191 break; 206 break;
192 } while (--i); 207 } while (--i);
@@ -196,36 +211,10 @@ int mt76x0_wait_bbp_ready(struct mt76x02_dev *dev)
196 return -EIO; 211 return -EIO;
197 } 212 }
198 213
214 dev_dbg(dev->mt76.dev, "BBP version %08x\n", val);
199 return 0; 215 return 0;
200} 216}
201 217
202static void
203mt76x0_bbp_set_ctrlch(struct mt76x02_dev *dev, enum nl80211_chan_width width,
204 u8 ctrl)
205{
206 int core_val, agc_val;
207
208 switch (width) {
209 case NL80211_CHAN_WIDTH_80:
210 core_val = 3;
211 agc_val = 7;
212 break;
213 case NL80211_CHAN_WIDTH_40:
214 core_val = 2;
215 agc_val = 3;
216 break;
217 default:
218 core_val = 0;
219 agc_val = 1;
220 break;
221 }
222
223 mt76_rmw_field(dev, MT_BBP(CORE, 1), MT_BBP_CORE_R1_BW, core_val);
224 mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_BW, agc_val);
225 mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_CTRL_CHAN, ctrl);
226 mt76_rmw_field(dev, MT_BBP(TXBE, 0), MT_BBP_TXBE_R0_CTRL_CHAN, ctrl);
227}
228
229static void mt76x0_vco_cal(struct mt76x02_dev *dev, u8 channel) 218static void mt76x0_vco_cal(struct mt76x02_dev *dev, u8 channel)
230{ 219{
231 u8 val; 220 u8 val;
@@ -283,13 +272,6 @@ static void mt76x0_vco_cal(struct mt76x02_dev *dev, u8 channel)
283} 272}
284 273
285static void 274static void
286mt76x0_mac_set_ctrlch(struct mt76x02_dev *dev, bool primary_upper)
287{
288 mt76_rmw_field(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_UPPER_40M,
289 primary_upper);
290}
291
292static void
293mt76x0_phy_set_band(struct mt76x02_dev *dev, enum nl80211_band band) 275mt76x0_phy_set_band(struct mt76x02_dev *dev, enum nl80211_band band)
294{ 276{
295 switch (band) { 277 switch (band) {
@@ -299,9 +281,6 @@ mt76x0_phy_set_band(struct mt76x02_dev *dev, enum nl80211_band band)
299 rf_wr(dev, MT_RF(5, 0), 0x45); 281 rf_wr(dev, MT_RF(5, 0), 0x45);
300 rf_wr(dev, MT_RF(6, 0), 0x44); 282 rf_wr(dev, MT_RF(6, 0), 0x44);
301 283
302 mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G);
303 mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G);
304
305 mt76_wr(dev, MT_TX_ALC_VGA3, 0x00050007); 284 mt76_wr(dev, MT_TX_ALC_VGA3, 0x00050007);
306 mt76_wr(dev, MT_TX0_RF_GAIN_CORR, 0x003E0002); 285 mt76_wr(dev, MT_TX0_RF_GAIN_CORR, 0x003E0002);
307 break; 286 break;
@@ -311,9 +290,6 @@ mt76x0_phy_set_band(struct mt76x02_dev *dev, enum nl80211_band band)
311 rf_wr(dev, MT_RF(5, 0), 0x44); 290 rf_wr(dev, MT_RF(5, 0), 0x44);
312 rf_wr(dev, MT_RF(6, 0), 0x45); 291 rf_wr(dev, MT_RF(6, 0), 0x45);
313 292
314 mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G);
315 mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G);
316
317 mt76_wr(dev, MT_TX_ALC_VGA3, 0x00000005); 293 mt76_wr(dev, MT_TX_ALC_VGA3, 0x00000005);
318 mt76_wr(dev, MT_TX0_RF_GAIN_CORR, 0x01010102); 294 mt76_wr(dev, MT_TX0_RF_GAIN_CORR, 0x01010102);
319 break; 295 break;
@@ -475,7 +451,7 @@ mt76x0_phy_set_chan_rf_params(struct mt76x02_dev *dev, u8 channel, u16 rf_bw_ban
475 mt76_wr(dev, MT_RF_MISC, mac_reg); 451 mt76_wr(dev, MT_RF_MISC, mac_reg);
476 452
477 band = (rf_band & RF_G_BAND) ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; 453 band = (rf_band & RF_G_BAND) ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
478 if (mt76x02_ext_pa_enabled(&dev->mt76, band)) { 454 if (mt76x02_ext_pa_enabled(dev, band)) {
479 /* 455 /*
480 MT_RF_MISC (offset: 0x0518) 456 MT_RF_MISC (offset: 0x0518)
481 [2]1'b1: enable external A band PA, 1'b0: disable external A band PA 457 [2]1'b1: enable external A band PA, 1'b0: disable external A band PA
@@ -514,7 +490,7 @@ mt76x0_phy_set_chan_rf_params(struct mt76x02_dev *dev, u8 channel, u16 rf_bw_ban
514} 490}
515 491
516static void 492static void
517mt76x0_phy_set_chan_bbp_params(struct mt76x02_dev *dev, u8 channel, u16 rf_bw_band) 493mt76x0_phy_set_chan_bbp_params(struct mt76x02_dev *dev, u16 rf_bw_band)
518{ 494{
519 int i; 495 int i;
520 496
@@ -587,7 +563,7 @@ mt76x0_bbp_set_bw(struct mt76x02_dev *dev, enum nl80211_chan_width width)
587 return ; 563 return ;
588 } 564 }
589 565
590 mt76x02_mcu_function_select(&dev->mt76, BW_SETTING, bw, false); 566 mt76x02_mcu_function_select(dev, BW_SETTING, bw, false);
591} 567}
592 568
593void mt76x0_phy_set_txpower(struct mt76x02_dev *dev) 569void mt76x0_phy_set_txpower(struct mt76x02_dev *dev)
@@ -603,8 +579,50 @@ void mt76x0_phy_set_txpower(struct mt76x02_dev *dev)
603 dev->mt76.txpower_cur = mt76x02_get_max_rate_power(t); 579 dev->mt76.txpower_cur = mt76x02_get_max_rate_power(t);
604 mt76x02_add_rate_power_offset(t, -info[0]); 580 mt76x02_add_rate_power_offset(t, -info[0]);
605 581
606 mt76x02_phy_set_txpower(&dev->mt76, info[0], info[1]); 582 mt76x02_phy_set_txpower(dev, info[0], info[1]);
583}
584
585void mt76x0_phy_calibrate(struct mt76x02_dev *dev, bool power_on)
586{
587 struct ieee80211_channel *chan = dev->mt76.chandef.chan;
588 u32 val, tx_alc, reg_val;
589
590 if (power_on) {
591 mt76x02_mcu_calibrate(dev, MCU_CAL_R, 0, false);
592 mt76x02_mcu_calibrate(dev, MCU_CAL_VCO, chan->hw_value,
593 false);
594 usleep_range(10, 20);
595 /* XXX: tssi */
596 }
597
598 tx_alc = mt76_rr(dev, MT_TX_ALC_CFG_0);
599 mt76_wr(dev, MT_TX_ALC_CFG_0, 0);
600 usleep_range(500, 700);
601
602 reg_val = mt76_rr(dev, MT_BBP(IBI, 9));
603 mt76_wr(dev, MT_BBP(IBI, 9), 0xffffff7e);
604
605 if (chan->band == NL80211_BAND_5GHZ) {
606 if (chan->hw_value < 100)
607 val = 0x701;
608 else if (chan->hw_value < 140)
609 val = 0x801;
610 else
611 val = 0x901;
612 } else {
613 val = 0x600;
614 }
615
616 mt76x02_mcu_calibrate(dev, MCU_CAL_FULL, val, false);
617 msleep(350);
618 mt76x02_mcu_calibrate(dev, MCU_CAL_LC, 1, false);
619 usleep_range(15000, 20000);
620
621 mt76_wr(dev, MT_BBP(IBI, 9), reg_val);
622 mt76_wr(dev, MT_TX_ALC_CFG_0, tx_alc);
623 mt76x02_mcu_calibrate(dev, MCU_CAL_RXDCOC, 1, false);
607} 624}
625EXPORT_SYMBOL_GPL(mt76x0_phy_calibrate);
608 626
609int mt76x0_phy_set_channel(struct mt76x02_dev *dev, 627int mt76x0_phy_set_channel(struct mt76x02_dev *dev,
610 struct cfg80211_chan_def *chandef) 628 struct cfg80211_chan_def *chandef)
@@ -665,9 +683,19 @@ int mt76x0_phy_set_channel(struct mt76x02_dev *dev,
665 break; 683 break;
666 } 684 }
667 685
668 mt76x0_bbp_set_bw(dev, chandef->width); 686 if (mt76_is_usb(dev)) {
669 mt76x0_bbp_set_ctrlch(dev, chandef->width, ch_group_index); 687 mt76x0_bbp_set_bw(dev, chandef->width);
670 mt76x0_mac_set_ctrlch(dev, ch_group_index & 1); 688 } else {
689 if (chandef->width == NL80211_CHAN_WIDTH_80 ||
690 chandef->width == NL80211_CHAN_WIDTH_40)
691 val = 0x201;
692 else
693 val = 0x601;
694 mt76_wr(dev, MT_TX_SW_CFG0, val);
695 }
696 mt76x02_phy_set_bw(dev, chandef->width, ch_group_index);
697 mt76x02_phy_set_band(dev, chandef->chan->band,
698 ch_group_index & 1);
671 mt76x0_ant_select(dev); 699 mt76x0_ant_select(dev);
672 700
673 mt76_rmw(dev, MT_EXT_CCA_CFG, 701 mt76_rmw(dev, MT_EXT_CCA_CFG,
@@ -680,7 +708,6 @@ int mt76x0_phy_set_channel(struct mt76x02_dev *dev,
680 708
681 mt76x0_phy_set_band(dev, chandef->chan->band); 709 mt76x0_phy_set_band(dev, chandef->chan->band);
682 mt76x0_phy_set_chan_rf_params(dev, channel, rf_bw_band); 710 mt76x0_phy_set_chan_rf_params(dev, channel, rf_bw_band);
683 mt76x0_read_rx_gain(dev);
684 711
685 /* set Japan Tx filter at channel 14 */ 712 /* set Japan Tx filter at channel 14 */
686 val = mt76_rr(dev, MT_BBP(CORE, 1)); 713 val = mt76_rr(dev, MT_BBP(CORE, 1));
@@ -690,17 +717,27 @@ int mt76x0_phy_set_channel(struct mt76x02_dev *dev,
690 val &= ~0x20; 717 val &= ~0x20;
691 mt76_wr(dev, MT_BBP(CORE, 1), val); 718 mt76_wr(dev, MT_BBP(CORE, 1), val);
692 719
693 mt76x0_phy_set_chan_bbp_params(dev, channel, rf_bw_band); 720 mt76x0_read_rx_gain(dev);
721 mt76x0_phy_set_chan_bbp_params(dev, rf_bw_band);
722 mt76x02_init_agc_gain(dev);
694 723
695 /* Vendor driver don't do it */ 724 if (mt76_is_usb(dev)) {
696 /* mt76x0_phy_set_tx_power(dev, channel, rf_bw_band); */ 725 mt76x0_vco_cal(dev, channel);
726 } else {
727 /* enable vco */
728 rf_set(dev, MT_RF(0, 4), BIT(7));
729 }
697 730
698 mt76x0_vco_cal(dev, channel);
699 if (scan) 731 if (scan)
700 mt76x02_mcu_calibrate(&dev->mt76, MCU_CAL_RXDCOC, 1, false); 732 return 0;
701 733
734 if (mt76_is_mmio(dev))
735 mt76x0_phy_calibrate(dev, false);
702 mt76x0_phy_set_txpower(dev); 736 mt76x0_phy_set_txpower(dev);
703 737
738 ieee80211_queue_delayed_work(dev->mt76.hw, &dev->cal_work,
739 MT_CALIBRATE_INTERVAL);
740
704 return 0; 741 return 0;
705} 742}
706 743
@@ -710,7 +747,7 @@ void mt76x0_phy_recalibrate_after_assoc(struct mt76x02_dev *dev)
710 u8 channel = dev->mt76.chandef.chan->hw_value; 747 u8 channel = dev->mt76.chandef.chan->hw_value;
711 int is_5ghz = (dev->mt76.chandef.chan->band == NL80211_BAND_5GHZ) ? 1 : 0; 748 int is_5ghz = (dev->mt76.chandef.chan->band == NL80211_BAND_5GHZ) ? 1 : 0;
712 749
713 mt76x02_mcu_calibrate(&dev->mt76, MCU_CAL_R, 0, false); 750 mt76x02_mcu_calibrate(dev, MCU_CAL_R, 0, false);
714 751
715 mt76x0_vco_cal(dev, channel); 752 mt76x0_vco_cal(dev, channel);
716 753
@@ -718,109 +755,113 @@ void mt76x0_phy_recalibrate_after_assoc(struct mt76x02_dev *dev)
718 mt76_wr(dev, MT_TX_ALC_CFG_0, 0); 755 mt76_wr(dev, MT_TX_ALC_CFG_0, 0);
719 usleep_range(500, 700); 756 usleep_range(500, 700);
720 757
721 reg_val = mt76_rr(dev, 0x2124); 758 reg_val = mt76_rr(dev, MT_BBP(IBI, 9));
722 reg_val &= 0xffffff7e; 759 mt76_wr(dev, MT_BBP(IBI, 9), 0xffffff7e);
723 mt76_wr(dev, 0x2124, reg_val);
724 760
725 mt76x02_mcu_calibrate(&dev->mt76, MCU_CAL_RXDCOC, 0, false); 761 mt76x02_mcu_calibrate(dev, MCU_CAL_RXDCOC, 0, false);
726 762
727 mt76x02_mcu_calibrate(&dev->mt76, MCU_CAL_LC, is_5ghz, false); 763 mt76x02_mcu_calibrate(dev, MCU_CAL_LC, is_5ghz, false);
728 mt76x02_mcu_calibrate(&dev->mt76, MCU_CAL_LOFT, is_5ghz, false); 764 mt76x02_mcu_calibrate(dev, MCU_CAL_LOFT, is_5ghz, false);
729 mt76x02_mcu_calibrate(&dev->mt76, MCU_CAL_TXIQ, is_5ghz, false); 765 mt76x02_mcu_calibrate(dev, MCU_CAL_TXIQ, is_5ghz, false);
730 mt76x02_mcu_calibrate(&dev->mt76, MCU_CAL_TX_GROUP_DELAY, 766 mt76x02_mcu_calibrate(dev, MCU_CAL_TX_GROUP_DELAY, is_5ghz, false);
731 is_5ghz, false); 767 mt76x02_mcu_calibrate(dev, MCU_CAL_RXIQ, is_5ghz, false);
732 mt76x02_mcu_calibrate(&dev->mt76, MCU_CAL_RXIQ, is_5ghz, false); 768 mt76x02_mcu_calibrate(dev, MCU_CAL_RX_GROUP_DELAY, is_5ghz, false);
733 mt76x02_mcu_calibrate(&dev->mt76, MCU_CAL_RX_GROUP_DELAY,
734 is_5ghz, false);
735 769
736 mt76_wr(dev, 0x2124, reg_val); 770 mt76_wr(dev, MT_BBP(IBI, 9), reg_val);
737 mt76_wr(dev, MT_TX_ALC_CFG_0, tx_alc); 771 mt76_wr(dev, MT_TX_ALC_CFG_0, tx_alc);
738 msleep(100); 772 msleep(100);
739 773
740 mt76x02_mcu_calibrate(&dev->mt76, MCU_CAL_RXDCOC, 1, false); 774 mt76x02_mcu_calibrate(dev, MCU_CAL_RXDCOC, 1, false);
741}
742
743void mt76x0_agc_save(struct mt76x02_dev *dev)
744{
745 /* Only one RX path */
746 dev->agc_save = FIELD_GET(MT_BBP_AGC_GAIN, mt76_rr(dev, MT_BBP(AGC, 8)));
747}
748
749void mt76x0_agc_restore(struct mt76x02_dev *dev)
750{
751 mt76_rmw_field(dev, MT_BBP(AGC, 8), MT_BBP_AGC_GAIN, dev->agc_save);
752} 775}
753 776
754static void mt76x0_temp_sensor(struct mt76x02_dev *dev) 777static void mt76x0_temp_sensor(struct mt76x02_dev *dev)
755{ 778{
756 u8 rf_b7_73, rf_b0_66, rf_b0_67; 779 u8 rf_b7_73, rf_b0_66, rf_b0_67;
757 int cycle, temp; 780 s8 val;
758 u32 val;
759 s32 sval;
760 781
761 rf_b7_73 = rf_rr(dev, MT_RF(7, 73)); 782 rf_b7_73 = rf_rr(dev, MT_RF(7, 73));
762 rf_b0_66 = rf_rr(dev, MT_RF(0, 66)); 783 rf_b0_66 = rf_rr(dev, MT_RF(0, 66));
763 rf_b0_67 = rf_rr(dev, MT_RF(0, 73)); 784 rf_b0_67 = rf_rr(dev, MT_RF(0, 67));
764 785
765 rf_wr(dev, MT_RF(7, 73), 0x02); 786 rf_wr(dev, MT_RF(7, 73), 0x02);
766 rf_wr(dev, MT_RF(0, 66), 0x23); 787 rf_wr(dev, MT_RF(0, 66), 0x23);
767 rf_wr(dev, MT_RF(0, 73), 0x01); 788 rf_wr(dev, MT_RF(0, 67), 0x01);
768 789
769 mt76_wr(dev, MT_BBP(CORE, 34), 0x00080055); 790 mt76_wr(dev, MT_BBP(CORE, 34), 0x00080055);
770 791
771 for (cycle = 0; cycle < 2000; cycle++) { 792 if (!mt76_poll(dev, MT_BBP(CORE, 34), BIT(4), 0, 2000)) {
772 val = mt76_rr(dev, MT_BBP(CORE, 34)); 793 mt76_clear(dev, MT_BBP(CORE, 34), BIT(4));
773 if (!(val & 0x10))
774 break;
775 udelay(3);
776 }
777
778 if (cycle >= 2000) {
779 val &= 0x10;
780 mt76_wr(dev, MT_BBP(CORE, 34), val);
781 goto done; 794 goto done;
782 } 795 }
783 796
784 sval = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff; 797 val = mt76_rr(dev, MT_BBP(CORE, 35));
785 if (!(sval & 0x80)) 798 val = (35 * (val - dev->cal.rx.temp_offset)) / 10 + 25;
786 sval &= 0x7f; /* Positive */
787 else
788 sval |= 0xffffff00; /* Negative */
789 799
790 temp = (35 * (sval - dev->cal.rx.temp_offset)) / 10 + 25; 800 if (abs(val - dev->cal.temp_vco) > 20) {
801 mt76x02_mcu_calibrate(dev, MCU_CAL_VCO,
802 dev->mt76.chandef.chan->hw_value,
803 false);
804 dev->cal.temp_vco = val;
805 }
806 if (abs(val - dev->cal.temp) > 30) {
807 mt76x0_phy_calibrate(dev, false);
808 dev->cal.temp = val;
809 }
791 810
792done: 811done:
793 rf_wr(dev, MT_RF(7, 73), rf_b7_73); 812 rf_wr(dev, MT_RF(7, 73), rf_b7_73);
794 rf_wr(dev, MT_RF(0, 66), rf_b0_66); 813 rf_wr(dev, MT_RF(0, 66), rf_b0_66);
795 rf_wr(dev, MT_RF(0, 73), rf_b0_67); 814 rf_wr(dev, MT_RF(0, 67), rf_b0_67);
796} 815}
797 816
798static void mt76x0_dynamic_vga_tuning(struct mt76x02_dev *dev) 817static void mt76x0_phy_set_gain_val(struct mt76x02_dev *dev)
799{ 818{
800 struct cfg80211_chan_def *chandef = &dev->mt76.chandef; 819 u8 gain = dev->cal.agc_gain_cur[0] - dev->cal.agc_gain_adjust;
801 u32 val, init_vga; 820 u32 val = 0x122c << 16 | 0xf2;
802 int avg_rssi; 821
803 822 mt76_wr(dev, MT_BBP(AGC, 8),
804 init_vga = chandef->chan->band == NL80211_BAND_5GHZ ? 0x54 : 0x4E; 823 val | FIELD_PREP(MT_BBP_AGC_GAIN, gain));
805 avg_rssi = mt76x02_phy_get_min_avg_rssi(&dev->mt76); 824}
806 if (avg_rssi > -60) 825
807 init_vga -= 0x20; 826static void
808 else if (avg_rssi > -70) 827mt76x0_phy_update_channel_gain(struct mt76x02_dev *dev)
809 init_vga -= 0x10; 828{
810 829 bool gain_change;
811 val = mt76_rr(dev, MT_BBP(AGC, 8)); 830 u8 gain_delta;
812 val &= 0xFFFF80FF; 831 int low_gain;
813 val |= init_vga << 8; 832
814 mt76_wr(dev, MT_BBP(AGC,8), val); 833 dev->cal.avg_rssi_all = mt76x02_phy_get_min_avg_rssi(dev);
834
835 low_gain = (dev->cal.avg_rssi_all > mt76x02_get_rssi_gain_thresh(dev)) +
836 (dev->cal.avg_rssi_all > mt76x02_get_low_rssi_gain_thresh(dev));
837
838 gain_change = (dev->cal.low_gain & 2) ^ (low_gain & 2);
839 dev->cal.low_gain = low_gain;
840
841 if (!gain_change) {
842 if (mt76x02_phy_adjust_vga_gain(dev))
843 mt76x0_phy_set_gain_val(dev);
844 return;
845 }
846
847 dev->cal.agc_gain_adjust = (low_gain == 2) ? 0 : 10;
848 gain_delta = (low_gain == 2) ? 10 : 0;
849
850 dev->cal.agc_gain_cur[0] = dev->cal.agc_gain_init[0] - gain_delta;
851 mt76x0_phy_set_gain_val(dev);
852
853 /* clear false CCA counters */
854 mt76_rr(dev, MT_RX_STAT_1);
815} 855}
816 856
817static void mt76x0_phy_calibrate(struct work_struct *work) 857static void mt76x0_phy_calibration_work(struct work_struct *work)
818{ 858{
819 struct mt76x02_dev *dev = container_of(work, struct mt76x02_dev, 859 struct mt76x02_dev *dev = container_of(work, struct mt76x02_dev,
820 cal_work.work); 860 cal_work.work);
821 861
822 mt76x0_dynamic_vga_tuning(dev); 862 mt76x0_phy_update_channel_gain(dev);
823 mt76x0_temp_sensor(dev); 863 if (!mt76x0_tssi_enabled(dev))
864 mt76x0_temp_sensor(dev);
824 865
825 ieee80211_queue_delayed_work(dev->mt76.hw, &dev->cal_work, 866 ieee80211_queue_delayed_work(dev->mt76.hw, &dev->cal_work,
826 MT_CALIBRATE_INTERVAL); 867 MT_CALIBRATE_INTERVAL);
@@ -881,9 +922,9 @@ static void mt76x0_rf_init(struct mt76x02_dev *dev)
881 922
882void mt76x0_phy_init(struct mt76x02_dev *dev) 923void mt76x0_phy_init(struct mt76x02_dev *dev)
883{ 924{
884 INIT_DELAYED_WORK(&dev->cal_work, mt76x0_phy_calibrate); 925 INIT_DELAYED_WORK(&dev->cal_work, mt76x0_phy_calibration_work);
885 926
886 mt76x0_rf_init(dev); 927 mt76x0_rf_init(dev);
887 mt76x02_phy_set_rxpath(&dev->mt76); 928 mt76x02_phy_set_rxpath(dev);
888 mt76x02_phy_set_txdac(&dev->mt76); 929 mt76x02_phy_set_txdac(dev);
889} 930}
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x0/usb_mcu.c b/drivers/net/wireless/mediatek/mt76/mt76x0/usb_mcu.c
index fb6fa1fa5548..a9f14d5149d1 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x0/usb_mcu.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x0/usb_mcu.c
@@ -40,8 +40,7 @@ mt76x0u_upload_firmware(struct mt76x02_dev *dev,
40 ilm_len = le32_to_cpu(hdr->ilm_len) - MT_MCU_IVB_SIZE; 40 ilm_len = le32_to_cpu(hdr->ilm_len) - MT_MCU_IVB_SIZE;
41 dev_dbg(dev->mt76.dev, "loading FW - ILM %u + IVB %u\n", 41 dev_dbg(dev->mt76.dev, "loading FW - ILM %u + IVB %u\n",
42 ilm_len, MT_MCU_IVB_SIZE); 42 ilm_len, MT_MCU_IVB_SIZE);
43 err = mt76x02u_mcu_fw_send_data(&dev->mt76, 43 err = mt76x02u_mcu_fw_send_data(dev, fw_payload + MT_MCU_IVB_SIZE,
44 fw_payload + MT_MCU_IVB_SIZE,
45 ilm_len, MCU_FW_URB_MAX_PAYLOAD, 44 ilm_len, MCU_FW_URB_MAX_PAYLOAD,
46 MT_MCU_IVB_SIZE); 45 MT_MCU_IVB_SIZE);
47 if (err) 46 if (err)
@@ -49,7 +48,7 @@ mt76x0u_upload_firmware(struct mt76x02_dev *dev,
49 48
50 dlm_len = le32_to_cpu(hdr->dlm_len); 49 dlm_len = le32_to_cpu(hdr->dlm_len);
51 dev_dbg(dev->mt76.dev, "loading FW - DLM %u\n", dlm_len); 50 dev_dbg(dev->mt76.dev, "loading FW - DLM %u\n", dlm_len);
52 err = mt76x02u_mcu_fw_send_data(&dev->mt76, 51 err = mt76x02u_mcu_fw_send_data(dev,
53 fw_payload + le32_to_cpu(hdr->ilm_len), 52 fw_payload + le32_to_cpu(hdr->ilm_len),
54 dlm_len, MCU_FW_URB_MAX_PAYLOAD, 53 dlm_len, MCU_FW_URB_MAX_PAYLOAD,
55 MT_MCU_DLM_OFFSET); 54 MT_MCU_DLM_OFFSET);
@@ -121,7 +120,7 @@ static int mt76x0u_load_firmware(struct mt76x02_dev *dev)
121 mt76_set(dev, MT_USB_DMA_CFG, 120 mt76_set(dev, MT_USB_DMA_CFG,
122 (MT_USB_DMA_CFG_RX_BULK_EN | MT_USB_DMA_CFG_TX_BULK_EN) | 121 (MT_USB_DMA_CFG_RX_BULK_EN | MT_USB_DMA_CFG_TX_BULK_EN) |
123 FIELD_PREP(MT_USB_DMA_CFG_RX_BULK_AGG_TOUT, 0x20)); 122 FIELD_PREP(MT_USB_DMA_CFG_RX_BULK_AGG_TOUT, 0x20));
124 mt76x02u_mcu_fw_reset(&dev->mt76); 123 mt76x02u_mcu_fw_reset(dev);
125 usleep_range(5000, 6000); 124 usleep_range(5000, 6000);
126/* 125/*
127 mt76x0_rmw(dev, MT_PBF_CFG, 0, (MT_PBF_CFG_TX0Q_EN | 126 mt76x0_rmw(dev, MT_PBF_CFG, 0, (MT_PBF_CFG_TX0Q_EN |
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x02.h b/drivers/net/wireless/mediatek/mt76/mt76x02.h
index 65174817ebc4..47c42c607964 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x02.h
+++ b/drivers/net/wireless/mediatek/mt76/mt76x02.h
@@ -55,7 +55,8 @@ struct mt76x02_calibration {
55 s8 agc_gain_adjust; 55 s8 agc_gain_adjust;
56 s8 low_gain; 56 s8 low_gain;
57 57
58 u8 temp; 58 s8 temp_vco;
59 s8 temp;
59 60
60 bool init_cal_done; 61 bool init_cal_done;
61 bool tssi_cal_done; 62 bool tssi_cal_done;
@@ -101,8 +102,6 @@ struct mt76x02_dev {
101 102
102 bool no_2ghz; 103 bool no_2ghz;
103 104
104 u8 agc_save;
105
106 u8 coverage_class; 105 u8 coverage_class;
107 u8 slottime; 106 u8 slottime;
108 107
@@ -119,8 +118,8 @@ int mt76x02_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
119int mt76x02_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 118int mt76x02_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
120 struct ieee80211_sta *sta); 119 struct ieee80211_sta *sta);
121 120
122void mt76x02_vif_init(struct mt76_dev *dev, struct ieee80211_vif *vif, 121void mt76x02_vif_init(struct mt76x02_dev *dev, struct ieee80211_vif *vif,
123 unsigned int idx); 122 unsigned int idx);
124int mt76x02_add_interface(struct ieee80211_hw *hw, 123int mt76x02_add_interface(struct ieee80211_hw *hw,
125 struct ieee80211_vif *vif); 124 struct ieee80211_vif *vif);
126void mt76x02_remove_interface(struct ieee80211_hw *hw, 125void mt76x02_remove_interface(struct ieee80211_hw *hw,
@@ -136,14 +135,15 @@ int mt76x02_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
136void mt76x02_sta_rate_tbl_update(struct ieee80211_hw *hw, 135void mt76x02_sta_rate_tbl_update(struct ieee80211_hw *hw,
137 struct ieee80211_vif *vif, 136 struct ieee80211_vif *vif,
138 struct ieee80211_sta *sta); 137 struct ieee80211_sta *sta);
139s8 mt76x02_tx_get_max_txpwr_adj(struct mt76_dev *dev, 138s8 mt76x02_tx_get_max_txpwr_adj(struct mt76x02_dev *dev,
140 const struct ieee80211_tx_rate *rate); 139 const struct ieee80211_tx_rate *rate);
141s8 mt76x02_tx_get_txpwr_adj(struct mt76_dev *mdev, s8 txpwr, s8 max_txpwr_adj); 140s8 mt76x02_tx_get_txpwr_adj(struct mt76x02_dev *dev, s8 txpwr,
141 s8 max_txpwr_adj);
142void mt76x02_tx_set_txpwr_auto(struct mt76x02_dev *dev, s8 txpwr); 142void mt76x02_tx_set_txpwr_auto(struct mt76x02_dev *dev, s8 txpwr);
143int mt76x02_insert_hdr_pad(struct sk_buff *skb); 143int mt76x02_insert_hdr_pad(struct sk_buff *skb);
144void mt76x02_remove_hdr_pad(struct sk_buff *skb, int len); 144void mt76x02_remove_hdr_pad(struct sk_buff *skb, int len);
145void mt76x02_tx_complete(struct mt76_dev *dev, struct sk_buff *skb); 145void mt76x02_tx_complete(struct mt76_dev *dev, struct sk_buff *skb);
146bool mt76x02_tx_status_data(struct mt76_dev *dev, u8 *update); 146bool mt76x02_tx_status_data(struct mt76_dev *mdev, u8 *update);
147void mt76x02_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 147void mt76x02_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
148 struct sk_buff *skb); 148 struct sk_buff *skb);
149void mt76x02_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q); 149void mt76x02_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q);
@@ -156,10 +156,17 @@ int mt76x02_tx_prepare_skb(struct mt76_dev *mdev, void *txwi,
156 u32 *tx_info); 156 u32 *tx_info);
157 157
158extern const u16 mt76x02_beacon_offsets[16]; 158extern const u16 mt76x02_beacon_offsets[16];
159void mt76x02_set_beacon_offsets(struct mt76_dev *dev); 159void mt76x02_set_beacon_offsets(struct mt76x02_dev *dev);
160void mt76x02_set_irq_mask(struct mt76x02_dev *dev, u32 clear, u32 set); 160void mt76x02_set_irq_mask(struct mt76x02_dev *dev, u32 clear, u32 set);
161void mt76x02_mac_start(struct mt76x02_dev *dev); 161void mt76x02_mac_start(struct mt76x02_dev *dev);
162 162
163static inline bool is_mt76x2(struct mt76x02_dev *dev)
164{
165 return mt76_chip(&dev->mt76) == 0x7612 ||
166 mt76_chip(&dev->mt76) == 0x7662 ||
167 mt76_chip(&dev->mt76) == 0x7602;
168}
169
163static inline void mt76x02_irq_enable(struct mt76x02_dev *dev, u32 mask) 170static inline void mt76x02_irq_enable(struct mt76x02_dev *dev, u32 mask)
164{ 171{
165 mt76x02_set_irq_mask(dev, 0, mask); 172 mt76x02_set_irq_mask(dev, 0, mask);
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c b/drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c
index d3efeb8a72b7..9390de2a323e 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.c
@@ -17,46 +17,43 @@
17 17
18#include <asm/unaligned.h> 18#include <asm/unaligned.h>
19 19
20#include "mt76.h"
21#include "mt76x02_eeprom.h" 20#include "mt76x02_eeprom.h"
22#include "mt76x02_regs.h"
23 21
24static int 22static int
25mt76x02_efuse_read(struct mt76_dev *dev, u16 addr, u8 *data, 23mt76x02_efuse_read(struct mt76x02_dev *dev, u16 addr, u8 *data,
26 enum mt76x02_eeprom_modes mode) 24 enum mt76x02_eeprom_modes mode)
27{ 25{
28 u32 val; 26 u32 val;
29 int i; 27 int i;
30 28
31 val = __mt76_rr(dev, MT_EFUSE_CTRL); 29 val = mt76_rr(dev, MT_EFUSE_CTRL);
32 val &= ~(MT_EFUSE_CTRL_AIN | 30 val &= ~(MT_EFUSE_CTRL_AIN |
33 MT_EFUSE_CTRL_MODE); 31 MT_EFUSE_CTRL_MODE);
34 val |= FIELD_PREP(MT_EFUSE_CTRL_AIN, addr & ~0xf); 32 val |= FIELD_PREP(MT_EFUSE_CTRL_AIN, addr & ~0xf);
35 val |= FIELD_PREP(MT_EFUSE_CTRL_MODE, mode); 33 val |= FIELD_PREP(MT_EFUSE_CTRL_MODE, mode);
36 val |= MT_EFUSE_CTRL_KICK; 34 val |= MT_EFUSE_CTRL_KICK;
37 __mt76_wr(dev, MT_EFUSE_CTRL, val); 35 mt76_wr(dev, MT_EFUSE_CTRL, val);
38 36
39 if (!__mt76_poll_msec(dev, MT_EFUSE_CTRL, MT_EFUSE_CTRL_KICK, 37 if (!mt76_poll_msec(dev, MT_EFUSE_CTRL, MT_EFUSE_CTRL_KICK, 0, 1000))
40 0, 1000))
41 return -ETIMEDOUT; 38 return -ETIMEDOUT;
42 39
43 udelay(2); 40 udelay(2);
44 41
45 val = __mt76_rr(dev, MT_EFUSE_CTRL); 42 val = mt76_rr(dev, MT_EFUSE_CTRL);
46 if ((val & MT_EFUSE_CTRL_AOUT) == MT_EFUSE_CTRL_AOUT) { 43 if ((val & MT_EFUSE_CTRL_AOUT) == MT_EFUSE_CTRL_AOUT) {
47 memset(data, 0xff, 16); 44 memset(data, 0xff, 16);
48 return 0; 45 return 0;
49 } 46 }
50 47
51 for (i = 0; i < 4; i++) { 48 for (i = 0; i < 4; i++) {
52 val = __mt76_rr(dev, MT_EFUSE_DATA(i)); 49 val = mt76_rr(dev, MT_EFUSE_DATA(i));
53 put_unaligned_le32(val, data + 4 * i); 50 put_unaligned_le32(val, data + 4 * i);
54 } 51 }
55 52
56 return 0; 53 return 0;
57} 54}
58 55
59int mt76x02_get_efuse_data(struct mt76_dev *dev, u16 base, void *buf, 56int mt76x02_get_efuse_data(struct mt76x02_dev *dev, u16 base, void *buf,
60 int len, enum mt76x02_eeprom_modes mode) 57 int len, enum mt76x02_eeprom_modes mode)
61{ 58{
62 int ret, i; 59 int ret, i;
@@ -71,26 +68,26 @@ int mt76x02_get_efuse_data(struct mt76_dev *dev, u16 base, void *buf,
71} 68}
72EXPORT_SYMBOL_GPL(mt76x02_get_efuse_data); 69EXPORT_SYMBOL_GPL(mt76x02_get_efuse_data);
73 70
74void mt76x02_eeprom_parse_hw_cap(struct mt76_dev *dev) 71void mt76x02_eeprom_parse_hw_cap(struct mt76x02_dev *dev)
75{ 72{
76 u16 val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_0); 73 u16 val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_0);
77 74
78 switch (FIELD_GET(MT_EE_NIC_CONF_0_BOARD_TYPE, val)) { 75 switch (FIELD_GET(MT_EE_NIC_CONF_0_BOARD_TYPE, val)) {
79 case BOARD_TYPE_5GHZ: 76 case BOARD_TYPE_5GHZ:
80 dev->cap.has_5ghz = true; 77 dev->mt76.cap.has_5ghz = true;
81 break; 78 break;
82 case BOARD_TYPE_2GHZ: 79 case BOARD_TYPE_2GHZ:
83 dev->cap.has_2ghz = true; 80 dev->mt76.cap.has_2ghz = true;
84 break; 81 break;
85 default: 82 default:
86 dev->cap.has_2ghz = true; 83 dev->mt76.cap.has_2ghz = true;
87 dev->cap.has_5ghz = true; 84 dev->mt76.cap.has_5ghz = true;
88 break; 85 break;
89 } 86 }
90} 87}
91EXPORT_SYMBOL_GPL(mt76x02_eeprom_parse_hw_cap); 88EXPORT_SYMBOL_GPL(mt76x02_eeprom_parse_hw_cap);
92 89
93bool mt76x02_ext_pa_enabled(struct mt76_dev *dev, enum nl80211_band band) 90bool mt76x02_ext_pa_enabled(struct mt76x02_dev *dev, enum nl80211_band band)
94{ 91{
95 u16 conf0 = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_0); 92 u16 conf0 = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_0);
96 93
@@ -101,7 +98,7 @@ bool mt76x02_ext_pa_enabled(struct mt76_dev *dev, enum nl80211_band band)
101} 98}
102EXPORT_SYMBOL_GPL(mt76x02_ext_pa_enabled); 99EXPORT_SYMBOL_GPL(mt76x02_ext_pa_enabled);
103 100
104void mt76x02_get_rx_gain(struct mt76_dev *dev, enum nl80211_band band, 101void mt76x02_get_rx_gain(struct mt76x02_dev *dev, enum nl80211_band band,
105 u16 *rssi_offset, s8 *lna_2g, s8 *lna_5g) 102 u16 *rssi_offset, s8 *lna_2g, s8 *lna_5g)
106{ 103{
107 u16 val; 104 u16 val;
@@ -129,7 +126,7 @@ void mt76x02_get_rx_gain(struct mt76_dev *dev, enum nl80211_band band,
129} 126}
130EXPORT_SYMBOL_GPL(mt76x02_get_rx_gain); 127EXPORT_SYMBOL_GPL(mt76x02_get_rx_gain);
131 128
132u8 mt76x02_get_lna_gain(struct mt76_dev *dev, 129u8 mt76x02_get_lna_gain(struct mt76x02_dev *dev,
133 s8 *lna_2g, s8 *lna_5g, 130 s8 *lna_2g, s8 *lna_5g,
134 struct ieee80211_channel *chan) 131 struct ieee80211_channel *chan)
135{ 132{
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h b/drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h
index bcd05f7c5f45..b3ec74835d10 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h
+++ b/drivers/net/wireless/mediatek/mt76/mt76x02_eeprom.h
@@ -18,6 +18,8 @@
18#ifndef __MT76x02_EEPROM_H 18#ifndef __MT76x02_EEPROM_H
19#define __MT76x02_EEPROM_H 19#define __MT76x02_EEPROM_H
20 20
21#include "mt76x02.h"
22
21enum mt76x02_eeprom_field { 23enum mt76x02_eeprom_field {
22 MT_EE_CHIP_ID = 0x000, 24 MT_EE_CHIP_ID = 0x000,
23 MT_EE_VERSION = 0x002, 25 MT_EE_VERSION = 0x002,
@@ -168,44 +170,23 @@ static inline s8 mt76x02_rate_power_val(u8 val)
168} 170}
169 171
170static inline int 172static inline int
171mt76x02_eeprom_get(struct mt76_dev *dev, 173mt76x02_eeprom_get(struct mt76x02_dev *dev,
172 enum mt76x02_eeprom_field field) 174 enum mt76x02_eeprom_field field)
173{ 175{
174 if ((field & 1) || field >= __MT_EE_MAX) 176 if ((field & 1) || field >= __MT_EE_MAX)
175 return -1; 177 return -1;
176 178
177 return get_unaligned_le16(dev->eeprom.data + field); 179 return get_unaligned_le16(dev->mt76.eeprom.data + field);
178}
179
180static inline bool
181mt76x02_temp_tx_alc_enabled(struct mt76_dev *dev)
182{
183 u16 val;
184
185 val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_EXT_PA_5G);
186 if (!(val & BIT(15)))
187 return false;
188
189 return mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_1) &
190 MT_EE_NIC_CONF_1_TEMP_TX_ALC;
191}
192
193static inline bool
194mt76x02_tssi_enabled(struct mt76_dev *dev)
195{
196 return !mt76x02_temp_tx_alc_enabled(dev) &&
197 (mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_1) &
198 MT_EE_NIC_CONF_1_TX_ALC_EN);
199} 180}
200 181
201bool mt76x02_ext_pa_enabled(struct mt76_dev *dev, enum nl80211_band band); 182bool mt76x02_ext_pa_enabled(struct mt76x02_dev *dev, enum nl80211_band band);
202int mt76x02_get_efuse_data(struct mt76_dev *dev, u16 base, void *buf, 183int mt76x02_get_efuse_data(struct mt76x02_dev *dev, u16 base, void *buf,
203 int len, enum mt76x02_eeprom_modes mode); 184 int len, enum mt76x02_eeprom_modes mode);
204void mt76x02_get_rx_gain(struct mt76_dev *dev, enum nl80211_band band, 185void mt76x02_get_rx_gain(struct mt76x02_dev *dev, enum nl80211_band band,
205 u16 *rssi_offset, s8 *lna_2g, s8 *lna_5g); 186 u16 *rssi_offset, s8 *lna_2g, s8 *lna_5g);
206u8 mt76x02_get_lna_gain(struct mt76_dev *dev, 187u8 mt76x02_get_lna_gain(struct mt76x02_dev *dev,
207 s8 *lna_2g, s8 *lna_5g, 188 s8 *lna_2g, s8 *lna_5g,
208 struct ieee80211_channel *chan); 189 struct ieee80211_channel *chan);
209void mt76x02_eeprom_parse_hw_cap(struct mt76_dev *dev); 190void mt76x02_eeprom_parse_hw_cap(struct mt76x02_dev *dev);
210 191
211#endif /* __MT76x02_EEPROM_H */ 192#endif /* __MT76x02_EEPROM_H */
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x02_mac.c b/drivers/net/wireless/mediatek/mt76/mt76x02_mac.c
index 244245418ebb..10578e4cb269 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x02_mac.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x02_mac.c
@@ -45,8 +45,8 @@ mt76x02_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data)
45} 45}
46EXPORT_SYMBOL_GPL(mt76x02_mac_get_key_info); 46EXPORT_SYMBOL_GPL(mt76x02_mac_get_key_info);
47 47
48int mt76x02_mac_shared_key_setup(struct mt76_dev *dev, u8 vif_idx, u8 key_idx, 48int mt76x02_mac_shared_key_setup(struct mt76x02_dev *dev, u8 vif_idx,
49 struct ieee80211_key_conf *key) 49 u8 key_idx, struct ieee80211_key_conf *key)
50{ 50{
51 enum mt76x02_cipher_type cipher; 51 enum mt76x02_cipher_type cipher;
52 u8 key_data[32]; 52 u8 key_data[32];
@@ -56,20 +56,20 @@ int mt76x02_mac_shared_key_setup(struct mt76_dev *dev, u8 vif_idx, u8 key_idx,
56 if (cipher == MT_CIPHER_NONE && key) 56 if (cipher == MT_CIPHER_NONE && key)
57 return -EOPNOTSUPP; 57 return -EOPNOTSUPP;
58 58
59 val = __mt76_rr(dev, MT_SKEY_MODE(vif_idx)); 59 val = mt76_rr(dev, MT_SKEY_MODE(vif_idx));
60 val &= ~(MT_SKEY_MODE_MASK << MT_SKEY_MODE_SHIFT(vif_idx, key_idx)); 60 val &= ~(MT_SKEY_MODE_MASK << MT_SKEY_MODE_SHIFT(vif_idx, key_idx));
61 val |= cipher << MT_SKEY_MODE_SHIFT(vif_idx, key_idx); 61 val |= cipher << MT_SKEY_MODE_SHIFT(vif_idx, key_idx);
62 __mt76_wr(dev, MT_SKEY_MODE(vif_idx), val); 62 mt76_wr(dev, MT_SKEY_MODE(vif_idx), val);
63 63
64 __mt76_wr_copy(dev, MT_SKEY(vif_idx, key_idx), key_data, 64 mt76_wr_copy(dev, MT_SKEY(vif_idx, key_idx), key_data,
65 sizeof(key_data)); 65 sizeof(key_data));
66 66
67 return 0; 67 return 0;
68} 68}
69EXPORT_SYMBOL_GPL(mt76x02_mac_shared_key_setup); 69EXPORT_SYMBOL_GPL(mt76x02_mac_shared_key_setup);
70 70
71int mt76x02_mac_wcid_set_key(struct mt76_dev *dev, u8 idx, 71int mt76x02_mac_wcid_set_key(struct mt76x02_dev *dev, u8 idx,
72 struct ieee80211_key_conf *key) 72 struct ieee80211_key_conf *key)
73{ 73{
74 enum mt76x02_cipher_type cipher; 74 enum mt76x02_cipher_type cipher;
75 u8 key_data[32]; 75 u8 key_data[32];
@@ -79,25 +79,26 @@ int mt76x02_mac_wcid_set_key(struct mt76_dev *dev, u8 idx,
79 if (cipher == MT_CIPHER_NONE && key) 79 if (cipher == MT_CIPHER_NONE && key)
80 return -EOPNOTSUPP; 80 return -EOPNOTSUPP;
81 81
82 __mt76_wr_copy(dev, MT_WCID_KEY(idx), key_data, sizeof(key_data)); 82 mt76_wr_copy(dev, MT_WCID_KEY(idx), key_data, sizeof(key_data));
83 __mt76_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PKEY_MODE, cipher); 83 mt76_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PKEY_MODE, cipher);
84 84
85 memset(iv_data, 0, sizeof(iv_data)); 85 memset(iv_data, 0, sizeof(iv_data));
86 if (key) { 86 if (key) {
87 __mt76_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PAIRWISE, 87 mt76_rmw_field(dev, MT_WCID_ATTR(idx), MT_WCID_ATTR_PAIRWISE,
88 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); 88 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
89 iv_data[3] = key->keyidx << 6; 89 iv_data[3] = key->keyidx << 6;
90 if (cipher >= MT_CIPHER_TKIP) 90 if (cipher >= MT_CIPHER_TKIP)
91 iv_data[3] |= 0x20; 91 iv_data[3] |= 0x20;
92 } 92 }
93 93
94 __mt76_wr_copy(dev, MT_WCID_IV(idx), iv_data, sizeof(iv_data)); 94 mt76_wr_copy(dev, MT_WCID_IV(idx), iv_data, sizeof(iv_data));
95 95
96 return 0; 96 return 0;
97} 97}
98EXPORT_SYMBOL_GPL(mt76x02_mac_wcid_set_key); 98EXPORT_SYMBOL_GPL(mt76x02_mac_wcid_set_key);
99 99
100void mt76x02_mac_wcid_setup(struct mt76_dev *dev, u8 idx, u8 vif_idx, u8 *mac) 100void mt76x02_mac_wcid_setup(struct mt76x02_dev *dev, u8 idx,
101 u8 vif_idx, u8 *mac)
101{ 102{
102 struct mt76_wcid_addr addr = {}; 103 struct mt76_wcid_addr addr = {};
103 u32 attr; 104 u32 attr;
@@ -105,10 +106,10 @@ void mt76x02_mac_wcid_setup(struct mt76_dev *dev, u8 idx, u8 vif_idx, u8 *mac)
105 attr = FIELD_PREP(MT_WCID_ATTR_BSS_IDX, vif_idx & 7) | 106 attr = FIELD_PREP(MT_WCID_ATTR_BSS_IDX, vif_idx & 7) |
106 FIELD_PREP(MT_WCID_ATTR_BSS_IDX_EXT, !!(vif_idx & 8)); 107 FIELD_PREP(MT_WCID_ATTR_BSS_IDX_EXT, !!(vif_idx & 8));
107 108
108 __mt76_wr(dev, MT_WCID_ATTR(idx), attr); 109 mt76_wr(dev, MT_WCID_ATTR(idx), attr);
109 110
110 __mt76_wr(dev, MT_WCID_TX_RATE(idx), 0); 111 mt76_wr(dev, MT_WCID_TX_RATE(idx), 0);
111 __mt76_wr(dev, MT_WCID_TX_RATE(idx) + 4, 0); 112 mt76_wr(dev, MT_WCID_TX_RATE(idx) + 4, 0);
112 113
113 if (idx >= 128) 114 if (idx >= 128)
114 return; 115 return;
@@ -116,22 +117,22 @@ void mt76x02_mac_wcid_setup(struct mt76_dev *dev, u8 idx, u8 vif_idx, u8 *mac)
116 if (mac) 117 if (mac)
117 memcpy(addr.macaddr, mac, ETH_ALEN); 118 memcpy(addr.macaddr, mac, ETH_ALEN);
118 119
119 __mt76_wr_copy(dev, MT_WCID_ADDR(idx), &addr, sizeof(addr)); 120 mt76_wr_copy(dev, MT_WCID_ADDR(idx), &addr, sizeof(addr));
120} 121}
121EXPORT_SYMBOL_GPL(mt76x02_mac_wcid_setup); 122EXPORT_SYMBOL_GPL(mt76x02_mac_wcid_setup);
122 123
123void mt76x02_mac_wcid_set_drop(struct mt76_dev *dev, u8 idx, bool drop) 124void mt76x02_mac_wcid_set_drop(struct mt76x02_dev *dev, u8 idx, bool drop)
124{ 125{
125 u32 val = __mt76_rr(dev, MT_WCID_DROP(idx)); 126 u32 val = mt76_rr(dev, MT_WCID_DROP(idx));
126 u32 bit = MT_WCID_DROP_MASK(idx); 127 u32 bit = MT_WCID_DROP_MASK(idx);
127 128
128 /* prevent unnecessary writes */ 129 /* prevent unnecessary writes */
129 if ((val & bit) != (bit * drop)) 130 if ((val & bit) != (bit * drop))
130 __mt76_wr(dev, MT_WCID_DROP(idx), (val & ~bit) | (bit * drop)); 131 mt76_wr(dev, MT_WCID_DROP(idx), (val & ~bit) | (bit * drop));
131} 132}
132EXPORT_SYMBOL_GPL(mt76x02_mac_wcid_set_drop); 133EXPORT_SYMBOL_GPL(mt76x02_mac_wcid_set_drop);
133 134
134void mt76x02_txq_init(struct mt76_dev *dev, struct ieee80211_txq *txq) 135void mt76x02_txq_init(struct mt76x02_dev *dev, struct ieee80211_txq *txq)
135{ 136{
136 struct mt76_txq *mtxq; 137 struct mt76_txq *mtxq;
137 138
@@ -151,55 +152,13 @@ void mt76x02_txq_init(struct mt76_dev *dev, struct ieee80211_txq *txq)
151 mtxq->wcid = &mvif->group_wcid; 152 mtxq->wcid = &mvif->group_wcid;
152 } 153 }
153 154
154 mt76_txq_init(dev, txq); 155 mt76_txq_init(&dev->mt76, txq);
155} 156}
156EXPORT_SYMBOL_GPL(mt76x02_txq_init); 157EXPORT_SYMBOL_GPL(mt76x02_txq_init);
157 158
158static void
159mt76x02_mac_fill_txwi(struct mt76x02_txwi *txwi, struct sk_buff *skb,
160 struct ieee80211_sta *sta, int len, u8 nss)
161{
162 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
163 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
164 u16 txwi_flags = 0;
165
166 if (info->flags & IEEE80211_TX_CTL_LDPC)
167 txwi->rate |= cpu_to_le16(MT_RXWI_RATE_LDPC);
168 if ((info->flags & IEEE80211_TX_CTL_STBC) && nss == 1)
169 txwi->rate |= cpu_to_le16(MT_RXWI_RATE_STBC);
170 if (nss > 1 && sta && sta->smps_mode == IEEE80211_SMPS_DYNAMIC)
171 txwi_flags |= MT_TXWI_FLAGS_MMPS;
172 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK))
173 txwi->ack_ctl |= MT_TXWI_ACK_CTL_REQ;
174 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)
175 txwi->ack_ctl |= MT_TXWI_ACK_CTL_NSEQ;
176 if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)
177 txwi->pktid |= MT_TXWI_PKTID_PROBE;
178 if ((info->flags & IEEE80211_TX_CTL_AMPDU) && sta) {
179 u8 ba_size = IEEE80211_MIN_AMPDU_BUF;
180
181 ba_size <<= sta->ht_cap.ampdu_factor;
182 ba_size = min_t(int, 63, ba_size - 1);
183 if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)
184 ba_size = 0;
185 txwi->ack_ctl |= FIELD_PREP(MT_TXWI_ACK_CTL_BA_WINDOW, ba_size);
186
187 txwi_flags |= MT_TXWI_FLAGS_AMPDU |
188 FIELD_PREP(MT_TXWI_FLAGS_MPDU_DENSITY,
189 sta->ht_cap.ampdu_density);
190 }
191
192 if (ieee80211_is_probe_resp(hdr->frame_control) ||
193 ieee80211_is_beacon(hdr->frame_control))
194 txwi_flags |= MT_TXWI_FLAGS_TS;
195
196 txwi->flags |= cpu_to_le16(txwi_flags);
197 txwi->len_ctl = cpu_to_le16(len);
198}
199
200static __le16 159static __le16
201mt76x02_mac_tx_rate_val(struct mt76_dev *dev, 160mt76x02_mac_tx_rate_val(struct mt76x02_dev *dev,
202 const struct ieee80211_tx_rate *rate, u8 *nss_val) 161 const struct ieee80211_tx_rate *rate, u8 *nss_val)
203{ 162{
204 u16 rateval; 163 u16 rateval;
205 u8 phy, rate_idx; 164 u8 phy, rate_idx;
@@ -224,10 +183,10 @@ mt76x02_mac_tx_rate_val(struct mt76_dev *dev,
224 bw = 1; 183 bw = 1;
225 } else { 184 } else {
226 const struct ieee80211_rate *r; 185 const struct ieee80211_rate *r;
227 int band = dev->chandef.chan->band; 186 int band = dev->mt76.chandef.chan->band;
228 u16 val; 187 u16 val;
229 188
230 r = &dev->hw->wiphy->bands[band]->bitrates[rate->idx]; 189 r = &dev->mt76.hw->wiphy->bands[band]->bitrates[rate->idx];
231 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 190 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
232 val = r->hw_value_short; 191 val = r->hw_value_short;
233 else 192 else
@@ -248,22 +207,22 @@ mt76x02_mac_tx_rate_val(struct mt76_dev *dev,
248 return cpu_to_le16(rateval); 207 return cpu_to_le16(rateval);
249} 208}
250 209
251void mt76x02_mac_wcid_set_rate(struct mt76_dev *dev, struct mt76_wcid *wcid, 210void mt76x02_mac_wcid_set_rate(struct mt76x02_dev *dev, struct mt76_wcid *wcid,
252 const struct ieee80211_tx_rate *rate) 211 const struct ieee80211_tx_rate *rate)
253{ 212{
254 spin_lock_bh(&dev->lock); 213 spin_lock_bh(&dev->mt76.lock);
255 wcid->tx_rate = mt76x02_mac_tx_rate_val(dev, rate, &wcid->tx_rate_nss); 214 wcid->tx_rate = mt76x02_mac_tx_rate_val(dev, rate, &wcid->tx_rate_nss);
256 wcid->tx_rate_set = true; 215 wcid->tx_rate_set = true;
257 spin_unlock_bh(&dev->lock); 216 spin_unlock_bh(&dev->mt76.lock);
258} 217}
259 218
260bool mt76x02_mac_load_tx_status(struct mt76_dev *dev, 219bool mt76x02_mac_load_tx_status(struct mt76x02_dev *dev,
261 struct mt76x02_tx_status *stat) 220 struct mt76x02_tx_status *stat)
262{ 221{
263 u32 stat1, stat2; 222 u32 stat1, stat2;
264 223
265 stat2 = __mt76_rr(dev, MT_TX_STAT_FIFO_EXT); 224 stat2 = mt76_rr(dev, MT_TX_STAT_FIFO_EXT);
266 stat1 = __mt76_rr(dev, MT_TX_STAT_FIFO); 225 stat1 = mt76_rr(dev, MT_TX_STAT_FIFO);
267 226
268 stat->valid = !!(stat1 & MT_TX_STAT_FIFO_VALID); 227 stat->valid = !!(stat1 & MT_TX_STAT_FIFO_VALID);
269 if (!stat->valid) 228 if (!stat->valid)
@@ -339,17 +298,19 @@ mt76x02_mac_process_tx_rate(struct ieee80211_tx_rate *txrate, u16 rate,
339 return 0; 298 return 0;
340} 299}
341 300
342void mt76x02_mac_write_txwi(struct mt76_dev *dev, struct mt76x02_txwi *txwi, 301void mt76x02_mac_write_txwi(struct mt76x02_dev *dev, struct mt76x02_txwi *txwi,
343 struct sk_buff *skb, struct mt76_wcid *wcid, 302 struct sk_buff *skb, struct mt76_wcid *wcid,
344 struct ieee80211_sta *sta, int len) 303 struct ieee80211_sta *sta, int len)
345{ 304{
305 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
346 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 306 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
347 struct ieee80211_tx_rate *rate = &info->control.rates[0]; 307 struct ieee80211_tx_rate *rate = &info->control.rates[0];
348 struct ieee80211_key_conf *key = info->control.hw_key; 308 struct ieee80211_key_conf *key = info->control.hw_key;
349 u16 rate_ht_mask = FIELD_PREP(MT_RXWI_RATE_PHY, BIT(1) | BIT(2)); 309 u16 rate_ht_mask = FIELD_PREP(MT_RXWI_RATE_PHY, BIT(1) | BIT(2));
310 u16 txwi_flags = 0;
350 u8 nss; 311 u8 nss;
351 s8 txpwr_adj, max_txpwr_adj; 312 s8 txpwr_adj, max_txpwr_adj;
352 u8 ccmp_pn[8], nstreams = dev->chainmask & 0xf; 313 u8 ccmp_pn[8], nstreams = dev->mt76.chainmask & 0xf;
353 314
354 memset(txwi, 0, sizeof(*txwi)); 315 memset(txwi, 0, sizeof(*txwi));
355 316
@@ -374,7 +335,7 @@ void mt76x02_mac_write_txwi(struct mt76_dev *dev, struct mt76x02_txwi *txwi,
374 txwi->eiv = *((__le32 *)&ccmp_pn[1]); 335 txwi->eiv = *((__le32 *)&ccmp_pn[1]);
375 } 336 }
376 337
377 spin_lock_bh(&dev->lock); 338 spin_lock_bh(&dev->mt76.lock);
378 if (wcid && (rate->idx < 0 || !rate->count)) { 339 if (wcid && (rate->idx < 0 || !rate->count)) {
379 txwi->rate = wcid->tx_rate; 340 txwi->rate = wcid->tx_rate;
380 max_txpwr_adj = wcid->max_txpwr_adj; 341 max_txpwr_adj = wcid->max_txpwr_adj;
@@ -383,26 +344,57 @@ void mt76x02_mac_write_txwi(struct mt76_dev *dev, struct mt76x02_txwi *txwi,
383 txwi->rate = mt76x02_mac_tx_rate_val(dev, rate, &nss); 344 txwi->rate = mt76x02_mac_tx_rate_val(dev, rate, &nss);
384 max_txpwr_adj = mt76x02_tx_get_max_txpwr_adj(dev, rate); 345 max_txpwr_adj = mt76x02_tx_get_max_txpwr_adj(dev, rate);
385 } 346 }
386 spin_unlock_bh(&dev->lock); 347 spin_unlock_bh(&dev->mt76.lock);
387 348
388 txpwr_adj = mt76x02_tx_get_txpwr_adj(dev, dev->txpower_conf, 349 txpwr_adj = mt76x02_tx_get_txpwr_adj(dev, dev->mt76.txpower_conf,
389 max_txpwr_adj); 350 max_txpwr_adj);
390 txwi->ctl2 = FIELD_PREP(MT_TX_PWR_ADJ, txpwr_adj); 351 txwi->ctl2 = FIELD_PREP(MT_TX_PWR_ADJ, txpwr_adj);
391 352
392 if (nstreams > 1 && mt76_rev(dev) >= MT76XX_REV_E4) 353 if (nstreams > 1 && mt76_rev(&dev->mt76) >= MT76XX_REV_E4)
393 txwi->txstream = 0x13; 354 txwi->txstream = 0x13;
394 else if (nstreams > 1 && mt76_rev(dev) >= MT76XX_REV_E3 && 355 else if (nstreams > 1 && mt76_rev(&dev->mt76) >= MT76XX_REV_E3 &&
395 !(txwi->rate & cpu_to_le16(rate_ht_mask))) 356 !(txwi->rate & cpu_to_le16(rate_ht_mask)))
396 txwi->txstream = 0x93; 357 txwi->txstream = 0x93;
397 358
398 mt76x02_mac_fill_txwi(txwi, skb, sta, len, nss); 359 if (is_mt76x2(dev) && (info->flags & IEEE80211_TX_CTL_LDPC))
360 txwi->rate |= cpu_to_le16(MT_RXWI_RATE_LDPC);
361 if ((info->flags & IEEE80211_TX_CTL_STBC) && nss == 1)
362 txwi->rate |= cpu_to_le16(MT_RXWI_RATE_STBC);
363 if (nss > 1 && sta && sta->smps_mode == IEEE80211_SMPS_DYNAMIC)
364 txwi_flags |= MT_TXWI_FLAGS_MMPS;
365 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK))
366 txwi->ack_ctl |= MT_TXWI_ACK_CTL_REQ;
367 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)
368 txwi->ack_ctl |= MT_TXWI_ACK_CTL_NSEQ;
369 if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)
370 txwi->pktid |= MT_TXWI_PKTID_PROBE;
371 if ((info->flags & IEEE80211_TX_CTL_AMPDU) && sta) {
372 u8 ba_size = IEEE80211_MIN_AMPDU_BUF;
373
374 ba_size <<= sta->ht_cap.ampdu_factor;
375 ba_size = min_t(int, 63, ba_size - 1);
376 if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)
377 ba_size = 0;
378 txwi->ack_ctl |= FIELD_PREP(MT_TXWI_ACK_CTL_BA_WINDOW, ba_size);
379
380 txwi_flags |= MT_TXWI_FLAGS_AMPDU |
381 FIELD_PREP(MT_TXWI_FLAGS_MPDU_DENSITY,
382 sta->ht_cap.ampdu_density);
383 }
384
385 if (ieee80211_is_probe_resp(hdr->frame_control) ||
386 ieee80211_is_beacon(hdr->frame_control))
387 txwi_flags |= MT_TXWI_FLAGS_TS;
388
389 txwi->flags |= cpu_to_le16(txwi_flags);
390 txwi->len_ctl = cpu_to_le16(len);
399} 391}
400EXPORT_SYMBOL_GPL(mt76x02_mac_write_txwi); 392EXPORT_SYMBOL_GPL(mt76x02_mac_write_txwi);
401 393
402static void 394static void
403mt76x02_mac_fill_tx_status(struct mt76_dev *dev, 395mt76x02_mac_fill_tx_status(struct mt76x02_dev *dev,
404 struct ieee80211_tx_info *info, 396 struct ieee80211_tx_info *info,
405 struct mt76x02_tx_status *st, int n_frames) 397 struct mt76x02_tx_status *st, int n_frames)
406{ 398{
407 struct ieee80211_tx_rate *rate = info->status.rates; 399 struct ieee80211_tx_rate *rate = info->status.rates;
408 int cur_idx, last_rate; 400 int cur_idx, last_rate;
@@ -413,7 +405,7 @@ mt76x02_mac_fill_tx_status(struct mt76_dev *dev,
413 405
414 last_rate = min_t(int, st->retry, IEEE80211_TX_MAX_RATES - 1); 406 last_rate = min_t(int, st->retry, IEEE80211_TX_MAX_RATES - 1);
415 mt76x02_mac_process_tx_rate(&rate[last_rate], st->rate, 407 mt76x02_mac_process_tx_rate(&rate[last_rate], st->rate,
416 dev->chandef.chan->band); 408 dev->mt76.chandef.chan->band);
417 if (last_rate < IEEE80211_TX_MAX_RATES - 1) 409 if (last_rate < IEEE80211_TX_MAX_RATES - 1)
418 rate[last_rate + 1].idx = -1; 410 rate[last_rate + 1].idx = -1;
419 411
@@ -441,8 +433,8 @@ mt76x02_mac_fill_tx_status(struct mt76_dev *dev,
441 info->flags |= IEEE80211_TX_STAT_ACK; 433 info->flags |= IEEE80211_TX_STAT_ACK;
442} 434}
443 435
444void mt76x02_send_tx_status(struct mt76_dev *dev, 436void mt76x02_send_tx_status(struct mt76x02_dev *dev,
445 struct mt76x02_tx_status *stat, u8 *update) 437 struct mt76x02_tx_status *stat, u8 *update)
446{ 438{
447 struct ieee80211_tx_info info = {}; 439 struct ieee80211_tx_info info = {};
448 struct ieee80211_sta *sta = NULL; 440 struct ieee80211_sta *sta = NULL;
@@ -450,8 +442,8 @@ void mt76x02_send_tx_status(struct mt76_dev *dev,
450 struct mt76x02_sta *msta = NULL; 442 struct mt76x02_sta *msta = NULL;
451 443
452 rcu_read_lock(); 444 rcu_read_lock();
453 if (stat->wcid < ARRAY_SIZE(dev->wcid)) 445 if (stat->wcid < ARRAY_SIZE(dev->mt76.wcid))
454 wcid = rcu_dereference(dev->wcid[stat->wcid]); 446 wcid = rcu_dereference(dev->mt76.wcid[stat->wcid]);
455 447
456 if (wcid) { 448 if (wcid) {
457 void *priv; 449 void *priv;
@@ -476,7 +468,7 @@ void mt76x02_send_tx_status(struct mt76_dev *dev,
476 } 468 }
477 469
478 mt76x02_mac_fill_tx_status(dev, &info, &msta->status, 470 mt76x02_mac_fill_tx_status(dev, &info, &msta->status,
479 msta->n_frames); 471 msta->n_frames);
480 472
481 msta->status = *stat; 473 msta->status = *stat;
482 msta->n_frames = 1; 474 msta->n_frames = 1;
@@ -486,7 +478,7 @@ void mt76x02_send_tx_status(struct mt76_dev *dev,
486 *update = 1; 478 *update = 1;
487 } 479 }
488 480
489 ieee80211_tx_status_noskb(dev->hw, sta, &info); 481 ieee80211_tx_status_noskb(dev->mt76.hw, sta, &info);
490 482
491out: 483out:
492 rcu_read_unlock(); 484 rcu_read_unlock();
@@ -561,21 +553,21 @@ mt76x02_mac_process_rate(struct mt76_rx_status *status, u16 rate)
561} 553}
562EXPORT_SYMBOL_GPL(mt76x02_mac_process_rate); 554EXPORT_SYMBOL_GPL(mt76x02_mac_process_rate);
563 555
564void mt76x02_mac_setaddr(struct mt76_dev *dev, u8 *addr) 556void mt76x02_mac_setaddr(struct mt76x02_dev *dev, u8 *addr)
565{ 557{
566 ether_addr_copy(dev->macaddr, addr); 558 ether_addr_copy(dev->mt76.macaddr, addr);
567 559
568 if (!is_valid_ether_addr(dev->macaddr)) { 560 if (!is_valid_ether_addr(dev->mt76.macaddr)) {
569 eth_random_addr(dev->macaddr); 561 eth_random_addr(dev->mt76.macaddr);
570 dev_info(dev->dev, 562 dev_info(dev->mt76.dev,
571 "Invalid MAC address, using random address %pM\n", 563 "Invalid MAC address, using random address %pM\n",
572 dev->macaddr); 564 dev->mt76.macaddr);
573 } 565 }
574 566
575 __mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(dev->macaddr)); 567 mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(dev->mt76.macaddr));
576 __mt76_wr(dev, MT_MAC_ADDR_DW1, 568 mt76_wr(dev, MT_MAC_ADDR_DW1,
577 get_unaligned_le16(dev->macaddr + 4) | 569 get_unaligned_le16(dev->mt76.macaddr + 4) |
578 FIELD_PREP(MT_MAC_ADDR_DW1_U2ME_MASK, 0xff)); 570 FIELD_PREP(MT_MAC_ADDR_DW1_U2ME_MASK, 0xff));
579} 571}
580EXPORT_SYMBOL_GPL(mt76x02_mac_setaddr); 572EXPORT_SYMBOL_GPL(mt76x02_mac_setaddr);
581 573
@@ -697,7 +689,7 @@ void mt76x02_mac_poll_tx_status(struct mt76x02_dev *dev, bool irq)
697 689
698 while (!irq || !kfifo_is_full(&dev->txstatus_fifo)) { 690 while (!irq || !kfifo_is_full(&dev->txstatus_fifo)) {
699 spin_lock_irqsave(&dev->mt76.mmio.irq_lock, flags); 691 spin_lock_irqsave(&dev->mt76.mmio.irq_lock, flags);
700 ret = mt76x02_mac_load_tx_status(&dev->mt76, &stat); 692 ret = mt76x02_mac_load_tx_status(dev, &stat);
701 spin_unlock_irqrestore(&dev->mt76.mmio.irq_lock, flags); 693 spin_unlock_irqrestore(&dev->mt76.mmio.irq_lock, flags);
702 694
703 if (!ret) 695 if (!ret)
@@ -706,7 +698,7 @@ void mt76x02_mac_poll_tx_status(struct mt76x02_dev *dev, bool irq)
706 trace_mac_txstat_fetch(dev, &stat); 698 trace_mac_txstat_fetch(dev, &stat);
707 699
708 if (!irq) { 700 if (!irq) {
709 mt76x02_send_tx_status(&dev->mt76, &stat, &update); 701 mt76x02_send_tx_status(dev, &stat, &update);
710 continue; 702 continue;
711 } 703 }
712 704
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x02_mac.h b/drivers/net/wireless/mediatek/mt76/mt76x02_mac.h
index 4f7ee4620ab5..d99c18743969 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x02_mac.h
+++ b/drivers/net/wireless/mediatek/mt76/mt76x02_mac.h
@@ -198,28 +198,29 @@ mt76x02_skb_tx_info(struct sk_buff *skb)
198 return (void *)info->status.status_driver_data; 198 return (void *)info->status.status_driver_data;
199} 199}
200 200
201void mt76x02_txq_init(struct mt76_dev *dev, struct ieee80211_txq *txq); 201void mt76x02_txq_init(struct mt76x02_dev *dev, struct ieee80211_txq *txq);
202enum mt76x02_cipher_type 202enum mt76x02_cipher_type
203mt76x02_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data); 203mt76x02_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data);
204 204
205int mt76x02_mac_shared_key_setup(struct mt76_dev *dev, u8 vif_idx, u8 key_idx, 205int mt76x02_mac_shared_key_setup(struct mt76x02_dev *dev, u8 vif_idx,
206 struct ieee80211_key_conf *key); 206 u8 key_idx, struct ieee80211_key_conf *key);
207int mt76x02_mac_wcid_set_key(struct mt76_dev *dev, u8 idx, 207int mt76x02_mac_wcid_set_key(struct mt76x02_dev *dev, u8 idx,
208 struct ieee80211_key_conf *key); 208 struct ieee80211_key_conf *key);
209void mt76x02_mac_wcid_setup(struct mt76_dev *dev, u8 idx, u8 vif_idx, u8 *mac); 209void mt76x02_mac_wcid_setup(struct mt76x02_dev *dev, u8 idx, u8 vif_idx,
210void mt76x02_mac_wcid_set_drop(struct mt76_dev *dev, u8 idx, bool drop); 210 u8 *mac);
211void mt76x02_mac_wcid_set_rate(struct mt76_dev *dev, struct mt76_wcid *wcid, 211void mt76x02_mac_wcid_set_drop(struct mt76x02_dev *dev, u8 idx, bool drop);
212 const struct ieee80211_tx_rate *rate); 212void mt76x02_mac_wcid_set_rate(struct mt76x02_dev *dev, struct mt76_wcid *wcid,
213bool mt76x02_mac_load_tx_status(struct mt76_dev *dev, 213 const struct ieee80211_tx_rate *rate);
214 struct mt76x02_tx_status *stat); 214bool mt76x02_mac_load_tx_status(struct mt76x02_dev *dev,
215void mt76x02_send_tx_status(struct mt76_dev *dev, 215 struct mt76x02_tx_status *stat);
216 struct mt76x02_tx_status *stat, u8 *update); 216void mt76x02_send_tx_status(struct mt76x02_dev *dev,
217 struct mt76x02_tx_status *stat, u8 *update);
217int mt76x02_mac_process_rx(struct mt76x02_dev *dev, struct sk_buff *skb, 218int mt76x02_mac_process_rx(struct mt76x02_dev *dev, struct sk_buff *skb,
218 void *rxi); 219 void *rxi);
219int 220int
220mt76x02_mac_process_rate(struct mt76_rx_status *status, u16 rate); 221mt76x02_mac_process_rate(struct mt76_rx_status *status, u16 rate);
221void mt76x02_mac_setaddr(struct mt76_dev *dev, u8 *addr); 222void mt76x02_mac_setaddr(struct mt76x02_dev *dev, u8 *addr);
222void mt76x02_mac_write_txwi(struct mt76_dev *dev, struct mt76x02_txwi *txwi, 223void mt76x02_mac_write_txwi(struct mt76x02_dev *dev, struct mt76x02_txwi *txwi,
223 struct sk_buff *skb, struct mt76_wcid *wcid, 224 struct sk_buff *skb, struct mt76_wcid *wcid,
224 struct ieee80211_sta *sta, int len); 225 struct ieee80211_sta *sta, int len);
225void mt76x02_mac_poll_tx_status(struct mt76x02_dev *dev, bool irq); 226void mt76x02_mac_poll_tx_status(struct mt76x02_dev *dev, bool irq);
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x02_mcu.c b/drivers/net/wireless/mediatek/mt76/mt76x02_mcu.c
index 6d565133b7af..1b853bb723fb 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x02_mcu.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x02_mcu.c
@@ -19,9 +19,7 @@
19#include <linux/firmware.h> 19#include <linux/firmware.h>
20#include <linux/delay.h> 20#include <linux/delay.h>
21 21
22#include "mt76.h"
23#include "mt76x02_mcu.h" 22#include "mt76x02_mcu.h"
24#include "mt76x02_dma.h"
25 23
26struct sk_buff *mt76x02_mcu_msg_alloc(const void *data, int len) 24struct sk_buff *mt76x02_mcu_msg_alloc(const void *data, int len)
27{ 25{
@@ -37,7 +35,7 @@ struct sk_buff *mt76x02_mcu_msg_alloc(const void *data, int len)
37EXPORT_SYMBOL_GPL(mt76x02_mcu_msg_alloc); 35EXPORT_SYMBOL_GPL(mt76x02_mcu_msg_alloc);
38 36
39static struct sk_buff * 37static struct sk_buff *
40mt76x02_mcu_get_response(struct mt76_dev *dev, unsigned long expires) 38mt76x02_mcu_get_response(struct mt76x02_dev *dev, unsigned long expires)
41{ 39{
42 unsigned long timeout; 40 unsigned long timeout;
43 41
@@ -45,17 +43,17 @@ mt76x02_mcu_get_response(struct mt76_dev *dev, unsigned long expires)
45 return NULL; 43 return NULL;
46 44
47 timeout = expires - jiffies; 45 timeout = expires - jiffies;
48 wait_event_timeout(dev->mmio.mcu.wait, 46 wait_event_timeout(dev->mt76.mmio.mcu.wait,
49 !skb_queue_empty(&dev->mmio.mcu.res_q), 47 !skb_queue_empty(&dev->mt76.mmio.mcu.res_q),
50 timeout); 48 timeout);
51 return skb_dequeue(&dev->mmio.mcu.res_q); 49 return skb_dequeue(&dev->mt76.mmio.mcu.res_q);
52} 50}
53 51
54static int 52static int
55mt76x02_tx_queue_mcu(struct mt76_dev *dev, enum mt76_txq_id qid, 53mt76x02_tx_queue_mcu(struct mt76x02_dev *dev, enum mt76_txq_id qid,
56 struct sk_buff *skb, int cmd, int seq) 54 struct sk_buff *skb, int cmd, int seq)
57{ 55{
58 struct mt76_queue *q = &dev->q_tx[qid]; 56 struct mt76_queue *q = &dev->mt76.q_tx[qid];
59 struct mt76_queue_buf buf; 57 struct mt76_queue_buf buf;
60 dma_addr_t addr; 58 dma_addr_t addr;
61 u32 tx_info; 59 u32 tx_info;
@@ -66,24 +64,26 @@ mt76x02_tx_queue_mcu(struct mt76_dev *dev, enum mt76_txq_id qid,
66 FIELD_PREP(MT_MCU_MSG_PORT, CPU_TX_PORT) | 64 FIELD_PREP(MT_MCU_MSG_PORT, CPU_TX_PORT) |
67 FIELD_PREP(MT_MCU_MSG_LEN, skb->len); 65 FIELD_PREP(MT_MCU_MSG_LEN, skb->len);
68 66
69 addr = dma_map_single(dev->dev, skb->data, skb->len, 67 addr = dma_map_single(dev->mt76.dev, skb->data, skb->len,
70 DMA_TO_DEVICE); 68 DMA_TO_DEVICE);
71 if (dma_mapping_error(dev->dev, addr)) 69 if (dma_mapping_error(dev->mt76.dev, addr))
72 return -ENOMEM; 70 return -ENOMEM;
73 71
74 buf.addr = addr; 72 buf.addr = addr;
75 buf.len = skb->len; 73 buf.len = skb->len;
74
76 spin_lock_bh(&q->lock); 75 spin_lock_bh(&q->lock);
77 dev->queue_ops->add_buf(dev, q, &buf, 1, tx_info, skb, NULL); 76 mt76_queue_add_buf(dev, q, &buf, 1, tx_info, skb, NULL);
78 dev->queue_ops->kick(dev, q); 77 mt76_queue_kick(dev, q);
79 spin_unlock_bh(&q->lock); 78 spin_unlock_bh(&q->lock);
80 79
81 return 0; 80 return 0;
82} 81}
83 82
84int mt76x02_mcu_msg_send(struct mt76_dev *dev, struct sk_buff *skb, 83int mt76x02_mcu_msg_send(struct mt76_dev *mdev, struct sk_buff *skb,
85 int cmd, bool wait_resp) 84 int cmd, bool wait_resp)
86{ 85{
86 struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);
87 unsigned long expires = jiffies + HZ; 87 unsigned long expires = jiffies + HZ;
88 int ret; 88 int ret;
89 u8 seq; 89 u8 seq;
@@ -91,11 +91,11 @@ int mt76x02_mcu_msg_send(struct mt76_dev *dev, struct sk_buff *skb,
91 if (!skb) 91 if (!skb)
92 return -EINVAL; 92 return -EINVAL;
93 93
94 mutex_lock(&dev->mmio.mcu.mutex); 94 mutex_lock(&mdev->mmio.mcu.mutex);
95 95
96 seq = ++dev->mmio.mcu.msg_seq & 0xf; 96 seq = ++mdev->mmio.mcu.msg_seq & 0xf;
97 if (!seq) 97 if (!seq)
98 seq = ++dev->mmio.mcu.msg_seq & 0xf; 98 seq = ++mdev->mmio.mcu.msg_seq & 0xf;
99 99
100 ret = mt76x02_tx_queue_mcu(dev, MT_TXQ_MCU, skb, cmd, seq); 100 ret = mt76x02_tx_queue_mcu(dev, MT_TXQ_MCU, skb, cmd, seq);
101 if (ret) 101 if (ret)
@@ -107,7 +107,7 @@ int mt76x02_mcu_msg_send(struct mt76_dev *dev, struct sk_buff *skb,
107 107
108 skb = mt76x02_mcu_get_response(dev, expires); 108 skb = mt76x02_mcu_get_response(dev, expires);
109 if (!skb) { 109 if (!skb) {
110 dev_err(dev->dev, 110 dev_err(mdev->dev,
111 "MCU message %d (seq %d) timed out\n", cmd, 111 "MCU message %d (seq %d) timed out\n", cmd,
112 seq); 112 seq);
113 ret = -ETIMEDOUT; 113 ret = -ETIMEDOUT;
@@ -125,13 +125,13 @@ int mt76x02_mcu_msg_send(struct mt76_dev *dev, struct sk_buff *skb,
125 } 125 }
126 126
127out: 127out:
128 mutex_unlock(&dev->mmio.mcu.mutex); 128 mutex_unlock(&mdev->mmio.mcu.mutex);
129 129
130 return ret; 130 return ret;
131} 131}
132EXPORT_SYMBOL_GPL(mt76x02_mcu_msg_send); 132EXPORT_SYMBOL_GPL(mt76x02_mcu_msg_send);
133 133
134int mt76x02_mcu_function_select(struct mt76_dev *dev, 134int mt76x02_mcu_function_select(struct mt76x02_dev *dev,
135 enum mcu_function func, 135 enum mcu_function func,
136 u32 val, bool wait_resp) 136 u32 val, bool wait_resp)
137{ 137{
@@ -144,13 +144,12 @@ int mt76x02_mcu_function_select(struct mt76_dev *dev,
144 .value = cpu_to_le32(val), 144 .value = cpu_to_le32(val),
145 }; 145 };
146 146
147 skb = dev->mcu_ops->mcu_msg_alloc(&msg, sizeof(msg)); 147 skb = mt76_mcu_msg_alloc(dev, &msg, sizeof(msg));
148 return dev->mcu_ops->mcu_send_msg(dev, skb, CMD_FUN_SET_OP, 148 return mt76_mcu_send_msg(dev, skb, CMD_FUN_SET_OP, wait_resp);
149 wait_resp);
150} 149}
151EXPORT_SYMBOL_GPL(mt76x02_mcu_function_select); 150EXPORT_SYMBOL_GPL(mt76x02_mcu_function_select);
152 151
153int mt76x02_mcu_set_radio_state(struct mt76_dev *dev, bool on, 152int mt76x02_mcu_set_radio_state(struct mt76x02_dev *dev, bool on,
154 bool wait_resp) 153 bool wait_resp)
155{ 154{
156 struct sk_buff *skb; 155 struct sk_buff *skb;
@@ -162,13 +161,12 @@ int mt76x02_mcu_set_radio_state(struct mt76_dev *dev, bool on,
162 .level = cpu_to_le32(0), 161 .level = cpu_to_le32(0),
163 }; 162 };
164 163
165 skb = dev->mcu_ops->mcu_msg_alloc(&msg, sizeof(msg)); 164 skb = mt76_mcu_msg_alloc(dev, &msg, sizeof(msg));
166 return dev->mcu_ops->mcu_send_msg(dev, skb, CMD_POWER_SAVING_OP, 165 return mt76_mcu_send_msg(dev, skb, CMD_POWER_SAVING_OP, wait_resp);
167 wait_resp);
168} 166}
169EXPORT_SYMBOL_GPL(mt76x02_mcu_set_radio_state); 167EXPORT_SYMBOL_GPL(mt76x02_mcu_set_radio_state);
170 168
171int mt76x02_mcu_calibrate(struct mt76_dev *dev, int type, 169int mt76x02_mcu_calibrate(struct mt76x02_dev *dev, int type,
172 u32 param, bool wait) 170 u32 param, bool wait)
173{ 171{
174 struct sk_buff *skb; 172 struct sk_buff *skb;
@@ -182,44 +180,44 @@ int mt76x02_mcu_calibrate(struct mt76_dev *dev, int type,
182 int ret; 180 int ret;
183 181
184 if (wait) 182 if (wait)
185 dev->bus->rmw(dev, MT_MCU_COM_REG0, BIT(31), 0); 183 mt76_rmw(dev, MT_MCU_COM_REG0, BIT(31), 0);
186 184
187 skb = dev->mcu_ops->mcu_msg_alloc(&msg, sizeof(msg)); 185 skb = mt76_mcu_msg_alloc(dev, &msg, sizeof(msg));
188 ret = dev->mcu_ops->mcu_send_msg(dev, skb, CMD_CALIBRATION_OP, true); 186 ret = mt76_mcu_send_msg(dev, skb, CMD_CALIBRATION_OP, true);
189 if (ret) 187 if (ret)
190 return ret; 188 return ret;
191 189
192 if (wait && 190 if (wait &&
193 WARN_ON(!__mt76_poll_msec(dev, MT_MCU_COM_REG0, 191 WARN_ON(!mt76_poll_msec(dev, MT_MCU_COM_REG0,
194 BIT(31), BIT(31), 100))) 192 BIT(31), BIT(31), 100)))
195 return -ETIMEDOUT; 193 return -ETIMEDOUT;
196 194
197 return 0; 195 return 0;
198} 196}
199EXPORT_SYMBOL_GPL(mt76x02_mcu_calibrate); 197EXPORT_SYMBOL_GPL(mt76x02_mcu_calibrate);
200 198
201int mt76x02_mcu_cleanup(struct mt76_dev *dev) 199int mt76x02_mcu_cleanup(struct mt76x02_dev *dev)
202{ 200{
203 struct sk_buff *skb; 201 struct sk_buff *skb;
204 202
205 dev->bus->wr(dev, MT_MCU_INT_LEVEL, 1); 203 mt76_wr(dev, MT_MCU_INT_LEVEL, 1);
206 usleep_range(20000, 30000); 204 usleep_range(20000, 30000);
207 205
208 while ((skb = skb_dequeue(&dev->mmio.mcu.res_q)) != NULL) 206 while ((skb = skb_dequeue(&dev->mt76.mmio.mcu.res_q)) != NULL)
209 dev_kfree_skb(skb); 207 dev_kfree_skb(skb);
210 208
211 return 0; 209 return 0;
212} 210}
213EXPORT_SYMBOL_GPL(mt76x02_mcu_cleanup); 211EXPORT_SYMBOL_GPL(mt76x02_mcu_cleanup);
214 212
215void mt76x02_set_ethtool_fwver(struct mt76_dev *dev, 213void mt76x02_set_ethtool_fwver(struct mt76x02_dev *dev,
216 const struct mt76x02_fw_header *h) 214 const struct mt76x02_fw_header *h)
217{ 215{
218 u16 bld = le16_to_cpu(h->build_ver); 216 u16 bld = le16_to_cpu(h->build_ver);
219 u16 ver = le16_to_cpu(h->fw_ver); 217 u16 ver = le16_to_cpu(h->fw_ver);
220 218
221 snprintf(dev->hw->wiphy->fw_version, 219 snprintf(dev->mt76.hw->wiphy->fw_version,
222 sizeof(dev->hw->wiphy->fw_version), 220 sizeof(dev->mt76.hw->wiphy->fw_version),
223 "%d.%d.%02d-b%x", 221 "%d.%d.%02d-b%x",
224 (ver >> 12) & 0xf, (ver >> 8) & 0xf, ver & 0xf, bld); 222 (ver >> 12) & 0xf, (ver >> 8) & 0xf, ver & 0xf, bld);
225} 223}
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x02_mcu.h b/drivers/net/wireless/mediatek/mt76/mt76x02_mcu.h
index ce664f8b1c94..2d8fd2514570 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x02_mcu.h
+++ b/drivers/net/wireless/mediatek/mt76/mt76x02_mcu.h
@@ -17,6 +17,8 @@
17#ifndef __MT76x02_MCU_H 17#ifndef __MT76x02_MCU_H
18#define __MT76x02_MCU_H 18#define __MT76x02_MCU_H
19 19
20#include "mt76x02.h"
21
20#define MT_MCU_RESET_CTL 0x070C 22#define MT_MCU_RESET_CTL 0x070C
21#define MT_MCU_INT_LEVEL 0x0718 23#define MT_MCU_INT_LEVEL 0x0718
22#define MT_MCU_COM_REG0 0x0730 24#define MT_MCU_COM_REG0 0x0730
@@ -94,18 +96,18 @@ struct mt76x02_patch_header {
94 u8 pad[2]; 96 u8 pad[2];
95}; 97};
96 98
97int mt76x02_mcu_cleanup(struct mt76_dev *dev); 99int mt76x02_mcu_cleanup(struct mt76x02_dev *dev);
98int mt76x02_mcu_calibrate(struct mt76_dev *dev, int type, 100int mt76x02_mcu_calibrate(struct mt76x02_dev *dev, int type,
99 u32 param, bool wait); 101 u32 param, bool wait);
100struct sk_buff *mt76x02_mcu_msg_alloc(const void *data, int len); 102struct sk_buff *mt76x02_mcu_msg_alloc(const void *data, int len);
101int mt76x02_mcu_msg_send(struct mt76_dev *dev, struct sk_buff *skb, 103int mt76x02_mcu_msg_send(struct mt76_dev *mdev, struct sk_buff *skb,
102 int cmd, bool wait_resp); 104 int cmd, bool wait_resp);
103int mt76x02_mcu_function_select(struct mt76_dev *dev, 105int mt76x02_mcu_function_select(struct mt76x02_dev *dev,
104 enum mcu_function func, 106 enum mcu_function func,
105 u32 val, bool wait_resp); 107 u32 val, bool wait_resp);
106int mt76x02_mcu_set_radio_state(struct mt76_dev *dev, bool on, 108int mt76x02_mcu_set_radio_state(struct mt76x02_dev *dev, bool on,
107 bool wait_resp); 109 bool wait_resp);
108void mt76x02_set_ethtool_fwver(struct mt76_dev *dev, 110void mt76x02_set_ethtool_fwver(struct mt76x02_dev *dev,
109 const struct mt76x02_fw_header *h); 111 const struct mt76x02_fw_header *h);
110 112
111#endif /* __MT76x02_MCU_H */ 113#endif /* __MT76x02_MCU_H */
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x02_mmio.c b/drivers/net/wireless/mediatek/mt76/mt76x02_mmio.c
index 1b945079c802..39f092034240 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x02_mmio.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x02_mmio.c
@@ -65,7 +65,7 @@ static void mt76x02_process_tx_status_fifo(struct mt76x02_dev *dev)
65 u8 update = 1; 65 u8 update = 1;
66 66
67 while (kfifo_get(&dev->txstatus_fifo, &stat)) 67 while (kfifo_get(&dev->txstatus_fifo, &stat))
68 mt76x02_send_tx_status(&dev->mt76, &stat, &update); 68 mt76x02_send_tx_status(dev, &stat, &update);
69} 69}
70 70
71static void mt76x02_tx_tasklet(unsigned long data) 71static void mt76x02_tx_tasklet(unsigned long data)
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x02_phy.c b/drivers/net/wireless/mediatek/mt76/mt76x02_phy.c
index d31ce1d7b689..0f1d7b5c9f68 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x02_phy.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x02_phy.c
@@ -17,18 +17,17 @@
17 17
18#include <linux/kernel.h> 18#include <linux/kernel.h>
19 19
20#include "mt76.h" 20#include "mt76x02.h"
21#include "mt76x02_phy.h" 21#include "mt76x02_phy.h"
22#include "mt76x02_mac.h"
23 22
24void mt76x02_phy_set_rxpath(struct mt76_dev *dev) 23void mt76x02_phy_set_rxpath(struct mt76x02_dev *dev)
25{ 24{
26 u32 val; 25 u32 val;
27 26
28 val = __mt76_rr(dev, MT_BBP(AGC, 0)); 27 val = mt76_rr(dev, MT_BBP(AGC, 0));
29 val &= ~BIT(4); 28 val &= ~BIT(4);
30 29
31 switch (dev->chainmask & 0xf) { 30 switch (dev->mt76.chainmask & 0xf) {
32 case 2: 31 case 2:
33 val |= BIT(3); 32 val |= BIT(3);
34 break; 33 break;
@@ -37,23 +36,23 @@ void mt76x02_phy_set_rxpath(struct mt76_dev *dev)
37 break; 36 break;
38 } 37 }
39 38
40 __mt76_wr(dev, MT_BBP(AGC, 0), val); 39 mt76_wr(dev, MT_BBP(AGC, 0), val);
41 mb(); 40 mb();
42 val = __mt76_rr(dev, MT_BBP(AGC, 0)); 41 val = mt76_rr(dev, MT_BBP(AGC, 0));
43} 42}
44EXPORT_SYMBOL_GPL(mt76x02_phy_set_rxpath); 43EXPORT_SYMBOL_GPL(mt76x02_phy_set_rxpath);
45 44
46void mt76x02_phy_set_txdac(struct mt76_dev *dev) 45void mt76x02_phy_set_txdac(struct mt76x02_dev *dev)
47{ 46{
48 int txpath; 47 int txpath;
49 48
50 txpath = (dev->chainmask >> 8) & 0xf; 49 txpath = (dev->mt76.chainmask >> 8) & 0xf;
51 switch (txpath) { 50 switch (txpath) {
52 case 2: 51 case 2:
53 __mt76_set(dev, MT_BBP(TXBE, 5), 0x3); 52 mt76_set(dev, MT_BBP(TXBE, 5), 0x3);
54 break; 53 break;
55 default: 54 default:
56 __mt76_clear(dev, MT_BBP(TXBE, 5), 0x3); 55 mt76_clear(dev, MT_BBP(TXBE, 5), 0x3);
57 break; 56 break;
58 } 57 }
59} 58}
@@ -102,40 +101,38 @@ void mt76x02_add_rate_power_offset(struct mt76_rate_power *r, int offset)
102} 101}
103EXPORT_SYMBOL_GPL(mt76x02_add_rate_power_offset); 102EXPORT_SYMBOL_GPL(mt76x02_add_rate_power_offset);
104 103
105void mt76x02_phy_set_txpower(struct mt76_dev *dev, int txp_0, int txp_1) 104void mt76x02_phy_set_txpower(struct mt76x02_dev *dev, int txp_0, int txp_1)
106{ 105{
107 struct mt76_rate_power *t = &dev->rate_power; 106 struct mt76_rate_power *t = &dev->mt76.rate_power;
108 107
109 __mt76_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_0, 108 mt76_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_0, txp_0);
110 txp_0); 109 mt76_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_1, txp_1);
111 __mt76_rmw_field(dev, MT_TX_ALC_CFG_0, MT_TX_ALC_CFG_0_CH_INIT_1, 110
112 txp_1); 111 mt76_wr(dev, MT_TX_PWR_CFG_0,
113 112 mt76x02_tx_power_mask(t->cck[0], t->cck[2], t->ofdm[0],
114 __mt76_wr(dev, MT_TX_PWR_CFG_0, 113 t->ofdm[2]));
115 mt76x02_tx_power_mask(t->cck[0], t->cck[2], t->ofdm[0], 114 mt76_wr(dev, MT_TX_PWR_CFG_1,
116 t->ofdm[2])); 115 mt76x02_tx_power_mask(t->ofdm[4], t->ofdm[6], t->ht[0],
117 __mt76_wr(dev, MT_TX_PWR_CFG_1, 116 t->ht[2]));
118 mt76x02_tx_power_mask(t->ofdm[4], t->ofdm[6], t->ht[0], 117 mt76_wr(dev, MT_TX_PWR_CFG_2,
119 t->ht[2])); 118 mt76x02_tx_power_mask(t->ht[4], t->ht[6], t->ht[8],
120 __mt76_wr(dev, MT_TX_PWR_CFG_2, 119 t->ht[10]));
121 mt76x02_tx_power_mask(t->ht[4], t->ht[6], t->ht[8], 120 mt76_wr(dev, MT_TX_PWR_CFG_3,
122 t->ht[10])); 121 mt76x02_tx_power_mask(t->ht[12], t->ht[14], t->stbc[0],
123 __mt76_wr(dev, MT_TX_PWR_CFG_3, 122 t->stbc[2]));
124 mt76x02_tx_power_mask(t->ht[12], t->ht[14], t->stbc[0], 123 mt76_wr(dev, MT_TX_PWR_CFG_4,
125 t->stbc[2])); 124 mt76x02_tx_power_mask(t->stbc[4], t->stbc[6], 0, 0));
126 __mt76_wr(dev, MT_TX_PWR_CFG_4, 125 mt76_wr(dev, MT_TX_PWR_CFG_7,
127 mt76x02_tx_power_mask(t->stbc[4], t->stbc[6], 0, 0)); 126 mt76x02_tx_power_mask(t->ofdm[7], t->vht[8], t->ht[7],
128 __mt76_wr(dev, MT_TX_PWR_CFG_7, 127 t->vht[9]));
129 mt76x02_tx_power_mask(t->ofdm[7], t->vht[8], t->ht[7], 128 mt76_wr(dev, MT_TX_PWR_CFG_8,
130 t->vht[9])); 129 mt76x02_tx_power_mask(t->ht[14], 0, t->vht[8], t->vht[9]));
131 __mt76_wr(dev, MT_TX_PWR_CFG_8, 130 mt76_wr(dev, MT_TX_PWR_CFG_9,
132 mt76x02_tx_power_mask(t->ht[14], 0, t->vht[8], t->vht[9])); 131 mt76x02_tx_power_mask(t->ht[7], 0, t->stbc[8], t->stbc[9]));
133 __mt76_wr(dev, MT_TX_PWR_CFG_9,
134 mt76x02_tx_power_mask(t->ht[7], 0, t->stbc[8], t->stbc[9]));
135} 132}
136EXPORT_SYMBOL_GPL(mt76x02_phy_set_txpower); 133EXPORT_SYMBOL_GPL(mt76x02_phy_set_txpower);
137 134
138int mt76x02_phy_get_min_avg_rssi(struct mt76_dev *dev) 135int mt76x02_phy_get_min_avg_rssi(struct mt76x02_dev *dev)
139{ 136{
140 struct mt76x02_sta *sta; 137 struct mt76x02_sta *sta;
141 struct mt76_wcid *wcid; 138 struct mt76_wcid *wcid;
@@ -145,8 +142,8 @@ int mt76x02_phy_get_min_avg_rssi(struct mt76_dev *dev)
145 local_bh_disable(); 142 local_bh_disable();
146 rcu_read_lock(); 143 rcu_read_lock();
147 144
148 for (i = 0; i < ARRAY_SIZE(dev->wcid_mask); i++) { 145 for (i = 0; i < ARRAY_SIZE(dev->mt76.wcid_mask); i++) {
149 unsigned long mask = dev->wcid_mask[i]; 146 unsigned long mask = dev->mt76.wcid_mask[i];
150 147
151 if (!mask) 148 if (!mask)
152 continue; 149 continue;
@@ -155,17 +152,17 @@ int mt76x02_phy_get_min_avg_rssi(struct mt76_dev *dev)
155 if (!(mask & 1)) 152 if (!(mask & 1))
156 continue; 153 continue;
157 154
158 wcid = rcu_dereference(dev->wcid[j]); 155 wcid = rcu_dereference(dev->mt76.wcid[j]);
159 if (!wcid) 156 if (!wcid)
160 continue; 157 continue;
161 158
162 sta = container_of(wcid, struct mt76x02_sta, wcid); 159 sta = container_of(wcid, struct mt76x02_sta, wcid);
163 spin_lock(&dev->rx_lock); 160 spin_lock(&dev->mt76.rx_lock);
164 if (sta->inactive_count++ < 5) 161 if (sta->inactive_count++ < 5)
165 cur_rssi = ewma_signal_read(&sta->rssi); 162 cur_rssi = ewma_signal_read(&sta->rssi);
166 else 163 else
167 cur_rssi = 0; 164 cur_rssi = 0;
168 spin_unlock(&dev->rx_lock); 165 spin_unlock(&dev->mt76.rx_lock);
169 166
170 if (cur_rssi < min_rssi) 167 if (cur_rssi < min_rssi)
171 min_rssi = cur_rssi; 168 min_rssi = cur_rssi;
@@ -181,3 +178,81 @@ int mt76x02_phy_get_min_avg_rssi(struct mt76_dev *dev)
181 return min_rssi; 178 return min_rssi;
182} 179}
183EXPORT_SYMBOL_GPL(mt76x02_phy_get_min_avg_rssi); 180EXPORT_SYMBOL_GPL(mt76x02_phy_get_min_avg_rssi);
181
182void mt76x02_phy_set_bw(struct mt76x02_dev *dev, int width, u8 ctrl)
183{
184 int core_val, agc_val;
185
186 switch (width) {
187 case NL80211_CHAN_WIDTH_80:
188 core_val = 3;
189 agc_val = 7;
190 break;
191 case NL80211_CHAN_WIDTH_40:
192 core_val = 2;
193 agc_val = 3;
194 break;
195 default:
196 core_val = 0;
197 agc_val = 1;
198 break;
199 }
200
201 mt76_rmw_field(dev, MT_BBP(CORE, 1), MT_BBP_CORE_R1_BW, core_val);
202 mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_BW, agc_val);
203 mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_CTRL_CHAN, ctrl);
204 mt76_rmw_field(dev, MT_BBP(TXBE, 0), MT_BBP_TXBE_R0_CTRL_CHAN, ctrl);
205}
206EXPORT_SYMBOL_GPL(mt76x02_phy_set_bw);
207
208void mt76x02_phy_set_band(struct mt76x02_dev *dev, int band,
209 bool primary_upper)
210{
211 switch (band) {
212 case NL80211_BAND_2GHZ:
213 mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G);
214 mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G);
215 break;
216 case NL80211_BAND_5GHZ:
217 mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G);
218 mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G);
219 break;
220 }
221
222 mt76_rmw_field(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_UPPER_40M,
223 primary_upper);
224}
225EXPORT_SYMBOL_GPL(mt76x02_phy_set_band);
226
227bool mt76x02_phy_adjust_vga_gain(struct mt76x02_dev *dev)
228{
229 u8 limit = dev->cal.low_gain > 0 ? 16 : 4;
230 bool ret = false;
231 u32 false_cca;
232
233 false_cca = FIELD_GET(MT_RX_STAT_1_CCA_ERRORS, mt76_rr(dev, MT_RX_STAT_1));
234 dev->cal.false_cca = false_cca;
235 if (false_cca > 800 && dev->cal.agc_gain_adjust < limit) {
236 dev->cal.agc_gain_adjust += 2;
237 ret = true;
238 } else if ((false_cca < 10 && dev->cal.agc_gain_adjust > 0) ||
239 (dev->cal.agc_gain_adjust >= limit && false_cca < 500)) {
240 dev->cal.agc_gain_adjust -= 2;
241 ret = true;
242 }
243
244 return ret;
245}
246EXPORT_SYMBOL_GPL(mt76x02_phy_adjust_vga_gain);
247
248void mt76x02_init_agc_gain(struct mt76x02_dev *dev)
249{
250 dev->cal.agc_gain_init[0] = mt76_get_field(dev, MT_BBP(AGC, 8),
251 MT_BBP_AGC_GAIN);
252 dev->cal.agc_gain_init[1] = mt76_get_field(dev, MT_BBP(AGC, 9),
253 MT_BBP_AGC_GAIN);
254 memcpy(dev->cal.agc_gain_cur, dev->cal.agc_gain_init,
255 sizeof(dev->cal.agc_gain_cur));
256 dev->cal.low_gain = -1;
257}
258EXPORT_SYMBOL_GPL(mt76x02_init_agc_gain);
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x02_phy.h b/drivers/net/wireless/mediatek/mt76/mt76x02_phy.h
index e70ea6eeb077..2b316cf7c70c 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x02_phy.h
+++ b/drivers/net/wireless/mediatek/mt76/mt76x02_phy.h
@@ -19,12 +19,43 @@
19 19
20#include "mt76x02_regs.h" 20#include "mt76x02_regs.h"
21 21
22static inline int
23mt76x02_get_rssi_gain_thresh(struct mt76x02_dev *dev)
24{
25 switch (dev->mt76.chandef.width) {
26 case NL80211_CHAN_WIDTH_80:
27 return -62;
28 case NL80211_CHAN_WIDTH_40:
29 return -65;
30 default:
31 return -68;
32 }
33}
34
35static inline int
36mt76x02_get_low_rssi_gain_thresh(struct mt76x02_dev *dev)
37{
38 switch (dev->mt76.chandef.width) {
39 case NL80211_CHAN_WIDTH_80:
40 return -76;
41 case NL80211_CHAN_WIDTH_40:
42 return -79;
43 default:
44 return -82;
45 }
46}
47
22void mt76x02_add_rate_power_offset(struct mt76_rate_power *r, int offset); 48void mt76x02_add_rate_power_offset(struct mt76_rate_power *r, int offset);
23void mt76x02_phy_set_txpower(struct mt76_dev *dev, int txp_0, int txp_2); 49void mt76x02_phy_set_txpower(struct mt76x02_dev *dev, int txp_0, int txp_2);
24void mt76x02_limit_rate_power(struct mt76_rate_power *r, int limit); 50void mt76x02_limit_rate_power(struct mt76_rate_power *r, int limit);
25int mt76x02_get_max_rate_power(struct mt76_rate_power *r); 51int mt76x02_get_max_rate_power(struct mt76_rate_power *r);
26void mt76x02_phy_set_rxpath(struct mt76_dev *dev); 52void mt76x02_phy_set_rxpath(struct mt76x02_dev *dev);
27void mt76x02_phy_set_txdac(struct mt76_dev *dev); 53void mt76x02_phy_set_txdac(struct mt76x02_dev *dev);
28int mt76x02_phy_get_min_avg_rssi(struct mt76_dev *dev); 54int mt76x02_phy_get_min_avg_rssi(struct mt76x02_dev *dev);
55void mt76x02_phy_set_bw(struct mt76x02_dev *dev, int width, u8 ctrl);
56void mt76x02_phy_set_band(struct mt76x02_dev *dev, int band,
57 bool primary_upper);
58bool mt76x02_phy_adjust_vga_gain(struct mt76x02_dev *dev);
59void mt76x02_init_agc_gain(struct mt76x02_dev *dev);
29 60
30#endif /* __MT76x02_PHY_H */ 61#endif /* __MT76x02_PHY_H */
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x02_regs.h b/drivers/net/wireless/mediatek/mt76/mt76x02_regs.h
index 24d1e6d747dd..f7de77d09d28 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x02_regs.h
+++ b/drivers/net/wireless/mediatek/mt76/mt76x02_regs.h
@@ -205,8 +205,8 @@
205#define MT_TXQ_STA 0x0434 205#define MT_TXQ_STA 0x0434
206#define MT_RF_CSR_CFG 0x0500 206#define MT_RF_CSR_CFG 0x0500
207#define MT_RF_CSR_CFG_DATA GENMASK(7, 0) 207#define MT_RF_CSR_CFG_DATA GENMASK(7, 0)
208#define MT_RF_CSR_CFG_REG_ID GENMASK(13, 8) 208#define MT_RF_CSR_CFG_REG_ID GENMASK(14, 8)
209#define MT_RF_CSR_CFG_REG_BANK GENMASK(17, 14) 209#define MT_RF_CSR_CFG_REG_BANK GENMASK(17, 15)
210#define MT_RF_CSR_CFG_WR BIT(30) 210#define MT_RF_CSR_CFG_WR BIT(30)
211#define MT_RF_CSR_CFG_KICK BIT(31) 211#define MT_RF_CSR_CFG_KICK BIT(31)
212 212
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x02_txrx.c b/drivers/net/wireless/mediatek/mt76/mt76x02_txrx.c
index 830377221739..d3de08872d6e 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x02_txrx.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x02_txrx.c
@@ -71,7 +71,7 @@ void mt76x02_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
71} 71}
72EXPORT_SYMBOL_GPL(mt76x02_queue_rx_skb); 72EXPORT_SYMBOL_GPL(mt76x02_queue_rx_skb);
73 73
74s8 mt76x02_tx_get_max_txpwr_adj(struct mt76_dev *dev, 74s8 mt76x02_tx_get_max_txpwr_adj(struct mt76x02_dev *dev,
75 const struct ieee80211_tx_rate *rate) 75 const struct ieee80211_tx_rate *rate)
76{ 76{
77 s8 max_txpwr; 77 s8 max_txpwr;
@@ -80,23 +80,23 @@ s8 mt76x02_tx_get_max_txpwr_adj(struct mt76_dev *dev,
80 u8 mcs = ieee80211_rate_get_vht_mcs(rate); 80 u8 mcs = ieee80211_rate_get_vht_mcs(rate);
81 81
82 if (mcs == 8 || mcs == 9) { 82 if (mcs == 8 || mcs == 9) {
83 max_txpwr = dev->rate_power.vht[8]; 83 max_txpwr = dev->mt76.rate_power.vht[8];
84 } else { 84 } else {
85 u8 nss, idx; 85 u8 nss, idx;
86 86
87 nss = ieee80211_rate_get_vht_nss(rate); 87 nss = ieee80211_rate_get_vht_nss(rate);
88 idx = ((nss - 1) << 3) + mcs; 88 idx = ((nss - 1) << 3) + mcs;
89 max_txpwr = dev->rate_power.ht[idx & 0xf]; 89 max_txpwr = dev->mt76.rate_power.ht[idx & 0xf];
90 } 90 }
91 } else if (rate->flags & IEEE80211_TX_RC_MCS) { 91 } else if (rate->flags & IEEE80211_TX_RC_MCS) {
92 max_txpwr = dev->rate_power.ht[rate->idx & 0xf]; 92 max_txpwr = dev->mt76.rate_power.ht[rate->idx & 0xf];
93 } else { 93 } else {
94 enum nl80211_band band = dev->chandef.chan->band; 94 enum nl80211_band band = dev->mt76.chandef.chan->band;
95 95
96 if (band == NL80211_BAND_2GHZ) { 96 if (band == NL80211_BAND_2GHZ) {
97 const struct ieee80211_rate *r; 97 const struct ieee80211_rate *r;
98 struct wiphy *wiphy = dev->hw->wiphy; 98 struct wiphy *wiphy = dev->mt76.hw->wiphy;
99 struct mt76_rate_power *rp = &dev->rate_power; 99 struct mt76_rate_power *rp = &dev->mt76.rate_power;
100 100
101 r = &wiphy->bands[band]->bitrates[rate->idx]; 101 r = &wiphy->bands[band]->bitrates[rate->idx];
102 if (r->flags & IEEE80211_RATE_SHORT_PREAMBLE) 102 if (r->flags & IEEE80211_RATE_SHORT_PREAMBLE)
@@ -104,7 +104,7 @@ s8 mt76x02_tx_get_max_txpwr_adj(struct mt76_dev *dev,
104 else 104 else
105 max_txpwr = rp->ofdm[r->hw_value & 0x7]; 105 max_txpwr = rp->ofdm[r->hw_value & 0x7];
106 } else { 106 } else {
107 max_txpwr = dev->rate_power.ofdm[rate->idx & 0x7]; 107 max_txpwr = dev->mt76.rate_power.ofdm[rate->idx & 0x7];
108 } 108 }
109 } 109 }
110 110
@@ -112,10 +112,8 @@ s8 mt76x02_tx_get_max_txpwr_adj(struct mt76_dev *dev,
112} 112}
113EXPORT_SYMBOL_GPL(mt76x02_tx_get_max_txpwr_adj); 113EXPORT_SYMBOL_GPL(mt76x02_tx_get_max_txpwr_adj);
114 114
115s8 mt76x02_tx_get_txpwr_adj(struct mt76_dev *mdev, s8 txpwr, s8 max_txpwr_adj) 115s8 mt76x02_tx_get_txpwr_adj(struct mt76x02_dev *dev, s8 txpwr, s8 max_txpwr_adj)
116{ 116{
117 struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);
118
119 txpwr = min_t(s8, txpwr, dev->mt76.txpower_conf); 117 txpwr = min_t(s8, txpwr, dev->mt76.txpower_conf);
120 txpwr -= (dev->target_power + dev->target_power_delta[0]); 118 txpwr -= (dev->target_power + dev->target_power_delta[0]);
121 txpwr = min_t(s8, txpwr, max_txpwr_adj); 119 txpwr = min_t(s8, txpwr, max_txpwr_adj);
@@ -133,7 +131,7 @@ void mt76x02_tx_set_txpwr_auto(struct mt76x02_dev *dev, s8 txpwr)
133{ 131{
134 s8 txpwr_adj; 132 s8 txpwr_adj;
135 133
136 txpwr_adj = mt76x02_tx_get_txpwr_adj(&dev->mt76, txpwr, 134 txpwr_adj = mt76x02_tx_get_txpwr_adj(dev, txpwr,
137 dev->mt76.rate_power.ofdm[4]); 135 dev->mt76.rate_power.ofdm[4]);
138 mt76_rmw_field(dev, MT_PROT_AUTO_TX_CFG, 136 mt76_rmw_field(dev, MT_PROT_AUTO_TX_CFG,
139 MT_PROT_AUTO_TX_CFG_PROT_PADJ, txpwr_adj); 137 MT_PROT_AUTO_TX_CFG_PROT_PADJ, txpwr_adj);
@@ -157,8 +155,9 @@ void mt76x02_tx_complete(struct mt76_dev *dev, struct sk_buff *skb)
157} 155}
158EXPORT_SYMBOL_GPL(mt76x02_tx_complete); 156EXPORT_SYMBOL_GPL(mt76x02_tx_complete);
159 157
160bool mt76x02_tx_status_data(struct mt76_dev *dev, u8 *update) 158bool mt76x02_tx_status_data(struct mt76_dev *mdev, u8 *update)
161{ 159{
160 struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);
162 struct mt76x02_tx_status stat; 161 struct mt76x02_tx_status stat;
163 162
164 if (!mt76x02_mac_load_tx_status(dev, &stat)) 163 if (!mt76x02_mac_load_tx_status(dev, &stat))
@@ -181,9 +180,9 @@ int mt76x02_tx_prepare_skb(struct mt76_dev *mdev, void *txwi,
181 int ret; 180 int ret;
182 181
183 if (q == &dev->mt76.q_tx[MT_TXQ_PSD] && wcid && wcid->idx < 128) 182 if (q == &dev->mt76.q_tx[MT_TXQ_PSD] && wcid && wcid->idx < 128)
184 mt76x02_mac_wcid_set_drop(&dev->mt76, wcid->idx, false); 183 mt76x02_mac_wcid_set_drop(dev, wcid->idx, false);
185 184
186 mt76x02_mac_write_txwi(mdev, txwi, skb, wcid, sta, skb->len); 185 mt76x02_mac_write_txwi(dev, txwi, skb, wcid, sta, skb->len);
187 186
188 ret = mt76x02_insert_hdr_pad(skb); 187 ret = mt76x02_insert_hdr_pad(skb);
189 if (ret < 0) 188 if (ret < 0)
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x02_usb.h b/drivers/net/wireless/mediatek/mt76/mt76x02_usb.h
index 6b2138328eb2..0126e51d77ed 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x02_usb.h
+++ b/drivers/net/wireless/mediatek/mt76/mt76x02_usb.h
@@ -17,15 +17,15 @@
17#ifndef __MT76x02_USB_H 17#ifndef __MT76x02_USB_H
18#define __MT76x02_USB_H 18#define __MT76x02_USB_H
19 19
20#include "mt76.h" 20#include "mt76x02.h"
21 21
22void mt76x02u_init_mcu(struct mt76_dev *dev); 22void mt76x02u_init_mcu(struct mt76_dev *dev);
23void mt76x02u_mcu_fw_reset(struct mt76_dev *dev); 23void mt76x02u_mcu_fw_reset(struct mt76x02_dev *dev);
24int mt76x02u_mcu_fw_send_data(struct mt76_dev *dev, const void *data, 24int mt76x02u_mcu_fw_send_data(struct mt76x02_dev *dev, const void *data,
25 int data_len, u32 max_payload, u32 offset); 25 int data_len, u32 max_payload, u32 offset);
26 26
27int mt76x02u_skb_dma_info(struct sk_buff *skb, int port, u32 flags); 27int mt76x02u_skb_dma_info(struct sk_buff *skb, int port, u32 flags);
28int mt76x02u_tx_prepare_skb(struct mt76_dev *dev, void *data, 28int mt76x02u_tx_prepare_skb(struct mt76_dev *mdev, void *data,
29 struct sk_buff *skb, struct mt76_queue *q, 29 struct sk_buff *skb, struct mt76_queue *q,
30 struct mt76_wcid *wcid, struct ieee80211_sta *sta, 30 struct mt76_wcid *wcid, struct ieee80211_sta *sta,
31 u32 *tx_info); 31 u32 *tx_info);
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x02_usb_core.c b/drivers/net/wireless/mediatek/mt76/mt76x02_usb_core.c
index 7c6c973af386..dc2226c722dd 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x02_usb_core.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x02_usb_core.c
@@ -34,17 +34,6 @@ void mt76x02u_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue *q,
34} 34}
35EXPORT_SYMBOL_GPL(mt76x02u_tx_complete_skb); 35EXPORT_SYMBOL_GPL(mt76x02u_tx_complete_skb);
36 36
37static int mt76x02u_check_skb_rooms(struct sk_buff *skb)
38{
39 int hdr_len = ieee80211_get_hdrlen_from_skb(skb);
40 u32 need_head;
41
42 need_head = sizeof(struct mt76x02_txwi) + MT_DMA_HDR_LEN;
43 if (hdr_len % 4)
44 need_head += 2;
45 return skb_cow(skb, need_head);
46}
47
48int mt76x02u_skb_dma_info(struct sk_buff *skb, int port, u32 flags) 37int mt76x02u_skb_dma_info(struct sk_buff *skb, int port, u32 flags)
49{ 38{
50 struct sk_buff *iter, *last = skb; 39 struct sk_buff *iter, *last = skb;
@@ -99,17 +88,14 @@ mt76x02u_set_txinfo(struct sk_buff *skb, struct mt76_wcid *wcid, u8 ep)
99 return mt76x02u_skb_dma_info(skb, WLAN_PORT, flags); 88 return mt76x02u_skb_dma_info(skb, WLAN_PORT, flags);
100} 89}
101 90
102int mt76x02u_tx_prepare_skb(struct mt76_dev *dev, void *data, 91int mt76x02u_tx_prepare_skb(struct mt76_dev *mdev, void *data,
103 struct sk_buff *skb, struct mt76_queue *q, 92 struct sk_buff *skb, struct mt76_queue *q,
104 struct mt76_wcid *wcid, struct ieee80211_sta *sta, 93 struct mt76_wcid *wcid, struct ieee80211_sta *sta,
105 u32 *tx_info) 94 u32 *tx_info)
106{ 95{
96 struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);
107 struct mt76x02_txwi *txwi; 97 struct mt76x02_txwi *txwi;
108 int err, len = skb->len; 98 int len = skb->len;
109
110 err = mt76x02u_check_skb_rooms(skb);
111 if (err < 0)
112 return -ENOMEM;
113 99
114 mt76x02_insert_hdr_pad(skb); 100 mt76x02_insert_hdr_pad(skb);
115 101
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x02_usb_mcu.c b/drivers/net/wireless/mediatek/mt76/mt76x02_usb_mcu.c
index cb5f073f08af..da299b8a1334 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x02_usb_mcu.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x02_usb_mcu.c
@@ -17,8 +17,7 @@
17#include <linux/module.h> 17#include <linux/module.h>
18#include <linux/firmware.h> 18#include <linux/firmware.h>
19 19
20#include "mt76.h" 20#include "mt76x02.h"
21#include "mt76x02_dma.h"
22#include "mt76x02_mcu.h" 21#include "mt76x02_mcu.h"
23#include "mt76x02_usb.h" 22#include "mt76x02_usb.h"
24 23
@@ -255,16 +254,16 @@ mt76x02u_mcu_rd_rp(struct mt76_dev *dev, u32 base,
255 return ret; 254 return ret;
256} 255}
257 256
258void mt76x02u_mcu_fw_reset(struct mt76_dev *dev) 257void mt76x02u_mcu_fw_reset(struct mt76x02_dev *dev)
259{ 258{
260 mt76u_vendor_request(dev, MT_VEND_DEV_MODE, 259 mt76u_vendor_request(&dev->mt76, MT_VEND_DEV_MODE,
261 USB_DIR_OUT | USB_TYPE_VENDOR, 260 USB_DIR_OUT | USB_TYPE_VENDOR,
262 0x1, 0, NULL, 0); 261 0x1, 0, NULL, 0);
263} 262}
264EXPORT_SYMBOL_GPL(mt76x02u_mcu_fw_reset); 263EXPORT_SYMBOL_GPL(mt76x02u_mcu_fw_reset);
265 264
266static int 265static int
267__mt76x02u_mcu_fw_send_data(struct mt76_dev *dev, struct mt76u_buf *buf, 266__mt76x02u_mcu_fw_send_data(struct mt76x02_dev *dev, struct mt76u_buf *buf,
268 const void *fw_data, int len, u32 dst_addr) 267 const void *fw_data, int len, u32 dst_addr)
269{ 268{
270 u8 *data = sg_virt(&buf->urb->sg[0]); 269 u8 *data = sg_virt(&buf->urb->sg[0]);
@@ -281,14 +280,14 @@ __mt76x02u_mcu_fw_send_data(struct mt76_dev *dev, struct mt76u_buf *buf,
281 memcpy(data + sizeof(info), fw_data, len); 280 memcpy(data + sizeof(info), fw_data, len);
282 memset(data + sizeof(info) + len, 0, 4); 281 memset(data + sizeof(info) + len, 0, 4);
283 282
284 mt76u_single_wr(dev, MT_VEND_WRITE_FCE, 283 mt76u_single_wr(&dev->mt76, MT_VEND_WRITE_FCE,
285 MT_FCE_DMA_ADDR, dst_addr); 284 MT_FCE_DMA_ADDR, dst_addr);
286 len = roundup(len, 4); 285 len = roundup(len, 4);
287 mt76u_single_wr(dev, MT_VEND_WRITE_FCE, 286 mt76u_single_wr(&dev->mt76, MT_VEND_WRITE_FCE,
288 MT_FCE_DMA_LEN, len << 16); 287 MT_FCE_DMA_LEN, len << 16);
289 288
290 buf->len = MT_CMD_HDR_LEN + len + sizeof(info); 289 buf->len = MT_CMD_HDR_LEN + len + sizeof(info);
291 err = mt76u_submit_buf(dev, USB_DIR_OUT, 290 err = mt76u_submit_buf(&dev->mt76, USB_DIR_OUT,
292 MT_EP_OUT_INBAND_CMD, 291 MT_EP_OUT_INBAND_CMD,
293 buf, GFP_KERNEL, 292 buf, GFP_KERNEL,
294 mt76u_mcu_complete_urb, &cmpl); 293 mt76u_mcu_complete_urb, &cmpl);
@@ -297,31 +296,31 @@ __mt76x02u_mcu_fw_send_data(struct mt76_dev *dev, struct mt76u_buf *buf,
297 296
298 if (!wait_for_completion_timeout(&cmpl, 297 if (!wait_for_completion_timeout(&cmpl,
299 msecs_to_jiffies(1000))) { 298 msecs_to_jiffies(1000))) {
300 dev_err(dev->dev, "firmware upload timed out\n"); 299 dev_err(dev->mt76.dev, "firmware upload timed out\n");
301 usb_kill_urb(buf->urb); 300 usb_kill_urb(buf->urb);
302 return -ETIMEDOUT; 301 return -ETIMEDOUT;
303 } 302 }
304 303
305 if (mt76u_urb_error(buf->urb)) { 304 if (mt76u_urb_error(buf->urb)) {
306 dev_err(dev->dev, "firmware upload failed: %d\n", 305 dev_err(dev->mt76.dev, "firmware upload failed: %d\n",
307 buf->urb->status); 306 buf->urb->status);
308 return buf->urb->status; 307 return buf->urb->status;
309 } 308 }
310 309
311 val = mt76u_rr(dev, MT_TX_CPU_FROM_FCE_CPU_DESC_IDX); 310 val = mt76_rr(dev, MT_TX_CPU_FROM_FCE_CPU_DESC_IDX);
312 val++; 311 val++;
313 mt76u_wr(dev, MT_TX_CPU_FROM_FCE_CPU_DESC_IDX, val); 312 mt76_wr(dev, MT_TX_CPU_FROM_FCE_CPU_DESC_IDX, val);
314 313
315 return 0; 314 return 0;
316} 315}
317 316
318int mt76x02u_mcu_fw_send_data(struct mt76_dev *dev, const void *data, 317int mt76x02u_mcu_fw_send_data(struct mt76x02_dev *dev, const void *data,
319 int data_len, u32 max_payload, u32 offset) 318 int data_len, u32 max_payload, u32 offset)
320{ 319{
321 int err, len, pos = 0, max_len = max_payload - 8; 320 int err, len, pos = 0, max_len = max_payload - 8;
322 struct mt76u_buf buf; 321 struct mt76u_buf buf;
323 322
324 err = mt76u_buf_alloc(dev, &buf, 1, max_payload, max_payload, 323 err = mt76u_buf_alloc(&dev->mt76, &buf, 1, max_payload, max_payload,
325 GFP_KERNEL); 324 GFP_KERNEL);
326 if (err < 0) 325 if (err < 0)
327 return err; 326 return err;
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x02_util.c b/drivers/net/wireless/mediatek/mt76/mt76x02_util.c
index 5851ab6b7e26..ca05332f81fc 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x02_util.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x02_util.c
@@ -48,21 +48,21 @@ struct ieee80211_rate mt76x02_rates[] = {
48EXPORT_SYMBOL_GPL(mt76x02_rates); 48EXPORT_SYMBOL_GPL(mt76x02_rates);
49 49
50void mt76x02_configure_filter(struct ieee80211_hw *hw, 50void mt76x02_configure_filter(struct ieee80211_hw *hw,
51 unsigned int changed_flags, 51 unsigned int changed_flags,
52 unsigned int *total_flags, u64 multicast) 52 unsigned int *total_flags, u64 multicast)
53{ 53{
54 struct mt76_dev *dev = hw->priv; 54 struct mt76x02_dev *dev = hw->priv;
55 u32 flags = 0; 55 u32 flags = 0;
56 56
57#define MT76_FILTER(_flag, _hw) do { \ 57#define MT76_FILTER(_flag, _hw) do { \
58 flags |= *total_flags & FIF_##_flag; \ 58 flags |= *total_flags & FIF_##_flag; \
59 dev->rxfilter &= ~(_hw); \ 59 dev->mt76.rxfilter &= ~(_hw); \
60 dev->rxfilter |= !(flags & FIF_##_flag) * (_hw); \ 60 dev->mt76.rxfilter |= !(flags & FIF_##_flag) * (_hw); \
61 } while (0) 61 } while (0)
62 62
63 mutex_lock(&dev->mutex); 63 mutex_lock(&dev->mt76.mutex);
64 64
65 dev->rxfilter &= ~MT_RX_FILTR_CFG_OTHER_BSS; 65 dev->mt76.rxfilter &= ~MT_RX_FILTR_CFG_OTHER_BSS;
66 66
67 MT76_FILTER(FCSFAIL, MT_RX_FILTR_CFG_CRC_ERR); 67 MT76_FILTER(FCSFAIL, MT_RX_FILTR_CFG_CRC_ERR);
68 MT76_FILTER(PLCPFAIL, MT_RX_FILTR_CFG_PHY_ERR); 68 MT76_FILTER(PLCPFAIL, MT_RX_FILTR_CFG_PHY_ERR);
@@ -75,25 +75,25 @@ void mt76x02_configure_filter(struct ieee80211_hw *hw,
75 MT76_FILTER(PSPOLL, MT_RX_FILTR_CFG_PSPOLL); 75 MT76_FILTER(PSPOLL, MT_RX_FILTR_CFG_PSPOLL);
76 76
77 *total_flags = flags; 77 *total_flags = flags;
78 dev->bus->wr(dev, MT_RX_FILTR_CFG, dev->rxfilter); 78 mt76_wr(dev, MT_RX_FILTR_CFG, dev->mt76.rxfilter);
79 79
80 mutex_unlock(&dev->mutex); 80 mutex_unlock(&dev->mt76.mutex);
81} 81}
82EXPORT_SYMBOL_GPL(mt76x02_configure_filter); 82EXPORT_SYMBOL_GPL(mt76x02_configure_filter);
83 83
84int mt76x02_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 84int mt76x02_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
85 struct ieee80211_sta *sta) 85 struct ieee80211_sta *sta)
86{ 86{
87 struct mt76_dev *dev = hw->priv; 87 struct mt76x02_dev *dev = hw->priv;
88 struct mt76x02_sta *msta = (struct mt76x02_sta *) sta->drv_priv; 88 struct mt76x02_sta *msta = (struct mt76x02_sta *)sta->drv_priv;
89 struct mt76x02_vif *mvif = (struct mt76x02_vif *) vif->drv_priv; 89 struct mt76x02_vif *mvif = (struct mt76x02_vif *)vif->drv_priv;
90 int ret = 0; 90 int ret = 0;
91 int idx = 0; 91 int idx = 0;
92 int i; 92 int i;
93 93
94 mutex_lock(&dev->mutex); 94 mutex_lock(&dev->mt76.mutex);
95 95
96 idx = mt76_wcid_alloc(dev->wcid_mask, ARRAY_SIZE(dev->wcid)); 96 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, ARRAY_SIZE(dev->mt76.wcid));
97 if (idx < 0) { 97 if (idx < 0) {
98 ret = -ENOSPC; 98 ret = -ENOSPC;
99 goto out; 99 goto out;
@@ -113,40 +113,40 @@ int mt76x02_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
113 113
114 ewma_signal_init(&msta->rssi); 114 ewma_signal_init(&msta->rssi);
115 115
116 rcu_assign_pointer(dev->wcid[idx], &msta->wcid); 116 rcu_assign_pointer(dev->mt76.wcid[idx], &msta->wcid);
117 117
118out: 118out:
119 mutex_unlock(&dev->mutex); 119 mutex_unlock(&dev->mt76.mutex);
120 120
121 return ret; 121 return ret;
122} 122}
123EXPORT_SYMBOL_GPL(mt76x02_sta_add); 123EXPORT_SYMBOL_GPL(mt76x02_sta_add);
124 124
125int mt76x02_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 125int mt76x02_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
126 struct ieee80211_sta *sta) 126 struct ieee80211_sta *sta)
127{ 127{
128 struct mt76_dev *dev = hw->priv; 128 struct mt76x02_dev *dev = hw->priv;
129 struct mt76x02_sta *msta = (struct mt76x02_sta *) sta->drv_priv; 129 struct mt76x02_sta *msta = (struct mt76x02_sta *)sta->drv_priv;
130 int idx = msta->wcid.idx; 130 int idx = msta->wcid.idx;
131 int i; 131 int i;
132 132
133 mutex_lock(&dev->mutex); 133 mutex_lock(&dev->mt76.mutex);
134 rcu_assign_pointer(dev->wcid[idx], NULL); 134 rcu_assign_pointer(dev->mt76.wcid[idx], NULL);
135 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 135 for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
136 mt76_txq_remove(dev, sta->txq[i]); 136 mt76_txq_remove(&dev->mt76, sta->txq[i]);
137 mt76x02_mac_wcid_set_drop(dev, idx, true); 137 mt76x02_mac_wcid_set_drop(dev, idx, true);
138 mt76_wcid_free(dev->wcid_mask, idx); 138 mt76_wcid_free(dev->mt76.wcid_mask, idx);
139 mt76x02_mac_wcid_setup(dev, idx, 0, NULL); 139 mt76x02_mac_wcid_setup(dev, idx, 0, NULL);
140 mutex_unlock(&dev->mutex); 140 mutex_unlock(&dev->mt76.mutex);
141 141
142 return 0; 142 return 0;
143} 143}
144EXPORT_SYMBOL_GPL(mt76x02_sta_remove); 144EXPORT_SYMBOL_GPL(mt76x02_sta_remove);
145 145
146void mt76x02_vif_init(struct mt76_dev *dev, struct ieee80211_vif *vif, 146void mt76x02_vif_init(struct mt76x02_dev *dev, struct ieee80211_vif *vif,
147 unsigned int idx) 147 unsigned int idx)
148{ 148{
149 struct mt76x02_vif *mvif = (struct mt76x02_vif *) vif->drv_priv; 149 struct mt76x02_vif *mvif = (struct mt76x02_vif *)vif->drv_priv;
150 150
151 mvif->idx = idx; 151 mvif->idx = idx;
152 mvif->group_wcid.idx = MT_VIF_WCID(idx); 152 mvif->group_wcid.idx = MT_VIF_WCID(idx);
@@ -158,11 +158,11 @@ EXPORT_SYMBOL_GPL(mt76x02_vif_init);
158int 158int
159mt76x02_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 159mt76x02_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
160{ 160{
161 struct mt76_dev *dev = hw->priv; 161 struct mt76x02_dev *dev = hw->priv;
162 unsigned int idx = 0; 162 unsigned int idx = 0;
163 163
164 if (vif->addr[0] & BIT(1)) 164 if (vif->addr[0] & BIT(1))
165 idx = 1 + (((dev->macaddr[0] ^ vif->addr[0]) >> 2) & 7); 165 idx = 1 + (((dev->mt76.macaddr[0] ^ vif->addr[0]) >> 2) & 7);
166 166
167 /* 167 /*
168 * Client mode typically only has one configurable BSSID register, 168 * Client mode typically only has one configurable BSSID register,
@@ -186,20 +186,20 @@ mt76x02_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
186EXPORT_SYMBOL_GPL(mt76x02_add_interface); 186EXPORT_SYMBOL_GPL(mt76x02_add_interface);
187 187
188void mt76x02_remove_interface(struct ieee80211_hw *hw, 188void mt76x02_remove_interface(struct ieee80211_hw *hw,
189 struct ieee80211_vif *vif) 189 struct ieee80211_vif *vif)
190{ 190{
191 struct mt76_dev *dev = hw->priv; 191 struct mt76x02_dev *dev = hw->priv;
192 192
193 mt76_txq_remove(dev, vif->txq); 193 mt76_txq_remove(&dev->mt76, vif->txq);
194} 194}
195EXPORT_SYMBOL_GPL(mt76x02_remove_interface); 195EXPORT_SYMBOL_GPL(mt76x02_remove_interface);
196 196
197int mt76x02_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 197int mt76x02_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
198 struct ieee80211_ampdu_params *params) 198 struct ieee80211_ampdu_params *params)
199{ 199{
200 enum ieee80211_ampdu_mlme_action action = params->action; 200 enum ieee80211_ampdu_mlme_action action = params->action;
201 struct ieee80211_sta *sta = params->sta; 201 struct ieee80211_sta *sta = params->sta;
202 struct mt76_dev *dev = hw->priv; 202 struct mt76x02_dev *dev = hw->priv;
203 struct mt76x02_sta *msta = (struct mt76x02_sta *) sta->drv_priv; 203 struct mt76x02_sta *msta = (struct mt76x02_sta *) sta->drv_priv;
204 struct ieee80211_txq *txq = sta->txq[params->tid]; 204 struct ieee80211_txq *txq = sta->txq[params->tid];
205 u16 tid = params->tid; 205 u16 tid = params->tid;
@@ -213,12 +213,14 @@ int mt76x02_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
213 213
214 switch (action) { 214 switch (action) {
215 case IEEE80211_AMPDU_RX_START: 215 case IEEE80211_AMPDU_RX_START:
216 mt76_rx_aggr_start(dev, &msta->wcid, tid, *ssn, params->buf_size); 216 mt76_rx_aggr_start(&dev->mt76, &msta->wcid, tid,
217 __mt76_set(dev, MT_WCID_ADDR(msta->wcid.idx) + 4, BIT(16 + tid)); 217 *ssn, params->buf_size);
218 mt76_set(dev, MT_WCID_ADDR(msta->wcid.idx) + 4, BIT(16 + tid));
218 break; 219 break;
219 case IEEE80211_AMPDU_RX_STOP: 220 case IEEE80211_AMPDU_RX_STOP:
220 mt76_rx_aggr_stop(dev, &msta->wcid, tid); 221 mt76_rx_aggr_stop(&dev->mt76, &msta->wcid, tid);
221 __mt76_clear(dev, MT_WCID_ADDR(msta->wcid.idx) + 4, BIT(16 + tid)); 222 mt76_clear(dev, MT_WCID_ADDR(msta->wcid.idx) + 4,
223 BIT(16 + tid));
222 break; 224 break;
223 case IEEE80211_AMPDU_TX_OPERATIONAL: 225 case IEEE80211_AMPDU_TX_OPERATIONAL:
224 mtxq->aggr = true; 226 mtxq->aggr = true;
@@ -245,11 +247,11 @@ int mt76x02_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
245EXPORT_SYMBOL_GPL(mt76x02_ampdu_action); 247EXPORT_SYMBOL_GPL(mt76x02_ampdu_action);
246 248
247int mt76x02_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 249int mt76x02_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
248 struct ieee80211_vif *vif, struct ieee80211_sta *sta, 250 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
249 struct ieee80211_key_conf *key) 251 struct ieee80211_key_conf *key)
250{ 252{
251 struct mt76_dev *dev = hw->priv; 253 struct mt76x02_dev *dev = hw->priv;
252 struct mt76x02_vif *mvif = (struct mt76x02_vif *) vif->drv_priv; 254 struct mt76x02_vif *mvif = (struct mt76x02_vif *)vif->drv_priv;
253 struct mt76x02_sta *msta; 255 struct mt76x02_sta *msta;
254 struct mt76_wcid *wcid; 256 struct mt76_wcid *wcid;
255 int idx = key->keyidx; 257 int idx = key->keyidx;
@@ -295,7 +297,7 @@ int mt76x02_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
295 297
296 key = NULL; 298 key = NULL;
297 } 299 }
298 mt76_wcid_key_setup(dev, wcid, key); 300 mt76_wcid_key_setup(&dev->mt76, wcid, key);
299 301
300 if (!msta) { 302 if (!msta) {
301 if (key || wcid->hw_key_idx == idx) { 303 if (key || wcid->hw_key_idx == idx) {
@@ -312,13 +314,13 @@ int mt76x02_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
312EXPORT_SYMBOL_GPL(mt76x02_set_key); 314EXPORT_SYMBOL_GPL(mt76x02_set_key);
313 315
314int mt76x02_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 316int mt76x02_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
315 u16 queue, const struct ieee80211_tx_queue_params *params) 317 u16 queue, const struct ieee80211_tx_queue_params *params)
316{ 318{
317 struct mt76_dev *dev = hw->priv; 319 struct mt76x02_dev *dev = hw->priv;
318 u8 cw_min = 5, cw_max = 10, qid; 320 u8 cw_min = 5, cw_max = 10, qid;
319 u32 val; 321 u32 val;
320 322
321 qid = dev->q_tx[queue].hw_idx; 323 qid = dev->mt76.q_tx[queue].hw_idx;
322 324
323 if (params->cw_min) 325 if (params->cw_min)
324 cw_min = fls(params->cw_min); 326 cw_min = fls(params->cw_min);
@@ -329,27 +331,27 @@ int mt76x02_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
329 FIELD_PREP(MT_EDCA_CFG_AIFSN, params->aifs) | 331 FIELD_PREP(MT_EDCA_CFG_AIFSN, params->aifs) |
330 FIELD_PREP(MT_EDCA_CFG_CWMIN, cw_min) | 332 FIELD_PREP(MT_EDCA_CFG_CWMIN, cw_min) |
331 FIELD_PREP(MT_EDCA_CFG_CWMAX, cw_max); 333 FIELD_PREP(MT_EDCA_CFG_CWMAX, cw_max);
332 __mt76_wr(dev, MT_EDCA_CFG_AC(qid), val); 334 mt76_wr(dev, MT_EDCA_CFG_AC(qid), val);
333 335
334 val = __mt76_rr(dev, MT_WMM_TXOP(qid)); 336 val = mt76_rr(dev, MT_WMM_TXOP(qid));
335 val &= ~(MT_WMM_TXOP_MASK << MT_WMM_TXOP_SHIFT(qid)); 337 val &= ~(MT_WMM_TXOP_MASK << MT_WMM_TXOP_SHIFT(qid));
336 val |= params->txop << MT_WMM_TXOP_SHIFT(qid); 338 val |= params->txop << MT_WMM_TXOP_SHIFT(qid);
337 __mt76_wr(dev, MT_WMM_TXOP(qid), val); 339 mt76_wr(dev, MT_WMM_TXOP(qid), val);
338 340
339 val = __mt76_rr(dev, MT_WMM_AIFSN); 341 val = mt76_rr(dev, MT_WMM_AIFSN);
340 val &= ~(MT_WMM_AIFSN_MASK << MT_WMM_AIFSN_SHIFT(qid)); 342 val &= ~(MT_WMM_AIFSN_MASK << MT_WMM_AIFSN_SHIFT(qid));
341 val |= params->aifs << MT_WMM_AIFSN_SHIFT(qid); 343 val |= params->aifs << MT_WMM_AIFSN_SHIFT(qid);
342 __mt76_wr(dev, MT_WMM_AIFSN, val); 344 mt76_wr(dev, MT_WMM_AIFSN, val);
343 345
344 val = __mt76_rr(dev, MT_WMM_CWMIN); 346 val = mt76_rr(dev, MT_WMM_CWMIN);
345 val &= ~(MT_WMM_CWMIN_MASK << MT_WMM_CWMIN_SHIFT(qid)); 347 val &= ~(MT_WMM_CWMIN_MASK << MT_WMM_CWMIN_SHIFT(qid));
346 val |= cw_min << MT_WMM_CWMIN_SHIFT(qid); 348 val |= cw_min << MT_WMM_CWMIN_SHIFT(qid);
347 __mt76_wr(dev, MT_WMM_CWMIN, val); 349 mt76_wr(dev, MT_WMM_CWMIN, val);
348 350
349 val = __mt76_rr(dev, MT_WMM_CWMAX); 351 val = mt76_rr(dev, MT_WMM_CWMAX);
350 val &= ~(MT_WMM_CWMAX_MASK << MT_WMM_CWMAX_SHIFT(qid)); 352 val &= ~(MT_WMM_CWMAX_MASK << MT_WMM_CWMAX_SHIFT(qid));
351 val |= cw_max << MT_WMM_CWMAX_SHIFT(qid); 353 val |= cw_max << MT_WMM_CWMAX_SHIFT(qid);
352 __mt76_wr(dev, MT_WMM_CWMAX, val); 354 mt76_wr(dev, MT_WMM_CWMAX, val);
353 355
354 return 0; 356 return 0;
355} 357}
@@ -359,7 +361,7 @@ void mt76x02_sta_rate_tbl_update(struct ieee80211_hw *hw,
359 struct ieee80211_vif *vif, 361 struct ieee80211_vif *vif,
360 struct ieee80211_sta *sta) 362 struct ieee80211_sta *sta)
361{ 363{
362 struct mt76_dev *dev = hw->priv; 364 struct mt76x02_dev *dev = hw->priv;
363 struct mt76x02_sta *msta = (struct mt76x02_sta *) sta->drv_priv; 365 struct mt76x02_sta *msta = (struct mt76x02_sta *) sta->drv_priv;
364 struct ieee80211_sta_rates *rates = rcu_dereference(sta->rates); 366 struct ieee80211_sta_rates *rates = rcu_dereference(sta->rates);
365 struct ieee80211_tx_rate rate = {}; 367 struct ieee80211_tx_rate rate = {};
@@ -425,7 +427,7 @@ const u16 mt76x02_beacon_offsets[16] = {
425}; 427};
426EXPORT_SYMBOL_GPL(mt76x02_beacon_offsets); 428EXPORT_SYMBOL_GPL(mt76x02_beacon_offsets);
427 429
428void mt76x02_set_beacon_offsets(struct mt76_dev *dev) 430void mt76x02_set_beacon_offsets(struct mt76x02_dev *dev)
429{ 431{
430 u16 val, base = MT_BEACON_BASE; 432 u16 val, base = MT_BEACON_BASE;
431 u32 regs[4] = {}; 433 u32 regs[4] = {};
@@ -437,7 +439,7 @@ void mt76x02_set_beacon_offsets(struct mt76_dev *dev)
437 } 439 }
438 440
439 for (i = 0; i < 4; i++) 441 for (i = 0; i < 4; i++)
440 __mt76_wr(dev, MT_BCN_OFFSET(i), regs[i]); 442 mt76_wr(dev, MT_BCN_OFFSET(i), regs[i]);
441} 443}
442EXPORT_SYMBOL_GPL(mt76x02_set_beacon_offsets); 444EXPORT_SYMBOL_GPL(mt76x02_set_beacon_offsets);
443 445
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c b/drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c
index bbab021b5f1a..f39b622d03f4 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.c
@@ -177,8 +177,8 @@ mt76x2_eeprom_load(struct mt76x02_dev *dev)
177 177
178 efuse = dev->mt76.otp.data; 178 efuse = dev->mt76.otp.data;
179 179
180 if (mt76x02_get_efuse_data(&dev->mt76, 0, efuse, 180 if (mt76x02_get_efuse_data(dev, 0, efuse, MT7662_EEPROM_SIZE,
181 MT7662_EEPROM_SIZE, MT_EE_READ)) 181 MT_EE_READ))
182 goto out; 182 goto out;
183 183
184 if (found) { 184 if (found) {
@@ -248,22 +248,22 @@ mt76x2_get_5g_rx_gain(struct mt76x02_dev *dev, u8 channel)
248 group = mt76x2_get_cal_channel_group(channel); 248 group = mt76x2_get_cal_channel_group(channel);
249 switch (group) { 249 switch (group) {
250 case MT_CH_5G_JAPAN: 250 case MT_CH_5G_JAPAN:
251 return mt76x02_eeprom_get(&dev->mt76, 251 return mt76x02_eeprom_get(dev,
252 MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN); 252 MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN);
253 case MT_CH_5G_UNII_1: 253 case MT_CH_5G_UNII_1:
254 return mt76x02_eeprom_get(&dev->mt76, 254 return mt76x02_eeprom_get(dev,
255 MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN) >> 8; 255 MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN) >> 8;
256 case MT_CH_5G_UNII_2: 256 case MT_CH_5G_UNII_2:
257 return mt76x02_eeprom_get(&dev->mt76, 257 return mt76x02_eeprom_get(dev,
258 MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN); 258 MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN);
259 case MT_CH_5G_UNII_2E_1: 259 case MT_CH_5G_UNII_2E_1:
260 return mt76x02_eeprom_get(&dev->mt76, 260 return mt76x02_eeprom_get(dev,
261 MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN) >> 8; 261 MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN) >> 8;
262 case MT_CH_5G_UNII_2E_2: 262 case MT_CH_5G_UNII_2E_2:
263 return mt76x02_eeprom_get(&dev->mt76, 263 return mt76x02_eeprom_get(dev,
264 MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN); 264 MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN);
265 default: 265 default:
266 return mt76x02_eeprom_get(&dev->mt76, 266 return mt76x02_eeprom_get(dev,
267 MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN) >> 8; 267 MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN) >> 8;
268 } 268 }
269} 269}
@@ -277,14 +277,13 @@ void mt76x2_read_rx_gain(struct mt76x02_dev *dev)
277 u16 val; 277 u16 val;
278 278
279 if (chan->band == NL80211_BAND_2GHZ) 279 if (chan->band == NL80211_BAND_2GHZ)
280 val = mt76x02_eeprom_get(&dev->mt76, 280 val = mt76x02_eeprom_get(dev, MT_EE_RF_2G_RX_HIGH_GAIN) >> 8;
281 MT_EE_RF_2G_RX_HIGH_GAIN) >> 8;
282 else 281 else
283 val = mt76x2_get_5g_rx_gain(dev, channel); 282 val = mt76x2_get_5g_rx_gain(dev, channel);
284 283
285 mt76x2_set_rx_gain_group(dev, val); 284 mt76x2_set_rx_gain_group(dev, val);
286 285
287 mt76x02_get_rx_gain(&dev->mt76, chan->band, &val, &lna_2g, lna_5g); 286 mt76x02_get_rx_gain(dev, chan->band, &val, &lna_2g, lna_5g);
288 mt76x2_set_rssi_offset(dev, 0, val); 287 mt76x2_set_rssi_offset(dev, 0, val);
289 mt76x2_set_rssi_offset(dev, 1, val >> 8); 288 mt76x2_set_rssi_offset(dev, 1, val >> 8);
290 289
@@ -293,7 +292,7 @@ void mt76x2_read_rx_gain(struct mt76x02_dev *dev)
293 dev->cal.rx.mcu_gain |= (lna_5g[1] & 0xff) << 16; 292 dev->cal.rx.mcu_gain |= (lna_5g[1] & 0xff) << 16;
294 dev->cal.rx.mcu_gain |= (lna_5g[2] & 0xff) << 24; 293 dev->cal.rx.mcu_gain |= (lna_5g[2] & 0xff) << 24;
295 294
296 lna = mt76x02_get_lna_gain(&dev->mt76, &lna_2g, lna_5g, chan); 295 lna = mt76x02_get_lna_gain(dev, &lna_2g, lna_5g, chan);
297 dev->cal.rx.lna_gain = mt76x02_sign_extend(lna, 8); 296 dev->cal.rx.lna_gain = mt76x02_sign_extend(lna, 8);
298} 297}
299EXPORT_SYMBOL_GPL(mt76x2_read_rx_gain); 298EXPORT_SYMBOL_GPL(mt76x2_read_rx_gain);
@@ -308,53 +307,49 @@ void mt76x2_get_rate_power(struct mt76x02_dev *dev, struct mt76_rate_power *t,
308 307
309 memset(t, 0, sizeof(*t)); 308 memset(t, 0, sizeof(*t));
310 309
311 val = mt76x02_eeprom_get(&dev->mt76, MT_EE_TX_POWER_CCK); 310 val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_CCK);
312 t->cck[0] = t->cck[1] = mt76x02_rate_power_val(val); 311 t->cck[0] = t->cck[1] = mt76x02_rate_power_val(val);
313 t->cck[2] = t->cck[3] = mt76x02_rate_power_val(val >> 8); 312 t->cck[2] = t->cck[3] = mt76x02_rate_power_val(val >> 8);
314 313
315 if (is_5ghz) 314 if (is_5ghz)
316 val = mt76x02_eeprom_get(&dev->mt76, 315 val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_OFDM_5G_6M);
317 MT_EE_TX_POWER_OFDM_5G_6M);
318 else 316 else
319 val = mt76x02_eeprom_get(&dev->mt76, 317 val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_OFDM_2G_6M);
320 MT_EE_TX_POWER_OFDM_2G_6M);
321 t->ofdm[0] = t->ofdm[1] = mt76x02_rate_power_val(val); 318 t->ofdm[0] = t->ofdm[1] = mt76x02_rate_power_val(val);
322 t->ofdm[2] = t->ofdm[3] = mt76x02_rate_power_val(val >> 8); 319 t->ofdm[2] = t->ofdm[3] = mt76x02_rate_power_val(val >> 8);
323 320
324 if (is_5ghz) 321 if (is_5ghz)
325 val = mt76x02_eeprom_get(&dev->mt76, 322 val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_OFDM_5G_24M);
326 MT_EE_TX_POWER_OFDM_5G_24M);
327 else 323 else
328 val = mt76x02_eeprom_get(&dev->mt76, 324 val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_OFDM_2G_24M);
329 MT_EE_TX_POWER_OFDM_2G_24M);
330 t->ofdm[4] = t->ofdm[5] = mt76x02_rate_power_val(val); 325 t->ofdm[4] = t->ofdm[5] = mt76x02_rate_power_val(val);
331 t->ofdm[6] = t->ofdm[7] = mt76x02_rate_power_val(val >> 8); 326 t->ofdm[6] = t->ofdm[7] = mt76x02_rate_power_val(val >> 8);
332 327
333 val = mt76x02_eeprom_get(&dev->mt76, MT_EE_TX_POWER_HT_MCS0); 328 val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS0);
334 t->ht[0] = t->ht[1] = mt76x02_rate_power_val(val); 329 t->ht[0] = t->ht[1] = mt76x02_rate_power_val(val);
335 t->ht[2] = t->ht[3] = mt76x02_rate_power_val(val >> 8); 330 t->ht[2] = t->ht[3] = mt76x02_rate_power_val(val >> 8);
336 331
337 val = mt76x02_eeprom_get(&dev->mt76, MT_EE_TX_POWER_HT_MCS4); 332 val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS4);
338 t->ht[4] = t->ht[5] = mt76x02_rate_power_val(val); 333 t->ht[4] = t->ht[5] = mt76x02_rate_power_val(val);
339 t->ht[6] = t->ht[7] = mt76x02_rate_power_val(val >> 8); 334 t->ht[6] = t->ht[7] = mt76x02_rate_power_val(val >> 8);
340 335
341 val = mt76x02_eeprom_get(&dev->mt76, MT_EE_TX_POWER_HT_MCS8); 336 val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS8);
342 t->ht[8] = t->ht[9] = mt76x02_rate_power_val(val); 337 t->ht[8] = t->ht[9] = mt76x02_rate_power_val(val);
343 t->ht[10] = t->ht[11] = mt76x02_rate_power_val(val >> 8); 338 t->ht[10] = t->ht[11] = mt76x02_rate_power_val(val >> 8);
344 339
345 val = mt76x02_eeprom_get(&dev->mt76, MT_EE_TX_POWER_HT_MCS12); 340 val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS12);
346 t->ht[12] = t->ht[13] = mt76x02_rate_power_val(val); 341 t->ht[12] = t->ht[13] = mt76x02_rate_power_val(val);
347 t->ht[14] = t->ht[15] = mt76x02_rate_power_val(val >> 8); 342 t->ht[14] = t->ht[15] = mt76x02_rate_power_val(val >> 8);
348 343
349 val = mt76x02_eeprom_get(&dev->mt76, MT_EE_TX_POWER_VHT_MCS0); 344 val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_VHT_MCS0);
350 t->vht[0] = t->vht[1] = mt76x02_rate_power_val(val); 345 t->vht[0] = t->vht[1] = mt76x02_rate_power_val(val);
351 t->vht[2] = t->vht[3] = mt76x02_rate_power_val(val >> 8); 346 t->vht[2] = t->vht[3] = mt76x02_rate_power_val(val >> 8);
352 347
353 val = mt76x02_eeprom_get(&dev->mt76, MT_EE_TX_POWER_VHT_MCS4); 348 val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_VHT_MCS4);
354 t->vht[4] = t->vht[5] = mt76x02_rate_power_val(val); 349 t->vht[4] = t->vht[5] = mt76x02_rate_power_val(val);
355 t->vht[6] = t->vht[7] = mt76x02_rate_power_val(val >> 8); 350 t->vht[6] = t->vht[7] = mt76x02_rate_power_val(val >> 8);
356 351
357 val = mt76x02_eeprom_get(&dev->mt76, MT_EE_TX_POWER_VHT_MCS8); 352 val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_VHT_MCS8);
358 if (!is_5ghz) 353 if (!is_5ghz)
359 val >>= 8; 354 val >>= 8;
360 t->vht[8] = t->vht[9] = mt76x02_rate_power_val(val >> 8); 355 t->vht[8] = t->vht[9] = mt76x02_rate_power_val(val >> 8);
@@ -390,7 +385,7 @@ mt76x2_get_power_info_2g(struct mt76x02_dev *dev,
390 t->chain[chain].target_power = data[2]; 385 t->chain[chain].target_power = data[2];
391 t->chain[chain].delta = mt76x02_sign_extend_optional(data[delta_idx], 7); 386 t->chain[chain].delta = mt76x02_sign_extend_optional(data[delta_idx], 7);
392 387
393 val = mt76x02_eeprom_get(&dev->mt76, MT_EE_RF_2G_TSSI_OFF_TXPOWER); 388 val = mt76x02_eeprom_get(dev, MT_EE_RF_2G_TSSI_OFF_TXPOWER);
394 t->target_power = val >> 8; 389 t->target_power = val >> 8;
395} 390}
396 391
@@ -441,7 +436,7 @@ mt76x2_get_power_info_5g(struct mt76x02_dev *dev,
441 t->chain[chain].target_power = data[2]; 436 t->chain[chain].target_power = data[2];
442 t->chain[chain].delta = mt76x02_sign_extend_optional(data[delta_idx], 7); 437 t->chain[chain].delta = mt76x02_sign_extend_optional(data[delta_idx], 7);
443 438
444 val = mt76x02_eeprom_get(&dev->mt76, MT_EE_RF_2G_RX_HIGH_GAIN); 439 val = mt76x02_eeprom_get(dev, MT_EE_RF_2G_RX_HIGH_GAIN);
445 t->target_power = val & 0xff; 440 t->target_power = val & 0xff;
446} 441}
447 442
@@ -453,8 +448,8 @@ void mt76x2_get_power_info(struct mt76x02_dev *dev,
453 448
454 memset(t, 0, sizeof(*t)); 449 memset(t, 0, sizeof(*t));
455 450
456 bw40 = mt76x02_eeprom_get(&dev->mt76, MT_EE_TX_POWER_DELTA_BW40); 451 bw40 = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_DELTA_BW40);
457 bw80 = mt76x02_eeprom_get(&dev->mt76, MT_EE_TX_POWER_DELTA_BW80); 452 bw80 = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_DELTA_BW80);
458 453
459 if (chan->band == NL80211_BAND_5GHZ) { 454 if (chan->band == NL80211_BAND_5GHZ) {
460 bw40 >>= 8; 455 bw40 >>= 8;
@@ -469,7 +464,7 @@ void mt76x2_get_power_info(struct mt76x02_dev *dev,
469 MT_EE_TX_POWER_1_START_2G); 464 MT_EE_TX_POWER_1_START_2G);
470 } 465 }
471 466
472 if (mt76x02_tssi_enabled(&dev->mt76) || 467 if (mt76x2_tssi_enabled(dev) ||
473 !mt76x02_field_valid(t->target_power)) 468 !mt76x02_field_valid(t->target_power))
474 t->target_power = t->chain[0].target_power; 469 t->target_power = t->chain[0].target_power;
475 470
@@ -486,23 +481,20 @@ int mt76x2_get_temp_comp(struct mt76x02_dev *dev, struct mt76x2_temp_comp *t)
486 481
487 memset(t, 0, sizeof(*t)); 482 memset(t, 0, sizeof(*t));
488 483
489 if (!mt76x02_temp_tx_alc_enabled(&dev->mt76)) 484 if (!mt76x2_temp_tx_alc_enabled(dev))
490 return -EINVAL; 485 return -EINVAL;
491 486
492 if (!mt76x02_ext_pa_enabled(&dev->mt76, band)) 487 if (!mt76x02_ext_pa_enabled(dev, band))
493 return -EINVAL; 488 return -EINVAL;
494 489
495 val = mt76x02_eeprom_get(&dev->mt76, MT_EE_TX_POWER_EXT_PA_5G) >> 8; 490 val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_EXT_PA_5G) >> 8;
496 t->temp_25_ref = val & 0x7f; 491 t->temp_25_ref = val & 0x7f;
497 if (band == NL80211_BAND_5GHZ) { 492 if (band == NL80211_BAND_5GHZ) {
498 slope = mt76x02_eeprom_get(&dev->mt76, 493 slope = mt76x02_eeprom_get(dev, MT_EE_RF_TEMP_COMP_SLOPE_5G);
499 MT_EE_RF_TEMP_COMP_SLOPE_5G); 494 bounds = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_EXT_PA_5G);
500 bounds = mt76x02_eeprom_get(&dev->mt76,
501 MT_EE_TX_POWER_EXT_PA_5G);
502 } else { 495 } else {
503 slope = mt76x02_eeprom_get(&dev->mt76, 496 slope = mt76x02_eeprom_get(dev, MT_EE_RF_TEMP_COMP_SLOPE_2G);
504 MT_EE_RF_TEMP_COMP_SLOPE_2G); 497 bounds = mt76x02_eeprom_get(dev,
505 bounds = mt76x02_eeprom_get(&dev->mt76,
506 MT_EE_TX_POWER_DELTA_BW80) >> 8; 498 MT_EE_TX_POWER_DELTA_BW80) >> 8;
507 } 499 }
508 500
@@ -523,7 +515,7 @@ int mt76x2_eeprom_init(struct mt76x02_dev *dev)
523 if (ret) 515 if (ret)
524 return ret; 516 return ret;
525 517
526 mt76x02_eeprom_parse_hw_cap(&dev->mt76); 518 mt76x02_eeprom_parse_hw_cap(dev);
527 mt76x2_eeprom_get_macaddr(dev); 519 mt76x2_eeprom_get_macaddr(dev);
528 mt76_eeprom_override(&dev->mt76); 520 mt76_eeprom_override(&dev->mt76);
529 dev->mt76.macaddr[0] &= ~BIT(1); 521 dev->mt76.macaddr[0] &= ~BIT(1);
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.h b/drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.h
index c97b31c77d83..9e735524d367 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.h
+++ b/drivers/net/wireless/mediatek/mt76/mt76x2/eeprom.h
@@ -62,7 +62,7 @@ void mt76x2_read_rx_gain(struct mt76x02_dev *dev);
62static inline bool 62static inline bool
63mt76x2_has_ext_lna(struct mt76x02_dev *dev) 63mt76x2_has_ext_lna(struct mt76x02_dev *dev)
64{ 64{
65 u32 val = mt76x02_eeprom_get(&dev->mt76, MT_EE_NIC_CONF_1); 65 u32 val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_1);
66 66
67 if (dev->mt76.chandef.chan->band == NL80211_BAND_2GHZ) 67 if (dev->mt76.chandef.chan->band == NL80211_BAND_2GHZ)
68 return val & MT_EE_NIC_CONF_1_LNA_EXT_2G; 68 return val & MT_EE_NIC_CONF_1_LNA_EXT_2G;
@@ -70,4 +70,25 @@ mt76x2_has_ext_lna(struct mt76x02_dev *dev)
70 return val & MT_EE_NIC_CONF_1_LNA_EXT_5G; 70 return val & MT_EE_NIC_CONF_1_LNA_EXT_5G;
71} 71}
72 72
73static inline bool
74mt76x2_temp_tx_alc_enabled(struct mt76x02_dev *dev)
75{
76 u16 val;
77
78 val = mt76x02_eeprom_get(dev, MT_EE_TX_POWER_EXT_PA_5G);
79 if (!(val & BIT(15)))
80 return false;
81
82 return mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_1) &
83 MT_EE_NIC_CONF_1_TEMP_TX_ALC;
84}
85
86static inline bool
87mt76x2_tssi_enabled(struct mt76x02_dev *dev)
88{
89 return !mt76x2_temp_tx_alc_enabled(dev) &&
90 (mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_1) &
91 MT_EE_NIC_CONF_1_TX_ALC_EN);
92}
93
73#endif 94#endif
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x2/init.c b/drivers/net/wireless/mediatek/mt76/mt76x2/init.c
index ccd9bc9d3e1e..3c73fdeaf30f 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x2/init.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x2/init.c
@@ -167,6 +167,9 @@ void mt76x2_init_device(struct mt76x02_dev *dev)
167 hw->max_report_rates = 7; 167 hw->max_report_rates = 7;
168 hw->max_rate_tries = 1; 168 hw->max_rate_tries = 1;
169 hw->extra_tx_headroom = 2; 169 hw->extra_tx_headroom = 2;
170 if (mt76_is_usb(dev))
171 hw->extra_tx_headroom += sizeof(struct mt76x02_txwi) +
172 MT_DMA_HDR_LEN;
170 173
171 hw->sta_data_size = sizeof(struct mt76x02_sta); 174 hw->sta_data_size = sizeof(struct mt76x02_sta);
172 hw->vif_data_size = sizeof(struct mt76x02_vif); 175 hw->vif_data_size = sizeof(struct mt76x02_vif);
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x2/mcu.c b/drivers/net/wireless/mediatek/mt76/mt76x2/mcu.c
index 134037a227d7..88bd62cfbdf9 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x2/mcu.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x2/mcu.c
@@ -59,7 +59,6 @@ EXPORT_SYMBOL_GPL(mt76x2_mcu_set_channel);
59int mt76x2_mcu_load_cr(struct mt76x02_dev *dev, u8 type, u8 temp_level, 59int mt76x2_mcu_load_cr(struct mt76x02_dev *dev, u8 type, u8 temp_level,
60 u8 channel) 60 u8 channel)
61{ 61{
62 struct mt76_dev *mdev = &dev->mt76;
63 struct sk_buff *skb; 62 struct sk_buff *skb;
64 struct { 63 struct {
65 u8 cr_mode; 64 u8 cr_mode;
@@ -76,8 +75,8 @@ int mt76x2_mcu_load_cr(struct mt76x02_dev *dev, u8 type, u8 temp_level,
76 u32 val; 75 u32 val;
77 76
78 val = BIT(31); 77 val = BIT(31);
79 val |= (mt76x02_eeprom_get(mdev, MT_EE_NIC_CONF_0) >> 8) & 0x00ff; 78 val |= (mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_0) >> 8) & 0x00ff;
80 val |= (mt76x02_eeprom_get(mdev, MT_EE_NIC_CONF_1) << 8) & 0xff00; 79 val |= (mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_1) << 8) & 0xff00;
81 msg.cfg = cpu_to_le32(val); 80 msg.cfg = cpu_to_le32(val);
82 81
83 /* first set the channel without the extension channel info */ 82 /* first set the channel without the extension channel info */
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x2/mt76x2.h b/drivers/net/wireless/mediatek/mt76/mt76x2/mt76x2.h
index cbec8c6f1b2d..ab93125f46de 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x2/mt76x2.h
+++ b/drivers/net/wireless/mediatek/mt76/mt76x2/mt76x2.h
@@ -100,8 +100,6 @@ void mt76x2_phy_set_txpower_regs(struct mt76x02_dev *dev,
100 enum nl80211_band band); 100 enum nl80211_band band);
101void mt76x2_configure_tx_delay(struct mt76x02_dev *dev, 101void mt76x2_configure_tx_delay(struct mt76x02_dev *dev,
102 enum nl80211_band band, u8 bw); 102 enum nl80211_band band, u8 bw);
103void mt76x2_phy_set_bw(struct mt76x02_dev *dev, int width, u8 ctrl);
104void mt76x2_phy_set_band(struct mt76x02_dev *dev, int band, bool primary_upper);
105void mt76x2_apply_gain_adj(struct mt76x02_dev *dev); 103void mt76x2_apply_gain_adj(struct mt76x02_dev *dev);
106 104
107#endif 105#endif
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c b/drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c
index f229c6eb65dc..3824290b219d 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x2/pci_init.c
@@ -43,7 +43,7 @@ mt76x2_fixup_xtal(struct mt76x02_dev *dev)
43 u16 eep_val; 43 u16 eep_val;
44 s8 offset = 0; 44 s8 offset = 0;
45 45
46 eep_val = mt76x02_eeprom_get(&dev->mt76, MT_EE_XTAL_TRIM_2); 46 eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_2);
47 47
48 offset = eep_val & 0x7f; 48 offset = eep_val & 0x7f;
49 if ((eep_val & 0xff) == 0xff) 49 if ((eep_val & 0xff) == 0xff)
@@ -53,7 +53,7 @@ mt76x2_fixup_xtal(struct mt76x02_dev *dev)
53 53
54 eep_val >>= 8; 54 eep_val >>= 8;
55 if (eep_val == 0x00 || eep_val == 0xff) { 55 if (eep_val == 0x00 || eep_val == 0xff) {
56 eep_val = mt76x02_eeprom_get(&dev->mt76, MT_EE_XTAL_TRIM_1); 56 eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_1);
57 eep_val &= 0xff; 57 eep_val &= 0xff;
58 58
59 if (eep_val == 0x00 || eep_val == 0xff) 59 if (eep_val == 0x00 || eep_val == 0xff)
@@ -64,7 +64,7 @@ mt76x2_fixup_xtal(struct mt76x02_dev *dev)
64 mt76_rmw_field(dev, MT_XO_CTRL5, MT_XO_CTRL5_C2_VAL, eep_val + offset); 64 mt76_rmw_field(dev, MT_XO_CTRL5, MT_XO_CTRL5_C2_VAL, eep_val + offset);
65 mt76_set(dev, MT_XO_CTRL6, MT_XO_CTRL6_C2_CTRL); 65 mt76_set(dev, MT_XO_CTRL6, MT_XO_CTRL6_C2_CTRL);
66 66
67 eep_val = mt76x02_eeprom_get(&dev->mt76, MT_EE_NIC_CONF_2); 67 eep_val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_2);
68 switch (FIELD_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, eep_val)) { 68 switch (FIELD_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, eep_val)) {
69 case 0: 69 case 0:
70 mt76_wr(dev, MT_XO_CTRL7, 0x5c1fee80); 70 mt76_wr(dev, MT_XO_CTRL7, 0x5c1fee80);
@@ -143,14 +143,14 @@ static int mt76x2_mac_reset(struct mt76x02_dev *dev, bool hard)
143 mt76_wr(dev, MT_WCID_DROP_BASE + i * 4, 0); 143 mt76_wr(dev, MT_WCID_DROP_BASE + i * 4, 0);
144 144
145 for (i = 0; i < 256; i++) 145 for (i = 0; i < 256; i++)
146 mt76x02_mac_wcid_setup(&dev->mt76, i, 0, NULL); 146 mt76x02_mac_wcid_setup(dev, i, 0, NULL);
147 147
148 for (i = 0; i < MT_MAX_VIFS; i++) 148 for (i = 0; i < MT_MAX_VIFS; i++)
149 mt76x02_mac_wcid_setup(&dev->mt76, MT_VIF_WCID(i), i, NULL); 149 mt76x02_mac_wcid_setup(dev, MT_VIF_WCID(i), i, NULL);
150 150
151 for (i = 0; i < 16; i++) 151 for (i = 0; i < 16; i++)
152 for (k = 0; k < 4; k++) 152 for (k = 0; k < 4; k++)
153 mt76x02_mac_shared_key_setup(&dev->mt76, i, k, NULL); 153 mt76x02_mac_shared_key_setup(dev, i, k, NULL);
154 154
155 for (i = 0; i < 8; i++) { 155 for (i = 0; i < 8; i++) {
156 mt76x2_mac_set_bssid(dev, i, null_addr); 156 mt76x2_mac_set_bssid(dev, i, null_addr);
@@ -168,7 +168,7 @@ static int mt76x2_mac_reset(struct mt76x02_dev *dev, bool hard)
168 MT_CH_TIME_CFG_EIFS_AS_BUSY | 168 MT_CH_TIME_CFG_EIFS_AS_BUSY |
169 FIELD_PREP(MT_CH_TIME_CFG_CH_TIMER_CLR, 1)); 169 FIELD_PREP(MT_CH_TIME_CFG_CH_TIMER_CLR, 1));
170 170
171 mt76x02_set_beacon_offsets(&dev->mt76); 171 mt76x02_set_beacon_offsets(dev);
172 172
173 mt76x2_set_tx_ackto(dev); 173 mt76x2_set_tx_ackto(dev);
174 174
@@ -337,7 +337,7 @@ void mt76x2_stop_hardware(struct mt76x02_dev *dev)
337{ 337{
338 cancel_delayed_work_sync(&dev->cal_work); 338 cancel_delayed_work_sync(&dev->cal_work);
339 cancel_delayed_work_sync(&dev->mac_work); 339 cancel_delayed_work_sync(&dev->mac_work);
340 mt76x02_mcu_set_radio_state(&dev->mt76, false, true); 340 mt76x02_mcu_set_radio_state(dev, false, true);
341 mt76x2_mac_stop(dev, false); 341 mt76x2_mac_stop(dev, false);
342} 342}
343 343
@@ -347,7 +347,7 @@ void mt76x2_cleanup(struct mt76x02_dev *dev)
347 tasklet_disable(&dev->pre_tbtt_tasklet); 347 tasklet_disable(&dev->pre_tbtt_tasklet);
348 mt76x2_stop_hardware(dev); 348 mt76x2_stop_hardware(dev);
349 mt76x02_dma_cleanup(dev); 349 mt76x02_dma_cleanup(dev);
350 mt76x02_mcu_cleanup(&dev->mt76); 350 mt76x02_mcu_cleanup(dev);
351} 351}
352 352
353struct mt76x02_dev *mt76x2_alloc_device(struct device *pdev) 353struct mt76x02_dev *mt76x2_alloc_device(struct device *pdev)
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x2/pci_mac.c b/drivers/net/wireless/mediatek/mt76/mt76x2/pci_mac.c
index 08366c5988ea..4b331ed14bb2 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x2/pci_mac.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x2/pci_mac.c
@@ -36,7 +36,7 @@ mt76_write_beacon(struct mt76x02_dev *dev, int offset, struct sk_buff *skb)
36 if (WARN_ON_ONCE(beacon_len < skb->len + sizeof(struct mt76x02_txwi))) 36 if (WARN_ON_ONCE(beacon_len < skb->len + sizeof(struct mt76x02_txwi)))
37 return -ENOSPC; 37 return -ENOSPC;
38 38
39 mt76x02_mac_write_txwi(&dev->mt76, &txwi, skb, NULL, NULL, skb->len); 39 mt76x02_mac_write_txwi(dev, &txwi, skb, NULL, NULL, skb->len);
40 40
41 mt76_wr_copy(dev, offset, &txwi, sizeof(txwi)); 41 mt76_wr_copy(dev, offset, &txwi, sizeof(txwi));
42 offset += sizeof(txwi); 42 offset += sizeof(txwi);
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x2/pci_main.c b/drivers/net/wireless/mediatek/mt76/mt76x2/pci_main.c
index 65fef082e7cc..034a06295668 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x2/pci_main.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x2/pci_main.c
@@ -172,7 +172,7 @@ mt76x2_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps)
172 int idx = msta->wcid.idx; 172 int idx = msta->wcid.idx;
173 173
174 mt76_stop_tx_queues(&dev->mt76, sta, true); 174 mt76_stop_tx_queues(&dev->mt76, sta, true);
175 mt76x02_mac_wcid_set_drop(&dev->mt76, idx, ps); 175 mt76x02_mac_wcid_set_drop(dev, idx, ps);
176} 176}
177 177
178static void 178static void
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x2/pci_mcu.c b/drivers/net/wireless/mediatek/mt76/mt76x2/pci_mcu.c
index 898aa229671c..d8fa9ba56437 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x2/pci_mcu.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x2/pci_mcu.c
@@ -140,7 +140,7 @@ mt76pci_load_firmware(struct mt76x02_dev *dev)
140 140
141 mt76_wr(dev, MT_MCU_PCIE_REMAP_BASE4, 0); 141 mt76_wr(dev, MT_MCU_PCIE_REMAP_BASE4, 0);
142 142
143 val = mt76x02_eeprom_get(&dev->mt76, MT_EE_NIC_CONF_2); 143 val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_2);
144 if (FIELD_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, val) == 1) 144 if (FIELD_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, val) == 1)
145 mt76_set(dev, MT_MCU_COM_REG0, BIT(30)); 145 mt76_set(dev, MT_MCU_COM_REG0, BIT(30));
146 146
@@ -152,8 +152,8 @@ mt76pci_load_firmware(struct mt76x02_dev *dev)
152 return -ETIMEDOUT; 152 return -ETIMEDOUT;
153 } 153 }
154 154
155 mt76x02_set_ethtool_fwver(dev, hdr);
155 dev_info(dev->mt76.dev, "Firmware running!\n"); 156 dev_info(dev->mt76.dev, "Firmware running!\n");
156 mt76x02_set_ethtool_fwver(&dev->mt76, hdr);
157 157
158 release_firmware(fw); 158 release_firmware(fw);
159 159
@@ -183,6 +183,6 @@ int mt76x2_mcu_init(struct mt76x02_dev *dev)
183 if (ret) 183 if (ret)
184 return ret; 184 return ret;
185 185
186 mt76x02_mcu_function_select(&dev->mt76, Q_SELECT, 1, true); 186 mt76x02_mcu_function_select(dev, Q_SELECT, 1, true);
187 return 0; 187 return 0;
188} 188}
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c b/drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c
index 40ea5f7480fb..5bda44540225 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x2/pci_phy.c
@@ -26,7 +26,7 @@ mt76x2_phy_tssi_init_cal(struct mt76x02_dev *dev)
26 struct ieee80211_channel *chan = dev->mt76.chandef.chan; 26 struct ieee80211_channel *chan = dev->mt76.chandef.chan;
27 u32 flag = 0; 27 u32 flag = 0;
28 28
29 if (!mt76x02_tssi_enabled(&dev->mt76)) 29 if (!mt76x2_tssi_enabled(dev))
30 return false; 30 return false;
31 31
32 if (mt76x2_channel_silent(dev)) 32 if (mt76x2_channel_silent(dev))
@@ -35,10 +35,10 @@ mt76x2_phy_tssi_init_cal(struct mt76x02_dev *dev)
35 if (chan->band == NL80211_BAND_5GHZ) 35 if (chan->band == NL80211_BAND_5GHZ)
36 flag |= BIT(0); 36 flag |= BIT(0);
37 37
38 if (mt76x02_ext_pa_enabled(&dev->mt76, chan->band)) 38 if (mt76x02_ext_pa_enabled(dev, chan->band))
39 flag |= BIT(8); 39 flag |= BIT(8);
40 40
41 mt76x02_mcu_calibrate(&dev->mt76, MCU_CAL_TSSI, flag, true); 41 mt76x02_mcu_calibrate(dev, MCU_CAL_TSSI, flag, true);
42 dev->cal.tssi_cal_done = true; 42 dev->cal.tssi_cal_done = true;
43 return true; 43 return true;
44} 44}
@@ -62,13 +62,13 @@ mt76x2_phy_channel_calibrate(struct mt76x02_dev *dev, bool mac_stopped)
62 mt76x2_mac_stop(dev, false); 62 mt76x2_mac_stop(dev, false);
63 63
64 if (is_5ghz) 64 if (is_5ghz)
65 mt76x02_mcu_calibrate(&dev->mt76, MCU_CAL_LC, 0, true); 65 mt76x02_mcu_calibrate(dev, MCU_CAL_LC, 0, true);
66 66
67 mt76x02_mcu_calibrate(&dev->mt76, MCU_CAL_TX_LOFT, is_5ghz, true); 67 mt76x02_mcu_calibrate(dev, MCU_CAL_TX_LOFT, is_5ghz, true);
68 mt76x02_mcu_calibrate(&dev->mt76, MCU_CAL_TXIQ, is_5ghz, true); 68 mt76x02_mcu_calibrate(dev, MCU_CAL_TXIQ, is_5ghz, true);
69 mt76x02_mcu_calibrate(&dev->mt76, MCU_CAL_RXIQC_FI, is_5ghz, true); 69 mt76x02_mcu_calibrate(dev, MCU_CAL_RXIQC_FI, is_5ghz, true);
70 mt76x02_mcu_calibrate(&dev->mt76, MCU_CAL_TEMP_SENSOR, 0, true); 70 mt76x02_mcu_calibrate(dev, MCU_CAL_TEMP_SENSOR, 0, true);
71 mt76x02_mcu_calibrate(&dev->mt76, MCU_CAL_TX_SHAPING, 0, true); 71 mt76x02_mcu_calibrate(dev, MCU_CAL_TX_SHAPING, 0, true);
72 72
73 if (!mac_stopped) 73 if (!mac_stopped)
74 mt76x2_mac_resume(dev); 74 mt76x2_mac_resume(dev);
@@ -125,39 +125,6 @@ void mt76x2_phy_set_antenna(struct mt76x02_dev *dev)
125} 125}
126 126
127static void 127static void
128mt76x2_get_agc_gain(struct mt76x02_dev *dev, u8 *dest)
129{
130 dest[0] = mt76_get_field(dev, MT_BBP(AGC, 8), MT_BBP_AGC_GAIN);
131 dest[1] = mt76_get_field(dev, MT_BBP(AGC, 9), MT_BBP_AGC_GAIN);
132}
133
134static int
135mt76x2_get_rssi_gain_thresh(struct mt76x02_dev *dev)
136{
137 switch (dev->mt76.chandef.width) {
138 case NL80211_CHAN_WIDTH_80:
139 return -62;
140 case NL80211_CHAN_WIDTH_40:
141 return -65;
142 default:
143 return -68;
144 }
145}
146
147static int
148mt76x2_get_low_rssi_gain_thresh(struct mt76x02_dev *dev)
149{
150 switch (dev->mt76.chandef.width) {
151 case NL80211_CHAN_WIDTH_80:
152 return -76;
153 case NL80211_CHAN_WIDTH_40:
154 return -79;
155 default:
156 return -82;
157 }
158}
159
160static void
161mt76x2_phy_set_gain_val(struct mt76x02_dev *dev) 128mt76x2_phy_set_gain_val(struct mt76x02_dev *dev)
162{ 129{
163 u32 val; 130 u32 val;
@@ -183,25 +150,6 @@ mt76x2_phy_set_gain_val(struct mt76x02_dev *dev)
183} 150}
184 151
185static void 152static void
186mt76x2_phy_adjust_vga_gain(struct mt76x02_dev *dev)
187{
188 u32 false_cca;
189 u8 limit = dev->cal.low_gain > 0 ? 16 : 4;
190
191 false_cca = FIELD_GET(MT_RX_STAT_1_CCA_ERRORS, mt76_rr(dev, MT_RX_STAT_1));
192 dev->cal.false_cca = false_cca;
193 if (false_cca > 800 && dev->cal.agc_gain_adjust < limit)
194 dev->cal.agc_gain_adjust += 2;
195 else if ((false_cca < 10 && dev->cal.agc_gain_adjust > 0) ||
196 (dev->cal.agc_gain_adjust >= limit && false_cca < 500))
197 dev->cal.agc_gain_adjust -= 2;
198 else
199 return;
200
201 mt76x2_phy_set_gain_val(dev);
202}
203
204static void
205mt76x2_phy_update_channel_gain(struct mt76x02_dev *dev) 153mt76x2_phy_update_channel_gain(struct mt76x02_dev *dev)
206{ 154{
207 u8 *gain = dev->cal.agc_gain_init; 155 u8 *gain = dev->cal.agc_gain_init;
@@ -210,16 +158,17 @@ mt76x2_phy_update_channel_gain(struct mt76x02_dev *dev)
210 int low_gain; 158 int low_gain;
211 u32 val; 159 u32 val;
212 160
213 dev->cal.avg_rssi_all = mt76x02_phy_get_min_avg_rssi(&dev->mt76); 161 dev->cal.avg_rssi_all = mt76x02_phy_get_min_avg_rssi(dev);
214 162
215 low_gain = (dev->cal.avg_rssi_all > mt76x2_get_rssi_gain_thresh(dev)) + 163 low_gain = (dev->cal.avg_rssi_all > mt76x02_get_rssi_gain_thresh(dev)) +
216 (dev->cal.avg_rssi_all > mt76x2_get_low_rssi_gain_thresh(dev)); 164 (dev->cal.avg_rssi_all > mt76x02_get_low_rssi_gain_thresh(dev));
217 165
218 gain_change = (dev->cal.low_gain & 2) ^ (low_gain & 2); 166 gain_change = (dev->cal.low_gain & 2) ^ (low_gain & 2);
219 dev->cal.low_gain = low_gain; 167 dev->cal.low_gain = low_gain;
220 168
221 if (!gain_change) { 169 if (!gain_change) {
222 mt76x2_phy_adjust_vga_gain(dev); 170 if (mt76x02_phy_adjust_vga_gain(dev))
171 mt76x2_phy_set_gain_val(dev);
223 return; 172 return;
224 } 173 }
225 174
@@ -337,8 +286,8 @@ int mt76x2_phy_set_channel(struct mt76x02_dev *dev,
337 mt76x2_configure_tx_delay(dev, band, bw); 286 mt76x2_configure_tx_delay(dev, band, bw);
338 mt76x2_phy_set_txpower(dev); 287 mt76x2_phy_set_txpower(dev);
339 288
340 mt76x2_phy_set_band(dev, chan->band, ch_group_index & 1); 289 mt76x02_phy_set_band(dev, chan->band, ch_group_index & 1);
341 mt76x2_phy_set_bw(dev, chandef->width, ch_group_index); 290 mt76x02_phy_set_bw(dev, chandef->width, ch_group_index);
342 291
343 mt76_rmw(dev, MT_EXT_CCA_CFG, 292 mt76_rmw(dev, MT_EXT_CCA_CFG,
344 (MT_EXT_CCA_CFG_CCA0 | 293 (MT_EXT_CCA_CFG_CCA0 |
@@ -361,17 +310,17 @@ int mt76x2_phy_set_channel(struct mt76x02_dev *dev,
361 mt76_set(dev, MT_BBP(RXO, 13), BIT(10)); 310 mt76_set(dev, MT_BBP(RXO, 13), BIT(10));
362 311
363 if (!dev->cal.init_cal_done) { 312 if (!dev->cal.init_cal_done) {
364 u8 val = mt76x02_eeprom_get(&dev->mt76, MT_EE_BT_RCAL_RESULT); 313 u8 val = mt76x02_eeprom_get(dev, MT_EE_BT_RCAL_RESULT);
365 314
366 if (val != 0xff) 315 if (val != 0xff)
367 mt76x02_mcu_calibrate(&dev->mt76, MCU_CAL_R, 0, true); 316 mt76x02_mcu_calibrate(dev, MCU_CAL_R, 0, true);
368 } 317 }
369 318
370 mt76x02_mcu_calibrate(&dev->mt76, MCU_CAL_RXDCOC, channel, true); 319 mt76x02_mcu_calibrate(dev, MCU_CAL_RXDCOC, channel, true);
371 320
372 /* Rx LPF calibration */ 321 /* Rx LPF calibration */
373 if (!dev->cal.init_cal_done) 322 if (!dev->cal.init_cal_done)
374 mt76x02_mcu_calibrate(&dev->mt76, MCU_CAL_RC, 0, true); 323 mt76x02_mcu_calibrate(dev, MCU_CAL_RC, 0, true);
375 324
376 dev->cal.init_cal_done = true; 325 dev->cal.init_cal_done = true;
377 326
@@ -384,14 +333,11 @@ int mt76x2_phy_set_channel(struct mt76x02_dev *dev,
384 if (scan) 333 if (scan)
385 return 0; 334 return 0;
386 335
387 dev->cal.low_gain = -1;
388 mt76x2_phy_channel_calibrate(dev, true); 336 mt76x2_phy_channel_calibrate(dev, true);
389 mt76x2_get_agc_gain(dev, dev->cal.agc_gain_init); 337 mt76x02_init_agc_gain(dev);
390 memcpy(dev->cal.agc_gain_cur, dev->cal.agc_gain_init,
391 sizeof(dev->cal.agc_gain_cur));
392 338
393 /* init default values for temp compensation */ 339 /* init default values for temp compensation */
394 if (mt76x02_tssi_enabled(&dev->mt76)) { 340 if (mt76x2_tssi_enabled(dev)) {
395 mt76_rmw_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP, 341 mt76_rmw_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP,
396 0x38); 342 0x38);
397 mt76_rmw_field(dev, MT_TX_ALC_CFG_2, MT_TX_ALC_CFG_2_TEMP_COMP, 343 mt76_rmw_field(dev, MT_TX_ALC_CFG_2, MT_TX_ALC_CFG_2_TEMP_COMP,
@@ -449,7 +395,7 @@ int mt76x2_phy_start(struct mt76x02_dev *dev)
449{ 395{
450 int ret; 396 int ret;
451 397
452 ret = mt76x02_mcu_set_radio_state(&dev->mt76, true, true); 398 ret = mt76x02_mcu_set_radio_state(dev, true, true);
453 if (ret) 399 if (ret)
454 return ret; 400 return ret;
455 401
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x2/phy.c b/drivers/net/wireless/mediatek/mt76/mt76x2/phy.c
index f00aed915ee8..e9fff5b7f125 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x2/phy.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x2/phy.c
@@ -65,7 +65,7 @@ void mt76x2_phy_set_txpower_regs(struct mt76x02_dev *dev,
65 mt76_wr(dev, MT_TX_ALC_CFG_2, 0x35160a00); 65 mt76_wr(dev, MT_TX_ALC_CFG_2, 0x35160a00);
66 mt76_wr(dev, MT_TX_ALC_CFG_3, 0x35160a06); 66 mt76_wr(dev, MT_TX_ALC_CFG_3, 0x35160a06);
67 67
68 if (mt76x02_ext_pa_enabled(&dev->mt76, band)) { 68 if (mt76x02_ext_pa_enabled(dev, band)) {
69 mt76_wr(dev, MT_RF_PA_MODE_ADJ0, 0x0000ec00); 69 mt76_wr(dev, MT_RF_PA_MODE_ADJ0, 0x0000ec00);
70 mt76_wr(dev, MT_RF_PA_MODE_ADJ1, 0x0000ec00); 70 mt76_wr(dev, MT_RF_PA_MODE_ADJ1, 0x0000ec00);
71 } else { 71 } else {
@@ -76,7 +76,7 @@ void mt76x2_phy_set_txpower_regs(struct mt76x02_dev *dev,
76 pa_mode[0] = 0x0000ffff; 76 pa_mode[0] = 0x0000ffff;
77 pa_mode[1] = 0x00ff00ff; 77 pa_mode[1] = 0x00ff00ff;
78 78
79 if (mt76x02_ext_pa_enabled(&dev->mt76, band)) { 79 if (mt76x02_ext_pa_enabled(dev, band)) {
80 mt76_wr(dev, MT_TX_ALC_CFG_2, 0x2f0f0400); 80 mt76_wr(dev, MT_TX_ALC_CFG_2, 0x2f0f0400);
81 mt76_wr(dev, MT_TX_ALC_CFG_3, 0x2f0f0476); 81 mt76_wr(dev, MT_TX_ALC_CFG_3, 0x2f0f0476);
82 } else { 82 } else {
@@ -84,7 +84,7 @@ void mt76x2_phy_set_txpower_regs(struct mt76x02_dev *dev,
84 mt76_wr(dev, MT_TX_ALC_CFG_3, 0x1b0f0476); 84 mt76_wr(dev, MT_TX_ALC_CFG_3, 0x1b0f0476);
85 } 85 }
86 86
87 if (mt76x02_ext_pa_enabled(&dev->mt76, band)) 87 if (mt76x02_ext_pa_enabled(dev, band))
88 pa_mode_adj = 0x04000000; 88 pa_mode_adj = 0x04000000;
89 else 89 else
90 pa_mode_adj = 0; 90 pa_mode_adj = 0;
@@ -98,7 +98,7 @@ void mt76x2_phy_set_txpower_regs(struct mt76x02_dev *dev,
98 mt76_wr(dev, MT_RF_PA_MODE_CFG0, pa_mode[0]); 98 mt76_wr(dev, MT_RF_PA_MODE_CFG0, pa_mode[0]);
99 mt76_wr(dev, MT_RF_PA_MODE_CFG1, pa_mode[1]); 99 mt76_wr(dev, MT_RF_PA_MODE_CFG1, pa_mode[1]);
100 100
101 if (mt76x02_ext_pa_enabled(&dev->mt76, band)) { 101 if (mt76x02_ext_pa_enabled(dev, band)) {
102 u32 val; 102 u32 val;
103 103
104 if (band == NL80211_BAND_2GHZ) 104 if (band == NL80211_BAND_2GHZ)
@@ -187,7 +187,7 @@ void mt76x2_phy_set_txpower(struct mt76x02_dev *dev)
187 dev->target_power_delta[1] = txp_1 - txp.chain[0].target_power; 187 dev->target_power_delta[1] = txp_1 - txp.chain[0].target_power;
188 dev->mt76.rate_power = t; 188 dev->mt76.rate_power = t;
189 189
190 mt76x02_phy_set_txpower(&dev->mt76, txp_0, txp_1); 190 mt76x02_phy_set_txpower(dev, txp_0, txp_1);
191} 191}
192EXPORT_SYMBOL_GPL(mt76x2_phy_set_txpower); 192EXPORT_SYMBOL_GPL(mt76x2_phy_set_txpower);
193 193
@@ -196,7 +196,7 @@ void mt76x2_configure_tx_delay(struct mt76x02_dev *dev,
196{ 196{
197 u32 cfg0, cfg1; 197 u32 cfg0, cfg1;
198 198
199 if (mt76x02_ext_pa_enabled(&dev->mt76, band)) { 199 if (mt76x02_ext_pa_enabled(dev, band)) {
200 cfg0 = bw ? 0x000b0c01 : 0x00101101; 200 cfg0 = bw ? 0x000b0c01 : 0x00101101;
201 cfg1 = 0x00011414; 201 cfg1 = 0x00011414;
202 } else { 202 } else {
@@ -210,50 +210,6 @@ void mt76x2_configure_tx_delay(struct mt76x02_dev *dev,
210} 210}
211EXPORT_SYMBOL_GPL(mt76x2_configure_tx_delay); 211EXPORT_SYMBOL_GPL(mt76x2_configure_tx_delay);
212 212
213void mt76x2_phy_set_bw(struct mt76x02_dev *dev, int width, u8 ctrl)
214{
215 int core_val, agc_val;
216
217 switch (width) {
218 case NL80211_CHAN_WIDTH_80:
219 core_val = 3;
220 agc_val = 7;
221 break;
222 case NL80211_CHAN_WIDTH_40:
223 core_val = 2;
224 agc_val = 3;
225 break;
226 default:
227 core_val = 0;
228 agc_val = 1;
229 break;
230 }
231
232 mt76_rmw_field(dev, MT_BBP(CORE, 1), MT_BBP_CORE_R1_BW, core_val);
233 mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_BW, agc_val);
234 mt76_rmw_field(dev, MT_BBP(AGC, 0), MT_BBP_AGC_R0_CTRL_CHAN, ctrl);
235 mt76_rmw_field(dev, MT_BBP(TXBE, 0), MT_BBP_TXBE_R0_CTRL_CHAN, ctrl);
236}
237EXPORT_SYMBOL_GPL(mt76x2_phy_set_bw);
238
239void mt76x2_phy_set_band(struct mt76x02_dev *dev, int band, bool primary_upper)
240{
241 switch (band) {
242 case NL80211_BAND_2GHZ:
243 mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G);
244 mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G);
245 break;
246 case NL80211_BAND_5GHZ:
247 mt76_clear(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_2G);
248 mt76_set(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_5G);
249 break;
250 }
251
252 mt76_rmw_field(dev, MT_TX_BAND_CFG, MT_TX_BAND_CFG_UPPER_40M,
253 primary_upper);
254}
255EXPORT_SYMBOL_GPL(mt76x2_phy_set_band);
256
257void mt76x2_phy_tssi_compensate(struct mt76x02_dev *dev, bool wait) 213void mt76x2_phy_tssi_compensate(struct mt76x02_dev *dev, bool wait)
258{ 214{
259 struct ieee80211_channel *chan = dev->mt76.chandef.chan; 215 struct ieee80211_channel *chan = dev->mt76.chandef.chan;
@@ -275,7 +231,7 @@ void mt76x2_phy_tssi_compensate(struct mt76x02_dev *dev, bool wait)
275 dev->cal.tssi_comp_pending = false; 231 dev->cal.tssi_comp_pending = false;
276 mt76x2_get_power_info(dev, &txp, chan); 232 mt76x2_get_power_info(dev, &txp, chan);
277 233
278 if (mt76x02_ext_pa_enabled(&dev->mt76, chan->band)) 234 if (mt76x02_ext_pa_enabled(dev, chan->band))
279 t.pa_mode = 1; 235 t.pa_mode = 1;
280 236
281 t.cal_mode = BIT(1); 237 t.cal_mode = BIT(1);
@@ -289,8 +245,7 @@ void mt76x2_phy_tssi_compensate(struct mt76x02_dev *dev, bool wait)
289 return; 245 return;
290 246
291 usleep_range(10000, 20000); 247 usleep_range(10000, 20000);
292 mt76x02_mcu_calibrate(&dev->mt76, MCU_CAL_DPD, 248 mt76x02_mcu_calibrate(dev, MCU_CAL_DPD, chan->hw_value, wait);
293 chan->hw_value, wait);
294 dev->cal.dpd_cal_done = true; 249 dev->cal.dpd_cal_done = true;
295 } 250 }
296} 251}
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c b/drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c
index c82f16efa327..13cce2937573 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x2/usb_init.c
@@ -130,7 +130,7 @@ static int mt76x2u_init_eeprom(struct mt76x02_dev *dev)
130 put_unaligned_le32(val, dev->mt76.eeprom.data + i); 130 put_unaligned_le32(val, dev->mt76.eeprom.data + i);
131 } 131 }
132 132
133 mt76x02_eeprom_parse_hw_cap(&dev->mt76); 133 mt76x02_eeprom_parse_hw_cap(dev);
134 return 0; 134 return 0;
135} 135}
136 136
@@ -204,8 +204,7 @@ int mt76x2u_init_hardware(struct mt76x02_dev *dev)
204 if (err < 0) 204 if (err < 0)
205 return err; 205 return err;
206 206
207 mt76x02_mac_setaddr(&dev->mt76, 207 mt76x02_mac_setaddr(dev, dev->mt76.eeprom.data + MT_EE_MAC_ADDR);
208 dev->mt76.eeprom.data + MT_EE_MAC_ADDR);
209 dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG); 208 dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG);
210 209
211 mt76x2u_init_beacon_offsets(dev); 210 mt76x2u_init_beacon_offsets(dev);
@@ -237,8 +236,8 @@ int mt76x2u_init_hardware(struct mt76x02_dev *dev)
237 if (err < 0) 236 if (err < 0)
238 return err; 237 return err;
239 238
240 mt76x02_phy_set_rxpath(&dev->mt76); 239 mt76x02_phy_set_rxpath(dev);
241 mt76x02_phy_set_txdac(&dev->mt76); 240 mt76x02_phy_set_txdac(dev);
242 241
243 return mt76x2u_mac_stop(dev); 242 return mt76x2u_mac_stop(dev);
244} 243}
@@ -303,7 +302,7 @@ void mt76x2u_stop_hw(struct mt76x02_dev *dev)
303 302
304void mt76x2u_cleanup(struct mt76x02_dev *dev) 303void mt76x2u_cleanup(struct mt76x02_dev *dev)
305{ 304{
306 mt76x02_mcu_set_radio_state(&dev->mt76, false, false); 305 mt76x02_mcu_set_radio_state(dev, false, false);
307 mt76x2u_stop_hw(dev); 306 mt76x2u_stop_hw(dev);
308 mt76u_queues_deinit(&dev->mt76); 307 mt76u_queues_deinit(&dev->mt76);
309 mt76u_mcu_deinit(&dev->mt76); 308 mt76u_mcu_deinit(&dev->mt76);
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x2/usb_mac.c b/drivers/net/wireless/mediatek/mt76/mt76x2/usb_mac.c
index dbd635aa763b..db2194a92e67 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x2/usb_mac.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x2/usb_mac.c
@@ -32,7 +32,7 @@ static void mt76x2u_mac_fixup_xtal(struct mt76x02_dev *dev)
32 s8 offset = 0; 32 s8 offset = 0;
33 u16 eep_val; 33 u16 eep_val;
34 34
35 eep_val = mt76x02_eeprom_get(&dev->mt76, MT_EE_XTAL_TRIM_2); 35 eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_2);
36 36
37 offset = eep_val & 0x7f; 37 offset = eep_val & 0x7f;
38 if ((eep_val & 0xff) == 0xff) 38 if ((eep_val & 0xff) == 0xff)
@@ -42,7 +42,7 @@ static void mt76x2u_mac_fixup_xtal(struct mt76x02_dev *dev)
42 42
43 eep_val >>= 8; 43 eep_val >>= 8;
44 if (eep_val == 0x00 || eep_val == 0xff) { 44 if (eep_val == 0x00 || eep_val == 0xff) {
45 eep_val = mt76x02_eeprom_get(&dev->mt76, MT_EE_XTAL_TRIM_1); 45 eep_val = mt76x02_eeprom_get(dev, MT_EE_XTAL_TRIM_1);
46 eep_val &= 0xff; 46 eep_val &= 0xff;
47 47
48 if (eep_val == 0x00 || eep_val == 0xff) 48 if (eep_val == 0x00 || eep_val == 0xff)
@@ -67,7 +67,7 @@ static void mt76x2u_mac_fixup_xtal(struct mt76x02_dev *dev)
67 /* init fce */ 67 /* init fce */
68 mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN); 68 mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN);
69 69
70 eep_val = mt76x02_eeprom_get(&dev->mt76, MT_EE_NIC_CONF_2); 70 eep_val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_2);
71 switch (FIELD_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, eep_val)) { 71 switch (FIELD_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, eep_val)) {
72 case 0: 72 case 0:
73 mt76_wr(dev, MT_XO_CTRL7, 0x5c1fee80); 73 mt76_wr(dev, MT_XO_CTRL7, 0x5c1fee80);
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x2/usb_main.c b/drivers/net/wireless/mediatek/mt76/mt76x2/usb_main.c
index 224609d6915f..1971a1b00038 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x2/usb_main.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x2/usb_main.c
@@ -50,9 +50,9 @@ static int mt76x2u_add_interface(struct ieee80211_hw *hw,
50 struct mt76x02_dev *dev = hw->priv; 50 struct mt76x02_dev *dev = hw->priv;
51 51
52 if (!ether_addr_equal(dev->mt76.macaddr, vif->addr)) 52 if (!ether_addr_equal(dev->mt76.macaddr, vif->addr))
53 mt76x02_mac_setaddr(&dev->mt76, vif->addr); 53 mt76x02_mac_setaddr(dev, vif->addr);
54 54
55 mt76x02_vif_init(&dev->mt76, vif, 0); 55 mt76x02_vif_init(dev, vif, 0);
56 return 0; 56 return 0;
57} 57}
58 58
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x2/usb_mcu.c b/drivers/net/wireless/mediatek/mt76/mt76x2/usb_mcu.c
index 259ceae2a3a9..3f1e558e5e6d 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x2/usb_mcu.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x2/usb_mcu.c
@@ -137,7 +137,7 @@ static int mt76x2u_mcu_load_rom_patch(struct mt76x02_dev *dev)
137 mt76_wr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG), val); 137 mt76_wr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG), val);
138 138
139 /* vendor reset */ 139 /* vendor reset */
140 mt76x02u_mcu_fw_reset(&dev->mt76); 140 mt76x02u_mcu_fw_reset(dev);
141 usleep_range(5000, 10000); 141 usleep_range(5000, 10000);
142 142
143 /* enable FCE to send in-band cmd */ 143 /* enable FCE to send in-band cmd */
@@ -151,7 +151,7 @@ static int mt76x2u_mcu_load_rom_patch(struct mt76x02_dev *dev)
151 /* FCE skip_fs_en */ 151 /* FCE skip_fs_en */
152 mt76_wr(dev, MT_FCE_SKIP_FS, 0x3); 152 mt76_wr(dev, MT_FCE_SKIP_FS, 0x3);
153 153
154 err = mt76x02u_mcu_fw_send_data(&dev->mt76, fw->data + sizeof(*hdr), 154 err = mt76x02u_mcu_fw_send_data(dev, fw->data + sizeof(*hdr),
155 fw->size - sizeof(*hdr), 155 fw->size - sizeof(*hdr),
156 MCU_ROM_PATCH_MAX_PAYLOAD, 156 MCU_ROM_PATCH_MAX_PAYLOAD,
157 MT76U_MCU_ROM_PATCH_OFFSET); 157 MT76U_MCU_ROM_PATCH_OFFSET);
@@ -210,7 +210,7 @@ static int mt76x2u_mcu_load_firmware(struct mt76x02_dev *dev)
210 dev_info(dev->mt76.dev, "Build Time: %.16s\n", hdr->build_time); 210 dev_info(dev->mt76.dev, "Build Time: %.16s\n", hdr->build_time);
211 211
212 /* vendor reset */ 212 /* vendor reset */
213 mt76x02u_mcu_fw_reset(&dev->mt76); 213 mt76x02u_mcu_fw_reset(dev);
214 usleep_range(5000, 10000); 214 usleep_range(5000, 10000);
215 215
216 /* enable USB_DMA_CFG */ 216 /* enable USB_DMA_CFG */
@@ -230,7 +230,7 @@ static int mt76x2u_mcu_load_firmware(struct mt76x02_dev *dev)
230 mt76_wr(dev, MT_FCE_SKIP_FS, 0x3); 230 mt76_wr(dev, MT_FCE_SKIP_FS, 0x3);
231 231
232 /* load ILM */ 232 /* load ILM */
233 err = mt76x02u_mcu_fw_send_data(&dev->mt76, fw->data + sizeof(*hdr), 233 err = mt76x02u_mcu_fw_send_data(dev, fw->data + sizeof(*hdr),
234 ilm_len, MCU_FW_URB_MAX_PAYLOAD, 234 ilm_len, MCU_FW_URB_MAX_PAYLOAD,
235 MT76U_MCU_ILM_OFFSET); 235 MT76U_MCU_ILM_OFFSET);
236 if (err < 0) { 236 if (err < 0) {
@@ -241,8 +241,7 @@ static int mt76x2u_mcu_load_firmware(struct mt76x02_dev *dev)
241 /* load DLM */ 241 /* load DLM */
242 if (mt76xx_rev(dev) >= MT76XX_REV_E3) 242 if (mt76xx_rev(dev) >= MT76XX_REV_E3)
243 dlm_offset += 0x800; 243 dlm_offset += 0x800;
244 err = mt76x02u_mcu_fw_send_data(&dev->mt76, 244 err = mt76x02u_mcu_fw_send_data(dev, fw->data + sizeof(*hdr) + ilm_len,
245 fw->data + sizeof(*hdr) + ilm_len,
246 dlm_len, MCU_FW_URB_MAX_PAYLOAD, 245 dlm_len, MCU_FW_URB_MAX_PAYLOAD,
247 dlm_offset); 246 dlm_offset);
248 if (err < 0) { 247 if (err < 0) {
@@ -260,8 +259,8 @@ static int mt76x2u_mcu_load_firmware(struct mt76x02_dev *dev)
260 mt76_set(dev, MT_MCU_COM_REG0, BIT(1)); 259 mt76_set(dev, MT_MCU_COM_REG0, BIT(1));
261 /* enable FCE to send in-band cmd */ 260 /* enable FCE to send in-band cmd */
262 mt76_wr(dev, MT_FCE_PSE_CTRL, 0x1); 261 mt76_wr(dev, MT_FCE_PSE_CTRL, 0x1);
262 mt76x02_set_ethtool_fwver(dev, hdr);
263 dev_dbg(dev->mt76.dev, "firmware running\n"); 263 dev_dbg(dev->mt76.dev, "firmware running\n");
264 mt76x02_set_ethtool_fwver(&dev->mt76, hdr);
265 264
266out: 265out:
267 release_firmware(fw); 266 release_firmware(fw);
@@ -283,10 +282,9 @@ int mt76x2u_mcu_init(struct mt76x02_dev *dev)
283{ 282{
284 int err; 283 int err;
285 284
286 err = mt76x02_mcu_function_select(&dev->mt76, Q_SELECT, 285 err = mt76x02_mcu_function_select(dev, Q_SELECT, 1, false);
287 1, false);
288 if (err < 0) 286 if (err < 0)
289 return err; 287 return err;
290 288
291 return mt76x02_mcu_set_radio_state(&dev->mt76, true, false); 289 return mt76x02_mcu_set_radio_state(dev, true, false);
292} 290}
diff --git a/drivers/net/wireless/mediatek/mt76/mt76x2/usb_phy.c b/drivers/net/wireless/mediatek/mt76/mt76x2/usb_phy.c
index b11f8a6a6254..ca96ba60510e 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x2/usb_phy.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x2/usb_phy.c
@@ -29,12 +29,12 @@ void mt76x2u_phy_channel_calibrate(struct mt76x02_dev *dev)
29 mt76x2u_mac_stop(dev); 29 mt76x2u_mac_stop(dev);
30 30
31 if (is_5ghz) 31 if (is_5ghz)
32 mt76x02_mcu_calibrate(&dev->mt76, MCU_CAL_LC, 0, false); 32 mt76x02_mcu_calibrate(dev, MCU_CAL_LC, 0, false);
33 33
34 mt76x02_mcu_calibrate(&dev->mt76, MCU_CAL_TX_LOFT, is_5ghz, false); 34 mt76x02_mcu_calibrate(dev, MCU_CAL_TX_LOFT, is_5ghz, false);
35 mt76x02_mcu_calibrate(&dev->mt76, MCU_CAL_TXIQ, is_5ghz, false); 35 mt76x02_mcu_calibrate(dev, MCU_CAL_TXIQ, is_5ghz, false);
36 mt76x02_mcu_calibrate(&dev->mt76, MCU_CAL_RXIQC_FI, is_5ghz, false); 36 mt76x02_mcu_calibrate(dev, MCU_CAL_RXIQC_FI, is_5ghz, false);
37 mt76x02_mcu_calibrate(&dev->mt76, MCU_CAL_TEMP_SENSOR, 0, false); 37 mt76x02_mcu_calibrate(dev, MCU_CAL_TEMP_SENSOR, 0, false);
38 38
39 mt76x2u_mac_resume(dev); 39 mt76x2u_mac_resume(dev);
40} 40}
@@ -69,7 +69,7 @@ mt76x2u_phy_update_channel_gain(struct mt76x02_dev *dev)
69 break; 69 break;
70 } 70 }
71 71
72 dev->cal.avg_rssi_all = mt76x02_phy_get_min_avg_rssi(&dev->mt76); 72 dev->cal.avg_rssi_all = mt76x02_phy_get_min_avg_rssi(dev);
73 false_cca = FIELD_GET(MT_RX_STAT_1_CCA_ERRORS, 73 false_cca = FIELD_GET(MT_RX_STAT_1_CCA_ERRORS,
74 mt76_rr(dev, MT_RX_STAT_1)); 74 mt76_rr(dev, MT_RX_STAT_1));
75 75
@@ -155,8 +155,8 @@ int mt76x2u_phy_set_channel(struct mt76x02_dev *dev,
155 mt76x2_configure_tx_delay(dev, chan->band, bw); 155 mt76x2_configure_tx_delay(dev, chan->band, bw);
156 mt76x2_phy_set_txpower(dev); 156 mt76x2_phy_set_txpower(dev);
157 157
158 mt76x2_phy_set_band(dev, chan->band, ch_group_index & 1); 158 mt76x02_phy_set_band(dev, chan->band, ch_group_index & 1);
159 mt76x2_phy_set_bw(dev, chandef->width, ch_group_index); 159 mt76x02_phy_set_bw(dev, chandef->width, ch_group_index);
160 160
161 mt76_rmw(dev, MT_EXT_CCA_CFG, 161 mt76_rmw(dev, MT_EXT_CCA_CFG,
162 (MT_EXT_CCA_CFG_CCA0 | 162 (MT_EXT_CCA_CFG_CCA0 |
@@ -177,18 +177,17 @@ int mt76x2u_phy_set_channel(struct mt76x02_dev *dev,
177 mt76_set(dev, MT_BBP(RXO, 13), BIT(10)); 177 mt76_set(dev, MT_BBP(RXO, 13), BIT(10));
178 178
179 if (!dev->cal.init_cal_done) { 179 if (!dev->cal.init_cal_done) {
180 u8 val = mt76x02_eeprom_get(&dev->mt76, MT_EE_BT_RCAL_RESULT); 180 u8 val = mt76x02_eeprom_get(dev, MT_EE_BT_RCAL_RESULT);
181 181
182 if (val != 0xff) 182 if (val != 0xff)
183 mt76x02_mcu_calibrate(&dev->mt76, MCU_CAL_R, 183 mt76x02_mcu_calibrate(dev, MCU_CAL_R, 0, false);
184 0, false);
185 } 184 }
186 185
187 mt76x02_mcu_calibrate(&dev->mt76, MCU_CAL_RXDCOC, channel, false); 186 mt76x02_mcu_calibrate(dev, MCU_CAL_RXDCOC, channel, false);
188 187
189 /* Rx LPF calibration */ 188 /* Rx LPF calibration */
190 if (!dev->cal.init_cal_done) 189 if (!dev->cal.init_cal_done)
191 mt76x02_mcu_calibrate(&dev->mt76, MCU_CAL_RC, 0, false); 190 mt76x02_mcu_calibrate(dev, MCU_CAL_RC, 0, false);
192 dev->cal.init_cal_done = true; 191 dev->cal.init_cal_done = true;
193 192
194 mt76_wr(dev, MT_BBP(AGC, 61), 0xff64a4e2); 193 mt76_wr(dev, MT_BBP(AGC, 61), 0xff64a4e2);
@@ -203,7 +202,7 @@ int mt76x2u_phy_set_channel(struct mt76x02_dev *dev,
203 if (scan) 202 if (scan)
204 return 0; 203 return 0;
205 204
206 if (mt76x02_tssi_enabled(&dev->mt76)) { 205 if (mt76x2_tssi_enabled(dev)) {
207 /* init default values for temp compensation */ 206 /* init default values for temp compensation */
208 mt76_rmw_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP, 207 mt76_rmw_field(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP,
209 0x38); 208 0x38);
@@ -218,10 +217,9 @@ int mt76x2u_phy_set_channel(struct mt76x02_dev *dev,
218 chan = dev->mt76.chandef.chan; 217 chan = dev->mt76.chandef.chan;
219 if (chan->band == NL80211_BAND_5GHZ) 218 if (chan->band == NL80211_BAND_5GHZ)
220 flag |= BIT(0); 219 flag |= BIT(0);
221 if (mt76x02_ext_pa_enabled(&dev->mt76, chan->band)) 220 if (mt76x02_ext_pa_enabled(dev, chan->band))
222 flag |= BIT(8); 221 flag |= BIT(8);
223 mt76x02_mcu_calibrate(&dev->mt76, MCU_CAL_TSSI, 222 mt76x02_mcu_calibrate(dev, MCU_CAL_TSSI, flag, false);
224 flag, false);
225 dev->cal.tssi_cal_done = true; 223 dev->cal.tssi_cal_done = true;
226 } 224 }
227 } 225 }
diff --git a/drivers/net/wireless/mediatek/mt76/tx.c b/drivers/net/wireless/mediatek/mt76/tx.c
index bf0e9e666bc4..7cbce03aa65b 100644
--- a/drivers/net/wireless/mediatek/mt76/tx.c
+++ b/drivers/net/wireless/mediatek/mt76/tx.c
@@ -96,7 +96,8 @@ mt76_check_agg_ssn(struct mt76_txq *mtxq, struct sk_buff *skb)
96{ 96{
97 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 97 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
98 98
99 if (!ieee80211_is_data_qos(hdr->frame_control)) 99 if (!ieee80211_is_data_qos(hdr->frame_control) ||
100 !ieee80211_is_data_present(hdr->frame_control))
100 return; 101 return;
101 102
102 mtxq->agg_ssn = le16_to_cpu(hdr->seq_ctrl) + 0x10; 103 mtxq->agg_ssn = le16_to_cpu(hdr->seq_ctrl) + 0x10;
diff --git a/drivers/net/wireless/mediatek/mt76/usb.c b/drivers/net/wireless/mediatek/mt76/usb.c
index 6a255643c1f0..5f0faf07c346 100644
--- a/drivers/net/wireless/mediatek/mt76/usb.c
+++ b/drivers/net/wireless/mediatek/mt76/usb.c
@@ -862,6 +862,7 @@ int mt76u_init(struct mt76_dev *dev,
862 .copy = mt76u_copy, 862 .copy = mt76u_copy,
863 .wr_rp = mt76u_wr_rp, 863 .wr_rp = mt76u_wr_rp,
864 .rd_rp = mt76u_rd_rp, 864 .rd_rp = mt76u_rd_rp,
865 .type = MT76_BUS_USB,
865 }; 866 };
866 struct mt76_usb *usb = &dev->usb; 867 struct mt76_usb *usb = &dev->usb;
867 868
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-28 07:27:12 -0400