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authorVladimir Kondratiev <qca_vkondrat@qca.qualcomm.com>2013-01-28 11:31:06 -0500
committerJohn W. Linville <linville@tuxdriver.com>2013-01-30 15:07:17 -0500
commit7743882d6f59b675809b59b5ac570677c94c426f (patch)
tree62ed61277a94ba1a0dab223ba8db07a0a2016e61 /drivers/net/wireless/ath/wil6210/interrupt.c
parente08b5906ccf323e2ad7b0448329b7cbcfda4c94e (diff)
wil6210: fix checkpatch CamelCase warnings
Signed-off-by: Vladimir Kondratiev <qca_vkondrat@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/wil6210/interrupt.c')
-rw-r--r--drivers/net/wireless/ath/wil6210/interrupt.c32
1 files changed, 16 insertions, 16 deletions
diff --git a/drivers/net/wireless/ath/wil6210/interrupt.c b/drivers/net/wireless/ath/wil6210/interrupt.c
index 660bacf32d01..865c33f1b1ce 100644
--- a/drivers/net/wireless/ath/wil6210/interrupt.c
+++ b/drivers/net/wireless/ath/wil6210/interrupt.c
@@ -96,7 +96,7 @@ static void wil6210_mask_irq_misc(struct wil6210_priv *wil)
96 96
97static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil) 97static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil)
98{ 98{
99 wil_dbg_IRQ(wil, "%s()\n", __func__); 99 wil_dbg_irq(wil, "%s()\n", __func__);
100 100
101 iowrite32(WIL6210_IRQ_DISABLE, wil->csr + 101 iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
102 HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW)); 102 HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));
@@ -127,7 +127,7 @@ static void wil6210_unmask_irq_misc(struct wil6210_priv *wil)
127 127
128static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil) 128static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil)
129{ 129{
130 wil_dbg_IRQ(wil, "%s()\n", __func__); 130 wil_dbg_irq(wil, "%s()\n", __func__);
131 131
132 set_bit(wil_status_irqen, &wil->status); 132 set_bit(wil_status_irqen, &wil->status);
133 133
@@ -137,7 +137,7 @@ static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil)
137 137
138void wil6210_disable_irq(struct wil6210_priv *wil) 138void wil6210_disable_irq(struct wil6210_priv *wil)
139{ 139{
140 wil_dbg_IRQ(wil, "%s()\n", __func__); 140 wil_dbg_irq(wil, "%s()\n", __func__);
141 141
142 wil6210_mask_irq_tx(wil); 142 wil6210_mask_irq_tx(wil);
143 wil6210_mask_irq_rx(wil); 143 wil6210_mask_irq_rx(wil);
@@ -147,7 +147,7 @@ void wil6210_disable_irq(struct wil6210_priv *wil)
147 147
148void wil6210_enable_irq(struct wil6210_priv *wil) 148void wil6210_enable_irq(struct wil6210_priv *wil)
149{ 149{
150 wil_dbg_IRQ(wil, "%s()\n", __func__); 150 wil_dbg_irq(wil, "%s()\n", __func__);
151 151
152 iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) + 152 iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) +
153 offsetof(struct RGF_ICR, ICC)); 153 offsetof(struct RGF_ICR, ICC));
@@ -169,7 +169,7 @@ static irqreturn_t wil6210_irq_rx(int irq, void *cookie)
169 HOSTADDR(RGF_DMA_EP_RX_ICR) + 169 HOSTADDR(RGF_DMA_EP_RX_ICR) +
170 offsetof(struct RGF_ICR, ICR)); 170 offsetof(struct RGF_ICR, ICR));
171 171
172 wil_dbg_IRQ(wil, "ISR RX 0x%08x\n", isr); 172 wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr);
173 173
174 if (!isr) { 174 if (!isr) {
175 wil_err(wil, "spurious IRQ: RX\n"); 175 wil_err(wil, "spurious IRQ: RX\n");
@@ -179,7 +179,7 @@ static irqreturn_t wil6210_irq_rx(int irq, void *cookie)
179 wil6210_mask_irq_rx(wil); 179 wil6210_mask_irq_rx(wil);
180 180
181 if (isr & BIT_DMA_EP_RX_ICR_RX_DONE) { 181 if (isr & BIT_DMA_EP_RX_ICR_RX_DONE) {
182 wil_dbg_IRQ(wil, "RX done\n"); 182 wil_dbg_irq(wil, "RX done\n");
183 isr &= ~BIT_DMA_EP_RX_ICR_RX_DONE; 183 isr &= ~BIT_DMA_EP_RX_ICR_RX_DONE;
184 wil_rx_handle(wil); 184 wil_rx_handle(wil);
185 } 185 }
@@ -199,7 +199,7 @@ static irqreturn_t wil6210_irq_tx(int irq, void *cookie)
199 HOSTADDR(RGF_DMA_EP_TX_ICR) + 199 HOSTADDR(RGF_DMA_EP_TX_ICR) +
200 offsetof(struct RGF_ICR, ICR)); 200 offsetof(struct RGF_ICR, ICR));
201 201
202 wil_dbg_IRQ(wil, "ISR TX 0x%08x\n", isr); 202 wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr);
203 203
204 if (!isr) { 204 if (!isr) {
205 wil_err(wil, "spurious IRQ: TX\n"); 205 wil_err(wil, "spurious IRQ: TX\n");
@@ -210,13 +210,13 @@ static irqreturn_t wil6210_irq_tx(int irq, void *cookie)
210 210
211 if (isr & BIT_DMA_EP_TX_ICR_TX_DONE) { 211 if (isr & BIT_DMA_EP_TX_ICR_TX_DONE) {
212 uint i; 212 uint i;
213 wil_dbg_IRQ(wil, "TX done\n"); 213 wil_dbg_irq(wil, "TX done\n");
214 isr &= ~BIT_DMA_EP_TX_ICR_TX_DONE; 214 isr &= ~BIT_DMA_EP_TX_ICR_TX_DONE;
215 for (i = 0; i < 24; i++) { 215 for (i = 0; i < 24; i++) {
216 u32 mask = BIT_DMA_EP_TX_ICR_TX_DONE_N(i); 216 u32 mask = BIT_DMA_EP_TX_ICR_TX_DONE_N(i);
217 if (isr & mask) { 217 if (isr & mask) {
218 isr &= ~mask; 218 isr &= ~mask;
219 wil_dbg_IRQ(wil, "TX done(%i)\n", i); 219 wil_dbg_irq(wil, "TX done(%i)\n", i);
220 wil_tx_complete(wil, i); 220 wil_tx_complete(wil, i);
221 } 221 }
222 } 222 }
@@ -248,7 +248,7 @@ static irqreturn_t wil6210_irq_misc(int irq, void *cookie)
248 HOSTADDR(RGF_DMA_EP_MISC_ICR) + 248 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
249 offsetof(struct RGF_ICR, ICR)); 249 offsetof(struct RGF_ICR, ICR));
250 250
251 wil_dbg_IRQ(wil, "ISR MISC 0x%08x\n", isr); 251 wil_dbg_irq(wil, "ISR MISC 0x%08x\n", isr);
252 252
253 if (!isr) { 253 if (!isr) {
254 wil_err(wil, "spurious IRQ: MISC\n"); 254 wil_err(wil, "spurious IRQ: MISC\n");
@@ -258,14 +258,14 @@ static irqreturn_t wil6210_irq_misc(int irq, void *cookie)
258 wil6210_mask_irq_misc(wil); 258 wil6210_mask_irq_misc(wil);
259 259
260 if (isr & ISR_MISC_FW_ERROR) { 260 if (isr & ISR_MISC_FW_ERROR) {
261 wil_dbg_IRQ(wil, "IRQ: Firmware error\n"); 261 wil_dbg_irq(wil, "IRQ: Firmware error\n");
262 clear_bit(wil_status_fwready, &wil->status); 262 clear_bit(wil_status_fwready, &wil->status);
263 wil_notify_fw_error(wil); 263 wil_notify_fw_error(wil);
264 isr &= ~ISR_MISC_FW_ERROR; 264 isr &= ~ISR_MISC_FW_ERROR;
265 } 265 }
266 266
267 if (isr & ISR_MISC_FW_READY) { 267 if (isr & ISR_MISC_FW_READY) {
268 wil_dbg_IRQ(wil, "IRQ: FW ready\n"); 268 wil_dbg_irq(wil, "IRQ: FW ready\n");
269 /** 269 /**
270 * Actual FW ready indicated by the 270 * Actual FW ready indicated by the
271 * WMI_FW_READY_EVENTID 271 * WMI_FW_READY_EVENTID
@@ -288,10 +288,10 @@ static irqreturn_t wil6210_irq_misc_thread(int irq, void *cookie)
288 struct wil6210_priv *wil = cookie; 288 struct wil6210_priv *wil = cookie;
289 u32 isr = wil->isr_misc; 289 u32 isr = wil->isr_misc;
290 290
291 wil_dbg_IRQ(wil, "Thread ISR MISC 0x%08x\n", isr); 291 wil_dbg_irq(wil, "Thread ISR MISC 0x%08x\n", isr);
292 292
293 if (isr & ISR_MISC_MBOX_EVT) { 293 if (isr & ISR_MISC_MBOX_EVT) {
294 wil_dbg_IRQ(wil, "MBOX event\n"); 294 wil_dbg_irq(wil, "MBOX event\n");
295 wmi_recv_cmd(wil); 295 wmi_recv_cmd(wil);
296 isr &= ~ISR_MISC_MBOX_EVT; 296 isr &= ~ISR_MISC_MBOX_EVT;
297 } 297 }
@@ -313,7 +313,7 @@ static irqreturn_t wil6210_thread_irq(int irq, void *cookie)
313{ 313{
314 struct wil6210_priv *wil = cookie; 314 struct wil6210_priv *wil = cookie;
315 315
316 wil_dbg_IRQ(wil, "Thread IRQ\n"); 316 wil_dbg_irq(wil, "Thread IRQ\n");
317 /* Discover real IRQ cause */ 317 /* Discover real IRQ cause */
318 if (wil->isr_misc) 318 if (wil->isr_misc)
319 wil6210_irq_misc_thread(irq, cookie); 319 wil6210_irq_misc_thread(irq, cookie);
@@ -390,7 +390,7 @@ static irqreturn_t wil6210_hardirq(int irq, void *cookie)
390 if (wil6210_debug_irq_mask(wil, pseudo_cause)) 390 if (wil6210_debug_irq_mask(wil, pseudo_cause))
391 return IRQ_NONE; 391 return IRQ_NONE;
392 392
393 wil_dbg_IRQ(wil, "Pseudo IRQ 0x%08x\n", pseudo_cause); 393 wil_dbg_irq(wil, "Pseudo IRQ 0x%08x\n", pseudo_cause);
394 394
395 wil6210_mask_irq_pseudo(wil); 395 wil6210_mask_irq_pseudo(wil);
396 396