Merge branch 'master' into for-davem

Conflicts:
	drivers/net/wireless/ath/ath9k/phy.c
	drivers/net/wireless/iwlwifi/iwl-6000.c
	drivers/net/wireless/iwlwifi/iwl-debugfs.c

1 files changed, 193 insertions, 297 deletions

diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c
index 4a2060e5a777..7bbf502563bc 100644
--- a/drivers/net/wireless/ath/ath9k/mac.c
+++ b/drivers/net/wireless/ath/ath9k/mac.c
@@ -25,6 +25,8 @@ static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
                   ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
                   ah->txurn_interrupt_mask);
 
+        ENABLE_REGWRITE_BUFFER(ah);
+
         REG_WRITE(ah, AR_IMR_S0,
                   SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK)
                   | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC));
@@ -35,6 +37,9 @@ static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
         ah->imrs2_reg &= ~AR_IMR_S2_QCU_TXURN;
         ah->imrs2_reg |= (ah->txurn_interrupt_mask & AR_IMR_S2_QCU_TXURN);
         REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
+
+        REGWRITE_BUFFER_FLUSH(ah);
+        DISABLE_REGWRITE_BUFFER(ah);
 }
 
 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q)
@@ -57,6 +62,18 @@ void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
 }
 EXPORT_SYMBOL(ath9k_hw_txstart);
 
+void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds)
+{
+        struct ar5416_desc *ads = AR5416DESC(ds);
+
+        ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
+        ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
+        ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
+        ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
+        ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
+}
+EXPORT_SYMBOL(ath9k_hw_cleartxdesc);
+
 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
 {
         u32 npend;
@@ -207,281 +224,6 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
 }
 EXPORT_SYMBOL(ath9k_hw_stoptxdma);
 
-void ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds,
-                         u32 segLen, bool firstSeg,
-                         bool lastSeg, const struct ath_desc *ds0)
-{
-        struct ar5416_desc *ads = AR5416DESC(ds);
-
-        if (firstSeg) {
-                ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
-        } else if (lastSeg) {
-                ads->ds_ctl0 = 0;
-                ads->ds_ctl1 = segLen;
-                ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
-                ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
-        } else {
-                ads->ds_ctl0 = 0;
-                ads->ds_ctl1 = segLen | AR_TxMore;
-                ads->ds_ctl2 = 0;
-                ads->ds_ctl3 = 0;
-        }
-        ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
-        ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
-        ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
-        ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
-        ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
-}
-EXPORT_SYMBOL(ath9k_hw_filltxdesc);
-
-void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds)
-{
-        struct ar5416_desc *ads = AR5416DESC(ds);
-
-        ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
-        ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
-        ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
-        ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
-        ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
-}
-EXPORT_SYMBOL(ath9k_hw_cleartxdesc);
-
-int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds,
-                        struct ath_tx_status *ts)
-{
-        struct ar5416_desc *ads = AR5416DESC(ds);
-
-        if ((ads->ds_txstatus9 & AR_TxDone) == 0)
-                return -EINPROGRESS;
-
-        ts->ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
-        ts->ts_tstamp = ads->AR_SendTimestamp;
-        ts->ts_status = 0;
-        ts->ts_flags = 0;
-
-        if (ads->ds_txstatus1 & AR_FrmXmitOK)
-                ts->ts_status |= ATH9K_TX_ACKED;
-        if (ads->ds_txstatus1 & AR_ExcessiveRetries)
-                ts->ts_status |= ATH9K_TXERR_XRETRY;
-        if (ads->ds_txstatus1 & AR_Filtered)
-                ts->ts_status |= ATH9K_TXERR_FILT;
-        if (ads->ds_txstatus1 & AR_FIFOUnderrun) {
-                ts->ts_status |= ATH9K_TXERR_FIFO;
-                ath9k_hw_updatetxtriglevel(ah, true);
-        }
-        if (ads->ds_txstatus9 & AR_TxOpExceeded)
-                ts->ts_status |= ATH9K_TXERR_XTXOP;
-        if (ads->ds_txstatus1 & AR_TxTimerExpired)
-                ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
-
-        if (ads->ds_txstatus1 & AR_DescCfgErr)
-                ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
-        if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
-                ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
-                ath9k_hw_updatetxtriglevel(ah, true);
-        }
-        if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
-                ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
-                ath9k_hw_updatetxtriglevel(ah, true);
-        }
-        if (ads->ds_txstatus0 & AR_TxBaStatus) {
-                ts->ts_flags |= ATH9K_TX_BA;
-                ts->ba_low = ads->AR_BaBitmapLow;
-                ts->ba_high = ads->AR_BaBitmapHigh;
-        }
-
-        ts->ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
-        switch (ts->ts_rateindex) {
-        case 0:
-                ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
-                break;
-        case 1:
-                ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
-                break;
-        case 2:
-                ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
-                break;
-        case 3:
-                ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
-                break;
-        }
-
-        ts->ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
-        ts->ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
-        ts->ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
-        ts->ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
-        ts->ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
-        ts->ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
-        ts->ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
-        ts->evm0 = ads->AR_TxEVM0;
-        ts->evm1 = ads->AR_TxEVM1;
-        ts->evm2 = ads->AR_TxEVM2;
-        ts->ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
-        ts->ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
-        ts->ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
-        ts->ts_antenna = 0;
-
-        return 0;
-}
-EXPORT_SYMBOL(ath9k_hw_txprocdesc);
-
-void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds,
-                            u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
-                            u32 keyIx, enum ath9k_key_type keyType, u32 flags)
-{
-        struct ar5416_desc *ads = AR5416DESC(ds);
-
-        txPower += ah->txpower_indexoffset;
-        if (txPower > 63)
-                txPower = 63;
-
-        ads->ds_ctl0 = (pktLen & AR_FrameLen)
-                | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
-                | SM(txPower, AR_XmitPower)
-                | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
-                | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
-                | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
-                | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
-
-        ads->ds_ctl1 =
-                (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
-                | SM(type, AR_FrameType)
-                | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
-                | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
-                | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
-
-        ads->ds_ctl6 = SM(keyType, AR_EncrType);
-
-        if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
-                ads->ds_ctl8 = 0;
-                ads->ds_ctl9 = 0;
-                ads->ds_ctl10 = 0;
-                ads->ds_ctl11 = 0;
-        }
-}
-EXPORT_SYMBOL(ath9k_hw_set11n_txdesc);
-
-void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds,
-                                  struct ath_desc *lastds,
-                                  u32 durUpdateEn, u32 rtsctsRate,
-                                  u32 rtsctsDuration,
-                                  struct ath9k_11n_rate_series series[],
-                                  u32 nseries, u32 flags)
-{
-        struct ar5416_desc *ads = AR5416DESC(ds);
-        struct ar5416_desc *last_ads = AR5416DESC(lastds);
-        u32 ds_ctl0;
-
-        if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
-                ds_ctl0 = ads->ds_ctl0;
-
-                if (flags & ATH9K_TXDESC_RTSENA) {
-                        ds_ctl0 &= ~AR_CTSEnable;
-                        ds_ctl0 |= AR_RTSEnable;
-                } else {
-                        ds_ctl0 &= ~AR_RTSEnable;
-                        ds_ctl0 |= AR_CTSEnable;
-                }
-
-                ads->ds_ctl0 = ds_ctl0;
-        } else {
-                ads->ds_ctl0 =
-                        (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
-        }
-
-        ads->ds_ctl2 = set11nTries(series, 0)
-                | set11nTries(series, 1)
-                | set11nTries(series, 2)
-                | set11nTries(series, 3)
-                | (durUpdateEn ? AR_DurUpdateEna : 0)
-                | SM(0, AR_BurstDur);
-
-        ads->ds_ctl3 = set11nRate(series, 0)
-                | set11nRate(series, 1)
-                | set11nRate(series, 2)
-                | set11nRate(series, 3);
-
-        ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
-                | set11nPktDurRTSCTS(series, 1);
-
-        ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
-                | set11nPktDurRTSCTS(series, 3);
-
-        ads->ds_ctl7 = set11nRateFlags(series, 0)
-                | set11nRateFlags(series, 1)
-                | set11nRateFlags(series, 2)
-                | set11nRateFlags(series, 3)
-                | SM(rtsctsRate, AR_RTSCTSRate);
-        last_ads->ds_ctl2 = ads->ds_ctl2;
-        last_ads->ds_ctl3 = ads->ds_ctl3;
-}
-EXPORT_SYMBOL(ath9k_hw_set11n_ratescenario);
-
-void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds,
-                                u32 aggrLen)
-{
-        struct ar5416_desc *ads = AR5416DESC(ds);
-
-        ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
-        ads->ds_ctl6 &= ~AR_AggrLen;
-        ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
-}
-EXPORT_SYMBOL(ath9k_hw_set11n_aggr_first);
-
-void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds,
-                                 u32 numDelims)
-{
-        struct ar5416_desc *ads = AR5416DESC(ds);
-        unsigned int ctl6;
-
-        ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
-
-        ctl6 = ads->ds_ctl6;
-        ctl6 &= ~AR_PadDelim;
-        ctl6 |= SM(numDelims, AR_PadDelim);
-        ads->ds_ctl6 = ctl6;
-}
-EXPORT_SYMBOL(ath9k_hw_set11n_aggr_middle);
-
-void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds)
-{
-        struct ar5416_desc *ads = AR5416DESC(ds);
-
-        ads->ds_ctl1 |= AR_IsAggr;
-        ads->ds_ctl1 &= ~AR_MoreAggr;
-        ads->ds_ctl6 &= ~AR_PadDelim;
-}
-EXPORT_SYMBOL(ath9k_hw_set11n_aggr_last);
-
-void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds)
-{
-        struct ar5416_desc *ads = AR5416DESC(ds);
-
-        ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
-}
-EXPORT_SYMBOL(ath9k_hw_clr11n_aggr);
-
-void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds,
-                                   u32 burstDuration)
-{
-        struct ar5416_desc *ads = AR5416DESC(ds);
-
-        ads->ds_ctl2 &= ~AR_BurstDur;
-        ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
-}
-EXPORT_SYMBOL(ath9k_hw_set11n_burstduration);
-
-void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds,
-                                     u32 vmf)
-{
-        struct ar5416_desc *ads = AR5416DESC(ds);
-
-        if (vmf)
-                ads->ds_ctl0 |= AR_VirtMoreFrag;
-        else
-                ads->ds_ctl0 &= ~AR_VirtMoreFrag;
-}
-
 void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs)
 {
         *txqs &= ah->intr_txqs;
@@ -733,6 +475,8 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
         } else
                 cwMin = qi->tqi_cwmin;
 
+        ENABLE_REGWRITE_BUFFER(ah);
+
         REG_WRITE(ah, AR_DLCL_IFS(q),
                   SM(cwMin, AR_D_LCL_IFS_CWMIN) |
                   SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) |
@@ -747,6 +491,8 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
         REG_WRITE(ah, AR_DMISC(q),
                   AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
 
+        REGWRITE_BUFFER_FLUSH(ah);
+
         if (qi->tqi_cbrPeriod) {
                 REG_WRITE(ah, AR_QCBRCFG(q),
                           SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
@@ -762,6 +508,8 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
                           AR_Q_RDYTIMECFG_EN);
         }
 
+        REGWRITE_BUFFER_FLUSH(ah);
+
         REG_WRITE(ah, AR_DCHNTIME(q),
                   SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
                   (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
@@ -779,6 +527,10 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
                           REG_READ(ah, AR_DMISC(q)) |
                           AR_D_MISC_POST_FR_BKOFF_DIS);
         }
+
+        REGWRITE_BUFFER_FLUSH(ah);
+        DISABLE_REGWRITE_BUFFER(ah);
+
         if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {
                 REG_WRITE(ah, AR_DMISC(q),
                           REG_READ(ah, AR_DMISC(q)) |
@@ -786,6 +538,8 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
         }
         switch (qi->tqi_type) {
         case ATH9K_TX_QUEUE_BEACON:
+                ENABLE_REGWRITE_BUFFER(ah);
+
                 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
                           | AR_Q_MISC_FSP_DBA_GATED
                           | AR_Q_MISC_BEACON_USE
@@ -796,8 +550,20 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
                              AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
                           | AR_D_MISC_BEACON_USE
                           | AR_D_MISC_POST_FR_BKOFF_DIS);
+
+                REGWRITE_BUFFER_FLUSH(ah);
+                DISABLE_REGWRITE_BUFFER(ah);
+
+                /* cwmin and cwmax should be 0 for beacon queue */
+                if (AR_SREV_9300_20_OR_LATER(ah)) {
+                        REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN)
+                                  | SM(0, AR_D_LCL_IFS_CWMAX)
+                                  | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
+                }
                 break;
         case ATH9K_TX_QUEUE_CAB:
+                ENABLE_REGWRITE_BUFFER(ah);
+
                 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
                           | AR_Q_MISC_FSP_DBA_GATED
                           | AR_Q_MISC_CBR_INCR_DIS1
@@ -811,6 +577,10 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
                 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
                           | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
                              AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
+
+                REGWRITE_BUFFER_FLUSH(ah);
+                DISABLE_REGWRITE_BUFFER(ah);
+
                 break;
         case ATH9K_TX_QUEUE_PSPOLL:
                 REG_WRITE(ah, AR_QMISC(q),
@@ -832,6 +602,9 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
                           AR_D_MISC_POST_FR_BKOFF_DIS);
         }
 
+        if (AR_SREV_9300_20_OR_LATER(ah))
+                REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
+
         if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE)
                 ah->txok_interrupt_mask |= 1 << q;
         else
@@ -940,22 +713,6 @@ int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
 }
 EXPORT_SYMBOL(ath9k_hw_rxprocdesc);
 
-void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
-                          u32 size, u32 flags)
-{
-        struct ar5416_desc *ads = AR5416DESC(ds);
-        struct ath9k_hw_capabilities *pCap = &ah->caps;
-
-        ads->ds_ctl1 = size & AR_BufLen;
-        if (flags & ATH9K_RXDESC_INTREQ)
-                ads->ds_ctl1 |= AR_RxIntrReq;
-
-        ads->ds_rxstatus8 &= ~AR_RxDone;
-        if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
-                memset(&(ads->u), 0, sizeof(ads->u));
-}
-EXPORT_SYMBOL(ath9k_hw_setuprxdesc);
-
 /*
  * This can stop or re-enables RX.
  *
@@ -999,12 +756,6 @@ void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp)
 }
 EXPORT_SYMBOL(ath9k_hw_putrxbuf);
 
-void ath9k_hw_rxena(struct ath_hw *ah)
-{
-        REG_WRITE(ah, AR_CR, AR_CR_RXE);
-}
-EXPORT_SYMBOL(ath9k_hw_rxena);
-
 void ath9k_hw_startpcureceive(struct ath_hw *ah)
 {
         ath9k_enable_mib_counters(ah);
@@ -1023,6 +774,14 @@ void ath9k_hw_stoppcurecv(struct ath_hw *ah)
 }
 EXPORT_SYMBOL(ath9k_hw_stoppcurecv);
 
+void ath9k_hw_abortpcurecv(struct ath_hw *ah)
+{
+        REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS);
+
+        ath9k_hw_disable_mib_counters(ah);
+}
+EXPORT_SYMBOL(ath9k_hw_abortpcurecv);
+
 bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
 {
 #define AH_RX_STOP_DMA_TIMEOUT 10000   /* usec */
@@ -1068,3 +827,140 @@ int ath9k_hw_beaconq_setup(struct ath_hw *ah)
         return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi);
 }
 EXPORT_SYMBOL(ath9k_hw_beaconq_setup);
+
+bool ath9k_hw_intrpend(struct ath_hw *ah)
+{
+        u32 host_isr;
+
+        if (AR_SREV_9100(ah))
+                return true;
+
+        host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
+        if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
+                return true;
+
+        host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
+        if ((host_isr & AR_INTR_SYNC_DEFAULT)
+            && (host_isr != AR_INTR_SPURIOUS))
+                return true;
+
+        return false;
+}
+EXPORT_SYMBOL(ath9k_hw_intrpend);
+
+enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
+                                              enum ath9k_int ints)
+{
+        enum ath9k_int omask = ah->imask;
+        u32 mask, mask2;
+        struct ath9k_hw_capabilities *pCap = &ah->caps;
+        struct ath_common *common = ath9k_hw_common(ah);
+
+        ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
+
+        if (omask & ATH9K_INT_GLOBAL) {
+                ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
+                REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
+                (void) REG_READ(ah, AR_IER);
+                if (!AR_SREV_9100(ah)) {
+                        REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
+                        (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
+
+                        REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
+                        (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
+                }
+        }
+
+        /* TODO: global int Ref count */
+        mask = ints & ATH9K_INT_COMMON;
+        mask2 = 0;
+
+        if (ints & ATH9K_INT_TX) {
+                if (ah->config.tx_intr_mitigation)
+                        mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
+                if (ah->txok_interrupt_mask)
+                        mask |= AR_IMR_TXOK;
+                if (ah->txdesc_interrupt_mask)
+                        mask |= AR_IMR_TXDESC;
+                if (ah->txerr_interrupt_mask)
+                        mask |= AR_IMR_TXERR;
+                if (ah->txeol_interrupt_mask)
+                        mask |= AR_IMR_TXEOL;
+        }
+        if (ints & ATH9K_INT_RX) {
+                if (AR_SREV_9300_20_OR_LATER(ah)) {
+                        mask |= AR_IMR_RXERR | AR_IMR_RXOK_HP;
+                        if (ah->config.rx_intr_mitigation) {
+                                mask &= ~AR_IMR_RXOK_LP;
+                                mask |=  AR_IMR_RXMINTR | AR_IMR_RXINTM;
+                        } else {
+                                mask |= AR_IMR_RXOK_LP;
+                        }
+                } else {
+                        if (ah->config.rx_intr_mitigation)
+                                mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
+                        else
+                                mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
+                }
+                if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
+                        mask |= AR_IMR_GENTMR;
+        }
+
+        if (ints & (ATH9K_INT_BMISC)) {
+                mask |= AR_IMR_BCNMISC;
+                if (ints & ATH9K_INT_TIM)
+                        mask2 |= AR_IMR_S2_TIM;
+                if (ints & ATH9K_INT_DTIM)
+                        mask2 |= AR_IMR_S2_DTIM;
+                if (ints & ATH9K_INT_DTIMSYNC)
+                        mask2 |= AR_IMR_S2_DTIMSYNC;
+                if (ints & ATH9K_INT_CABEND)
+                        mask2 |= AR_IMR_S2_CABEND;
+                if (ints & ATH9K_INT_TSFOOR)
+                        mask2 |= AR_IMR_S2_TSFOOR;
+        }
+
+        if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
+                mask |= AR_IMR_BCNMISC;
+                if (ints & ATH9K_INT_GTT)
+                        mask2 |= AR_IMR_S2_GTT;
+                if (ints & ATH9K_INT_CST)
+                        mask2 |= AR_IMR_S2_CST;
+        }
+
+        ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
+        REG_WRITE(ah, AR_IMR, mask);
+        ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
+                           AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
+                           AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
+        ah->imrs2_reg |= mask2;
+        REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
+
+        if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
+                if (ints & ATH9K_INT_TIM_TIMER)
+                        REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
+                else
+                        REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
+        }
+
+        if (ints & ATH9K_INT_GLOBAL) {
+                ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
+                REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
+                if (!AR_SREV_9100(ah)) {
+                        REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
+                                  AR_INTR_MAC_IRQ);
+                        REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
+
+
+                        REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
+                                  AR_INTR_SYNC_DEFAULT);
+                        REG_WRITE(ah, AR_INTR_SYNC_MASK,
+                                  AR_INTR_SYNC_DEFAULT);
+                }
+                ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
+                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
+        }
+
+        return omask;
+}
+EXPORT_SYMBOL(ath9k_hw_set_interrupts);