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authorLuis R. Rodriguez <lrodriguez@atheros.com>2010-04-15 17:39:28 -0400
committerJohn W. Linville <linville@tuxdriver.com>2010-04-16 15:43:45 -0400
commitb622a720b45def8dce816244a83b82992da4fe20 (patch)
tree0d9c2d852219a1b53e6387848a24dca97552f58e /drivers/net/wireless/ath/ath9k/ar9002_mac.c
parent744d402580f959072f6b805a98745837f185c8e0 (diff)
ath9k_hw: move AR9002 mac ops to its own file
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ar9002_mac.c')
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_mac.c480
1 files changed, 480 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_mac.c b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
new file mode 100644
index 000000000000..2be20d2070c4
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
@@ -0,0 +1,480 @@
1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "hw.h"
18
19#define AR_BufLen 0x00000fff
20
21static void ar9002_hw_rx_enable(struct ath_hw *ah)
22{
23 REG_WRITE(ah, AR_CR, AR_CR_RXE);
24}
25
26static void ar9002_hw_set_desc_link(void *ds, u32 ds_link)
27{
28 ((struct ath_desc*) ds)->ds_link = ds_link;
29}
30
31static void ar9002_hw_get_desc_link(void *ds, u32 **ds_link)
32{
33 *ds_link = &((struct ath_desc *)ds)->ds_link;
34}
35
36static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
37{
38 u32 isr = 0;
39 u32 mask2 = 0;
40 struct ath9k_hw_capabilities *pCap = &ah->caps;
41 u32 sync_cause = 0;
42 bool fatal_int = false;
43 struct ath_common *common = ath9k_hw_common(ah);
44
45 if (!AR_SREV_9100(ah)) {
46 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
47 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
48 == AR_RTC_STATUS_ON) {
49 isr = REG_READ(ah, AR_ISR);
50 }
51 }
52
53 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
54 AR_INTR_SYNC_DEFAULT;
55
56 *masked = 0;
57
58 if (!isr && !sync_cause)
59 return false;
60 } else {
61 *masked = 0;
62 isr = REG_READ(ah, AR_ISR);
63 }
64
65 if (isr) {
66 if (isr & AR_ISR_BCNMISC) {
67 u32 isr2;
68 isr2 = REG_READ(ah, AR_ISR_S2);
69 if (isr2 & AR_ISR_S2_TIM)
70 mask2 |= ATH9K_INT_TIM;
71 if (isr2 & AR_ISR_S2_DTIM)
72 mask2 |= ATH9K_INT_DTIM;
73 if (isr2 & AR_ISR_S2_DTIMSYNC)
74 mask2 |= ATH9K_INT_DTIMSYNC;
75 if (isr2 & (AR_ISR_S2_CABEND))
76 mask2 |= ATH9K_INT_CABEND;
77 if (isr2 & AR_ISR_S2_GTT)
78 mask2 |= ATH9K_INT_GTT;
79 if (isr2 & AR_ISR_S2_CST)
80 mask2 |= ATH9K_INT_CST;
81 if (isr2 & AR_ISR_S2_TSFOOR)
82 mask2 |= ATH9K_INT_TSFOOR;
83 }
84
85 isr = REG_READ(ah, AR_ISR_RAC);
86 if (isr == 0xffffffff) {
87 *masked = 0;
88 return false;
89 }
90
91 *masked = isr & ATH9K_INT_COMMON;
92
93 if (ah->config.rx_intr_mitigation) {
94 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
95 *masked |= ATH9K_INT_RX;
96 }
97
98 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
99 *masked |= ATH9K_INT_RX;
100 if (isr &
101 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
102 AR_ISR_TXEOL)) {
103 u32 s0_s, s1_s;
104
105 *masked |= ATH9K_INT_TX;
106
107 s0_s = REG_READ(ah, AR_ISR_S0_S);
108 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
109 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
110
111 s1_s = REG_READ(ah, AR_ISR_S1_S);
112 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
113 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
114 }
115
116 if (isr & AR_ISR_RXORN) {
117 ath_print(common, ATH_DBG_INTERRUPT,
118 "receive FIFO overrun interrupt\n");
119 }
120
121 if (!AR_SREV_9100(ah)) {
122 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
123 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
124 if (isr5 & AR_ISR_S5_TIM_TIMER)
125 *masked |= ATH9K_INT_TIM_TIMER;
126 }
127 }
128
129 *masked |= mask2;
130 }
131
132 if (AR_SREV_9100(ah))
133 return true;
134
135 if (isr & AR_ISR_GENTMR) {
136 u32 s5_s;
137
138 s5_s = REG_READ(ah, AR_ISR_S5_S);
139 if (isr & AR_ISR_GENTMR) {
140 ah->intr_gen_timer_trigger =
141 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
142
143 ah->intr_gen_timer_thresh =
144 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
145
146 if (ah->intr_gen_timer_trigger)
147 *masked |= ATH9K_INT_GENTIMER;
148
149 }
150 }
151
152 if (sync_cause) {
153 fatal_int =
154 (sync_cause &
155 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
156 ? true : false;
157
158 if (fatal_int) {
159 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
160 ath_print(common, ATH_DBG_ANY,
161 "received PCI FATAL interrupt\n");
162 }
163 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
164 ath_print(common, ATH_DBG_ANY,
165 "received PCI PERR interrupt\n");
166 }
167 *masked |= ATH9K_INT_FATAL;
168 }
169 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
170 ath_print(common, ATH_DBG_INTERRUPT,
171 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
172 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
173 REG_WRITE(ah, AR_RC, 0);
174 *masked |= ATH9K_INT_FATAL;
175 }
176 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
177 ath_print(common, ATH_DBG_INTERRUPT,
178 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
179 }
180
181 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
182 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
183 }
184
185 return true;
186}
187
188static void ar9002_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
189 bool is_firstseg, bool is_lastseg,
190 const void *ds0, dma_addr_t buf_addr,
191 unsigned int qcu)
192{
193 struct ar5416_desc *ads = AR5416DESC(ds);
194
195 ads->ds_data = buf_addr;
196
197 if (is_firstseg) {
198 ads->ds_ctl1 |= seglen | (is_lastseg ? 0 : AR_TxMore);
199 } else if (is_lastseg) {
200 ads->ds_ctl0 = 0;
201 ads->ds_ctl1 = seglen;
202 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
203 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
204 } else {
205 ads->ds_ctl0 = 0;
206 ads->ds_ctl1 = seglen | AR_TxMore;
207 ads->ds_ctl2 = 0;
208 ads->ds_ctl3 = 0;
209 }
210 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
211 ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
212 ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
213 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
214 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
215}
216
217static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds,
218 struct ath_tx_status *ts)
219{
220 struct ar5416_desc *ads = AR5416DESC(ds);
221
222 if ((ads->ds_txstatus9 & AR_TxDone) == 0)
223 return -EINPROGRESS;
224
225 ts->ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
226 ts->ts_tstamp = ads->AR_SendTimestamp;
227 ts->ts_status = 0;
228 ts->ts_flags = 0;
229
230 if (ads->ds_txstatus1 & AR_FrmXmitOK)
231 ts->ts_status |= ATH9K_TX_ACKED;
232 if (ads->ds_txstatus1 & AR_ExcessiveRetries)
233 ts->ts_status |= ATH9K_TXERR_XRETRY;
234 if (ads->ds_txstatus1 & AR_Filtered)
235 ts->ts_status |= ATH9K_TXERR_FILT;
236 if (ads->ds_txstatus1 & AR_FIFOUnderrun) {
237 ts->ts_status |= ATH9K_TXERR_FIFO;
238 ath9k_hw_updatetxtriglevel(ah, true);
239 }
240 if (ads->ds_txstatus9 & AR_TxOpExceeded)
241 ts->ts_status |= ATH9K_TXERR_XTXOP;
242 if (ads->ds_txstatus1 & AR_TxTimerExpired)
243 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
244
245 if (ads->ds_txstatus1 & AR_DescCfgErr)
246 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
247 if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
248 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
249 ath9k_hw_updatetxtriglevel(ah, true);
250 }
251 if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
252 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
253 ath9k_hw_updatetxtriglevel(ah, true);
254 }
255 if (ads->ds_txstatus0 & AR_TxBaStatus) {
256 ts->ts_flags |= ATH9K_TX_BA;
257 ts->ba_low = ads->AR_BaBitmapLow;
258 ts->ba_high = ads->AR_BaBitmapHigh;
259 }
260
261 ts->ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
262 switch (ts->ts_rateindex) {
263 case 0:
264 ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
265 break;
266 case 1:
267 ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
268 break;
269 case 2:
270 ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
271 break;
272 case 3:
273 ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
274 break;
275 }
276
277 ts->ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
278 ts->ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
279 ts->ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
280 ts->ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
281 ts->ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
282 ts->ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
283 ts->ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
284 ts->evm0 = ads->AR_TxEVM0;
285 ts->evm1 = ads->AR_TxEVM1;
286 ts->evm2 = ads->AR_TxEVM2;
287 ts->ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
288 ts->ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
289 ts->ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
290 ts->ts_antenna = 0;
291
292 return 0;
293}
294
295static void ar9002_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
296 u32 pktLen, enum ath9k_pkt_type type,
297 u32 txPower, u32 keyIx,
298 enum ath9k_key_type keyType, u32 flags)
299{
300 struct ar5416_desc *ads = AR5416DESC(ds);
301
302 txPower += ah->txpower_indexoffset;
303 if (txPower > 63)
304 txPower = 63;
305
306 ads->ds_ctl0 = (pktLen & AR_FrameLen)
307 | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
308 | SM(txPower, AR_XmitPower)
309 | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
310 | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
311 | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
312 | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
313
314 ads->ds_ctl1 =
315 (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
316 | SM(type, AR_FrameType)
317 | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
318 | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
319 | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
320
321 ads->ds_ctl6 = SM(keyType, AR_EncrType);
322
323 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
324 ads->ds_ctl8 = 0;
325 ads->ds_ctl9 = 0;
326 ads->ds_ctl10 = 0;
327 ads->ds_ctl11 = 0;
328 }
329}
330
331static void ar9002_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
332 void *lastds,
333 u32 durUpdateEn, u32 rtsctsRate,
334 u32 rtsctsDuration,
335 struct ath9k_11n_rate_series series[],
336 u32 nseries, u32 flags)
337{
338 struct ar5416_desc *ads = AR5416DESC(ds);
339 struct ar5416_desc *last_ads = AR5416DESC(lastds);
340 u32 ds_ctl0;
341
342 if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
343 ds_ctl0 = ads->ds_ctl0;
344
345 if (flags & ATH9K_TXDESC_RTSENA) {
346 ds_ctl0 &= ~AR_CTSEnable;
347 ds_ctl0 |= AR_RTSEnable;
348 } else {
349 ds_ctl0 &= ~AR_RTSEnable;
350 ds_ctl0 |= AR_CTSEnable;
351 }
352
353 ads->ds_ctl0 = ds_ctl0;
354 } else {
355 ads->ds_ctl0 =
356 (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
357 }
358
359 ads->ds_ctl2 = set11nTries(series, 0)
360 | set11nTries(series, 1)
361 | set11nTries(series, 2)
362 | set11nTries(series, 3)
363 | (durUpdateEn ? AR_DurUpdateEna : 0)
364 | SM(0, AR_BurstDur);
365
366 ads->ds_ctl3 = set11nRate(series, 0)
367 | set11nRate(series, 1)
368 | set11nRate(series, 2)
369 | set11nRate(series, 3);
370
371 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
372 | set11nPktDurRTSCTS(series, 1);
373
374 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
375 | set11nPktDurRTSCTS(series, 3);
376
377 ads->ds_ctl7 = set11nRateFlags(series, 0)
378 | set11nRateFlags(series, 1)
379 | set11nRateFlags(series, 2)
380 | set11nRateFlags(series, 3)
381 | SM(rtsctsRate, AR_RTSCTSRate);
382 last_ads->ds_ctl2 = ads->ds_ctl2;
383 last_ads->ds_ctl3 = ads->ds_ctl3;
384}
385
386static void ar9002_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
387 u32 aggrLen)
388{
389 struct ar5416_desc *ads = AR5416DESC(ds);
390
391 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
392 ads->ds_ctl6 &= ~AR_AggrLen;
393 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
394}
395
396static void ar9002_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
397 u32 numDelims)
398{
399 struct ar5416_desc *ads = AR5416DESC(ds);
400 unsigned int ctl6;
401
402 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
403
404 ctl6 = ads->ds_ctl6;
405 ctl6 &= ~AR_PadDelim;
406 ctl6 |= SM(numDelims, AR_PadDelim);
407 ads->ds_ctl6 = ctl6;
408}
409
410static void ar9002_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
411{
412 struct ar5416_desc *ads = AR5416DESC(ds);
413
414 ads->ds_ctl1 |= AR_IsAggr;
415 ads->ds_ctl1 &= ~AR_MoreAggr;
416 ads->ds_ctl6 &= ~AR_PadDelim;
417}
418
419static void ar9002_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
420{
421 struct ar5416_desc *ads = AR5416DESC(ds);
422
423 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
424}
425
426static void ar9002_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
427 u32 burstDuration)
428{
429 struct ar5416_desc *ads = AR5416DESC(ds);
430
431 ads->ds_ctl2 &= ~AR_BurstDur;
432 ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
433}
434
435static void ar9002_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
436 u32 vmf)
437{
438 struct ar5416_desc *ads = AR5416DESC(ds);
439
440 if (vmf)
441 ads->ds_ctl0 |= AR_VirtMoreFrag;
442 else
443 ads->ds_ctl0 &= ~AR_VirtMoreFrag;
444}
445
446void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
447 u32 size, u32 flags)
448{
449 struct ar5416_desc *ads = AR5416DESC(ds);
450 struct ath9k_hw_capabilities *pCap = &ah->caps;
451
452 ads->ds_ctl1 = size & AR_BufLen;
453 if (flags & ATH9K_RXDESC_INTREQ)
454 ads->ds_ctl1 |= AR_RxIntrReq;
455
456 ads->ds_rxstatus8 &= ~AR_RxDone;
457 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
458 memset(&(ads->u), 0, sizeof(ads->u));
459}
460EXPORT_SYMBOL(ath9k_hw_setuprxdesc);
461
462void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
463{
464 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
465
466 ops->rx_enable = ar9002_hw_rx_enable;
467 ops->set_desc_link = ar9002_hw_set_desc_link;
468 ops->get_desc_link = ar9002_hw_get_desc_link;
469 ops->get_isr = ar9002_hw_get_isr;
470 ops->fill_txdesc = ar9002_hw_fill_txdesc;
471 ops->proc_txdesc = ar9002_hw_proc_txdesc;
472 ops->set11n_txdesc = ar9002_hw_set11n_txdesc;
473 ops->set11n_ratescenario = ar9002_hw_set11n_ratescenario;
474 ops->set11n_aggr_first = ar9002_hw_set11n_aggr_first;
475 ops->set11n_aggr_middle = ar9002_hw_set11n_aggr_middle;
476 ops->set11n_aggr_last = ar9002_hw_set11n_aggr_last;
477 ops->clr11n_aggr = ar9002_hw_clr11n_aggr;
478 ops->set11n_burstduration = ar9002_hw_set11n_burstduration;
479 ops->set11n_virtualmorefrag = ar9002_hw_set11n_virtualmorefrag;
480}
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-25 02:32:25 -0500