ath10k: add error handling to ath10k_pci_wait()

ath10k_pci_wait() didn't notify any errors to callers, it
just printed a warning so add proper error handling. This fixes
a crash Ben reported:

ath10k: MSI-X interrupt handling (8 intrs)
ath10k: Unable to wakeup target
ath10k: target took longer 5000 us to wake up (awake count 1)
ath10k: Failed to get pcie state addr: -16
ath10k: early firmware event indicated
BUG: unable to handle kernel NULL pointer dereference at 0000000000000004
IP: [<ffffffffa06ae46c>] ath10k_ce_completed_send_next+0x47/0x122 [ath10k_pci]

Reported-by: Ben Greear <greearb@candelatech.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>

1 files changed, 24 insertions, 4 deletions

diff --git a/drivers/net/wireless/ath/ath10k/pci.c b/drivers/net/wireless/ath/ath10k/pci.c
index 5c7838398e9a..42d2473b56ba 100644
--- a/drivers/net/wireless/ath/ath10k/pci.c
+++ b/drivers/net/wireless/ath/ath10k/pci.c
@@ -526,15 +526,19 @@ static bool ath10k_pci_target_is_awake(struct ath10k *ar)
         return (RTC_STATE_V_GET(val) == RTC_STATE_V_ON);
 }
 
-static void ath10k_pci_wait(struct ath10k *ar)
+static int ath10k_pci_wait(struct ath10k *ar)
 {
         int n = 100;
 
         while (n-- && !ath10k_pci_target_is_awake(ar))
                 msleep(10);
 
-        if (n < 0)
+        if (n < 0) {
                 ath10k_warn("Unable to wakeup target\n");
+                return -ETIMEDOUT;
+        }
+
+        return 0;
 }
 
 int ath10k_do_pci_wake(struct ath10k *ar)
@@ -2155,7 +2159,13 @@ static int ath10k_pci_start_intr_legacy(struct ath10k *ar)
                   ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
                   PCIE_SOC_WAKE_ADDRESS);
 
-        ath10k_pci_wait(ar);
+        ret = ath10k_pci_wait(ar);
+        if (ret) {
+                ath10k_warn("Failed to enable legacy interrupt, target did not wake up: %d\n",
+                            ret);
+                free_irq(ar_pci->pdev->irq, ar);
+                return ret;
+        }
 
         /*
          * A potential race occurs here: The CORE_BASE write
@@ -2218,6 +2228,10 @@ static int ath10k_pci_start_intr(struct ath10k *ar)
         }
 
         ret = ath10k_pci_start_intr_legacy(ar);
+        if (ret) {
+                ath10k_warn("Failed to start legacy interrupts: %d\n", ret);
+                return ret;
+        }
 
 exit:
         ar_pci->num_msi_intrs = num;
@@ -2243,13 +2257,19 @@ static int ath10k_pci_reset_target(struct ath10k *ar)
 {
         struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
         int wait_limit = 300; /* 3 sec */
+        int ret;
 
         /* Wait for Target to finish initialization before we proceed. */
         iowrite32(PCIE_SOC_WAKE_V_MASK,
                   ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
                   PCIE_SOC_WAKE_ADDRESS);
 
-        ath10k_pci_wait(ar);
+        ret = ath10k_pci_wait(ar);
+        if (ret) {
+                ath10k_warn("Failed to reset target, target did not wake up: %d\n",
+                            ret);
+                return ret;
+        }
 
         while (wait_limit-- &&
                !(ioread32(ar_pci->mem + FW_INDICATOR_ADDRESS) &