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authorStefan Sørensen <stefan.sorensen@spectralink.com>2014-06-27 06:05:30 -0400
committerDavid S. Miller <davem@davemloft.net>2014-07-01 21:52:53 -0400
commitad01577aeb92d7cc72bb945aeb28def3749065da (patch)
tree965b1ab7f068d387bdc8a5a4c6cf4807c1ca5a3e /drivers/net/phy/dp83640.c
parent35e872ae6330e72c1b6045c021314b32a4a047de (diff)
dp83640: Increase supported perout pins to 7
This patch increases the number of supported periodic output pins from 1 to 7. The last pin is reserved for sync. Signed-off-by: Stefan Sørensen <stefan.sorensen@spectralink.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/phy/dp83640.c')
-rw-r--r--drivers/net/phy/dp83640.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/net/phy/dp83640.c b/drivers/net/phy/dp83640.c
index fcd50b77999f..eabecff9b740 100644
--- a/drivers/net/phy/dp83640.c
+++ b/drivers/net/phy/dp83640.c
@@ -40,6 +40,7 @@
40#define LAYER2 0x01 40#define LAYER2 0x01
41#define MAX_RXTS 64 41#define MAX_RXTS 64
42#define N_EXT_TS 6 42#define N_EXT_TS 6
43#define N_PER_OUT 7
43#define PSF_PTPVER 2 44#define PSF_PTPVER 2
44#define PSF_EVNT 0x4000 45#define PSF_EVNT 0x4000
45#define PSF_RX 0x2000 46#define PSF_RX 0x2000
@@ -47,7 +48,6 @@
47#define EXT_EVENT 1 48#define EXT_EVENT 1
48#define CAL_EVENT 7 49#define CAL_EVENT 7
49#define CAL_TRIGGER 7 50#define CAL_TRIGGER 7
50#define PER_TRIGGER 6
51#define DP83640_N_PINS 12 51#define DP83640_N_PINS 12
52 52
53#define MII_DP83640_MICR 0x11 53#define MII_DP83640_MICR 0x11
@@ -300,23 +300,23 @@ static u64 phy2txts(struct phy_txts *p)
300} 300}
301 301
302static int periodic_output(struct dp83640_clock *clock, 302static int periodic_output(struct dp83640_clock *clock,
303 struct ptp_clock_request *clkreq, bool on) 303 struct ptp_clock_request *clkreq, bool on,
304 int trigger)
304{ 305{
305 struct dp83640_private *dp83640 = clock->chosen; 306 struct dp83640_private *dp83640 = clock->chosen;
306 struct phy_device *phydev = dp83640->phydev; 307 struct phy_device *phydev = dp83640->phydev;
307 u32 sec, nsec, pwidth; 308 u32 sec, nsec, pwidth;
308 u16 gpio, ptp_trig, trigger, val; 309 u16 gpio, ptp_trig, val;
309 310
310 if (on) { 311 if (on) {
311 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT, 0); 312 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT,
313 trigger);
312 if (gpio < 1) 314 if (gpio < 1)
313 return -EINVAL; 315 return -EINVAL;
314 } else { 316 } else {
315 gpio = 0; 317 gpio = 0;
316 } 318 }
317 319
318 trigger = PER_TRIGGER;
319
320 ptp_trig = TRIG_WR | 320 ptp_trig = TRIG_WR |
321 (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT | 321 (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT |
322 (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT | 322 (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT |
@@ -496,9 +496,9 @@ static int ptp_dp83640_enable(struct ptp_clock_info *ptp,
496 return 0; 496 return 0;
497 497
498 case PTP_CLK_REQ_PEROUT: 498 case PTP_CLK_REQ_PEROUT:
499 if (rq->perout.index != 0) 499 if (rq->perout.index >= N_PER_OUT)
500 return -EINVAL; 500 return -EINVAL;
501 return periodic_output(clock, rq, on); 501 return periodic_output(clock, rq, on, rq->perout.index);
502 502
503 default: 503 default:
504 break; 504 break;
@@ -949,7 +949,7 @@ static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus)
949 clock->caps.max_adj = 1953124; 949 clock->caps.max_adj = 1953124;
950 clock->caps.n_alarm = 0; 950 clock->caps.n_alarm = 0;
951 clock->caps.n_ext_ts = N_EXT_TS; 951 clock->caps.n_ext_ts = N_EXT_TS;
952 clock->caps.n_per_out = 1; 952 clock->caps.n_per_out = N_PER_OUT;
953 clock->caps.n_pins = DP83640_N_PINS; 953 clock->caps.n_pins = DP83640_N_PINS;
954 clock->caps.pps = 0; 954 clock->caps.pps = 0;
955 clock->caps.adjfreq = ptp_dp83640_adjfreq; 955 clock->caps.adjfreq = ptp_dp83640_adjfreq;