diff options
author | Alvaro G. M <alvaro.gamez@hazent.com> | 2017-07-17 03:12:28 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2017-07-17 11:51:57 -0400 |
commit | ee06b1728b95643668e40fc58ae118aeb7c1753e (patch) | |
tree | d4864bc4af0c07c4996624982fceef6905e5d8fd /drivers/net/ethernet/xilinx/xilinx_axienet_main.c | |
parent | a288855151546d1026c8f94728084c1173126a01 (diff) |
net: axienet: add support for standard phy-mode binding
Keep supporting proprietary "xlnx,phy-type" attribute and add support for
MII connectivity to the PHY.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Alvaro Gamez Machado <alvaro.gamez@hazent.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/xilinx/xilinx_axienet_main.c')
-rw-r--r-- | drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 48 |
1 files changed, 36 insertions, 12 deletions
diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c index 33c595f4691d..e74e1e897864 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c | |||
@@ -531,11 +531,11 @@ static void axienet_adjust_link(struct net_device *ndev) | |||
531 | link_state = phy->speed | (phy->duplex << 1) | phy->link; | 531 | link_state = phy->speed | (phy->duplex << 1) | phy->link; |
532 | if (lp->last_link != link_state) { | 532 | if (lp->last_link != link_state) { |
533 | if ((phy->speed == SPEED_10) || (phy->speed == SPEED_100)) { | 533 | if ((phy->speed == SPEED_10) || (phy->speed == SPEED_100)) { |
534 | if (lp->phy_type == XAE_PHY_TYPE_1000BASE_X) | 534 | if (lp->phy_mode == PHY_INTERFACE_MODE_1000BASEX) |
535 | setspeed = 0; | 535 | setspeed = 0; |
536 | } else { | 536 | } else { |
537 | if ((phy->speed == SPEED_1000) && | 537 | if ((phy->speed == SPEED_1000) && |
538 | (lp->phy_type == XAE_PHY_TYPE_MII)) | 538 | (lp->phy_mode == PHY_INTERFACE_MODE_MII)) |
539 | setspeed = 0; | 539 | setspeed = 0; |
540 | } | 540 | } |
541 | 541 | ||
@@ -935,15 +935,8 @@ static int axienet_open(struct net_device *ndev) | |||
935 | return ret; | 935 | return ret; |
936 | 936 | ||
937 | if (lp->phy_node) { | 937 | if (lp->phy_node) { |
938 | if (lp->phy_type == XAE_PHY_TYPE_GMII) { | 938 | phydev = of_phy_connect(lp->ndev, lp->phy_node, |
939 | phydev = of_phy_connect(lp->ndev, lp->phy_node, | 939 | axienet_adjust_link, 0, lp->phy_mode); |
940 | axienet_adjust_link, 0, | ||
941 | PHY_INTERFACE_MODE_GMII); | ||
942 | } else if (lp->phy_type == XAE_PHY_TYPE_RGMII_2_0) { | ||
943 | phydev = of_phy_connect(lp->ndev, lp->phy_node, | ||
944 | axienet_adjust_link, 0, | ||
945 | PHY_INTERFACE_MODE_RGMII_ID); | ||
946 | } | ||
947 | 940 | ||
948 | if (!phydev) | 941 | if (!phydev) |
949 | dev_err(lp->dev, "of_phy_connect() failed\n"); | 942 | dev_err(lp->dev, "of_phy_connect() failed\n"); |
@@ -1539,7 +1532,38 @@ static int axienet_probe(struct platform_device *pdev) | |||
1539 | * the device-tree and accordingly set flags. | 1532 | * the device-tree and accordingly set flags. |
1540 | */ | 1533 | */ |
1541 | of_property_read_u32(pdev->dev.of_node, "xlnx,rxmem", &lp->rxmem); | 1534 | of_property_read_u32(pdev->dev.of_node, "xlnx,rxmem", &lp->rxmem); |
1542 | of_property_read_u32(pdev->dev.of_node, "xlnx,phy-type", &lp->phy_type); | 1535 | |
1536 | /* Start with the proprietary, and broken phy_type */ | ||
1537 | ret = of_property_read_u32(pdev->dev.of_node, "xlnx,phy-type", &value); | ||
1538 | if (!ret) { | ||
1539 | netdev_warn(ndev, "Please upgrade your device tree binary blob to use phy-mode"); | ||
1540 | switch (value) { | ||
1541 | case XAE_PHY_TYPE_MII: | ||
1542 | lp->phy_mode = PHY_INTERFACE_MODE_MII; | ||
1543 | break; | ||
1544 | case XAE_PHY_TYPE_GMII: | ||
1545 | lp->phy_mode = PHY_INTERFACE_MODE_GMII; | ||
1546 | break; | ||
1547 | case XAE_PHY_TYPE_RGMII_2_0: | ||
1548 | lp->phy_mode = PHY_INTERFACE_MODE_RGMII_ID; | ||
1549 | break; | ||
1550 | case XAE_PHY_TYPE_SGMII: | ||
1551 | lp->phy_mode = PHY_INTERFACE_MODE_SGMII; | ||
1552 | break; | ||
1553 | case XAE_PHY_TYPE_1000BASE_X: | ||
1554 | lp->phy_mode = PHY_INTERFACE_MODE_1000BASEX; | ||
1555 | break; | ||
1556 | default: | ||
1557 | ret = -EINVAL; | ||
1558 | goto free_netdev; | ||
1559 | } | ||
1560 | } else { | ||
1561 | lp->phy_mode = of_get_phy_mode(pdev->dev.of_node); | ||
1562 | if (lp->phy_mode < 0) { | ||
1563 | ret = -EINVAL; | ||
1564 | goto free_netdev; | ||
1565 | } | ||
1566 | } | ||
1543 | 1567 | ||
1544 | /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */ | 1568 | /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */ |
1545 | np = of_parse_phandle(pdev->dev.of_node, "axistream-connected", 0); | 1569 | np = of_parse_phandle(pdev->dev.of_node, "axistream-connected", 0); |