sfc: Allocate SRAM between buffer table and descriptor caches at init time

Each port has a block of 64-bit SRAM that is divided between buffer
table and descriptor cache regions at initialisation time.  Currently
we use a fixed allocation, but it needs to be changed to support
larger numbers of queues.

Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>

1 files changed, 19 insertions, 4 deletions

diff --git a/drivers/net/ethernet/sfc/nic.c b/drivers/net/ethernet/sfc/nic.c
index 2bdfb6374ce8..747cf9439164 100644
--- a/drivers/net/ethernet/sfc/nic.c
+++ b/drivers/net/ethernet/sfc/nic.c
@@ -1609,6 +1609,23 @@ void efx_nic_fini_interrupt(struct efx_nic *efx)
                 free_irq(efx->legacy_irq, efx);
 }
 
+void efx_nic_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw)
+{
+        unsigned vi_count, buftbl_min;
+
+        /* Account for the buffer table entries backing the datapath channels
+         * and the descriptor caches for those channels.
+         */
+        buftbl_min = ((efx->n_rx_channels * EFX_MAX_DMAQ_SIZE +
+                       efx->n_tx_channels * EFX_TXQ_TYPES * EFX_MAX_DMAQ_SIZE +
+                       efx->n_channels * EFX_MAX_EVQ_SIZE)
+                      * sizeof(efx_qword_t) / EFX_BUF_SIZE);
+        vi_count = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
+
+        efx->tx_dc_base = sram_lim_qw - vi_count * TX_DC_ENTRIES;
+        efx->rx_dc_base = efx->tx_dc_base - vi_count * RX_DC_ENTRIES;
+}
+
 u32 efx_nic_fpga_ver(struct efx_nic *efx)
 {
         efx_oword_t altera_build;
@@ -1621,11 +1638,9 @@ void efx_nic_init_common(struct efx_nic *efx)
         efx_oword_t temp;
 
         /* Set positions of descriptor caches in SRAM. */
-        EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR,
-                             efx->type->tx_dc_base / 8);
+        EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, efx->tx_dc_base);
         efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
-        EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR,
-                             efx->type->rx_dc_base / 8);
+        EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, efx->rx_dc_base);
         efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
 
         /* Set TX descriptor cache size. */