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authorJesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>2018-07-03 18:42:59 -0400
committerDavid S. Miller <davem@davemloft.net>2018-07-04 09:30:28 -0400
commit3048cf84d152344f874e993558770bba73a65c8f (patch)
tree0868b2697eef23b320c513bb5daccece9ccf477f /drivers/net/ethernet/intel/igb/igb_main.c
parent1b9231e7e148520a3ba63a604b27f11093f21bee (diff)
igb: Add support for ETF offload
Implement HW offload support for SO_TXTIME through igb's Launchtime feature. This is done by extending igb_setup_tc() so it supports TC_SETUP_QDISC_ETF and configuring i210 so time based transmit arbitration is enabled. The FQTSS transmission mode added before is extended so strict priority (SP) queues wait for stream reservation (SR) ones. igb_config_tx_modes() is extended so it can support enabling/disabling Launchtime following the previous approach used for the credit-based shaper (CBS). As the previous flow, FQTSS transmission mode is enabled automatically by the driver once Launchtime (or CBS, as before) is enabled. Similarly, it's automatically disabled when the feature is disabled for the last queue that had it setup on. The driver just consumes the transmit times from the skbuffs directly, so no special handling is done in case an 'invalid' time is provided. We assume this has been handled by the ETF qdisc already. Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/intel/igb/igb_main.c')
-rw-r--r--drivers/net/ethernet/intel/igb/igb_main.c138
1 files changed, 121 insertions, 17 deletions
diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c
index 445da8285d9b..e3a0c02721c9 100644
--- a/drivers/net/ethernet/intel/igb/igb_main.c
+++ b/drivers/net/ethernet/intel/igb/igb_main.c
@@ -1666,13 +1666,26 @@ static bool is_any_cbs_enabled(struct igb_adapter *adapter)
1666 return false; 1666 return false;
1667} 1667}
1668 1668
1669static bool is_any_txtime_enabled(struct igb_adapter *adapter)
1670{
1671 int i;
1672
1673 for (i = 0; i < adapter->num_tx_queues; i++) {
1674 if (adapter->tx_ring[i]->launchtime_enable)
1675 return true;
1676 }
1677
1678 return false;
1679}
1680
1669/** 1681/**
1670 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb 1682 * igb_config_tx_modes - Configure "Qav Tx mode" features on igb
1671 * @adapter: pointer to adapter struct 1683 * @adapter: pointer to adapter struct
1672 * @queue: queue number 1684 * @queue: queue number
1673 * 1685 *
1674 * Configure CBS for a given hardware queue. Parameters are retrieved 1686 * Configure CBS and Launchtime for a given hardware queue.
1675 * from the correct Tx ring, so igb_save_cbs_params() should be used 1687 * Parameters are retrieved from the correct Tx ring, so
1688 * igb_save_cbs_params() and igb_save_txtime_params() should be used
1676 * for setting those correctly prior to this function being called. 1689 * for setting those correctly prior to this function being called.
1677 **/ 1690 **/
1678static void igb_config_tx_modes(struct igb_adapter *adapter, int queue) 1691static void igb_config_tx_modes(struct igb_adapter *adapter, int queue)
@@ -1686,6 +1699,19 @@ static void igb_config_tx_modes(struct igb_adapter *adapter, int queue)
1686 WARN_ON(hw->mac.type != e1000_i210); 1699 WARN_ON(hw->mac.type != e1000_i210);
1687 WARN_ON(queue < 0 || queue > 1); 1700 WARN_ON(queue < 0 || queue > 1);
1688 1701
1702 /* If any of the Qav features is enabled, configure queues as SR and
1703 * with HIGH PRIO. If none is, then configure them with LOW PRIO and
1704 * as SP.
1705 */
1706 if (ring->cbs_enable || ring->launchtime_enable) {
1707 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH);
1708 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION);
1709 } else {
1710 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW);
1711 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY);
1712 }
1713
1714 /* If CBS is enabled, set DataTranARB and config its parameters. */
1689 if (ring->cbs_enable || queue == 0) { 1715 if (ring->cbs_enable || queue == 0) {
1690 /* i210 does not allow the queue 0 to be in the Strict 1716 /* i210 does not allow the queue 0 to be in the Strict
1691 * Priority mode while the Qav mode is enabled, so, 1717 * Priority mode while the Qav mode is enabled, so,
@@ -1702,9 +1728,6 @@ static void igb_config_tx_modes(struct igb_adapter *adapter, int queue)
1702 ring->hicredit = ETH_FRAME_LEN; 1728 ring->hicredit = ETH_FRAME_LEN;
1703 } 1729 }
1704 1730
1705 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH);
1706 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION);
1707
1708 /* Always set data transfer arbitration to credit-based 1731 /* Always set data transfer arbitration to credit-based
1709 * shaper algorithm on TQAVCTRL if CBS is enabled for any of 1732 * shaper algorithm on TQAVCTRL if CBS is enabled for any of
1710 * the queues. 1733 * the queues.
@@ -1780,8 +1803,6 @@ static void igb_config_tx_modes(struct igb_adapter *adapter, int queue)
1780 wr32(E1000_I210_TQAVHC(queue), 1803 wr32(E1000_I210_TQAVHC(queue),
1781 0x80000000 + ring->hicredit * 0x7735); 1804 0x80000000 + ring->hicredit * 0x7735);
1782 } else { 1805 } else {
1783 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW);
1784 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY);
1785 1806
1786 /* Set idleSlope to zero. */ 1807 /* Set idleSlope to zero. */
1787 tqavcc = rd32(E1000_I210_TQAVCC(queue)); 1808 tqavcc = rd32(E1000_I210_TQAVCC(queue));
@@ -1802,17 +1823,61 @@ static void igb_config_tx_modes(struct igb_adapter *adapter, int queue)
1802 } 1823 }
1803 } 1824 }
1804 1825
1826 /* If LaunchTime is enabled, set DataTranTIM. */
1827 if (ring->launchtime_enable) {
1828 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled
1829 * for any of the SR queues, and configure fetchtime delta.
1830 * XXX NOTE:
1831 * - LaunchTime will be enabled for all SR queues.
1832 * - A fixed offset can be added relative to the launch
1833 * time of all packets if configured at reg LAUNCH_OS0.
1834 * We are keeping it as 0 for now (default value).
1835 */
1836 tqavctrl = rd32(E1000_I210_TQAVCTRL);
1837 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM |
1838 E1000_TQAVCTRL_FETCHTIME_DELTA;
1839 wr32(E1000_I210_TQAVCTRL, tqavctrl);
1840 } else {
1841 /* If Launchtime is not enabled for any SR queues anymore,
1842 * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta,
1843 * effectively disabling Launchtime.
1844 */
1845 if (!is_any_txtime_enabled(adapter)) {
1846 tqavctrl = rd32(E1000_I210_TQAVCTRL);
1847 tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM;
1848 tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA;
1849 wr32(E1000_I210_TQAVCTRL, tqavctrl);
1850 }
1851 }
1852
1805 /* XXX: In i210 controller the sendSlope and loCredit parameters from 1853 /* XXX: In i210 controller the sendSlope and loCredit parameters from
1806 * CBS are not configurable by software so we don't do any 'controller 1854 * CBS are not configurable by software so we don't do any 'controller
1807 * configuration' in respect to these parameters. 1855 * configuration' in respect to these parameters.
1808 */ 1856 */
1809 1857
1810 netdev_dbg(netdev, "CBS %s: queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n", 1858 netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d \
1811 (ring->cbs_enable) ? "enabled" : "disabled", queue, 1859 idleslope %d sendslope %d hiCredit %d \
1860 locredit %d\n",
1861 (ring->cbs_enable) ? "enabled" : "disabled",
1862 (ring->launchtime_enable) ? "enabled" : "disabled", queue,
1812 ring->idleslope, ring->sendslope, ring->hicredit, 1863 ring->idleslope, ring->sendslope, ring->hicredit,
1813 ring->locredit); 1864 ring->locredit);
1814} 1865}
1815 1866
1867static int igb_save_txtime_params(struct igb_adapter *adapter, int queue,
1868 bool enable)
1869{
1870 struct igb_ring *ring;
1871
1872 if (queue < 0 || queue > adapter->num_tx_queues)
1873 return -EINVAL;
1874
1875 ring = adapter->tx_ring[queue];
1876 ring->launchtime_enable = enable;
1877
1878 return 0;
1879}
1880
1816static int igb_save_cbs_params(struct igb_adapter *adapter, int queue, 1881static int igb_save_cbs_params(struct igb_adapter *adapter, int queue,
1817 bool enable, int idleslope, int sendslope, 1882 bool enable, int idleslope, int sendslope,
1818 int hicredit, int locredit) 1883 int hicredit, int locredit)
@@ -1856,10 +1921,11 @@ static void igb_setup_tx_mode(struct igb_adapter *adapter)
1856 int i, max_queue; 1921 int i, max_queue;
1857 1922
1858 /* Configure TQAVCTRL register: set transmit mode to 'Qav', 1923 /* Configure TQAVCTRL register: set transmit mode to 'Qav',
1859 * set data fetch arbitration to 'round robin'. 1924 * set data fetch arbitration to 'round robin', set SP_WAIT_SR
1925 * so SP queues wait for SR ones.
1860 */ 1926 */
1861 val = rd32(E1000_I210_TQAVCTRL); 1927 val = rd32(E1000_I210_TQAVCTRL);
1862 val |= E1000_TQAVCTRL_XMIT_MODE; 1928 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR;
1863 val &= ~E1000_TQAVCTRL_DATAFETCHARB; 1929 val &= ~E1000_TQAVCTRL_DATAFETCHARB;
1864 wr32(E1000_I210_TQAVCTRL, val); 1930 wr32(E1000_I210_TQAVCTRL, val);
1865 1931
@@ -2483,7 +2549,7 @@ static void igb_offload_apply(struct igb_adapter *adapter, s32 queue)
2483 2549
2484 igb_config_tx_modes(adapter, queue); 2550 igb_config_tx_modes(adapter, queue);
2485 2551
2486 if (!is_any_cbs_enabled(adapter)) 2552 if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter))
2487 enable_fqtss(adapter, false); 2553 enable_fqtss(adapter, false);
2488} 2554}
2489 2555
@@ -2756,6 +2822,29 @@ static int igb_setup_tc_block(struct igb_adapter *adapter,
2756 } 2822 }
2757} 2823}
2758 2824
2825static int igb_offload_txtime(struct igb_adapter *adapter,
2826 struct tc_etf_qopt_offload *qopt)
2827{
2828 struct e1000_hw *hw = &adapter->hw;
2829 int err;
2830
2831 /* Launchtime offloading is only supported by i210 controller. */
2832 if (hw->mac.type != e1000_i210)
2833 return -EOPNOTSUPP;
2834
2835 /* Launchtime offloading is only supported by queues 0 and 1. */
2836 if (qopt->queue < 0 || qopt->queue > 1)
2837 return -EINVAL;
2838
2839 err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable);
2840 if (err)
2841 return err;
2842
2843 igb_offload_apply(adapter, qopt->queue);
2844
2845 return 0;
2846}
2847
2759static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type, 2848static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type,
2760 void *type_data) 2849 void *type_data)
2761{ 2850{
@@ -2766,6 +2855,8 @@ static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type,
2766 return igb_offload_cbs(adapter, type_data); 2855 return igb_offload_cbs(adapter, type_data);
2767 case TC_SETUP_BLOCK: 2856 case TC_SETUP_BLOCK:
2768 return igb_setup_tc_block(adapter, type_data); 2857 return igb_setup_tc_block(adapter, type_data);
2858 case TC_SETUP_QDISC_ETF:
2859 return igb_offload_txtime(adapter, type_data);
2769 2860
2770 default: 2861 default:
2771 return -EOPNOTSUPP; 2862 return -EOPNOTSUPP;
@@ -5586,11 +5677,14 @@ set_itr_now:
5586 } 5677 }
5587} 5678}
5588 5679
5589static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, 5680static void igb_tx_ctxtdesc(struct igb_ring *tx_ring,
5590 u32 type_tucmd, u32 mss_l4len_idx) 5681 struct igb_tx_buffer *first,
5682 u32 vlan_macip_lens, u32 type_tucmd,
5683 u32 mss_l4len_idx)
5591{ 5684{
5592 struct e1000_adv_tx_context_desc *context_desc; 5685 struct e1000_adv_tx_context_desc *context_desc;
5593 u16 i = tx_ring->next_to_use; 5686 u16 i = tx_ring->next_to_use;
5687 struct timespec64 ts;
5594 5688
5595 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 5689 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
5596 5690
@@ -5605,9 +5699,18 @@ static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
5605 mss_l4len_idx |= tx_ring->reg_idx << 4; 5699 mss_l4len_idx |= tx_ring->reg_idx << 4;
5606 5700
5607 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 5701 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5608 context_desc->seqnum_seed = 0;
5609 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 5702 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
5610 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 5703 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5704
5705 /* We assume there is always a valid tx time available. Invalid times
5706 * should have been handled by the upper layers.
5707 */
5708 if (tx_ring->launchtime_enable) {
5709 ts = ns_to_timespec64(first->skb->tstamp);
5710 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32);
5711 } else {
5712 context_desc->seqnum_seed = 0;
5713 }
5611} 5714}
5612 5715
5613static int igb_tso(struct igb_ring *tx_ring, 5716static int igb_tso(struct igb_ring *tx_ring,
@@ -5690,7 +5793,8 @@ static int igb_tso(struct igb_ring *tx_ring,
5690 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT; 5793 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT;
5691 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5794 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
5692 5795
5693 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 5796 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens,
5797 type_tucmd, mss_l4len_idx);
5694 5798
5695 return 1; 5799 return 1;
5696} 5800}
@@ -5745,7 +5849,7 @@ no_csum:
5745 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 5849 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
5746 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 5850 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
5747 5851
5748 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, 0); 5852 igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0);
5749} 5853}
5750 5854
5751#define IGB_SET_FLAG(_input, _flag, _result) \ 5855#define IGB_SET_FLAG(_input, _flag, _result) \