igb: Clear TSICR interrupts together with ICR

Issuing "ip link set up/down" can block TSICR interrupts, what results in
missing PTP Tx timestamp and no PPS pulse generation.

Problem happens when the link is set up with the TSICR interrupts pending.
ICR is cleared before enabling interrupts, while TSICR is not. When all TSICR
interrupts are pending at this moment, time_sync interrupt will never
be generated. TSICR should be cleared as well.

In order to reproduce the issue:
1. Setup linux with IEEE 1588 grandmaster and PPS output enabled
2. Continue setting link up/down with random intervals between commands
3. Wait until PPS is not generated ( only one pulse is generated and PPS
dies), and ptp4l complains constantly about Tx timeout.

Signed-off-by: Joanna Yurdal <jyu@trackman.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c
index 78574c06635b..20b728218d20 100644
--- a/drivers/net/ethernet/intel/igb/igb_main.c
+++ b/drivers/net/ethernet/intel/igb/igb_main.c
@@ -2058,6 +2058,7 @@ int igb_up(struct igb_adapter *adapter)
                 igb_assign_vector(adapter->q_vector[0], 0);
 
         /* Clear any pending interrupts. */
+        rd32(E1000_TSICR);
         rd32(E1000_ICR);
         igb_irq_enable(adapter);
 
@@ -3865,6 +3866,7 @@ static int __igb_open(struct net_device *netdev, bool resuming)
                 napi_enable(&(adapter->q_vector[i]->napi));
 
         /* Clear any pending interrupts. */
+        rd32(E1000_TSICR);
         rd32(E1000_ICR);
 
         igb_irq_enable(adapter);