ice: Remove runtime change of PFINT_OICR_ENA register

Runtime change of PFINT_OICR_ENA register is unnecessary.
The handlers should always clear the atomic bit for each
task as they start, because it will make sure that any late
interrupt will either 1) re-set the bit, or 2) be handled
directly in the "already running" task handler.

Signed-off-by: Md Fahad Iqbal Polash <md.fahad.iqbal.polash@intel.com>
Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

1 files changed, 2 insertions, 11 deletions

diff --git a/drivers/net/ethernet/intel/ice/ice_main.c b/drivers/net/ethernet/intel/ice/ice_main.c
index a32782be7f88..8f6f2a1e67ed 100644
--- a/drivers/net/ethernet/intel/ice/ice_main.c
+++ b/drivers/net/ethernet/intel/ice/ice_main.c
@@ -1096,7 +1096,7 @@ static void ice_handle_mdd_event(struct ice_pf *pf)
         u32 reg;
         int i;
 
-        if (!test_bit(__ICE_MDD_EVENT_PENDING, pf->state))
+        if (!test_and_clear_bit(__ICE_MDD_EVENT_PENDING, pf->state))
                 return;
 
         /* find what triggered the MDD event */
@@ -1229,12 +1229,6 @@ static void ice_handle_mdd_event(struct ice_pf *pf)
                 }
         }
 
-        /* re-enable MDD interrupt cause */
-        clear_bit(__ICE_MDD_EVENT_PENDING, pf->state);
-        reg = rd32(hw, PFINT_OICR_ENA);
-        reg |= PFINT_OICR_MAL_DETECT_M;
-        wr32(hw, PFINT_OICR_ENA, reg);
-        ice_flush(hw);
 }
 
 /**
@@ -1523,7 +1517,7 @@ static irqreturn_t ice_misc_intr(int __always_unused irq, void *data)
                         rd32(hw, PFHMC_ERRORDATA));
         }
 
-        /* Report and mask off any remaining unexpected interrupts */
+        /* Report any remaining unexpected interrupts */
         oicr &= ena_mask;
         if (oicr) {
                 dev_dbg(&pf->pdev->dev, "unhandled interrupt oicr=0x%08x\n",
@@ -1537,12 +1531,9 @@ static irqreturn_t ice_misc_intr(int __always_unused irq, void *data)
                         set_bit(__ICE_PFR_REQ, pf->state);
                         ice_service_task_schedule(pf);
                 }
-                ena_mask &= ~oicr;
         }
         ret = IRQ_HANDLED;
 
-        /* re-enable interrupt causes that are not handled during this pass */
-        wr32(hw, PFINT_OICR_ENA, ena_mask);
         if (!test_bit(__ICE_DOWN, pf->state)) {
                 ice_service_task_schedule(pf);
                 ice_irq_dynamic_ena(hw, NULL, NULL);