ice: Add more validation in ice_vc_cfg_irq_map_msg

Add few checks to validate msg from iavf driver.

Test if we have got enough q_vectors allocated in VSI connected with VF.
Add masks for itr_indx and msix_indx to avoid writing to reserved fieldi
of QINT. Clear q_vector->num_ring_rx/tx, without it we can increment this
value every time we send irq map msg from VF. So after second call this
value will be incorrect.

Decrement num_vectors from msg, because last vector in iavf msg is misc
vector (we don't set map for it).

Signed-off-by: Michal Swiatkowski <michal.swiatkowski@intel.com>
Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

1 files changed, 18 insertions, 14 deletions

diff --git a/drivers/net/ethernet/intel/ice/ice_lib.c b/drivers/net/ethernet/intel/ice/ice_lib.c
index 83d0aef7f77e..caa00e8873ec 100644
--- a/drivers/net/ethernet/intel/ice/ice_lib.c
+++ b/drivers/net/ethernet/intel/ice/ice_lib.c
@@ -1879,33 +1879,37 @@ void ice_vsi_cfg_msix(struct ice_vsi *vsi)
                  * tracked for this PF.
                  */
                 for (q = 0; q < q_vector->num_ring_tx; q++) {
-                        int itr_idx = q_vector->tx.itr_idx;
+                        int itr_idx = (q_vector->tx.itr_idx <<
+                                       QINT_TQCTL_ITR_INDX_S) &
+                                QINT_TQCTL_ITR_INDX_M;
                         u32 val;
 
                         if (vsi->type == ICE_VSI_VF)
-                                val = QINT_TQCTL_CAUSE_ENA_M |
-                                      (itr_idx << QINT_TQCTL_ITR_INDX_S)  |
-                                      ((i + 1) << QINT_TQCTL_MSIX_INDX_S);
+                                val = QINT_TQCTL_CAUSE_ENA_M | itr_idx |
+                                      (((i + 1) << QINT_TQCTL_MSIX_INDX_S) &
+                                       QINT_TQCTL_MSIX_INDX_M);
                         else
-                                val = QINT_TQCTL_CAUSE_ENA_M |
-                                      (itr_idx << QINT_TQCTL_ITR_INDX_S)  |
-                                      (reg_idx << QINT_TQCTL_MSIX_INDX_S);
+                                val = QINT_TQCTL_CAUSE_ENA_M | itr_idx |
+                                      ((reg_idx << QINT_TQCTL_MSIX_INDX_S) &
+                                       QINT_TQCTL_MSIX_INDX_M);
                         wr32(hw, QINT_TQCTL(vsi->txq_map[txq]), val);
                         txq++;
                 }
 
                 for (q = 0; q < q_vector->num_ring_rx; q++) {
-                        int itr_idx = q_vector->rx.itr_idx;
+                        int itr_idx = (q_vector->rx.itr_idx <<
+                                       QINT_RQCTL_ITR_INDX_S) &
+                                QINT_RQCTL_ITR_INDX_M;
                         u32 val;
 
                         if (vsi->type == ICE_VSI_VF)
-                                val = QINT_RQCTL_CAUSE_ENA_M |
-                                      (itr_idx << QINT_RQCTL_ITR_INDX_S)  |
-                                      ((i + 1) << QINT_RQCTL_MSIX_INDX_S);
+                                val = QINT_RQCTL_CAUSE_ENA_M | itr_idx |
+                                        (((i + 1) << QINT_RQCTL_MSIX_INDX_S) &
+                                         QINT_RQCTL_MSIX_INDX_M);
                         else
-                                val = QINT_RQCTL_CAUSE_ENA_M |
-                                      (itr_idx << QINT_RQCTL_ITR_INDX_S)  |
-                                      (reg_idx << QINT_RQCTL_MSIX_INDX_S);
+                                val = QINT_RQCTL_CAUSE_ENA_M | itr_idx |
+                                        ((reg_idx << QINT_RQCTL_MSIX_INDX_S) &
+                                         QINT_RQCTL_MSIX_INDX_M);
                         wr32(hw, QINT_RQCTL(vsi->rxq_map[rxq]), val);
                         rxq++;
                 }