aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/ethernet/intel/ice/ice_lib.c
diff options
context:
space:
mode:
authorBrett Creeley <brett.creeley@intel.com>2019-02-19 18:04:05 -0500
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2019-03-26 18:03:25 -0400
commit8244dd2d23b251dcba3238e42216e9277beb5729 (patch)
tree2daf864216a31bd9cea13bbd02ecc936652b75eb /drivers/net/ethernet/intel/ice/ice_lib.c
parent89f3e4a5b762db66de94c44cfea11195f9d549b3 (diff)
ice: Audit hotpath structures with pahole
Currently the ice_q_vector structure and ice_ring_container structure are taking up more space than necessary due to cache alignment holes and unnecessary variables respectively. This is not helping the driver's performance. The following fixes were done to improve cache alignment, reduce wasted space, and increase performance. 1. Remove the ice_latency_range enum as it is unused. 2. Remove the latency_range variable in the ice_ring_container structure. 3. Change the size of the itr_idx in the ice_ring_container structure from an int to an u16. This reduced the size of ice_ring_container structure to 32 Bytes so it has no holes or padding. 4. Re-arrange the ice_q_vector structure using pahole to align members as best as possible in regards to 64 Byte cache line size. Signed-off-by: Brett Creeley <brett.creeley@intel.com> Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ethernet/intel/ice/ice_lib.c')
-rw-r--r--drivers/net/ethernet/intel/ice/ice_lib.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/drivers/net/ethernet/intel/ice/ice_lib.c b/drivers/net/ethernet/intel/ice/ice_lib.c
index a64db22e6ba4..bf0160b6d6ac 100644
--- a/drivers/net/ethernet/intel/ice/ice_lib.c
+++ b/drivers/net/ethernet/intel/ice/ice_lib.c
@@ -1820,7 +1820,6 @@ ice_cfg_itr(struct ice_hw *hw, struct ice_q_vector *q_vector, u16 vector)
1820 rc->target_itr = ITR_TO_REG(rc->itr_setting); 1820 rc->target_itr = ITR_TO_REG(rc->itr_setting);
1821 rc->next_update = jiffies + 1; 1821 rc->next_update = jiffies + 1;
1822 rc->current_itr = rc->target_itr; 1822 rc->current_itr = rc->target_itr;
1823 rc->latency_range = ICE_LOW_LATENCY;
1824 wr32(hw, GLINT_ITR(rc->itr_idx, vector), 1823 wr32(hw, GLINT_ITR(rc->itr_idx, vector),
1825 ITR_REG_ALIGN(rc->current_itr) >> ICE_ITR_GRAN_S); 1824 ITR_REG_ALIGN(rc->current_itr) >> ICE_ITR_GRAN_S);
1826 } 1825 }
@@ -1835,7 +1834,6 @@ ice_cfg_itr(struct ice_hw *hw, struct ice_q_vector *q_vector, u16 vector)
1835 rc->target_itr = ITR_TO_REG(rc->itr_setting); 1834 rc->target_itr = ITR_TO_REG(rc->itr_setting);
1836 rc->next_update = jiffies + 1; 1835 rc->next_update = jiffies + 1;
1837 rc->current_itr = rc->target_itr; 1836 rc->current_itr = rc->target_itr;
1838 rc->latency_range = ICE_LOW_LATENCY;
1839 wr32(hw, GLINT_ITR(rc->itr_idx, vector), 1837 wr32(hw, GLINT_ITR(rc->itr_idx, vector),
1840 ITR_REG_ALIGN(rc->current_itr) >> ICE_ITR_GRAN_S); 1838 ITR_REG_ALIGN(rc->current_itr) >> ICE_ITR_GRAN_S);
1841 } 1839 }