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authorPaweł Jabłoński <pawel.jablonski@intel.com>2018-03-19 12:28:04 -0400
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2018-03-19 12:57:52 -0400
commit12d80bca0bb7178bc85a32e19795ff249a5903ad (patch)
treee703d38c8451ce06aa5e97db1398e029e311e9ed /drivers/net/ethernet/intel/i40e/i40e_common.c
parent6b9a9c26ef2f78911ee848446f845b77c45032f4 (diff)
i40e: Fix the polling mechanism of GLGEN_RSTAT.DEVSTATE
This fixes the polling mechanism of GLGEN_RSTAT.DEVSTATE in the PF Reset path when Global Reset is in progress. While the driver is polling for the end of the PF Reset and the Global Reset is triggered, abandon the PF Reset path and prepare for the upcoming Global Reset. Signed-off-by: Paweł Jabłoński <pawel.jablonski@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ethernet/intel/i40e/i40e_common.c')
-rw-r--r--drivers/net/ethernet/intel/i40e/i40e_common.c35
1 files changed, 29 insertions, 6 deletions
diff --git a/drivers/net/ethernet/intel/i40e/i40e_common.c b/drivers/net/ethernet/intel/i40e/i40e_common.c
index a40b8f37d48f..4fa31d87d9d2 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_common.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_common.c
@@ -1208,6 +1208,29 @@ static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1208 return media; 1208 return media;
1209} 1209}
1210 1210
1211/**
1212 * i40e_poll_globr - Poll for Global Reset completion
1213 * @hw: pointer to the hardware structure
1214 * @retry_limit: how many times to retry before failure
1215 **/
1216static i40e_status i40e_poll_globr(struct i40e_hw *hw,
1217 u32 retry_limit)
1218{
1219 u32 cnt, reg = 0;
1220
1221 for (cnt = 0; cnt < retry_limit; cnt++) {
1222 reg = rd32(hw, I40E_GLGEN_RSTAT);
1223 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1224 return 0;
1225 msleep(100);
1226 }
1227
1228 hw_dbg(hw, "Global reset failed.\n");
1229 hw_dbg(hw, "I40E_GLGEN_RSTAT = 0x%x\n", reg);
1230
1231 return I40E_ERR_RESET_FAILED;
1232}
1233
1211#define I40E_PF_RESET_WAIT_COUNT_A0 200 1234#define I40E_PF_RESET_WAIT_COUNT_A0 200
1212#define I40E_PF_RESET_WAIT_COUNT 200 1235#define I40E_PF_RESET_WAIT_COUNT 200
1213/** 1236/**
@@ -1284,14 +1307,14 @@ i40e_status i40e_pf_reset(struct i40e_hw *hw)
1284 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 1307 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1285 break; 1308 break;
1286 reg2 = rd32(hw, I40E_GLGEN_RSTAT); 1309 reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1287 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1310 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
1288 hw_dbg(hw, "Core reset upcoming. Skipping PF reset request.\n"); 1311 break;
1289 hw_dbg(hw, "I40E_GLGEN_RSTAT = 0x%x\n", reg2);
1290 return I40E_ERR_NOT_READY;
1291 }
1292 usleep_range(1000, 2000); 1312 usleep_range(1000, 2000);
1293 } 1313 }
1294 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 1314 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1315 if (i40e_poll_globr(hw, grst_del))
1316 return I40E_ERR_RESET_FAILED;
1317 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1295 hw_dbg(hw, "PF reset polling failed to complete.\n"); 1318 hw_dbg(hw, "PF reset polling failed to complete.\n");
1296 return I40E_ERR_RESET_FAILED; 1319 return I40E_ERR_RESET_FAILED;
1297 } 1320 }