i40e: Fix reporting of supported link modes

This patch fixes incorrect reporting of supported link modes on some NICs.

Signed-off-by: Filip Sadowski <filip.sadowski@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

1 files changed, 18 insertions, 2 deletions

diff --git a/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h b/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
index e2a9ec80a623..5d0291c1337e 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
+++ b/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
@@ -1734,6 +1734,8 @@ enum i40e_aq_phy_type {
         I40E_PHY_TYPE_10GBASE_CR1_CU            = 0xB,
         I40E_PHY_TYPE_10GBASE_AOC               = 0xC,
         I40E_PHY_TYPE_40GBASE_AOC               = 0xD,
+        I40E_PHY_TYPE_UNRECOGNIZED              = 0xE,
+        I40E_PHY_TYPE_UNSUPPORTED               = 0xF,
         I40E_PHY_TYPE_100BASE_TX                = 0x11,
         I40E_PHY_TYPE_1000BASE_T                = 0x12,
         I40E_PHY_TYPE_10GBASE_T                 = 0x13,
@@ -1752,6 +1754,8 @@ enum i40e_aq_phy_type {
         I40E_PHY_TYPE_25GBASE_CR                = 0x20,
         I40E_PHY_TYPE_25GBASE_SR                = 0x21,
         I40E_PHY_TYPE_25GBASE_LR                = 0x22,
+        I40E_PHY_TYPE_EMPTY                     = 0xFE,
+        I40E_PHY_TYPE_DEFAULT                   = 0xFF,
         I40E_PHY_TYPE_MAX
 };
 
@@ -1942,19 +1946,31 @@ struct i40e_aqc_get_link_status {
 #define I40E_AQ_25G_SERDES_UCODE_ERR    0X04
 #define I40E_AQ_25G_NIMB_UCODE_ERR      0X05
         u8      loopback; /* use defines from i40e_aqc_set_lb_mode */
+/* Since firmware API 1.7 loopback field keeps power class info as well */
+#define I40E_AQ_LOOPBACK_MASK           0x07
+#define I40E_AQ_PWR_CLASS_SHIFT_LB      6
+#define I40E_AQ_PWR_CLASS_MASK_LB       (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB)
         __le16  max_frame_size;
         u8      config;
 #define I40E_AQ_CONFIG_FEC_KR_ENA       0x01
 #define I40E_AQ_CONFIG_FEC_RS_ENA       0x02
 #define I40E_AQ_CONFIG_CRC_ENA          0x04
 #define I40E_AQ_CONFIG_PACING_MASK      0x78
-        u8      power_desc;
+        union {
+                struct {
+                        u8      power_desc;
 #define I40E_AQ_LINK_POWER_CLASS_1      0x00
 #define I40E_AQ_LINK_POWER_CLASS_2      0x01
 #define I40E_AQ_LINK_POWER_CLASS_3      0x02
 #define I40E_AQ_LINK_POWER_CLASS_4      0x03
 #define I40E_AQ_PWR_CLASS_MASK          0x03
-        u8      reserved[4];
+                        u8      reserved[4];
+                };
+                struct {
+                        u8      link_type[4];
+                        u8      link_type_ext;
+                };
+        };
 };
 
 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);