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authorMichael Chan <michael.chan@broadcom.com>2018-12-20 03:38:43 -0500
committerDavid S. Miller <davem@davemloft.net>2018-12-20 11:26:15 -0500
commit3322479e6d17ea17b75848fd7c7702ccf82c9c35 (patch)
tree6634a48cf32c92942a091f55f5d9f7f1d62953e9 /drivers/net/ethernet/broadcom
parentac68a3d3c3eba61c693d63a89223e1df8fe1f0c6 (diff)
bnxt_en: Update firmware interface spec. to 1.10.0.33.
The major changes are in the flow offload firmware APIs. Signed-off-by: Michael Chan <michael.chan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/broadcom')
-rw-r--r--drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h614
1 files changed, 502 insertions, 112 deletions
diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h b/drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h
index 5dd086059568..f1aaac8e6268 100644
--- a/drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h
+++ b/drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h
@@ -194,6 +194,8 @@ struct cmd_nums {
194 #define HWRM_STAT_CTX_QUERY 0xb2UL 194 #define HWRM_STAT_CTX_QUERY 0xb2UL
195 #define HWRM_STAT_CTX_CLR_STATS 0xb3UL 195 #define HWRM_STAT_CTX_CLR_STATS 0xb3UL
196 #define HWRM_PORT_QSTATS_EXT 0xb4UL 196 #define HWRM_PORT_QSTATS_EXT 0xb4UL
197 #define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL
198 #define HWRM_PORT_PHY_MDIO_READ 0xb6UL
197 #define HWRM_FW_RESET 0xc0UL 199 #define HWRM_FW_RESET 0xc0UL
198 #define HWRM_FW_QSTATUS 0xc1UL 200 #define HWRM_FW_QSTATUS 0xc1UL
199 #define HWRM_FW_HEALTH_CHECK 0xc2UL 201 #define HWRM_FW_HEALTH_CHECK 0xc2UL
@@ -213,6 +215,7 @@ struct cmd_nums {
213 #define HWRM_WOL_FILTER_FREE 0xf1UL 215 #define HWRM_WOL_FILTER_FREE 0xf1UL
214 #define HWRM_WOL_FILTER_QCFG 0xf2UL 216 #define HWRM_WOL_FILTER_QCFG 0xf2UL
215 #define HWRM_WOL_REASON_QCFG 0xf3UL 217 #define HWRM_WOL_REASON_QCFG 0xf3UL
218 #define HWRM_CFA_METER_QCAPS 0xf4UL
216 #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL 219 #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL
217 #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL 220 #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL
218 #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL 221 #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL
@@ -239,6 +242,24 @@ struct cmd_nums {
239 #define HWRM_FW_IPC_MSG 0x110UL 242 #define HWRM_FW_IPC_MSG 0x110UL
240 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL 243 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL
241 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL 244 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL
245 #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL
246 #define HWRM_CFA_FLOW_AGING_CFG 0x114UL
247 #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL
248 #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL
249 #define HWRM_CFA_CTX_MEM_RGTR 0x117UL
250 #define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL
251 #define HWRM_CFA_CTX_MEM_QCTX 0x119UL
252 #define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL
253 #define HWRM_CFA_COUNTER_QCAPS 0x11bUL
254 #define HWRM_CFA_COUNTER_CFG 0x11cUL
255 #define HWRM_CFA_COUNTER_QCFG 0x11dUL
256 #define HWRM_CFA_COUNTER_QSTATS 0x11eUL
257 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL
258 #define HWRM_CFA_EEM_QCAPS 0x120UL
259 #define HWRM_CFA_EEM_CFG 0x121UL
260 #define HWRM_CFA_EEM_QCFG 0x122UL
261 #define HWRM_CFA_EEM_OP 0x123UL
262 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL
242 #define HWRM_ENGINE_CKV_HELLO 0x12dUL 263 #define HWRM_ENGINE_CKV_HELLO 0x12dUL
243 #define HWRM_ENGINE_CKV_STATUS 0x12eUL 264 #define HWRM_ENGINE_CKV_STATUS 0x12eUL
244 #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL 265 #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL
@@ -335,6 +356,8 @@ struct ret_codes {
335 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL 356 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL
336 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL 357 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL
337 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL 358 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL
359 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL
360 #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL
338 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL 361 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL
339 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL 362 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL
340 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL 363 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL
@@ -363,8 +386,8 @@ struct hwrm_err_output {
363#define HWRM_VERSION_MAJOR 1 386#define HWRM_VERSION_MAJOR 1
364#define HWRM_VERSION_MINOR 10 387#define HWRM_VERSION_MINOR 10
365#define HWRM_VERSION_UPDATE 0 388#define HWRM_VERSION_UPDATE 0
366#define HWRM_VERSION_RSVD 3 389#define HWRM_VERSION_RSVD 33
367#define HWRM_VERSION_STR "1.10.0.3" 390#define HWRM_VERSION_STR "1.10.0.33"
368 391
369/* hwrm_ver_get_input (size:192b/24B) */ 392/* hwrm_ver_get_input (size:192b/24B) */
370struct hwrm_ver_get_input { 393struct hwrm_ver_get_input {
@@ -411,6 +434,10 @@ struct hwrm_ver_get_output {
411 #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL 434 #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL
412 #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL 435 #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL
413 #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL 436 #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL
437 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL
438 #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL
439 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL
440 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL
414 u8 roce_fw_maj_8b; 441 u8 roce_fw_maj_8b;
415 u8 roce_fw_min_8b; 442 u8 roce_fw_min_8b;
416 u8 roce_fw_bld_8b; 443 u8 roce_fw_bld_8b;
@@ -465,14 +492,27 @@ struct hwrm_ver_get_output {
465/* eject_cmpl (size:128b/16B) */ 492/* eject_cmpl (size:128b/16B) */
466struct eject_cmpl { 493struct eject_cmpl {
467 __le16 type; 494 __le16 type;
468 #define EJECT_CMPL_TYPE_MASK 0x3fUL 495 #define EJECT_CMPL_TYPE_MASK 0x3fUL
469 #define EJECT_CMPL_TYPE_SFT 0 496 #define EJECT_CMPL_TYPE_SFT 0
470 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 497 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL
471 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT 498 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
499 #define EJECT_CMPL_FLAGS_MASK 0xffc0UL
500 #define EJECT_CMPL_FLAGS_SFT 6
501 #define EJECT_CMPL_FLAGS_ERROR 0x40UL
472 __le16 len; 502 __le16 len;
473 __le32 opaque; 503 __le32 opaque;
474 __le32 v; 504 __le16 v;
475 #define EJECT_CMPL_V 0x1UL 505 #define EJECT_CMPL_V 0x1UL
506 #define EJECT_CMPL_ERRORS_MASK 0xfffeUL
507 #define EJECT_CMPL_ERRORS_SFT 1
508 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL
509 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
510 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1)
511 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1)
512 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1)
513 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1)
514 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
515 __le16 reserved16;
476 __le32 unused_2; 516 __le32 unused_2;
477}; 517};
478 518
@@ -552,6 +592,10 @@ struct hwrm_async_event_cmpl {
552 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL 592 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL
553 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL 593 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL
554 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL 594 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL
595 #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL
596 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL
597 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL
598 #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL
555 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 599 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL
556 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 600 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
557 __le32 event_data2; 601 __le32 event_data2;
@@ -647,6 +691,39 @@ struct hwrm_async_event_cmpl_link_speed_cfg_change {
647 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 691 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL
648}; 692};
649 693
694/* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
695struct hwrm_async_event_cmpl_reset_notify {
696 __le16 type;
697 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL
698 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0
699 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL
700 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
701 __le16 event_id;
702 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL
703 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
704 __le32 event_data2;
705 u8 opaque_v;
706 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL
707 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL
708 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
709 u8 timestamp_lo;
710 __le16 timestamp_hi;
711 __le32 event_data1;
712 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL
713 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0
714 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL
715 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL
716 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
717 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL
718 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8
719 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8)
720 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8)
721 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8)
722 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL
723 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL
724 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16
725};
726
650/* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ 727/* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
651struct hwrm_async_event_cmpl_vf_cfg_change { 728struct hwrm_async_event_cmpl_vf_cfg_change {
652 __le16 type; 729 __le16 type;
@@ -672,6 +749,74 @@ struct hwrm_async_event_cmpl_vf_cfg_change {
672 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL 749 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL
673}; 750};
674 751
752/* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
753struct hwrm_async_event_cmpl_hw_flow_aged {
754 __le16 type;
755 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL
756 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
757 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL
758 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
759 __le16 event_id;
760 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL
761 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
762 __le32 event_data2;
763 u8 opaque_v;
764 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL
765 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL
766 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
767 u8 timestamp_lo;
768 __le16 timestamp_hi;
769 __le32 event_data1;
770 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL
771 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0
772 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL
773 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31)
774 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31)
775 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
776};
777
778/* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
779struct hwrm_async_event_cmpl_eem_cache_flush_req {
780 __le16 type;
781 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL
782 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0
783 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL
784 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
785 __le16 event_id;
786 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL
787 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
788 __le32 event_data2;
789 u8 opaque_v;
790 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL
791 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL
792 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
793 u8 timestamp_lo;
794 __le16 timestamp_hi;
795 __le32 event_data1;
796};
797
798/* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
799struct hwrm_async_event_cmpl_eem_cache_flush_done {
800 __le16 type;
801 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL
802 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0
803 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
804 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
805 __le16 event_id;
806 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL
807 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
808 __le32 event_data2;
809 u8 opaque_v;
810 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL
811 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL
812 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
813 u8 timestamp_lo;
814 __le16 timestamp_hi;
815 __le32 event_data1;
816 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL
817 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0
818};
819
675/* hwrm_func_reset_input (size:192b/24B) */ 820/* hwrm_func_reset_input (size:192b/24B) */
676struct hwrm_func_reset_input { 821struct hwrm_func_reset_input {
677 __le16 req_type; 822 __le16 req_type;
@@ -867,6 +1012,8 @@ struct hwrm_func_qcaps_output {
867 #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL 1012 #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL
868 #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL 1013 #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL
869 #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL 1014 #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL
1015 #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL
1016 #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL
870 u8 mac_address[6]; 1017 u8 mac_address[6];
871 __le16 max_rsscos_ctx; 1018 __le16 max_rsscos_ctx;
872 __le16 max_cmpl_rings; 1019 __le16 max_cmpl_rings;
@@ -902,7 +1049,7 @@ struct hwrm_func_qcfg_input {
902 u8 unused_0[6]; 1049 u8 unused_0[6];
903}; 1050};
904 1051
905/* hwrm_func_qcfg_output (size:640b/80B) */ 1052/* hwrm_func_qcfg_output (size:704b/88B) */
906struct hwrm_func_qcfg_output { 1053struct hwrm_func_qcfg_output {
907 __le16 error_code; 1054 __le16 error_code;
908 __le16 req_type; 1055 __le16 req_type;
@@ -919,6 +1066,7 @@ struct hwrm_func_qcfg_output {
919 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 1066 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL
920 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 1067 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL
921 #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL 1068 #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL
1069 #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL
922 u8 mac_address[6]; 1070 u8 mac_address[6];
923 __le16 pci_id; 1071 __le16 pci_id;
924 __le16 alloc_rsscos_ctx; 1072 __le16 alloc_rsscos_ctx;
@@ -1000,7 +1148,11 @@ struct hwrm_func_qcfg_output {
1000 __le16 alloc_sp_tx_rings; 1148 __le16 alloc_sp_tx_rings;
1001 __le16 alloc_stat_ctx; 1149 __le16 alloc_stat_ctx;
1002 __le16 alloc_msix; 1150 __le16 alloc_msix;
1003 u8 unused_2[5]; 1151 __le16 registered_vfs;
1152 u8 unused_1[3];
1153 u8 always_1;
1154 __le32 reset_addr_poll;
1155 u8 unused_2[3];
1004 u8 valid; 1156 u8 valid;
1005}; 1157};
1006 1158
@@ -1031,6 +1183,7 @@ struct hwrm_func_cfg_input {
1031 #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL 1183 #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL
1032 #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL 1184 #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL
1033 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL 1185 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL
1186 #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL
1034 __le32 enables; 1187 __le32 enables;
1035 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL 1188 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL
1036 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 1189 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL
@@ -1235,6 +1388,7 @@ struct hwrm_func_drv_rgtr_input {
1235 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 1388 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL
1236 #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL 1389 #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL
1237 #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL 1390 #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL
1391 #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL
1238 __le32 enables; 1392 __le32 enables;
1239 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 1393 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL
1240 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 1394 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL
@@ -1888,7 +2042,8 @@ struct hwrm_func_drv_if_change_output {
1888 __le16 seq_id; 2042 __le16 seq_id;
1889 __le16 resp_len; 2043 __le16 resp_len;
1890 __le32 flags; 2044 __le32 flags;
1891 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL 2045 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL
2046 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL
1892 u8 unused_0[3]; 2047 u8 unused_0[3];
1893 u8 valid; 2048 u8 valid;
1894}; 2049};
@@ -2864,6 +3019,60 @@ struct hwrm_port_phy_i2c_read_output {
2864 u8 valid; 3019 u8 valid;
2865}; 3020};
2866 3021
3022/* hwrm_port_phy_mdio_write_input (size:320b/40B) */
3023struct hwrm_port_phy_mdio_write_input {
3024 __le16 req_type;
3025 __le16 cmpl_ring;
3026 __le16 seq_id;
3027 __le16 target_id;
3028 __le64 resp_addr;
3029 __le32 unused_0[2];
3030 __le16 port_id;
3031 u8 phy_addr;
3032 u8 dev_addr;
3033 __le16 reg_addr;
3034 __le16 reg_data;
3035 u8 cl45_mdio;
3036 u8 unused_1[7];
3037};
3038
3039/* hwrm_port_phy_mdio_write_output (size:128b/16B) */
3040struct hwrm_port_phy_mdio_write_output {
3041 __le16 error_code;
3042 __le16 req_type;
3043 __le16 seq_id;
3044 __le16 resp_len;
3045 u8 unused_0[7];
3046 u8 valid;
3047};
3048
3049/* hwrm_port_phy_mdio_read_input (size:256b/32B) */
3050struct hwrm_port_phy_mdio_read_input {
3051 __le16 req_type;
3052 __le16 cmpl_ring;
3053 __le16 seq_id;
3054 __le16 target_id;
3055 __le64 resp_addr;
3056 __le32 unused_0[2];
3057 __le16 port_id;
3058 u8 phy_addr;
3059 u8 dev_addr;
3060 __le16 reg_addr;
3061 u8 cl45_mdio;
3062 u8 unused_1;
3063};
3064
3065/* hwrm_port_phy_mdio_read_output (size:128b/16B) */
3066struct hwrm_port_phy_mdio_read_output {
3067 __le16 error_code;
3068 __le16 req_type;
3069 __le16 seq_id;
3070 __le16 resp_len;
3071 __le16 reg_data;
3072 u8 unused_0[5];
3073 u8 valid;
3074};
3075
2867/* hwrm_port_led_cfg_input (size:512b/64B) */ 3076/* hwrm_port_led_cfg_input (size:512b/64B) */
2868struct hwrm_port_led_cfg_input { 3077struct hwrm_port_led_cfg_input {
2869 __le16 req_type; 3078 __le16 req_type;
@@ -4869,6 +5078,10 @@ struct hwrm_ring_grp_free_output {
4869 u8 unused_0[7]; 5078 u8 unused_0[7];
4870 u8 valid; 5079 u8 valid;
4871}; 5080};
5081#define DEFAULT_FLOW_ID 0xFFFFFFFFUL
5082#define ROCEV1_FLOW_ID 0xFFFFFFFEUL
5083#define ROCEV2_FLOW_ID 0xFFFFFFFDUL
5084#define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
4872 5085
4873/* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ 5086/* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */
4874struct hwrm_cfa_l2_filter_alloc_input { 5087struct hwrm_cfa_l2_filter_alloc_input {
@@ -4937,20 +5150,21 @@ struct hwrm_cfa_l2_filter_alloc_input {
4937 u8 unused_3; 5150 u8 unused_3;
4938 __le32 src_id; 5151 __le32 src_id;
4939 u8 tunnel_type; 5152 u8 tunnel_type;
4940 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5153 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
4941 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5154 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
4942 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5155 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
4943 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5156 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
4944 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5157 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
4945 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5158 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
4946 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5159 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
4947 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5160 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
4948 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5161 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
4949 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5162 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
4950 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5163 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
4951 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5164 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
4952 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5165 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
4953 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5166 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
5167 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
4954 u8 unused_4; 5168 u8 unused_4;
4955 __le16 dst_id; 5169 __le16 dst_id;
4956 __le16 mirror_vnic_id; 5170 __le16 mirror_vnic_id;
@@ -5108,20 +5322,21 @@ struct hwrm_cfa_tunnel_filter_alloc_input {
5108 u8 l3_addr_type; 5322 u8 l3_addr_type;
5109 u8 t_l3_addr_type; 5323 u8 t_l3_addr_type;
5110 u8 tunnel_type; 5324 u8 tunnel_type;
5111 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5325 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
5112 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5326 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
5113 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5327 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
5114 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5328 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
5115 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5329 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
5116 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5330 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
5117 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5331 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
5118 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5332 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
5119 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5333 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
5120 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5334 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
5121 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5335 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
5122 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5336 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
5123 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5337 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
5124 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5338 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
5339 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
5125 u8 tunnel_flags; 5340 u8 tunnel_flags;
5126 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL 5341 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL
5127 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL 5342 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL
@@ -5326,20 +5541,21 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
5326 __le16 dst_id; 5541 __le16 dst_id;
5327 __le16 mirror_vnic_id; 5542 __le16 mirror_vnic_id;
5328 u8 tunnel_type; 5543 u8 tunnel_type;
5329 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5544 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
5330 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5545 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
5331 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5546 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
5332 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5547 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
5333 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5548 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
5334 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5549 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
5335 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5550 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
5336 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5551 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
5337 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5552 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
5338 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5553 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
5339 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5554 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
5340 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5555 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
5341 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5556 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
5342 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5557 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
5558 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
5343 u8 pri_hint; 5559 u8 pri_hint;
5344 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 5560 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL
5345 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 5561 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL
@@ -5459,20 +5675,21 @@ struct hwrm_cfa_decap_filter_alloc_input {
5459 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 5675 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL
5460 __be32 tunnel_id; 5676 __be32 tunnel_id;
5461 u8 tunnel_type; 5677 u8 tunnel_type;
5462 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5678 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
5463 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5679 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
5464 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5680 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
5465 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5681 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
5466 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5682 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
5467 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5683 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
5468 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5684 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
5469 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5685 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
5470 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5686 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
5471 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5687 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
5472 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5688 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
5473 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5689 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
5474 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5690 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
5475 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5691 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
5692 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
5476 u8 unused_0; 5693 u8 unused_0;
5477 __le16 unused_1; 5694 __le16 unused_1;
5478 u8 src_macaddr[6]; 5695 u8 src_macaddr[6];
@@ -5559,20 +5776,23 @@ struct hwrm_cfa_flow_alloc_input {
5559 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL 5776 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL
5560 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL 5777 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL
5561 #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL 5778 #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL
5779 #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN 0x200UL
5562 __le16 src_fid; 5780 __le16 src_fid;
5563 __le32 tunnel_handle; 5781 __le32 tunnel_handle;
5564 __le16 action_flags; 5782 __le16 action_flags;
5565 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL 5783 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL
5566 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL 5784 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL
5567 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL 5785 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL
5568 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL 5786 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL
5569 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL 5787 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL
5570 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL 5788 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL
5571 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL 5789 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL
5572 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL 5790 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL
5573 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL 5791 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL
5574 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL 5792 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL
5575 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL 5793 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL
5794 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL
5795 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT 0x1000UL
5576 __le16 dst_fid; 5796 __le16 dst_fid;
5577 __be16 l2_rewrite_vlan_tpid; 5797 __be16 l2_rewrite_vlan_tpid;
5578 __be16 l2_rewrite_vlan_tci; 5798 __be16 l2_rewrite_vlan_tci;
@@ -5597,20 +5817,21 @@ struct hwrm_cfa_flow_alloc_input {
5597 __be16 l2_rewrite_smac[3]; 5817 __be16 l2_rewrite_smac[3];
5598 u8 ip_proto; 5818 u8 ip_proto;
5599 u8 tunnel_type; 5819 u8 tunnel_type;
5600 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5820 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL
5601 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5821 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
5602 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5822 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL
5603 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5823 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL
5604 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5824 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL
5605 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5825 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
5606 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5826 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL
5607 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5827 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL
5608 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5828 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL
5609 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5829 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
5610 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5830 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
5611 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5831 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
5612 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5832 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
5613 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5833 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL
5834 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL
5614}; 5835};
5615 5836
5616/* hwrm_cfa_flow_alloc_output (size:256b/32B) */ 5837/* hwrm_cfa_flow_alloc_output (size:256b/32B) */
@@ -5623,7 +5844,8 @@ struct hwrm_cfa_flow_alloc_output {
5623 u8 unused_0[2]; 5844 u8 unused_0[2];
5624 __le32 flow_id; 5845 __le32 flow_id;
5625 __le64 ext_flow_handle; 5846 __le64 ext_flow_handle;
5626 u8 unused_1[7]; 5847 __le32 flow_counter_id;
5848 u8 unused_1[3];
5627 u8 valid; 5849 u8 valid;
5628}; 5850};
5629 5851
@@ -5651,6 +5873,46 @@ struct hwrm_cfa_flow_free_output {
5651 u8 valid; 5873 u8 valid;
5652}; 5874};
5653 5875
5876/* hwrm_cfa_flow_info_input (size:256b/32B) */
5877struct hwrm_cfa_flow_info_input {
5878 __le16 req_type;
5879 __le16 cmpl_ring;
5880 __le16 seq_id;
5881 __le16 target_id;
5882 __le64 resp_addr;
5883 __le16 flow_handle;
5884 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL
5885 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_SFT 0
5886 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL
5887 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL
5888 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL
5889 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL
5890 u8 unused_0[6];
5891 __le64 ext_flow_handle;
5892};
5893
5894/* hwrm_cfa_flow_info_output (size:448b/56B) */
5895struct hwrm_cfa_flow_info_output {
5896 __le16 error_code;
5897 __le16 req_type;
5898 __le16 seq_id;
5899 __le16 resp_len;
5900 u8 flags;
5901 u8 profile;
5902 __le16 src_fid;
5903 __le16 dst_fid;
5904 __le16 l2_ctxt_id;
5905 __le64 em_info;
5906 __le64 tcam_info;
5907 __le64 vfp_tcam_info;
5908 __le16 ar_id;
5909 __le16 flow_handle;
5910 __le32 tunnel_handle;
5911 __le16 flow_timer;
5912 u8 unused_0[5];
5913 u8 valid;
5914};
5915
5654/* hwrm_cfa_flow_stats_input (size:640b/80B) */ 5916/* hwrm_cfa_flow_stats_input (size:640b/80B) */
5655struct hwrm_cfa_flow_stats_input { 5917struct hwrm_cfa_flow_stats_input {
5656 __le16 req_type; 5918 __le16 req_type;
@@ -5757,6 +6019,128 @@ struct hwrm_cfa_vfr_free_output {
5757 u8 valid; 6019 u8 valid;
5758}; 6020};
5759 6021
6022/* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
6023struct hwrm_cfa_eem_qcaps_input {
6024 __le16 req_type;
6025 __le16 cmpl_ring;
6026 __le16 seq_id;
6027 __le16 target_id;
6028 __le64 resp_addr;
6029 __le32 flags;
6030 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX 0x1UL
6031 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX 0x2UL
6032 #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL
6033 __le32 unused_0;
6034};
6035
6036/* hwrm_cfa_eem_qcaps_output (size:256b/32B) */
6037struct hwrm_cfa_eem_qcaps_output {
6038 __le16 error_code;
6039 __le16 req_type;
6040 __le16 seq_id;
6041 __le16 resp_len;
6042 __le32 flags;
6043 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX 0x1UL
6044 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX 0x2UL
6045 __le32 unused_0;
6046 __le32 supported;
6047 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE 0x1UL
6048 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE 0x2UL
6049 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE 0x4UL
6050 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE 0x8UL
6051 __le32 max_entries_supported;
6052 __le16 key_entry_size;
6053 __le16 record_entry_size;
6054 __le16 efc_entry_size;
6055 u8 unused_1;
6056 u8 valid;
6057};
6058
6059/* hwrm_cfa_eem_cfg_input (size:320b/40B) */
6060struct hwrm_cfa_eem_cfg_input {
6061 __le16 req_type;
6062 __le16 cmpl_ring;
6063 __le16 seq_id;
6064 __le16 target_id;
6065 __le64 resp_addr;
6066 __le32 flags;
6067 #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX 0x1UL
6068 #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX 0x2UL
6069 #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL
6070 __le32 unused_0;
6071 __le32 num_entries;
6072 __le32 unused_1;
6073 __le16 key0_ctx_id;
6074 __le16 key1_ctx_id;
6075 __le16 record_ctx_id;
6076 __le16 efc_ctx_id;
6077};
6078
6079/* hwrm_cfa_eem_cfg_output (size:128b/16B) */
6080struct hwrm_cfa_eem_cfg_output {
6081 __le16 error_code;
6082 __le16 req_type;
6083 __le16 seq_id;
6084 __le16 resp_len;
6085 u8 unused_0[7];
6086 u8 valid;
6087};
6088
6089/* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
6090struct hwrm_cfa_eem_qcfg_input {
6091 __le16 req_type;
6092 __le16 cmpl_ring;
6093 __le16 seq_id;
6094 __le16 target_id;
6095 __le64 resp_addr;
6096 __le32 flags;
6097 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX 0x1UL
6098 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX 0x2UL
6099 __le32 unused_0;
6100};
6101
6102/* hwrm_cfa_eem_qcfg_output (size:128b/16B) */
6103struct hwrm_cfa_eem_qcfg_output {
6104 __le16 error_code;
6105 __le16 req_type;
6106 __le16 seq_id;
6107 __le16 resp_len;
6108 __le32 flags;
6109 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX 0x1UL
6110 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX 0x2UL
6111 #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD 0x4UL
6112 __le32 num_entries;
6113};
6114
6115/* hwrm_cfa_eem_op_input (size:192b/24B) */
6116struct hwrm_cfa_eem_op_input {
6117 __le16 req_type;
6118 __le16 cmpl_ring;
6119 __le16 seq_id;
6120 __le16 target_id;
6121 __le64 resp_addr;
6122 __le32 flags;
6123 #define CFA_EEM_OP_REQ_FLAGS_PATH_TX 0x1UL
6124 #define CFA_EEM_OP_REQ_FLAGS_PATH_RX 0x2UL
6125 __le16 unused_0;
6126 __le16 op;
6127 #define CFA_EEM_OP_REQ_OP_RESERVED 0x0UL
6128 #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL
6129 #define CFA_EEM_OP_REQ_OP_EEM_ENABLE 0x2UL
6130 #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL
6131 #define CFA_EEM_OP_REQ_OP_LAST CFA_EEM_OP_REQ_OP_EEM_CLEANUP
6132};
6133
6134/* hwrm_cfa_eem_op_output (size:128b/16B) */
6135struct hwrm_cfa_eem_op_output {
6136 __le16 error_code;
6137 __le16 req_type;
6138 __le16 seq_id;
6139 __le16 resp_len;
6140 u8 unused_0[7];
6141 u8 valid;
6142};
6143
5760/* hwrm_tunnel_dst_port_query_input (size:192b/24B) */ 6144/* hwrm_tunnel_dst_port_query_input (size:192b/24B) */
5761struct hwrm_tunnel_dst_port_query_input { 6145struct hwrm_tunnel_dst_port_query_input {
5762 __le16 req_type; 6146 __le16 req_type;
@@ -5765,12 +6149,13 @@ struct hwrm_tunnel_dst_port_query_input {
5765 __le16 target_id; 6149 __le16 target_id;
5766 __le64 resp_addr; 6150 __le64 resp_addr;
5767 u8 tunnel_type; 6151 u8 tunnel_type;
5768 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6152 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL
5769 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6153 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL
5770 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6154 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
5771 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6155 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
5772 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6156 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
5773 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 6157 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
6158 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6
5774 u8 unused_0[7]; 6159 u8 unused_0[7];
5775}; 6160};
5776 6161
@@ -5794,12 +6179,13 @@ struct hwrm_tunnel_dst_port_alloc_input {
5794 __le16 target_id; 6179 __le16 target_id;
5795 __le64 resp_addr; 6180 __le64 resp_addr;
5796 u8 tunnel_type; 6181 u8 tunnel_type;
5797 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6182 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL
5798 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6183 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL
5799 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6184 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
5800 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6185 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
5801 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6186 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
5802 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 6187 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
6188 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6
5803 u8 unused_0; 6189 u8 unused_0;
5804 __be16 tunnel_dst_port_val; 6190 __be16 tunnel_dst_port_val;
5805 u8 unused_1[4]; 6191 u8 unused_1[4];
@@ -5824,12 +6210,13 @@ struct hwrm_tunnel_dst_port_free_input {
5824 __le16 target_id; 6210 __le16 target_id;
5825 __le64 resp_addr; 6211 __le64 resp_addr;
5826 u8 tunnel_type; 6212 u8 tunnel_type;
5827 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6213 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL
5828 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6214 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL
5829 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6215 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL
5830 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6216 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL
5831 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6217 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL
5832 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 6218 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL
6219 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6
5833 u8 unused_0; 6220 u8 unused_0;
5834 __le16 tunnel_dst_port_id; 6221 __le16 tunnel_dst_port_id;
5835 u8 unused_1[4]; 6222 u8 unused_1[4];
@@ -6040,7 +6427,9 @@ struct hwrm_fw_reset_input {
6040 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 6427 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL
6041 #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 6428 #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE
6042 u8 host_idx; 6429 u8 host_idx;
6043 u8 unused_0[5]; 6430 u8 flags;
6431 #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL
6432 u8 unused_0[4];
6044}; 6433};
6045 6434
6046/* hwrm_fw_reset_output (size:128b/16B) */ 6435/* hwrm_fw_reset_output (size:128b/16B) */
@@ -6137,6 +6526,7 @@ struct hwrm_struct_hdr {
6137 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 6526 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL
6138 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 6527 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL
6139 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 6528 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL
6529 #define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL
6140 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 6530 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL
6141 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 6531 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL
6142 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL 6532 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-25 22:34:40 -0400