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authorHauke Mehrtens <hauke@hauke-m.de>2016-06-20 17:32:10 -0400
committerBoris Brezillon <boris.brezillon@free-electrons.com>2016-07-11 02:40:15 -0400
commit44772fa5ec4162ef133f1294299d1e1ada7d2d11 (patch)
treedf7bc14186a3826d26ff6fb3e07fa8d04ae7d1fb /drivers/mtd
parentf45eb7b522359260606852d79a8899e5db37d8f3 (diff)
mtd: nand: xway: remove manual reset
nand_scan() already resets the NAND flash chip, this driver does not have to call it manually. The xway_reset_chip() functions does the same as the normal NAND reset function. The waiting for the NAND_WAIT_WR_C is done in xway_cmd_ctrl(). Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Diffstat (limited to 'drivers/mtd')
-rw-r--r--drivers/mtd/nand/xway_nand.c20
1 files changed, 0 insertions, 20 deletions
diff --git a/drivers/mtd/nand/xway_nand.c b/drivers/mtd/nand/xway_nand.c
index 6028edbad644..ab93b3536877 100644
--- a/drivers/mtd/nand/xway_nand.c
+++ b/drivers/mtd/nand/xway_nand.c
@@ -35,7 +35,6 @@
35#define NAND_CMD_CS BIT(4) /* chip select */ 35#define NAND_CMD_CS BIT(4) /* chip select */
36#define NAND_CMD_SE BIT(5) /* spare area access latch */ 36#define NAND_CMD_SE BIT(5) /* spare area access latch */
37#define NAND_CMD_WP BIT(6) /* write protect */ 37#define NAND_CMD_WP BIT(6) /* write protect */
38#define NAND_WRITE_CMD_RESET 0xff
39#define NAND_WRITE_CMD (NAND_CMD_CS | NAND_CMD_CLE) 38#define NAND_WRITE_CMD (NAND_CMD_CS | NAND_CMD_CLE)
40#define NAND_WRITE_ADDR (NAND_CMD_CS | NAND_CMD_ALE) 39#define NAND_WRITE_ADDR (NAND_CMD_CS | NAND_CMD_ALE)
41#define NAND_WRITE_DATA (NAND_CMD_CS) 40#define NAND_WRITE_DATA (NAND_CMD_CS)
@@ -68,22 +67,6 @@ struct xway_nand_data {
68 struct nand_chip chip; 67 struct nand_chip chip;
69}; 68};
70 69
71static void xway_reset_chip(struct nand_chip *chip)
72{
73 unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W;
74 unsigned long flags;
75
76 nandaddr &= ~NAND_WRITE_ADDR;
77 nandaddr |= NAND_WRITE_CMD;
78
79 /* finish with a reset */
80 spin_lock_irqsave(&ebu_lock, flags);
81 writeb(NAND_WRITE_CMD_RESET, (void __iomem *) nandaddr);
82 while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
83 ;
84 spin_unlock_irqrestore(&ebu_lock, flags);
85}
86
87static void xway_select_chip(struct mtd_info *mtd, int chip) 70static void xway_select_chip(struct mtd_info *mtd, int chip)
88{ 71{
89 72
@@ -199,9 +182,6 @@ static int xway_nand_probe(struct platform_device *pdev)
199 | NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P 182 | NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P
200 | cs_flag, EBU_NAND_CON); 183 | cs_flag, EBU_NAND_CON);
201 184
202 /* finish with a reset */
203 xway_reset_chip(&data->chip);
204
205 /* Scan to find existence of the device */ 185 /* Scan to find existence of the device */
206 err = nand_scan(mtd, 1); 186 err = nand_scan(mtd, 1);
207 if (err) 187 if (err)