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authorJerome Brunet <jbrunet@baylibre.com>2017-08-31 05:29:58 -0400
committerUlf Hansson <ulf.hansson@linaro.org>2017-08-31 06:42:57 -0400
commit795c633f60936fd1ea0e4ef50e5a7534dd9fb74c (patch)
tree7a2494b959d3a5f04c593e61fdf27cee624d25be /drivers/mmc
parenta027b2c5fed78851e69fab395b02d127a7759fc7 (diff)
mmc: meson-gx: fix __ffsdi2 undefined on arm32
Using __bf_shf does not compile on arm 32 architecture. This has gone unnoticed till now cause the driver is only used on arm64. In addition, __bf_shf was already used in the driver without any issue. It was used on a constant value, so the call was probably optimized away. Replace __bf_shf by __ffs fixes the problem Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/host/meson-gx-mmc.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index 987bae98c61f..c885c2d4b904 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -196,13 +196,13 @@ static int meson_mmc_clk_get_phase(struct clk_hw *hw)
196 u32 val; 196 u32 val;
197 197
198 val = readl(mmc->reg); 198 val = readl(mmc->reg);
199 p = (val & mmc->phase_mask) >> __bf_shf(mmc->phase_mask); 199 p = (val & mmc->phase_mask) >> __ffs(mmc->phase_mask);
200 degrees = p * 360 / phase_num; 200 degrees = p * 360 / phase_num;
201 201
202 if (mmc->delay_mask) { 202 if (mmc->delay_mask) {
203 period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000, 203 period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
204 clk_get_rate(hw->clk)); 204 clk_get_rate(hw->clk));
205 d = (val & mmc->delay_mask) >> __bf_shf(mmc->delay_mask); 205 d = (val & mmc->delay_mask) >> __ffs(mmc->delay_mask);
206 degrees += d * mmc->delay_step_ps * 360 / period_ps; 206 degrees += d * mmc->delay_step_ps * 360 / period_ps;
207 degrees %= 360; 207 degrees %= 360;
208 } 208 }
@@ -218,11 +218,11 @@ static void meson_mmc_apply_phase_delay(struct meson_mmc_phase *mmc,
218 218
219 val = readl(mmc->reg); 219 val = readl(mmc->reg);
220 val &= ~mmc->phase_mask; 220 val &= ~mmc->phase_mask;
221 val |= phase << __bf_shf(mmc->phase_mask); 221 val |= phase << __ffs(mmc->phase_mask);
222 222
223 if (mmc->delay_mask) { 223 if (mmc->delay_mask) {
224 val &= ~mmc->delay_mask; 224 val &= ~mmc->delay_mask;
225 val |= delay << __bf_shf(mmc->delay_mask); 225 val |= delay << __ffs(mmc->delay_mask);
226 } 226 }
227 227
228 writel(val, mmc->reg); 228 writel(val, mmc->reg);
@@ -249,7 +249,7 @@ static int meson_mmc_clk_set_phase(struct clk_hw *hw, int degrees)
249 r = do_div(p, 360 / phase_num); 249 r = do_div(p, 360 / phase_num);
250 d = DIV_ROUND_CLOSEST(r * period_ps, 250 d = DIV_ROUND_CLOSEST(r * period_ps,
251 360 * mmc->delay_step_ps); 251 360 * mmc->delay_step_ps);
252 d = min(d, mmc->delay_mask >> __bf_shf(mmc->delay_mask)); 252 d = min(d, mmc->delay_mask >> __ffs(mmc->delay_mask));
253 } 253 }
254 254
255 meson_mmc_apply_phase_delay(mmc, p, d); 255 meson_mmc_apply_phase_delay(mmc, p, d);
@@ -506,7 +506,7 @@ static int meson_mmc_clk_init(struct meson_host *host)
506 init.num_parents = MUX_CLK_NUM_PARENTS; 506 init.num_parents = MUX_CLK_NUM_PARENTS;
507 507
508 mux->reg = host->regs + SD_EMMC_CLOCK; 508 mux->reg = host->regs + SD_EMMC_CLOCK;
509 mux->shift = __bf_shf(CLK_SRC_MASK); 509 mux->shift = __ffs(CLK_SRC_MASK);
510 mux->mask = CLK_SRC_MASK >> mux->shift; 510 mux->mask = CLK_SRC_MASK >> mux->shift;
511 mux->hw.init = &init; 511 mux->hw.init = &init;
512 512
@@ -528,7 +528,7 @@ static int meson_mmc_clk_init(struct meson_host *host)
528 init.num_parents = 1; 528 init.num_parents = 1;
529 529
530 div->reg = host->regs + SD_EMMC_CLOCK; 530 div->reg = host->regs + SD_EMMC_CLOCK;
531 div->shift = __bf_shf(CLK_DIV_MASK); 531 div->shift = __ffs(CLK_DIV_MASK);
532 div->width = __builtin_popcountl(CLK_DIV_MASK); 532 div->width = __builtin_popcountl(CLK_DIV_MASK);
533 div->hw.init = &init; 533 div->hw.init = &init;
534 div->flags = (CLK_DIVIDER_ONE_BASED | 534 div->flags = (CLK_DIVIDER_ONE_BASED |