Merge tag 'powerpc-4.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux

Pull powerpc updates from Michael Ellerman:
 "A bit of a small release, I suspect in part due to me travelling for
  KS. But my backlog of patches to review is smaller than usual, so I
  think in part folks just didn't send as much this cycle.

  Non-highlights:

   - Five fixes for the >128T address space handling, both to fix bugs
     in our implementation and to bring the semantics exactly into line
     with x86.

  Highlights:

   - Support for a new OPAL call on bare metal machines which gives us a
     true NMI (ie. is not masked by MSR[EE]=0) for debugging etc.

   - Support for Power9 DD2 in the CXL driver.

   - Improvements to machine check handling so that uncorrectable errors
     can be reported into the generic memory_failure() machinery.

   - Some fixes and improvements for VPHN, which is used under PowerVM
     to notify the Linux partition of topology changes.

   - Plumbing to enable TM (transactional memory) without suspend on
     some Power9 processors (PPC_FEATURE2_HTM_NO_SUSPEND).

   - Support for emulating vector loads form cache-inhibited memory, on
     some Power9 revisions.

   - Disable the fast-endian switch "syscall" by default (behind a
     CONFIG), we believe it has never had any users.

   - A major rework of the API drivers use when initiating and waiting
     for long running operations performed by OPAL firmware, and changes
     to the powernv_flash driver to use the new API.

   - Several fixes for the handling of FP/VMX/VSX while processes are
     using transactional memory.

   - Optimisations of TLB range flushes when using the radix MMU on
     Power9.

   - Improvements to the VAS facility used to access coprocessors on
     Power9, and related improvements to the way the NX crypto driver
     handles requests.

   - Implementation of PMEM_API and UACCESS_FLUSHCACHE for 64-bit.

  Thanks to: Alexey Kardashevskiy, Alistair Popple, Allen Pais, Andrew
  Donnellan, Aneesh Kumar K.V, Arnd Bergmann, Balbir Singh, Benjamin
  Herrenschmidt, Breno Leitao, Christophe Leroy, Christophe Lombard,
  Cyril Bur, Frederic Barrat, Gautham R. Shenoy, Geert Uytterhoeven,
  Guilherme G. Piccoli, Gustavo Romero, Haren Myneni, Joel Stanley,
  Kamalesh Babulal, Kautuk Consul, Markus Elfring, Masami Hiramatsu,
  Michael Bringmann, Michael Neuling, Michal Suchanek, Naveen N. Rao,
  Nicholas Piggin, Oliver O'Halloran, Paul Mackerras, Pedro Miraglia
  Franco de Carvalho, Philippe Bergheaud, Sandipan Das, Seth Forshee,
  Shriya, Stephen Rothwell, Stewart Smith, Sukadev Bhattiprolu, Tyrel
  Datwyler, Vaibhav Jain, Vaidyanathan Srinivasan, and William A.
  Kennington III"

* tag 'powerpc-4.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (151 commits)
  powerpc/64s: Fix Power9 DD2.0 workarounds by adding DD2.1 feature
  powerpc/64s: Fix masking of SRR1 bits on instruction fault
  powerpc/64s: mm_context.addr_limit is only used on hash
  powerpc/64s/radix: Fix 128TB-512TB virtual address boundary case allocation
  powerpc/64s/hash: Allow MAP_FIXED allocations to cross 128TB boundary
  powerpc/64s/hash: Fix fork() with 512TB process address space
  powerpc/64s/hash: Fix 128TB-512TB virtual address boundary case allocation
  powerpc/64s/hash: Fix 512T hint detection to use >= 128T
  powerpc: Fix DABR match on hash based systems
  powerpc/signal: Properly handle return value from uprobe_deny_signal()
  powerpc/fadump: use kstrtoint to handle sysfs store
  powerpc/lib: Implement UACCESS_FLUSHCACHE API
  powerpc/lib: Implement PMEM API
  powerpc/powernv/npu: Don't explicitly flush nmmu tlb
  powerpc/powernv/npu: Use flush_all_mm() instead of flush_tlb_mm()
  powerpc/powernv/idle: Round up latency and residency values
  powerpc/kprobes: refactor kprobe_lookup_name for safer string operations
  powerpc/kprobes: Blacklist emulate_update_regs() from kprobes
  powerpc/kprobes: Do not disable interrupts for optprobes and kprobes_on_ftrace
  powerpc/kprobes: Disable preemption before invoking probe handler for optprobes
  ...

1 files changed, 64 insertions, 24 deletions

diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index 3ba04f371380..bb7fd3f4edab 100644
--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c
@@ -401,7 +401,8 @@ int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid,
         *capp_unit_id = get_capp_unit_id(np, *phb_index);
         of_node_put(np);
         if (!*capp_unit_id) {
-                pr_err("cxl: invalid capp unit id\n");
+                pr_err("cxl: invalid capp unit id (phb_index: %d)\n",
+                       *phb_index);
                 return -ENODEV;
         }
 
@@ -475,37 +476,37 @@ static int init_implementation_adapter_regs_psl9(struct cxl *adapter,
         psl_fircntl |= 0x1ULL; /* ce_thresh */
         cxl_p1_write(adapter, CXL_PSL9_FIR_CNTL, psl_fircntl);
 
-        /* vccredits=0x1  pcklat=0x4 */
-        cxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x0000000000001810ULL);
-
-        /*
-         * For debugging with trace arrays.
-         * Configure RX trace 0 segmented mode.
-         * Configure CT trace 0 segmented mode.
-         * Configure LA0 trace 0 segmented mode.
-         * Configure LA1 trace 0 segmented mode.
+        /* Setup the PSL to transmit packets on the PCIe before the
+         * CAPP is enabled
          */
-        cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000000ULL);
-        cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000003ULL);
-        cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000005ULL);
-        cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000006ULL);
+        cxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x0001001000002A10ULL);
 
         /*
          * A response to an ASB_Notify request is returned by the
          * system as an MMIO write to the address defined in
-         * the PSL_TNR_ADDR register
+         * the PSL_TNR_ADDR register.
+         * keep the Reset Value: 0x00020000E0000000
          */
-        /* PSL_TNR_ADDR */
 
-        /* NORST */
-        cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x8000000000000000ULL);
+        /* Enable XSL rty limit */
+        cxl_p1_write(adapter, CXL_XSL9_DEF, 0x51F8000000000005ULL);
+
+        /* Change XSL_INV dummy read threshold */
+        cxl_p1_write(adapter, CXL_XSL9_INV, 0x0000040007FFC200ULL);
+
+        if (phb_index == 3) {
+                /* disable machines 31-47 and 20-27 for DMA */
+                cxl_p1_write(adapter, CXL_PSL9_APCDEDTYPE, 0x40000FF3FFFF0000ULL);
+        }
 
-        /* allocate the apc machines */
-        cxl_p1_write(adapter, CXL_PSL9_APCDEDTYPE, 0x40000003FFFF0000ULL);
+        /* Snoop machines */
+        cxl_p1_write(adapter, CXL_PSL9_APCDEDALLOC, 0x800F000200000000ULL);
 
-        /* Disable vc dd1 fix */
-        if (cxl_is_power9_dd1())
-                cxl_p1_write(adapter, CXL_PSL9_GP_CT, 0x0400000000000001ULL);
+        if (cxl_is_power9_dd1()) {
+                /* Disabling deadlock counter CAR */
+                cxl_p1_write(adapter, CXL_PSL9_GP_CT, 0x0020000000000001ULL);
+        } else
+                cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x4000000000000000ULL);
 
         return 0;
 }
@@ -1746,6 +1747,44 @@ static void cxl_deconfigure_adapter(struct cxl *adapter)
         pci_disable_device(pdev);
 }
 
+static void cxl_stop_trace_psl9(struct cxl *adapter)
+{
+        int traceid;
+        u64 trace_state, trace_mask;
+        struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
+
+        /* read each tracearray state and issue mmio to stop them is needed */
+        for (traceid = 0; traceid <= CXL_PSL9_TRACEID_MAX; ++traceid) {
+                trace_state = cxl_p1_read(adapter, CXL_PSL9_CTCCFG);
+                trace_mask = (0x3ULL << (62 - traceid * 2));
+                trace_state = (trace_state & trace_mask) >> (62 - traceid * 2);
+                dev_dbg(&dev->dev, "cxl: Traceid-%d trace_state=0x%0llX\n",
+                        traceid, trace_state);
+
+                /* issue mmio if the trace array isn't in FIN state */
+                if (trace_state != CXL_PSL9_TRACESTATE_FIN)
+                        cxl_p1_write(adapter, CXL_PSL9_TRACECFG,
+                                     0x8400000000000000ULL | traceid);
+        }
+}
+
+static void cxl_stop_trace_psl8(struct cxl *adapter)
+{
+        int slice;
+
+        /* Stop the trace */
+        cxl_p1_write(adapter, CXL_PSL_TRACE, 0x8000000000000017LL);
+
+        /* Stop the slice traces */
+        spin_lock(&adapter->afu_list_lock);
+        for (slice = 0; slice < adapter->slices; slice++) {
+                if (adapter->afu[slice])
+                        cxl_p1n_write(adapter->afu[slice], CXL_PSL_SLICE_TRACE,
+                                      0x8000000000000000LL);
+        }
+        spin_unlock(&adapter->afu_list_lock);
+}
+
 static const struct cxl_service_layer_ops psl9_ops = {
         .adapter_regs_init = init_implementation_adapter_regs_psl9,
         .invalidate_all = cxl_invalidate_all_psl9,
@@ -1762,6 +1801,7 @@ static const struct cxl_service_layer_ops psl9_ops = {
         .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl9,
         .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl9,
         .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl9,
+        .err_irq_dump_registers = cxl_native_err_irq_dump_regs_psl9,
         .debugfs_stop_trace = cxl_stop_trace_psl9,
         .write_timebase_ctrl = write_timebase_ctrl_psl9,
         .timebase_read = timebase_read_psl9,
@@ -1785,7 +1825,7 @@ static const struct cxl_service_layer_ops psl8_ops = {
         .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl8,
         .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl8,
         .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl8,
-        .err_irq_dump_registers = cxl_native_err_irq_dump_regs,
+        .err_irq_dump_registers = cxl_native_err_irq_dump_regs_psl8,
         .debugfs_stop_trace = cxl_stop_trace_psl8,
         .write_timebase_ctrl = write_timebase_ctrl_psl8,
         .timebase_read = timebase_read_psl8,