diff options
author | Frederic Barrat <fbarrat@linux.ibm.com> | 2018-06-28 06:05:07 -0400 |
---|---|---|
committer | Michael Ellerman <mpe@ellerman.id.au> | 2018-07-02 09:54:32 -0400 |
commit | 322dc4af6c95cddc4f9d806197fe6b376cfae350 (patch) | |
tree | 52b298be976cec9b3c3d6688b1a11a978d6a302a /drivers/misc/cxl/pci.c | |
parent | 8bf6b91a5125ad9972281666430691d6a282d794 (diff) |
Revert "cxl: Add cxl_slot_is_supported API"
Remove abandonned capi support for the Mellanox CX4.
This reverts commit 4e56f858bdde5cbfb70f61baddfaa56a8ed851bf.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Acked-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'drivers/misc/cxl/pci.c')
-rw-r--r-- | drivers/misc/cxl/pci.c | 37 |
1 files changed, 0 insertions, 37 deletions
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c index 193ff22f610b..0ca818396524 100644 --- a/drivers/misc/cxl/pci.c +++ b/drivers/misc/cxl/pci.c | |||
@@ -1808,43 +1808,6 @@ int cxl_slot_is_switched(struct pci_dev *dev) | |||
1808 | return (depth > CXL_MAX_PCIEX_PARENT); | 1808 | return (depth > CXL_MAX_PCIEX_PARENT); |
1809 | } | 1809 | } |
1810 | 1810 | ||
1811 | bool cxl_slot_is_supported(struct pci_dev *dev, int flags) | ||
1812 | { | ||
1813 | if (!cpu_has_feature(CPU_FTR_HVMODE)) | ||
1814 | return false; | ||
1815 | |||
1816 | if ((flags & CXL_SLOT_FLAG_DMA) && (!pvr_version_is(PVR_POWER8NVL))) { | ||
1817 | /* | ||
1818 | * CAPP DMA mode is technically supported on regular P8, but | ||
1819 | * will EEH if the card attempts to access memory < 4GB, which | ||
1820 | * we cannot realistically avoid. We might be able to work | ||
1821 | * around the issue, but until then return unsupported: | ||
1822 | */ | ||
1823 | return false; | ||
1824 | } | ||
1825 | |||
1826 | if (cxl_slot_is_switched(dev)) | ||
1827 | return false; | ||
1828 | |||
1829 | /* | ||
1830 | * XXX: This gets a little tricky on regular P8 (not POWER8NVL) since | ||
1831 | * the CAPP can be connected to PHB 0, 1 or 2 on a first come first | ||
1832 | * served basis, which is racy to check from here. If we need to | ||
1833 | * support this in future we might need to consider having this | ||
1834 | * function effectively reserve it ahead of time. | ||
1835 | * | ||
1836 | * Currently, the only user of this API is the Mellanox CX4, which is | ||
1837 | * only supported on P8NVL due to the above mentioned limitation of | ||
1838 | * CAPP DMA mode and therefore does not need to worry about this. If the | ||
1839 | * issue with CAPP DMA mode is later worked around on P8 we might need | ||
1840 | * to revisit this. | ||
1841 | */ | ||
1842 | |||
1843 | return true; | ||
1844 | } | ||
1845 | EXPORT_SYMBOL_GPL(cxl_slot_is_supported); | ||
1846 | |||
1847 | |||
1848 | static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id) | 1811 | static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id) |
1849 | { | 1812 | { |
1850 | struct cxl *adapter; | 1813 | struct cxl *adapter; |