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authorMichael Ellerman <mpe@ellerman.id.au>2017-07-03 09:05:43 -0400
committerMichael Ellerman <mpe@ellerman.id.au>2017-07-03 09:05:43 -0400
commit218ea31039e84901b449c3769035456688f6e17d (patch)
tree340773129b6a056c07b3ffe6d60326e0e89ef73c /drivers/misc/cxl/fault.c
parent5405c92bc2cd0c09c7f9716af234b45ef66faa94 (diff)
parentd6bd8194e2867e85ac2de63486d3b83ccfae4e62 (diff)
Merge branch 'fixes' into next
Merge our fixes branch, a few of them are tripping people up while working on top of next, and we also have a dependency between the CXL fixes and new CXL code we want to merge into next.
Diffstat (limited to 'drivers/misc/cxl/fault.c')
-rw-r--r--drivers/misc/cxl/fault.c23
1 files changed, 15 insertions, 8 deletions
diff --git a/drivers/misc/cxl/fault.c b/drivers/misc/cxl/fault.c
index 5344448f514e..c79e39bad7a4 100644
--- a/drivers/misc/cxl/fault.c
+++ b/drivers/misc/cxl/fault.c
@@ -187,7 +187,7 @@ static struct mm_struct *get_mem_context(struct cxl_context *ctx)
187 187
188static bool cxl_is_segment_miss(struct cxl_context *ctx, u64 dsisr) 188static bool cxl_is_segment_miss(struct cxl_context *ctx, u64 dsisr)
189{ 189{
190 if ((cxl_is_psl8(ctx->afu)) && (dsisr & CXL_PSL_DSISR_An_DS)) 190 if ((cxl_is_power8() && (dsisr & CXL_PSL_DSISR_An_DS)))
191 return true; 191 return true;
192 192
193 return false; 193 return false;
@@ -195,16 +195,23 @@ static bool cxl_is_segment_miss(struct cxl_context *ctx, u64 dsisr)
195 195
196static bool cxl_is_page_fault(struct cxl_context *ctx, u64 dsisr) 196static bool cxl_is_page_fault(struct cxl_context *ctx, u64 dsisr)
197{ 197{
198 if ((cxl_is_psl8(ctx->afu)) && (dsisr & CXL_PSL_DSISR_An_DM)) 198 u64 crs; /* Translation Checkout Response Status */
199 return true;
200 199
201 if ((cxl_is_psl9(ctx->afu)) && 200 if ((cxl_is_power8()) && (dsisr & CXL_PSL_DSISR_An_DM))
202 ((dsisr & CXL_PSL9_DSISR_An_CO_MASK) &
203 (CXL_PSL9_DSISR_An_PF_SLR | CXL_PSL9_DSISR_An_PF_RGC |
204 CXL_PSL9_DSISR_An_PF_RGP | CXL_PSL9_DSISR_An_PF_HRH |
205 CXL_PSL9_DSISR_An_PF_STEG)))
206 return true; 201 return true;
207 202
203 if (cxl_is_power9()) {
204 crs = (dsisr & CXL_PSL9_DSISR_An_CO_MASK);
205 if ((crs == CXL_PSL9_DSISR_An_PF_SLR) ||
206 (crs == CXL_PSL9_DSISR_An_PF_RGC) ||
207 (crs == CXL_PSL9_DSISR_An_PF_RGP) ||
208 (crs == CXL_PSL9_DSISR_An_PF_HRH) ||
209 (crs == CXL_PSL9_DSISR_An_PF_STEG) ||
210 (crs == CXL_PSL9_DSISR_An_URTCH)) {
211 return true;
212 }
213 }
214
208 return false; 215 return false;
209} 216}
210 217