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authorPhilipp Zabel <p.zabel@pengutronix.de>2018-09-06 05:02:14 -0400
committerMauro Carvalho Chehab <mchehab+samsung@kernel.org>2018-09-11 13:32:17 -0400
commit51abcf7fdb70b82b7f8a7c177271f29aed9866bd (patch)
tree5afc033dca3d58958c69485afc6ec0ed87c17ec6 /drivers/media
parentb0c351b55bfbc99a83f33536ae66c3f6104362cd (diff)
media: imx-pxp: add i.MX Pixel Pipeline driver
Add a V4L2 mem-to-mem scaler/CSC driver for the Pixel Pipeline (PXP) version found on i.MX6ULL SoCs. A similar variant is used on i.MX7D. Since this driver only uses the legacy pipeline, it should be reasonably easy to extend it to work with the older PXP versions found on i.MX6UL, i.MX6SX, i.MX6SL, i.MX28, and i.MX23. The driver supports scaling and colorspace conversion. There is currently no support for rotation, alpha-blending, and the LUTs. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Diffstat (limited to 'drivers/media')
-rw-r--r--drivers/media/platform/Kconfig9
-rw-r--r--drivers/media/platform/Makefile2
-rw-r--r--drivers/media/platform/imx-pxp.c1752
-rw-r--r--drivers/media/platform/imx-pxp.h1685
4 files changed, 3448 insertions, 0 deletions
diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
index 94c1fe0e9787..f6275874ec9e 100644
--- a/drivers/media/platform/Kconfig
+++ b/drivers/media/platform/Kconfig
@@ -181,6 +181,15 @@ config VIDEO_CODA
181config VIDEO_IMX_VDOA 181config VIDEO_IMX_VDOA
182 def_tristate VIDEO_CODA if SOC_IMX6Q || COMPILE_TEST 182 def_tristate VIDEO_CODA if SOC_IMX6Q || COMPILE_TEST
183 183
184config VIDEO_IMX_PXP
185 tristate "i.MX Pixel Pipeline (PXP)"
186 depends on VIDEO_DEV && VIDEO_V4L2 && (ARCH_MXC || COMPILE_TEST)
187 select VIDEOBUF2_DMA_CONTIG
188 select V4L2_MEM2MEM_DEV
189 help
190 The i.MX Pixel Pipeline is a memory-to-memory engine for scaling,
191 color space conversion, and rotation.
192
184config VIDEO_MEDIATEK_JPEG 193config VIDEO_MEDIATEK_JPEG
185 tristate "Mediatek JPEG Codec driver" 194 tristate "Mediatek JPEG Codec driver"
186 depends on MTK_IOMMU_V1 || COMPILE_TEST 195 depends on MTK_IOMMU_V1 || COMPILE_TEST
diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile
index 41322ab65802..6ab6200dd9c9 100644
--- a/drivers/media/platform/Makefile
+++ b/drivers/media/platform/Makefile
@@ -25,6 +25,8 @@ obj-$(CONFIG_VIDEO_TI_CAL) += ti-vpe/
25obj-$(CONFIG_VIDEO_MX2_EMMAPRP) += mx2_emmaprp.o 25obj-$(CONFIG_VIDEO_MX2_EMMAPRP) += mx2_emmaprp.o
26obj-$(CONFIG_VIDEO_CODA) += coda/ 26obj-$(CONFIG_VIDEO_CODA) += coda/
27 27
28obj-$(CONFIG_VIDEO_IMX_PXP) += imx-pxp.o
29
28obj-$(CONFIG_VIDEO_SH_VEU) += sh_veu.o 30obj-$(CONFIG_VIDEO_SH_VEU) += sh_veu.o
29 31
30obj-$(CONFIG_CEC_GPIO) += cec-gpio/ 32obj-$(CONFIG_CEC_GPIO) += cec-gpio/
diff --git a/drivers/media/platform/imx-pxp.c b/drivers/media/platform/imx-pxp.c
new file mode 100644
index 000000000000..68ecfed7098b
--- /dev/null
+++ b/drivers/media/platform/imx-pxp.c
@@ -0,0 +1,1752 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * i.MX Pixel Pipeline (PXP) mem-to-mem scaler/CSC/rotator driver
4 *
5 * Copyright (c) 2018 Pengutronix, Philipp Zabel
6 *
7 * based on vim2m
8 *
9 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
10 * Pawel Osciak, <pawel@osciak.com>
11 * Marek Szyprowski, <m.szyprowski@samsung.com>
12 */
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/dma-mapping.h>
16#include <linux/io.h>
17#include <linux/iopoll.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/sched.h>
21#include <linux/slab.h>
22
23#include <linux/platform_device.h>
24#include <media/v4l2-mem2mem.h>
25#include <media/v4l2-device.h>
26#include <media/v4l2-ioctl.h>
27#include <media/v4l2-ctrls.h>
28#include <media/v4l2-event.h>
29#include <media/videobuf2-dma-contig.h>
30
31#include "imx-pxp.h"
32
33static unsigned int debug;
34module_param(debug, uint, 0644);
35MODULE_PARM_DESC(debug, "activates debug info");
36
37#define MIN_W 8
38#define MIN_H 8
39#define MAX_W 4096
40#define MAX_H 4096
41#define ALIGN_W 3 /* 8x8 pixel blocks */
42#define ALIGN_H 3
43
44/* Flags that indicate a format can be used for capture/output */
45#define MEM2MEM_CAPTURE (1 << 0)
46#define MEM2MEM_OUTPUT (1 << 1)
47
48#define MEM2MEM_NAME "pxp"
49
50/* Flags that indicate processing mode */
51#define MEM2MEM_HFLIP (1 << 0)
52#define MEM2MEM_VFLIP (1 << 1)
53
54#define dprintk(dev, fmt, arg...) \
55 v4l2_dbg(1, debug, &dev->v4l2_dev, "%s: " fmt, __func__, ## arg)
56
57struct pxp_fmt {
58 u32 fourcc;
59 int depth;
60 /* Types the format can be used for */
61 u32 types;
62};
63
64static struct pxp_fmt formats[] = {
65 {
66 .fourcc = V4L2_PIX_FMT_XBGR32,
67 .depth = 32,
68 /* Both capture and output format */
69 .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
70 }, {
71 .fourcc = V4L2_PIX_FMT_ABGR32,
72 .depth = 32,
73 /* Capture-only format */
74 .types = MEM2MEM_CAPTURE,
75 }, {
76 .fourcc = V4L2_PIX_FMT_BGR24,
77 .depth = 24,
78 .types = MEM2MEM_CAPTURE,
79 }, {
80 .fourcc = V4L2_PIX_FMT_RGB565,
81 .depth = 16,
82 .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
83 }, {
84 .fourcc = V4L2_PIX_FMT_RGB555,
85 .depth = 16,
86 .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
87 }, {
88 .fourcc = V4L2_PIX_FMT_RGB444,
89 .depth = 16,
90 .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
91 }, {
92 .fourcc = V4L2_PIX_FMT_YUV32,
93 .depth = 32,
94 .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
95 }, {
96 .fourcc = V4L2_PIX_FMT_UYVY,
97 .depth = 16,
98 .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
99 }, {
100 .fourcc = V4L2_PIX_FMT_YUYV,
101 .depth = 16,
102 /* Output-only format */
103 .types = MEM2MEM_OUTPUT,
104 }, {
105 .fourcc = V4L2_PIX_FMT_VYUY,
106 .depth = 16,
107 .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
108 }, {
109 .fourcc = V4L2_PIX_FMT_YVYU,
110 .depth = 16,
111 .types = MEM2MEM_OUTPUT,
112 }, {
113 .fourcc = V4L2_PIX_FMT_GREY,
114 .depth = 8,
115 .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
116 }, {
117 .fourcc = V4L2_PIX_FMT_Y4,
118 .depth = 4,
119 .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
120 }, {
121 .fourcc = V4L2_PIX_FMT_NV16,
122 .depth = 16,
123 .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
124 }, {
125 .fourcc = V4L2_PIX_FMT_NV12,
126 .depth = 12,
127 .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
128 }, {
129 .fourcc = V4L2_PIX_FMT_NV21,
130 .depth = 12,
131 .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
132 }, {
133 .fourcc = V4L2_PIX_FMT_NV61,
134 .depth = 16,
135 .types = MEM2MEM_CAPTURE | MEM2MEM_OUTPUT,
136 }, {
137 .fourcc = V4L2_PIX_FMT_YUV422P,
138 .depth = 16,
139 .types = MEM2MEM_OUTPUT,
140 }, {
141 .fourcc = V4L2_PIX_FMT_YUV420,
142 .depth = 12,
143 .types = MEM2MEM_OUTPUT,
144 },
145};
146
147#define NUM_FORMATS ARRAY_SIZE(formats)
148
149/* Per-queue, driver-specific private data */
150struct pxp_q_data {
151 unsigned int width;
152 unsigned int height;
153 unsigned int bytesperline;
154 unsigned int sizeimage;
155 unsigned int sequence;
156 struct pxp_fmt *fmt;
157 enum v4l2_ycbcr_encoding ycbcr_enc;
158 enum v4l2_quantization quant;
159};
160
161enum {
162 V4L2_M2M_SRC = 0,
163 V4L2_M2M_DST = 1,
164};
165
166static struct pxp_fmt *find_format(struct v4l2_format *f)
167{
168 struct pxp_fmt *fmt;
169 unsigned int k;
170
171 for (k = 0; k < NUM_FORMATS; k++) {
172 fmt = &formats[k];
173 if (fmt->fourcc == f->fmt.pix.pixelformat)
174 break;
175 }
176
177 if (k == NUM_FORMATS)
178 return NULL;
179
180 return &formats[k];
181}
182
183struct pxp_dev {
184 struct v4l2_device v4l2_dev;
185 struct video_device vfd;
186
187 struct clk *clk;
188 void __iomem *mmio;
189
190 atomic_t num_inst;
191 struct mutex dev_mutex;
192 spinlock_t irqlock;
193
194 struct v4l2_m2m_dev *m2m_dev;
195};
196
197struct pxp_ctx {
198 struct v4l2_fh fh;
199 struct pxp_dev *dev;
200
201 struct v4l2_ctrl_handler hdl;
202
203 /* Abort requested by m2m */
204 int aborting;
205
206 /* Processing mode */
207 int mode;
208 u8 alpha_component;
209
210 enum v4l2_colorspace colorspace;
211 enum v4l2_xfer_func xfer_func;
212
213 /* Source and destination queue data */
214 struct pxp_q_data q_data[2];
215};
216
217static inline struct pxp_ctx *file2ctx(struct file *file)
218{
219 return container_of(file->private_data, struct pxp_ctx, fh);
220}
221
222static struct pxp_q_data *get_q_data(struct pxp_ctx *ctx,
223 enum v4l2_buf_type type)
224{
225 if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
226 return &ctx->q_data[V4L2_M2M_SRC];
227 else
228 return &ctx->q_data[V4L2_M2M_DST];
229}
230
231static u32 pxp_v4l2_pix_fmt_to_ps_format(u32 v4l2_pix_fmt)
232{
233 switch (v4l2_pix_fmt) {
234 case V4L2_PIX_FMT_XBGR32: return BV_PXP_PS_CTRL_FORMAT__RGB888;
235 case V4L2_PIX_FMT_RGB555: return BV_PXP_PS_CTRL_FORMAT__RGB555;
236 case V4L2_PIX_FMT_RGB444: return BV_PXP_PS_CTRL_FORMAT__RGB444;
237 case V4L2_PIX_FMT_RGB565: return BV_PXP_PS_CTRL_FORMAT__RGB565;
238 case V4L2_PIX_FMT_YUV32: return BV_PXP_PS_CTRL_FORMAT__YUV1P444;
239 case V4L2_PIX_FMT_UYVY: return BV_PXP_PS_CTRL_FORMAT__UYVY1P422;
240 case V4L2_PIX_FMT_YUYV: return BM_PXP_PS_CTRL_WB_SWAP |
241 BV_PXP_PS_CTRL_FORMAT__UYVY1P422;
242 case V4L2_PIX_FMT_VYUY: return BV_PXP_PS_CTRL_FORMAT__VYUY1P422;
243 case V4L2_PIX_FMT_YVYU: return BM_PXP_PS_CTRL_WB_SWAP |
244 BV_PXP_PS_CTRL_FORMAT__VYUY1P422;
245 case V4L2_PIX_FMT_GREY: return BV_PXP_PS_CTRL_FORMAT__Y8;
246 default:
247 case V4L2_PIX_FMT_Y4: return BV_PXP_PS_CTRL_FORMAT__Y4;
248 case V4L2_PIX_FMT_NV16: return BV_PXP_PS_CTRL_FORMAT__YUV2P422;
249 case V4L2_PIX_FMT_NV12: return BV_PXP_PS_CTRL_FORMAT__YUV2P420;
250 case V4L2_PIX_FMT_NV21: return BV_PXP_PS_CTRL_FORMAT__YVU2P420;
251 case V4L2_PIX_FMT_NV61: return BV_PXP_PS_CTRL_FORMAT__YVU2P422;
252 case V4L2_PIX_FMT_YUV422P: return BV_PXP_PS_CTRL_FORMAT__YUV422;
253 case V4L2_PIX_FMT_YUV420: return BV_PXP_PS_CTRL_FORMAT__YUV420;
254 }
255}
256
257static u32 pxp_v4l2_pix_fmt_to_out_format(u32 v4l2_pix_fmt)
258{
259 switch (v4l2_pix_fmt) {
260 case V4L2_PIX_FMT_XBGR32: return BV_PXP_OUT_CTRL_FORMAT__RGB888;
261 case V4L2_PIX_FMT_ABGR32: return BV_PXP_OUT_CTRL_FORMAT__ARGB8888;
262 case V4L2_PIX_FMT_BGR24: return BV_PXP_OUT_CTRL_FORMAT__RGB888P;
263 /* Missing V4L2 pixel formats for ARGB1555 and ARGB4444 */
264 case V4L2_PIX_FMT_RGB555: return BV_PXP_OUT_CTRL_FORMAT__RGB555;
265 case V4L2_PIX_FMT_RGB444: return BV_PXP_OUT_CTRL_FORMAT__RGB444;
266 case V4L2_PIX_FMT_RGB565: return BV_PXP_OUT_CTRL_FORMAT__RGB565;
267 case V4L2_PIX_FMT_YUV32: return BV_PXP_OUT_CTRL_FORMAT__YUV1P444;
268 case V4L2_PIX_FMT_UYVY: return BV_PXP_OUT_CTRL_FORMAT__UYVY1P422;
269 case V4L2_PIX_FMT_VYUY: return BV_PXP_OUT_CTRL_FORMAT__VYUY1P422;
270 case V4L2_PIX_FMT_GREY: return BV_PXP_OUT_CTRL_FORMAT__Y8;
271 default:
272 case V4L2_PIX_FMT_Y4: return BV_PXP_OUT_CTRL_FORMAT__Y4;
273 case V4L2_PIX_FMT_NV16: return BV_PXP_OUT_CTRL_FORMAT__YUV2P422;
274 case V4L2_PIX_FMT_NV12: return BV_PXP_OUT_CTRL_FORMAT__YUV2P420;
275 case V4L2_PIX_FMT_NV61: return BV_PXP_OUT_CTRL_FORMAT__YVU2P422;
276 case V4L2_PIX_FMT_NV21: return BV_PXP_OUT_CTRL_FORMAT__YVU2P420;
277 }
278}
279
280static bool pxp_v4l2_pix_fmt_is_yuv(u32 v4l2_pix_fmt)
281{
282 switch (v4l2_pix_fmt) {
283 case V4L2_PIX_FMT_YUV32:
284 case V4L2_PIX_FMT_UYVY:
285 case V4L2_PIX_FMT_YUYV:
286 case V4L2_PIX_FMT_VYUY:
287 case V4L2_PIX_FMT_YVYU:
288 case V4L2_PIX_FMT_NV16:
289 case V4L2_PIX_FMT_NV12:
290 case V4L2_PIX_FMT_NV61:
291 case V4L2_PIX_FMT_NV21:
292 case V4L2_PIX_FMT_YUV420:
293 case V4L2_PIX_FMT_YUV422P:
294 case V4L2_PIX_FMT_GREY:
295 case V4L2_PIX_FMT_Y4:
296 return true;
297 default:
298 return false;
299 }
300}
301
302static void pxp_setup_csc(struct pxp_ctx *ctx)
303{
304 struct pxp_dev *dev = ctx->dev;
305 enum v4l2_ycbcr_encoding ycbcr_enc;
306 enum v4l2_quantization quantization;
307
308 if (pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_SRC].fmt->fourcc) &&
309 !pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_DST].fmt->fourcc)) {
310 /*
311 * CSC1 YUV/YCbCr to RGB conversion is implemented as follows:
312 *
313 * |R| |C0 0 C1| |Y + Yoffset |
314 * |G| = |C0 C3 C2| * |Cb + UVoffset|
315 * |B| |C0 C4 0 | |Cr + UVoffset|
316 *
317 * Results are clamped to 0..255.
318 *
319 * BT.601 limited range:
320 *
321 * |R| |1.1644 0.0000 1.5960| |Y - 16 |
322 * |G| = |1.1644 -0.3917 -0.8129| * |Cb - 128|
323 * |B| |1.1644 2.0172 0.0000| |Cr - 128|
324 */
325 static const u32 csc1_coef_bt601_lim[3] = {
326 BM_PXP_CSC1_COEF0_YCBCR_MODE |
327 BF_PXP_CSC1_COEF0_C0(0x12a) | /* 1.1641 (-0.03 %) */
328 BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
329 BF_PXP_CSC1_COEF0_Y_OFFSET(-16),
330 BF_PXP_CSC1_COEF1_C1(0x198) | /* 1.5938 (-0.23 %) */
331 BF_PXP_CSC1_COEF1_C4(0x204), /* 2.0156 (-0.16 %) */
332 BF_PXP_CSC1_COEF2_C2(0x730) | /* -0.8125 (+0.04 %) */
333 BF_PXP_CSC1_COEF2_C3(0x79c), /* -0.3906 (+0.11 %) */
334 };
335 /*
336 * BT.601 full range:
337 *
338 * |R| |1.0000 0.0000 1.4020| |Y + 0 |
339 * |G| = |1.0000 -0.3441 -0.7141| * |Cb - 128|
340 * |B| |1.0000 1.7720 0.0000| |Cr - 128|
341 */
342 static const u32 csc1_coef_bt601_full[3] = {
343 BM_PXP_CSC1_COEF0_YCBCR_MODE |
344 BF_PXP_CSC1_COEF0_C0(0x100) | /* 1.0000 (+0.00 %) */
345 BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
346 BF_PXP_CSC1_COEF0_Y_OFFSET(0),
347 BF_PXP_CSC1_COEF1_C1(0x166) | /* 1.3984 (-0.36 %) */
348 BF_PXP_CSC1_COEF1_C4(0x1c5), /* 1.7695 (-0.25 %) */
349 BF_PXP_CSC1_COEF2_C2(0x74a) | /* -0.7109 (+0.32 %) */
350 BF_PXP_CSC1_COEF2_C3(0x7a8), /* -0.3438 (+0.04 %) */
351 };
352 /*
353 * Rec.709 limited range:
354 *
355 * |R| |1.1644 0.0000 1.7927| |Y - 16 |
356 * |G| = |1.1644 -0.2132 -0.5329| * |Cb - 128|
357 * |B| |1.1644 2.1124 0.0000| |Cr - 128|
358 */
359 static const u32 csc1_coef_rec709_lim[3] = {
360 BM_PXP_CSC1_COEF0_YCBCR_MODE |
361 BF_PXP_CSC1_COEF0_C0(0x12a) | /* 1.1641 (-0.03 %) */
362 BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
363 BF_PXP_CSC1_COEF0_Y_OFFSET(-16),
364 BF_PXP_CSC1_COEF1_C1(0x1ca) | /* 1.7891 (-0.37 %) */
365 BF_PXP_CSC1_COEF1_C4(0x21c), /* 2.1094 (-0.30 %) */
366 BF_PXP_CSC1_COEF2_C2(0x778) | /* -0.5312 (+0.16 %) */
367 BF_PXP_CSC1_COEF2_C3(0x7ca), /* -0.2109 (+0.23 %) */
368 };
369 /*
370 * Rec.709 full range:
371 *
372 * |R| |1.0000 0.0000 1.5748| |Y + 0 |
373 * |G| = |1.0000 -0.1873 -0.4681| * |Cb - 128|
374 * |B| |1.0000 1.8556 0.0000| |Cr - 128|
375 */
376 static const u32 csc1_coef_rec709_full[3] = {
377 BM_PXP_CSC1_COEF0_YCBCR_MODE |
378 BF_PXP_CSC1_COEF0_C0(0x100) | /* 1.0000 (+0.00 %) */
379 BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
380 BF_PXP_CSC1_COEF0_Y_OFFSET(0),
381 BF_PXP_CSC1_COEF1_C1(0x193) | /* 1.5742 (-0.06 %) */
382 BF_PXP_CSC1_COEF1_C4(0x1db), /* 1.8555 (-0.01 %) */
383 BF_PXP_CSC1_COEF2_C2(0x789) | /* -0.4648 (+0.33 %) */
384 BF_PXP_CSC1_COEF2_C3(0x7d1), /* -0.1836 (+0.37 %) */
385 };
386 /*
387 * BT.2020 limited range:
388 *
389 * |R| |1.1644 0.0000 1.6787| |Y - 16 |
390 * |G| = |1.1644 -0.1874 -0.6505| * |Cb - 128|
391 * |B| |1.1644 2.1418 0.0000| |Cr - 128|
392 */
393 static const u32 csc1_coef_bt2020_lim[3] = {
394 BM_PXP_CSC1_COEF0_YCBCR_MODE |
395 BF_PXP_CSC1_COEF0_C0(0x12a) | /* 1.1641 (-0.03 %) */
396 BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
397 BF_PXP_CSC1_COEF0_Y_OFFSET(-16),
398 BF_PXP_CSC1_COEF1_C1(0x1ad) | /* 1.6758 (-0.29 %) */
399 BF_PXP_CSC1_COEF1_C4(0x224), /* 2.1406 (-0.11 %) */
400 BF_PXP_CSC1_COEF2_C2(0x75a) | /* -0.6484 (+0.20 %) */
401 BF_PXP_CSC1_COEF2_C3(0x7d1), /* -0.1836 (+0.38 %) */
402 };
403 /*
404 * BT.2020 full range:
405 *
406 * |R| |1.0000 0.0000 1.4746| |Y + 0 |
407 * |G| = |1.0000 -0.1646 -0.5714| * |Cb - 128|
408 * |B| |1.0000 1.8814 0.0000| |Cr - 128|
409 */
410 static const u32 csc1_coef_bt2020_full[3] = {
411 BM_PXP_CSC1_COEF0_YCBCR_MODE |
412 BF_PXP_CSC1_COEF0_C0(0x100) | /* 1.0000 (+0.00 %) */
413 BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
414 BF_PXP_CSC1_COEF0_Y_OFFSET(0),
415 BF_PXP_CSC1_COEF1_C1(0x179) | /* 1.4727 (-0.19 %) */
416 BF_PXP_CSC1_COEF1_C4(0x1e1), /* 1.8789 (-0.25 %) */
417 BF_PXP_CSC1_COEF2_C2(0x76e) | /* -0.5703 (+0.11 %) */
418 BF_PXP_CSC1_COEF2_C3(0x7d6), /* -0.1641 (+0.05 %) */
419 };
420 /*
421 * SMPTE 240m limited range:
422 *
423 * |R| |1.1644 0.0000 1.7937| |Y - 16 |
424 * |G| = |1.1644 -0.2565 -0.5427| * |Cb - 128|
425 * |B| |1.1644 2.0798 0.0000| |Cr - 128|
426 */
427 static const u32 csc1_coef_smpte240m_lim[3] = {
428 BM_PXP_CSC1_COEF0_YCBCR_MODE |
429 BF_PXP_CSC1_COEF0_C0(0x12a) | /* 1.1641 (-0.03 %) */
430 BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
431 BF_PXP_CSC1_COEF0_Y_OFFSET(-16),
432 BF_PXP_CSC1_COEF1_C1(0x1cb) | /* 1.7930 (-0.07 %) */
433 BF_PXP_CSC1_COEF1_C4(0x214), /* 2.0781 (-0.17 %) */
434 BF_PXP_CSC1_COEF2_C2(0x776) | /* -0.5391 (+0.36 %) */
435 BF_PXP_CSC1_COEF2_C3(0x7bf), /* -0.2539 (+0.26 %) */
436 };
437 /*
438 * SMPTE 240m full range:
439 *
440 * |R| |1.0000 0.0000 1.5756| |Y + 0 |
441 * |G| = |1.0000 -0.2253 -0.4767| * |Cb - 128|
442 * |B| |1.0000 1.8270 0.0000| |Cr - 128|
443 */
444 static const u32 csc1_coef_smpte240m_full[3] = {
445 BM_PXP_CSC1_COEF0_YCBCR_MODE |
446 BF_PXP_CSC1_COEF0_C0(0x100) | /* 1.0000 (+0.00 %) */
447 BF_PXP_CSC1_COEF0_UV_OFFSET(-128) |
448 BF_PXP_CSC1_COEF0_Y_OFFSET(0),
449 BF_PXP_CSC1_COEF1_C1(0x193) | /* 1.5742 (-0.14 %) */
450 BF_PXP_CSC1_COEF1_C4(0x1d3), /* 1.8242 (-0.28 %) */
451 BF_PXP_CSC1_COEF2_C2(0x786) | /* -0.4766 (+0.01 %) */
452 BF_PXP_CSC1_COEF2_C3(0x7c7), /* -0.2227 (+0.26 %) */
453 };
454 const u32 *csc1_coef;
455
456 ycbcr_enc = ctx->q_data[V4L2_M2M_SRC].ycbcr_enc;
457 quantization = ctx->q_data[V4L2_M2M_SRC].quant;
458
459 if (ycbcr_enc == V4L2_YCBCR_ENC_601) {
460 if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
461 csc1_coef = csc1_coef_bt601_full;
462 else
463 csc1_coef = csc1_coef_bt601_lim;
464 } else if (ycbcr_enc == V4L2_YCBCR_ENC_709) {
465 if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
466 csc1_coef = csc1_coef_rec709_full;
467 else
468 csc1_coef = csc1_coef_rec709_lim;
469 } else if (ycbcr_enc == V4L2_YCBCR_ENC_BT2020) {
470 if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
471 csc1_coef = csc1_coef_bt2020_full;
472 else
473 csc1_coef = csc1_coef_bt2020_lim;
474 } else {
475 if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
476 csc1_coef = csc1_coef_smpte240m_full;
477 else
478 csc1_coef = csc1_coef_smpte240m_lim;
479 }
480
481 writel(csc1_coef[0], dev->mmio + HW_PXP_CSC1_COEF0);
482 writel(csc1_coef[1], dev->mmio + HW_PXP_CSC1_COEF1);
483 writel(csc1_coef[2], dev->mmio + HW_PXP_CSC1_COEF2);
484 } else {
485 writel(BM_PXP_CSC1_COEF0_BYPASS, dev->mmio + HW_PXP_CSC1_COEF0);
486 }
487
488 if (!pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_SRC].fmt->fourcc) &&
489 pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_DST].fmt->fourcc)) {
490 /*
491 * CSC2 RGB to YUV/YCbCr conversion is implemented as follows:
492 *
493 * |Y | |A1 A2 A3| |R| |D1|
494 * |Cb| = |B1 B2 B3| * |G| + |D2|
495 * |Cr| |C1 C2 C3| |B| |D3|
496 *
497 * Results are clamped to 0..255.
498 *
499 * BT.601 limited range:
500 *
501 * |Y | | 0.2568 0.5041 0.0979| |R| |16 |
502 * |Cb| = |-0.1482 -0.2910 0.4392| * |G| + |128|
503 * |Cr| | 0.4392 0.4392 -0.3678| |B| |128|
504 */
505 static const u32 csc2_coef_bt601_lim[6] = {
506 BF_PXP_CSC2_COEF0_A2(0x081) | /* 0.5039 (-0.02 %) */
507 BF_PXP_CSC2_COEF0_A1(0x041), /* 0.2539 (-0.29 %) */
508 BF_PXP_CSC2_COEF1_B1(0x7db) | /* -0.1445 (+0.37 %) */
509 BF_PXP_CSC2_COEF1_A3(0x019), /* 0.0977 (-0.02 %) */
510 BF_PXP_CSC2_COEF2_B3(0x070) | /* 0.4375 (-0.17 %) */
511 BF_PXP_CSC2_COEF2_B2(0x7b6), /* -0.2891 (+0.20 %) */
512 BF_PXP_CSC2_COEF3_C2(0x7a2) | /* -0.3672 (+0.06 %) */
513 BF_PXP_CSC2_COEF3_C1(0x070), /* 0.4375 (-0.17 %) */
514 BF_PXP_CSC2_COEF4_D1(16) |
515 BF_PXP_CSC2_COEF4_C3(0x7ee), /* -0.0703 (+0.11 %) */
516 BF_PXP_CSC2_COEF5_D3(128) |
517 BF_PXP_CSC2_COEF5_D2(128),
518 };
519 /*
520 * BT.601 full range:
521 *
522 * |Y | | 0.2990 0.5870 0.1140| |R| |0 |
523 * |Cb| = |-0.1687 -0.3313 0.5000| * |G| + |128|
524 * |Cr| | 0.5000 0.5000 -0.4187| |B| |128|
525 */
526 static const u32 csc2_coef_bt601_full[6] = {
527 BF_PXP_CSC2_COEF0_A2(0x096) | /* 0.5859 (-0.11 %) */
528 BF_PXP_CSC2_COEF0_A1(0x04c), /* 0.2969 (-0.21 %) */
529 BF_PXP_CSC2_COEF1_B1(0x7d5) | /* -0.1680 (+0.07 %) */
530 BF_PXP_CSC2_COEF1_A3(0x01d), /* 0.1133 (-0.07 %) */
531 BF_PXP_CSC2_COEF2_B3(0x080) | /* 0.5000 (+0.00 %) */
532 BF_PXP_CSC2_COEF2_B2(0x7ac), /* -0.3281 (+0.32 %) */
533 BF_PXP_CSC2_COEF3_C2(0x795) | /* -0.4180 (+0.07 %) */
534 BF_PXP_CSC2_COEF3_C1(0x080), /* 0.5000 (+0.00 %) */
535 BF_PXP_CSC2_COEF4_D1(0) |
536 BF_PXP_CSC2_COEF4_C3(0x7ec), /* -0.0781 (+0.32 %) */
537 BF_PXP_CSC2_COEF5_D3(128) |
538 BF_PXP_CSC2_COEF5_D2(128),
539 };
540 /*
541 * Rec.709 limited range:
542 *
543 * |Y | | 0.1826 0.6142 0.0620| |R| |16 |
544 * |Cb| = |-0.1007 -0.3385 0.4392| * |G| + |128|
545 * |Cr| | 0.4392 0.4392 -0.3990| |B| |128|
546 */
547 static const u32 csc2_coef_rec709_lim[6] = {
548 BF_PXP_CSC2_COEF0_A2(0x09d) | /* 0.6133 (-0.09 %) */
549 BF_PXP_CSC2_COEF0_A1(0x02e), /* 0.1797 (-0.29 %) */
550 BF_PXP_CSC2_COEF1_B1(0x7e7) | /* -0.0977 (+0.30 %) */
551 BF_PXP_CSC2_COEF1_A3(0x00f), /* 0.0586 (-0.34 %) */
552 BF_PXP_CSC2_COEF2_B3(0x070) | /* 0.4375 (-0.17 %) */
553 BF_PXP_CSC2_COEF2_B2(0x7aa), /* -0.3359 (+0.26 %) */
554 BF_PXP_CSC2_COEF3_C2(0x79a) | /* -0.3984 (+0.05 %) */
555 BF_PXP_CSC2_COEF3_C1(0x070), /* 0.4375 (-0.17 %) */
556 BF_PXP_CSC2_COEF4_D1(16) |
557 BF_PXP_CSC2_COEF4_C3(0x7f6), /* -0.0391 (+0.12 %) */
558 BF_PXP_CSC2_COEF5_D3(128) |
559 BF_PXP_CSC2_COEF5_D2(128),
560 };
561 /*
562 * Rec.709 full range:
563 *
564 * |Y | | 0.2126 0.7152 0.0722| |R| |0 |
565 * |Cb| = |-0.1146 -0.3854 0.5000| * |G| + |128|
566 * |Cr| | 0.5000 0.5000 -0.4542| |B| |128|
567 */
568 static const u32 csc2_coef_rec709_full[6] = {
569 BF_PXP_CSC2_COEF0_A2(0x0b7) | /* 0.7148 (-0.04 %) */
570 BF_PXP_CSC2_COEF0_A1(0x036), /* 0.2109 (-0.17 %) */
571 BF_PXP_CSC2_COEF1_B1(0x7e3) | /* -0.1133 (+0.13 %) */
572 BF_PXP_CSC2_COEF1_A3(0x012), /* 0.0703 (-0.19 %) */
573 BF_PXP_CSC2_COEF2_B3(0x080) | /* 0.5000 (+0.00 %) */
574 BF_PXP_CSC2_COEF2_B2(0x79e), /* -0.3828 (+0.26 %) */
575 BF_PXP_CSC2_COEF3_C2(0x78c) | /* -0.4531 (+0.11 %) */
576 BF_PXP_CSC2_COEF3_C1(0x080), /* 0.5000 (+0.00 %) */
577 BF_PXP_CSC2_COEF4_D1(0) |
578 BF_PXP_CSC2_COEF4_C3(0x7f5), /* -0.0430 (+0.28 %) */
579 BF_PXP_CSC2_COEF5_D3(128) |
580 BF_PXP_CSC2_COEF5_D2(128),
581 };
582 /*
583 * BT.2020 limited range:
584 *
585 * |Y | | 0.2256 0.5823 0.0509| |R| |16 |
586 * |Cb| = |-0.1226 -0.3166 0.4392| * |G| + |128|
587 * |Cr| | 0.4392 0.4392 -0.4039| |B| |128|
588 */
589 static const u32 csc2_coef_bt2020_lim[6] = {
590 BF_PXP_CSC2_COEF0_A2(0x095) | /* 0.5820 (-0.03 %) */
591 BF_PXP_CSC2_COEF0_A1(0x039), /* 0.2227 (-0.30 %) */
592 BF_PXP_CSC2_COEF1_B1(0x7e1) | /* -0.1211 (+0.15 %) */
593 BF_PXP_CSC2_COEF1_A3(0x00d), /* 0.0508 (-0.01 %) */
594 BF_PXP_CSC2_COEF2_B3(0x070) | /* 0.4375 (-0.17 %) */
595 BF_PXP_CSC2_COEF2_B2(0x7af), /* -0.3164 (+0.02 %) */
596 BF_PXP_CSC2_COEF3_C2(0x799) | /* -0.4023 (+0.16 %) */
597 BF_PXP_CSC2_COEF3_C1(0x070), /* 0.4375 (-0.17 %) */
598 BF_PXP_CSC2_COEF4_D1(16) |
599 BF_PXP_CSC2_COEF4_C3(0x7f7), /* -0.0352 (+0.02 %) */
600 BF_PXP_CSC2_COEF5_D3(128) |
601 BF_PXP_CSC2_COEF5_D2(128),
602 };
603 /*
604 * BT.2020 full range:
605 *
606 * |Y | | 0.2627 0.6780 0.0593| |R| |0 |
607 * |Cb| = |-0.1396 -0.3604 0.5000| * |G| + |128|
608 * |Cr| | 0.5000 0.5000 -0.4598| |B| |128|
609 */
610 static const u32 csc2_coef_bt2020_full[6] = {
611 BF_PXP_CSC2_COEF0_A2(0x0ad) | /* 0.6758 (-0.22 %) */
612 BF_PXP_CSC2_COEF0_A1(0x043), /* 0.2617 (-0.10 %) */
613 BF_PXP_CSC2_COEF1_B1(0x7dd) | /* -0.1367 (+0.29 %) */
614 BF_PXP_CSC2_COEF1_A3(0x00f), /* 0.0586 (-0.07 %) */
615 BF_PXP_CSC2_COEF2_B3(0x080) | /* 0.5000 (+0.00 %) */
616 BF_PXP_CSC2_COEF2_B2(0x7a4), /* -0.3594 (+0.10 %) */
617 BF_PXP_CSC2_COEF3_C2(0x78b) | /* -0.4570 (+0.28 %) */
618 BF_PXP_CSC2_COEF3_C1(0x080), /* 0.5000 (+0.00 %) */
619 BF_PXP_CSC2_COEF4_D1(0) |
620 BF_PXP_CSC2_COEF4_C3(0x7f6), /* -0.0391 (+0.11 %) */
621 BF_PXP_CSC2_COEF5_D3(128) |
622 BF_PXP_CSC2_COEF5_D2(128),
623 };
624 /*
625 * SMPTE 240m limited range:
626 *
627 * |Y | | 0.1821 0.6020 0.0747| |R| |16 |
628 * |Cb| = |-0.1019 -0.3373 0.4392| * |G| + |128|
629 * |Cr| | 0.4392 0.4392 -0.3909| |B| |128|
630 */
631 static const u32 csc2_coef_smpte240m_lim[6] = {
632 BF_PXP_CSC2_COEF0_A2(0x09a) | /* 0.6016 (-0.05 %) */
633 BF_PXP_CSC2_COEF0_A1(0x02e), /* 0.1797 (-0.24 %) */
634 BF_PXP_CSC2_COEF1_B1(0x7e6) | /* -0.1016 (+0.03 %) */
635 BF_PXP_CSC2_COEF1_A3(0x013), /* 0.0742 (-0.05 %) */
636 BF_PXP_CSC2_COEF2_B3(0x070) | /* 0.4375 (-0.17 %) */
637 BF_PXP_CSC2_COEF2_B2(0x7aa), /* -0.3359 (+0.14 %) */
638 BF_PXP_CSC2_COEF3_C2(0x79c) | /* -0.3906 (+0.03 %) */
639 BF_PXP_CSC2_COEF3_C1(0x070), /* 0.4375 (-0.17 %) */
640 BF_PXP_CSC2_COEF4_D1(16) |
641 BF_PXP_CSC2_COEF4_C3(0x7f4), /* -0.0469 (+0.14 %) */
642 BF_PXP_CSC2_COEF5_D3(128) |
643 BF_PXP_CSC2_COEF5_D2(128),
644 };
645 /*
646 * SMPTE 240m full range:
647 *
648 * |Y | | 0.2120 0.7010 0.0870| |R| |0 |
649 * |Cb| = |-0.1160 -0.3840 0.5000| * |G| + |128|
650 * |Cr| | 0.5000 0.5000 -0.4450| |B| |128|
651 */
652 static const u32 csc2_coef_smpte240m_full[6] = {
653 BF_PXP_CSC2_COEF0_A2(0x0b3) | /* 0.6992 (-0.18 %) */
654 BF_PXP_CSC2_COEF0_A1(0x036), /* 0.2109 (-0.11 %) */
655 BF_PXP_CSC2_COEF1_B1(0x7e3) | /* -0.1133 (+0.27 %) */
656 BF_PXP_CSC2_COEF1_A3(0x016), /* 0.0859 (-0.11 %) */
657 BF_PXP_CSC2_COEF2_B3(0x080) | /* 0.5000 (+0.00 %) */
658 BF_PXP_CSC2_COEF2_B2(0x79e), /* -0.3828 (+0.12 %) */
659 BF_PXP_CSC2_COEF3_C2(0x78f) | /* -0.4414 (+0.36 %) */
660 BF_PXP_CSC2_COEF3_C1(0x080), /* 0.5000 (+0.00 %) */
661 BF_PXP_CSC2_COEF4_D1(0) |
662 BF_PXP_CSC2_COEF4_C3(0x7f2), /* -0.0547 (+0.03 %) */
663 BF_PXP_CSC2_COEF5_D3(128) |
664 BF_PXP_CSC2_COEF5_D2(128),
665 };
666 const u32 *csc2_coef;
667 u32 csc2_ctrl;
668
669 ycbcr_enc = ctx->q_data[V4L2_M2M_DST].ycbcr_enc;
670 quantization = ctx->q_data[V4L2_M2M_DST].quant;
671
672 if (ycbcr_enc == V4L2_YCBCR_ENC_601) {
673 if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
674 csc2_coef = csc2_coef_bt601_full;
675 else
676 csc2_coef = csc2_coef_bt601_lim;
677 } else if (ycbcr_enc == V4L2_YCBCR_ENC_709) {
678 if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
679 csc2_coef = csc2_coef_rec709_full;
680 else
681 csc2_coef = csc2_coef_rec709_lim;
682 } else if (ycbcr_enc == V4L2_YCBCR_ENC_709) {
683 if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
684 csc2_coef = csc2_coef_bt2020_full;
685 else
686 csc2_coef = csc2_coef_bt2020_lim;
687 } else {
688 if (quantization == V4L2_QUANTIZATION_FULL_RANGE)
689 csc2_coef = csc2_coef_smpte240m_full;
690 else
691 csc2_coef = csc2_coef_smpte240m_lim;
692 }
693 if (quantization == V4L2_QUANTIZATION_FULL_RANGE) {
694 csc2_ctrl = BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YUV <<
695 BP_PXP_CSC2_CTRL_CSC_MODE;
696 } else {
697 csc2_ctrl = BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YCbCr <<
698 BP_PXP_CSC2_CTRL_CSC_MODE;
699 }
700
701 writel(csc2_ctrl, dev->mmio + HW_PXP_CSC2_CTRL);
702 writel(csc2_coef[0], dev->mmio + HW_PXP_CSC2_COEF0);
703 writel(csc2_coef[1], dev->mmio + HW_PXP_CSC2_COEF1);
704 writel(csc2_coef[2], dev->mmio + HW_PXP_CSC2_COEF2);
705 writel(csc2_coef[3], dev->mmio + HW_PXP_CSC2_COEF3);
706 writel(csc2_coef[4], dev->mmio + HW_PXP_CSC2_COEF4);
707 writel(csc2_coef[5], dev->mmio + HW_PXP_CSC2_COEF5);
708 } else {
709 writel(BM_PXP_CSC2_CTRL_BYPASS, dev->mmio + HW_PXP_CSC2_CTRL);
710 }
711}
712
713static int pxp_start(struct pxp_ctx *ctx, struct vb2_v4l2_buffer *in_vb,
714 struct vb2_v4l2_buffer *out_vb)
715{
716 struct pxp_dev *dev = ctx->dev;
717 struct pxp_q_data *q_data;
718 u32 src_width, src_height, src_stride, src_fourcc;
719 u32 dst_width, dst_height, dst_stride, dst_fourcc;
720 dma_addr_t p_in, p_out;
721 u32 ctrl, out_ctrl, out_buf, out_buf2, out_pitch, out_lrc, out_ps_ulc;
722 u32 out_ps_lrc;
723 u32 ps_ctrl, ps_buf, ps_ubuf, ps_vbuf, ps_pitch, ps_scale, ps_offset;
724 u32 as_ulc, as_lrc;
725 u32 y_size;
726 u32 decx, decy, xscale, yscale;
727
728 q_data = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
729
730 src_width = ctx->q_data[V4L2_M2M_SRC].width;
731 dst_width = ctx->q_data[V4L2_M2M_DST].width;
732 src_height = ctx->q_data[V4L2_M2M_SRC].height;
733 dst_height = ctx->q_data[V4L2_M2M_DST].height;
734 src_stride = ctx->q_data[V4L2_M2M_SRC].bytesperline;
735 dst_stride = ctx->q_data[V4L2_M2M_DST].bytesperline;
736 src_fourcc = ctx->q_data[V4L2_M2M_SRC].fmt->fourcc;
737 dst_fourcc = ctx->q_data[V4L2_M2M_DST].fmt->fourcc;
738
739 p_in = vb2_dma_contig_plane_dma_addr(&in_vb->vb2_buf, 0);
740 p_out = vb2_dma_contig_plane_dma_addr(&out_vb->vb2_buf, 0);
741
742 if (!p_in || !p_out) {
743 v4l2_err(&dev->v4l2_dev,
744 "Acquiring DMA addresses of buffers failed\n");
745 return -EFAULT;
746 }
747
748 out_vb->sequence =
749 get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE)->sequence++;
750 in_vb->sequence = q_data->sequence++;
751 out_vb->vb2_buf.timestamp = in_vb->vb2_buf.timestamp;
752
753 if (in_vb->flags & V4L2_BUF_FLAG_TIMECODE)
754 out_vb->timecode = in_vb->timecode;
755 out_vb->field = in_vb->field;
756 out_vb->flags = in_vb->flags &
757 (V4L2_BUF_FLAG_TIMECODE |
758 V4L2_BUF_FLAG_KEYFRAME |
759 V4L2_BUF_FLAG_PFRAME |
760 V4L2_BUF_FLAG_BFRAME |
761 V4L2_BUF_FLAG_TSTAMP_SRC_MASK);
762
763 /* Rotation disabled, 8x8 block size */
764 ctrl = BF_PXP_CTRL_VFLIP0(!!(ctx->mode & MEM2MEM_VFLIP)) |
765 BF_PXP_CTRL_HFLIP0(!!(ctx->mode & MEM2MEM_HFLIP));
766 /* Always write alpha value as V4L2_CID_ALPHA_COMPONENT */
767 out_ctrl = BF_PXP_OUT_CTRL_ALPHA(ctx->alpha_component) |
768 BF_PXP_OUT_CTRL_ALPHA_OUTPUT(1) |
769 pxp_v4l2_pix_fmt_to_out_format(dst_fourcc);
770 out_buf = p_out;
771 switch (dst_fourcc) {
772 case V4L2_PIX_FMT_NV12:
773 case V4L2_PIX_FMT_NV21:
774 case V4L2_PIX_FMT_NV16:
775 case V4L2_PIX_FMT_NV61:
776 out_buf2 = out_buf + dst_stride * dst_height;
777 break;
778 default:
779 out_buf2 = 0;
780 }
781
782 out_pitch = BF_PXP_OUT_PITCH_PITCH(dst_stride);
783 out_lrc = BF_PXP_OUT_LRC_X(dst_width - 1) |
784 BF_PXP_OUT_LRC_Y(dst_height - 1);
785 /* PS covers whole output */
786 out_ps_ulc = BF_PXP_OUT_PS_ULC_X(0) | BF_PXP_OUT_PS_ULC_Y(0);
787 out_ps_lrc = BF_PXP_OUT_PS_LRC_X(dst_width - 1) |
788 BF_PXP_OUT_PS_LRC_Y(dst_height - 1);
789 /* no AS */
790 as_ulc = BF_PXP_OUT_AS_ULC_X(1) | BF_PXP_OUT_AS_ULC_Y(1);
791 as_lrc = BF_PXP_OUT_AS_LRC_X(0) | BF_PXP_OUT_AS_LRC_Y(0);
792
793 decx = (src_width <= dst_width) ? 0 : ilog2(src_width / dst_width);
794 decy = (src_height <= dst_height) ? 0 : ilog2(src_height / dst_height);
795 ps_ctrl = BF_PXP_PS_CTRL_DECX(decx) | BF_PXP_PS_CTRL_DECY(decy) |
796 pxp_v4l2_pix_fmt_to_ps_format(src_fourcc);
797 ps_buf = p_in;
798 y_size = src_stride * src_height;
799 switch (src_fourcc) {
800 case V4L2_PIX_FMT_YUV420:
801 ps_ubuf = ps_buf + y_size;
802 ps_vbuf = ps_ubuf + y_size / 4;
803 break;
804 case V4L2_PIX_FMT_YUV422P:
805 ps_ubuf = ps_buf + y_size;
806 ps_vbuf = ps_ubuf + y_size / 2;
807 break;
808 case V4L2_PIX_FMT_NV12:
809 case V4L2_PIX_FMT_NV21:
810 case V4L2_PIX_FMT_NV16:
811 case V4L2_PIX_FMT_NV61:
812 ps_ubuf = ps_buf + y_size;
813 ps_vbuf = 0;
814 break;
815 case V4L2_PIX_FMT_GREY:
816 case V4L2_PIX_FMT_Y4:
817 ps_ubuf = 0;
818 /* In grayscale mode, ps_vbuf contents are reused as CbCr */
819 ps_vbuf = 0x8080;
820 break;
821 default:
822 ps_ubuf = 0;
823 ps_vbuf = 0;
824 break;
825 }
826 ps_pitch = BF_PXP_PS_PITCH_PITCH(src_stride);
827 if (decx) {
828 xscale = (src_width >> decx) * 0x1000 / dst_width;
829 } else {
830 switch (src_fourcc) {
831 case V4L2_PIX_FMT_UYVY:
832 case V4L2_PIX_FMT_YUYV:
833 case V4L2_PIX_FMT_VYUY:
834 case V4L2_PIX_FMT_YVYU:
835 case V4L2_PIX_FMT_NV16:
836 case V4L2_PIX_FMT_NV12:
837 case V4L2_PIX_FMT_NV21:
838 case V4L2_PIX_FMT_NV61:
839 case V4L2_PIX_FMT_YUV422P:
840 case V4L2_PIX_FMT_YUV420:
841 /*
842 * This avoids sampling past the right edge for
843 * horizontally chroma subsampled formats.
844 */
845 xscale = (src_width - 2) * 0x1000 / (dst_width - 1);
846 break;
847 default:
848 xscale = (src_width - 1) * 0x1000 / (dst_width - 1);
849 break;
850 }
851 }
852 if (decy)
853 yscale = (src_height >> decy) * 0x1000 / dst_height;
854 else
855 yscale = (src_height - 1) * 0x1000 / (dst_height - 1);
856 ps_scale = BF_PXP_PS_SCALE_YSCALE(yscale) |
857 BF_PXP_PS_SCALE_XSCALE(xscale);
858 ps_offset = BF_PXP_PS_OFFSET_YOFFSET(0) | BF_PXP_PS_OFFSET_XOFFSET(0);
859
860 writel(ctrl, dev->mmio + HW_PXP_CTRL);
861 /* skip STAT */
862 writel(out_ctrl, dev->mmio + HW_PXP_OUT_CTRL);
863 writel(out_buf, dev->mmio + HW_PXP_OUT_BUF);
864 writel(out_buf2, dev->mmio + HW_PXP_OUT_BUF2);
865 writel(out_pitch, dev->mmio + HW_PXP_OUT_PITCH);
866 writel(out_lrc, dev->mmio + HW_PXP_OUT_LRC);
867 writel(out_ps_ulc, dev->mmio + HW_PXP_OUT_PS_ULC);
868 writel(out_ps_lrc, dev->mmio + HW_PXP_OUT_PS_LRC);
869 writel(as_ulc, dev->mmio + HW_PXP_OUT_AS_ULC);
870 writel(as_lrc, dev->mmio + HW_PXP_OUT_AS_LRC);
871 writel(ps_ctrl, dev->mmio + HW_PXP_PS_CTRL);
872 writel(ps_buf, dev->mmio + HW_PXP_PS_BUF);
873 writel(ps_ubuf, dev->mmio + HW_PXP_PS_UBUF);
874 writel(ps_vbuf, dev->mmio + HW_PXP_PS_VBUF);
875 writel(ps_pitch, dev->mmio + HW_PXP_PS_PITCH);
876 writel(0x00ffffff, dev->mmio + HW_PXP_PS_BACKGROUND_0);
877 writel(ps_scale, dev->mmio + HW_PXP_PS_SCALE);
878 writel(ps_offset, dev->mmio + HW_PXP_PS_OFFSET);
879 /* disable processed surface color keying */
880 writel(0x00ffffff, dev->mmio + HW_PXP_PS_CLRKEYLOW_0);
881 writel(0x00000000, dev->mmio + HW_PXP_PS_CLRKEYHIGH_0);
882
883 /* disable alpha surface color keying */
884 writel(0x00ffffff, dev->mmio + HW_PXP_AS_CLRKEYLOW_0);
885 writel(0x00000000, dev->mmio + HW_PXP_AS_CLRKEYHIGH_0);
886
887 /* setup CSC */
888 pxp_setup_csc(ctx);
889
890 /* bypass LUT */
891 writel(BM_PXP_LUT_CTRL_BYPASS, dev->mmio + HW_PXP_LUT_CTRL);
892
893 writel(BF_PXP_DATA_PATH_CTRL0_MUX15_SEL(0)|
894 BF_PXP_DATA_PATH_CTRL0_MUX14_SEL(1)|
895 BF_PXP_DATA_PATH_CTRL0_MUX13_SEL(0)|
896 BF_PXP_DATA_PATH_CTRL0_MUX12_SEL(0)|
897 BF_PXP_DATA_PATH_CTRL0_MUX11_SEL(0)|
898 BF_PXP_DATA_PATH_CTRL0_MUX10_SEL(0)|
899 BF_PXP_DATA_PATH_CTRL0_MUX9_SEL(1)|
900 BF_PXP_DATA_PATH_CTRL0_MUX8_SEL(0)|
901 BF_PXP_DATA_PATH_CTRL0_MUX7_SEL(0)|
902 BF_PXP_DATA_PATH_CTRL0_MUX6_SEL(0)|
903 BF_PXP_DATA_PATH_CTRL0_MUX5_SEL(0)|
904 BF_PXP_DATA_PATH_CTRL0_MUX4_SEL(0)|
905 BF_PXP_DATA_PATH_CTRL0_MUX3_SEL(0)|
906 BF_PXP_DATA_PATH_CTRL0_MUX2_SEL(0)|
907 BF_PXP_DATA_PATH_CTRL0_MUX1_SEL(0)|
908 BF_PXP_DATA_PATH_CTRL0_MUX0_SEL(0),
909 dev->mmio + HW_PXP_DATA_PATH_CTRL0);
910 writel(BF_PXP_DATA_PATH_CTRL1_MUX17_SEL(1) |
911 BF_PXP_DATA_PATH_CTRL1_MUX16_SEL(1),
912 dev->mmio + HW_PXP_DATA_PATH_CTRL1);
913
914 writel(0xffff, dev->mmio + HW_PXP_IRQ_MASK);
915
916 /* ungate, enable PS/AS/OUT and PXP operation */
917 writel(BM_PXP_CTRL_IRQ_ENABLE, dev->mmio + HW_PXP_CTRL_SET);
918 writel(BM_PXP_CTRL_ENABLE | BM_PXP_CTRL_ENABLE_CSC2 |
919 BM_PXP_CTRL_ENABLE_LUT | BM_PXP_CTRL_ENABLE_ROTATE0 |
920 BM_PXP_CTRL_ENABLE_PS_AS_OUT, dev->mmio + HW_PXP_CTRL_SET);
921
922 return 0;
923}
924
925static void pxp_job_finish(struct pxp_dev *dev)
926{
927 struct pxp_ctx *curr_ctx;
928 struct vb2_v4l2_buffer *src_vb, *dst_vb;
929 unsigned long flags;
930
931 curr_ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
932
933 if (curr_ctx == NULL) {
934 pr_err("Instance released before the end of transaction\n");
935 return;
936 }
937
938 src_vb = v4l2_m2m_src_buf_remove(curr_ctx->fh.m2m_ctx);
939 dst_vb = v4l2_m2m_dst_buf_remove(curr_ctx->fh.m2m_ctx);
940
941 spin_lock_irqsave(&dev->irqlock, flags);
942 v4l2_m2m_buf_done(src_vb, VB2_BUF_STATE_DONE);
943 v4l2_m2m_buf_done(dst_vb, VB2_BUF_STATE_DONE);
944 spin_unlock_irqrestore(&dev->irqlock, flags);
945
946 dprintk(curr_ctx->dev, "Finishing transaction\n");
947 v4l2_m2m_job_finish(dev->m2m_dev, curr_ctx->fh.m2m_ctx);
948}
949
950/*
951 * mem2mem callbacks
952 */
953static void pxp_device_run(void *priv)
954{
955 struct pxp_ctx *ctx = priv;
956 struct vb2_v4l2_buffer *src_buf, *dst_buf;
957
958 src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
959 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
960
961 pxp_start(ctx, src_buf, dst_buf);
962}
963
964static int pxp_job_ready(void *priv)
965{
966 struct pxp_ctx *ctx = priv;
967
968 if (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) < 1 ||
969 v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) < 1) {
970 dprintk(ctx->dev, "Not enough buffers available\n");
971 return 0;
972 }
973
974 return 1;
975}
976
977static void pxp_job_abort(void *priv)
978{
979 struct pxp_ctx *ctx = priv;
980
981 /* Will cancel the transaction in the next interrupt handler */
982 ctx->aborting = 1;
983}
984
985/*
986 * interrupt handler
987 */
988static irqreturn_t pxp_irq_handler(int irq, void *dev_id)
989{
990 struct pxp_dev *dev = dev_id;
991 u32 stat;
992
993 stat = readl(dev->mmio + HW_PXP_STAT);
994
995 if (stat & BM_PXP_STAT_IRQ0) {
996 /* we expect x = 0, y = height, irq0 = 1 */
997 if (stat & ~(BM_PXP_STAT_BLOCKX | BM_PXP_STAT_BLOCKY |
998 BM_PXP_STAT_IRQ0))
999 dprintk(dev, "%s: stat = 0x%08x\n", __func__, stat);
1000 writel(BM_PXP_STAT_IRQ0, dev->mmio + HW_PXP_STAT_CLR);
1001
1002 pxp_job_finish(dev);
1003 } else {
1004 u32 irq = readl(dev->mmio + HW_PXP_IRQ);
1005
1006 dprintk(dev, "%s: stat = 0x%08x\n", __func__, stat);
1007 dprintk(dev, "%s: irq = 0x%08x\n", __func__, irq);
1008
1009 writel(irq, dev->mmio + HW_PXP_IRQ_CLR);
1010 }
1011
1012 return IRQ_HANDLED;
1013}
1014
1015/*
1016 * video ioctls
1017 */
1018static int pxp_querycap(struct file *file, void *priv,
1019 struct v4l2_capability *cap)
1020{
1021 strlcpy(cap->driver, MEM2MEM_NAME, sizeof(cap->driver));
1022 strlcpy(cap->card, MEM2MEM_NAME, sizeof(cap->card));
1023 snprintf(cap->bus_info, sizeof(cap->bus_info),
1024 "platform:%s", MEM2MEM_NAME);
1025 return 0;
1026}
1027
1028static int pxp_enum_fmt(struct v4l2_fmtdesc *f, u32 type)
1029{
1030 int i, num;
1031 struct pxp_fmt *fmt;
1032
1033 num = 0;
1034
1035 for (i = 0; i < NUM_FORMATS; ++i) {
1036 if (formats[i].types & type) {
1037 /* index-th format of type type found ? */
1038 if (num == f->index)
1039 break;
1040 /*
1041 * Correct type but haven't reached our index yet,
1042 * just increment per-type index
1043 */
1044 ++num;
1045 }
1046 }
1047
1048 if (i < NUM_FORMATS) {
1049 /* Format found */
1050 fmt = &formats[i];
1051 f->pixelformat = fmt->fourcc;
1052 return 0;
1053 }
1054
1055 /* Format not found */
1056 return -EINVAL;
1057}
1058
1059static int pxp_enum_fmt_vid_cap(struct file *file, void *priv,
1060 struct v4l2_fmtdesc *f)
1061{
1062 return pxp_enum_fmt(f, MEM2MEM_CAPTURE);
1063}
1064
1065static int pxp_enum_fmt_vid_out(struct file *file, void *priv,
1066 struct v4l2_fmtdesc *f)
1067{
1068 return pxp_enum_fmt(f, MEM2MEM_OUTPUT);
1069}
1070
1071static int pxp_g_fmt(struct pxp_ctx *ctx, struct v4l2_format *f)
1072{
1073 struct vb2_queue *vq;
1074 struct pxp_q_data *q_data;
1075
1076 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
1077 if (!vq)
1078 return -EINVAL;
1079
1080 q_data = get_q_data(ctx, f->type);
1081
1082 f->fmt.pix.width = q_data->width;
1083 f->fmt.pix.height = q_data->height;
1084 f->fmt.pix.field = V4L2_FIELD_NONE;
1085 f->fmt.pix.pixelformat = q_data->fmt->fourcc;
1086 f->fmt.pix.bytesperline = q_data->bytesperline;
1087 f->fmt.pix.sizeimage = q_data->sizeimage;
1088 f->fmt.pix.colorspace = ctx->colorspace;
1089 f->fmt.pix.xfer_func = ctx->xfer_func;
1090 f->fmt.pix.ycbcr_enc = q_data->ycbcr_enc;
1091 f->fmt.pix.quantization = q_data->quant;
1092
1093 return 0;
1094}
1095
1096static int pxp_g_fmt_vid_out(struct file *file, void *priv,
1097 struct v4l2_format *f)
1098{
1099 return pxp_g_fmt(file2ctx(file), f);
1100}
1101
1102static int pxp_g_fmt_vid_cap(struct file *file, void *priv,
1103 struct v4l2_format *f)
1104{
1105 return pxp_g_fmt(file2ctx(file), f);
1106}
1107
1108static inline u32 pxp_bytesperline(struct pxp_fmt *fmt, u32 width)
1109{
1110 switch (fmt->fourcc) {
1111 case V4L2_PIX_FMT_YUV420:
1112 case V4L2_PIX_FMT_NV12:
1113 case V4L2_PIX_FMT_NV21:
1114 case V4L2_PIX_FMT_YUV422P:
1115 case V4L2_PIX_FMT_NV16:
1116 case V4L2_PIX_FMT_NV61:
1117 return width;
1118 default:
1119 return (width * fmt->depth) >> 3;
1120 }
1121}
1122
1123static inline u32 pxp_sizeimage(struct pxp_fmt *fmt, u32 width, u32 height)
1124{
1125 return (fmt->depth * width * height) >> 3;
1126}
1127
1128static int pxp_try_fmt(struct v4l2_format *f, struct pxp_fmt *fmt)
1129{
1130 v4l_bound_align_image(&f->fmt.pix.width, MIN_W, MAX_W, ALIGN_W,
1131 &f->fmt.pix.height, MIN_H, MAX_H, ALIGN_H, 0);
1132
1133 f->fmt.pix.bytesperline = pxp_bytesperline(fmt, f->fmt.pix.width);
1134 f->fmt.pix.sizeimage = pxp_sizeimage(fmt, f->fmt.pix.width,
1135 f->fmt.pix.height);
1136 f->fmt.pix.field = V4L2_FIELD_NONE;
1137
1138 return 0;
1139}
1140
1141static void
1142pxp_fixup_colorimetry_cap(struct pxp_ctx *ctx, u32 dst_fourcc,
1143 enum v4l2_ycbcr_encoding *ycbcr_enc,
1144 enum v4l2_quantization *quantization)
1145{
1146 bool dst_is_yuv = pxp_v4l2_pix_fmt_is_yuv(dst_fourcc);
1147
1148 if (pxp_v4l2_pix_fmt_is_yuv(ctx->q_data[V4L2_M2M_SRC].fmt->fourcc) ==
1149 dst_is_yuv) {
1150 /*
1151 * There is no support for conversion between different YCbCr
1152 * encodings or between RGB limited and full range.
1153 */
1154 *ycbcr_enc = ctx->q_data[V4L2_M2M_SRC].ycbcr_enc;
1155 *quantization = ctx->q_data[V4L2_M2M_SRC].quant;
1156 } else {
1157 *ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(ctx->colorspace);
1158 *quantization = V4L2_MAP_QUANTIZATION_DEFAULT(!dst_is_yuv,
1159 ctx->colorspace,
1160 *ycbcr_enc);
1161 }
1162}
1163
1164static int pxp_try_fmt_vid_cap(struct file *file, void *priv,
1165 struct v4l2_format *f)
1166{
1167 struct pxp_fmt *fmt;
1168 struct pxp_ctx *ctx = file2ctx(file);
1169
1170 fmt = find_format(f);
1171 if (!fmt) {
1172 f->fmt.pix.pixelformat = formats[0].fourcc;
1173 fmt = find_format(f);
1174 }
1175 if (!(fmt->types & MEM2MEM_CAPTURE)) {
1176 v4l2_err(&ctx->dev->v4l2_dev,
1177 "Fourcc format (0x%08x) invalid.\n",
1178 f->fmt.pix.pixelformat);
1179 return -EINVAL;
1180 }
1181
1182 f->fmt.pix.colorspace = ctx->colorspace;
1183 f->fmt.pix.xfer_func = ctx->xfer_func;
1184
1185 pxp_fixup_colorimetry_cap(ctx, fmt->fourcc,
1186 &f->fmt.pix.ycbcr_enc,
1187 &f->fmt.pix.quantization);
1188
1189 return pxp_try_fmt(f, fmt);
1190}
1191
1192static int pxp_try_fmt_vid_out(struct file *file, void *priv,
1193 struct v4l2_format *f)
1194{
1195 struct pxp_fmt *fmt;
1196 struct pxp_ctx *ctx = file2ctx(file);
1197
1198 fmt = find_format(f);
1199 if (!fmt) {
1200 f->fmt.pix.pixelformat = formats[0].fourcc;
1201 fmt = find_format(f);
1202 }
1203 if (!(fmt->types & MEM2MEM_OUTPUT)) {
1204 v4l2_err(&ctx->dev->v4l2_dev,
1205 "Fourcc format (0x%08x) invalid.\n",
1206 f->fmt.pix.pixelformat);
1207 return -EINVAL;
1208 }
1209
1210 if (!f->fmt.pix.colorspace)
1211 f->fmt.pix.colorspace = V4L2_COLORSPACE_REC709;
1212
1213 return pxp_try_fmt(f, fmt);
1214}
1215
1216static int pxp_s_fmt(struct pxp_ctx *ctx, struct v4l2_format *f)
1217{
1218 struct pxp_q_data *q_data;
1219 struct vb2_queue *vq;
1220
1221 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
1222 if (!vq)
1223 return -EINVAL;
1224
1225 q_data = get_q_data(ctx, f->type);
1226 if (!q_data)
1227 return -EINVAL;
1228
1229 if (vb2_is_busy(vq)) {
1230 v4l2_err(&ctx->dev->v4l2_dev, "%s queue busy\n", __func__);
1231 return -EBUSY;
1232 }
1233
1234 q_data->fmt = find_format(f);
1235 q_data->width = f->fmt.pix.width;
1236 q_data->height = f->fmt.pix.height;
1237 q_data->bytesperline = f->fmt.pix.bytesperline;
1238 q_data->sizeimage = f->fmt.pix.sizeimage;
1239
1240 dprintk(ctx->dev,
1241 "Setting format for type %d, wxh: %dx%d, fmt: %d\n",
1242 f->type, q_data->width, q_data->height, q_data->fmt->fourcc);
1243
1244 return 0;
1245}
1246
1247static int pxp_s_fmt_vid_cap(struct file *file, void *priv,
1248 struct v4l2_format *f)
1249{
1250 struct pxp_ctx *ctx = file2ctx(file);
1251 int ret;
1252
1253 ret = pxp_try_fmt_vid_cap(file, priv, f);
1254 if (ret)
1255 return ret;
1256
1257 ret = pxp_s_fmt(file2ctx(file), f);
1258 if (ret)
1259 return ret;
1260
1261 ctx->q_data[V4L2_M2M_DST].ycbcr_enc = f->fmt.pix.ycbcr_enc;
1262 ctx->q_data[V4L2_M2M_DST].quant = f->fmt.pix.quantization;
1263
1264 return 0;
1265}
1266
1267static int pxp_s_fmt_vid_out(struct file *file, void *priv,
1268 struct v4l2_format *f)
1269{
1270 struct pxp_ctx *ctx = file2ctx(file);
1271 int ret;
1272
1273 ret = pxp_try_fmt_vid_out(file, priv, f);
1274 if (ret)
1275 return ret;
1276
1277 ret = pxp_s_fmt(file2ctx(file), f);
1278 if (ret)
1279 return ret;
1280
1281 ctx->colorspace = f->fmt.pix.colorspace;
1282 ctx->xfer_func = f->fmt.pix.xfer_func;
1283 ctx->q_data[V4L2_M2M_SRC].ycbcr_enc = f->fmt.pix.ycbcr_enc;
1284 ctx->q_data[V4L2_M2M_SRC].quant = f->fmt.pix.quantization;
1285
1286 pxp_fixup_colorimetry_cap(ctx, ctx->q_data[V4L2_M2M_DST].fmt->fourcc,
1287 &ctx->q_data[V4L2_M2M_DST].ycbcr_enc,
1288 &ctx->q_data[V4L2_M2M_DST].quant);
1289
1290 return 0;
1291}
1292
1293static int pxp_s_ctrl(struct v4l2_ctrl *ctrl)
1294{
1295 struct pxp_ctx *ctx =
1296 container_of(ctrl->handler, struct pxp_ctx, hdl);
1297
1298 switch (ctrl->id) {
1299 case V4L2_CID_HFLIP:
1300 if (ctrl->val)
1301 ctx->mode |= MEM2MEM_HFLIP;
1302 else
1303 ctx->mode &= ~MEM2MEM_HFLIP;
1304 break;
1305
1306 case V4L2_CID_VFLIP:
1307 if (ctrl->val)
1308 ctx->mode |= MEM2MEM_VFLIP;
1309 else
1310 ctx->mode &= ~MEM2MEM_VFLIP;
1311 break;
1312
1313 case V4L2_CID_ALPHA_COMPONENT:
1314 ctx->alpha_component = ctrl->val;
1315 break;
1316
1317 default:
1318 v4l2_err(&ctx->dev->v4l2_dev, "Invalid control\n");
1319 return -EINVAL;
1320 }
1321
1322 return 0;
1323}
1324
1325static const struct v4l2_ctrl_ops pxp_ctrl_ops = {
1326 .s_ctrl = pxp_s_ctrl,
1327};
1328
1329static const struct v4l2_ioctl_ops pxp_ioctl_ops = {
1330 .vidioc_querycap = pxp_querycap,
1331
1332 .vidioc_enum_fmt_vid_cap = pxp_enum_fmt_vid_cap,
1333 .vidioc_g_fmt_vid_cap = pxp_g_fmt_vid_cap,
1334 .vidioc_try_fmt_vid_cap = pxp_try_fmt_vid_cap,
1335 .vidioc_s_fmt_vid_cap = pxp_s_fmt_vid_cap,
1336
1337 .vidioc_enum_fmt_vid_out = pxp_enum_fmt_vid_out,
1338 .vidioc_g_fmt_vid_out = pxp_g_fmt_vid_out,
1339 .vidioc_try_fmt_vid_out = pxp_try_fmt_vid_out,
1340 .vidioc_s_fmt_vid_out = pxp_s_fmt_vid_out,
1341
1342 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
1343 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
1344 .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
1345 .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
1346 .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
1347 .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
1348 .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
1349
1350 .vidioc_streamon = v4l2_m2m_ioctl_streamon,
1351 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
1352
1353 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1354 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1355};
1356
1357/*
1358 * Queue operations
1359 */
1360static int pxp_queue_setup(struct vb2_queue *vq,
1361 unsigned int *nbuffers, unsigned int *nplanes,
1362 unsigned int sizes[], struct device *alloc_devs[])
1363{
1364 struct pxp_ctx *ctx = vb2_get_drv_priv(vq);
1365 struct pxp_q_data *q_data;
1366 unsigned int size, count = *nbuffers;
1367
1368 q_data = get_q_data(ctx, vq->type);
1369
1370 size = q_data->sizeimage;
1371
1372 *nbuffers = count;
1373
1374 if (*nplanes)
1375 return sizes[0] < size ? -EINVAL : 0;
1376
1377 *nplanes = 1;
1378 sizes[0] = size;
1379
1380 dprintk(ctx->dev, "get %d buffer(s) of size %d each.\n", count, size);
1381
1382 return 0;
1383}
1384
1385static int pxp_buf_prepare(struct vb2_buffer *vb)
1386{
1387 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1388 struct pxp_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1389 struct pxp_dev *dev = ctx->dev;
1390 struct pxp_q_data *q_data;
1391
1392 dprintk(ctx->dev, "type: %d\n", vb->vb2_queue->type);
1393
1394 q_data = get_q_data(ctx, vb->vb2_queue->type);
1395 if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) {
1396 if (vbuf->field == V4L2_FIELD_ANY)
1397 vbuf->field = V4L2_FIELD_NONE;
1398 if (vbuf->field != V4L2_FIELD_NONE) {
1399 dprintk(dev, "%s field isn't supported\n", __func__);
1400 return -EINVAL;
1401 }
1402 }
1403
1404 if (vb2_plane_size(vb, 0) < q_data->sizeimage) {
1405 dprintk(dev, "%s data will not fit into plane (%lu < %lu)\n",
1406 __func__, vb2_plane_size(vb, 0),
1407 (long)q_data->sizeimage);
1408 return -EINVAL;
1409 }
1410
1411 vb2_set_plane_payload(vb, 0, q_data->sizeimage);
1412
1413 return 0;
1414}
1415
1416static void pxp_buf_queue(struct vb2_buffer *vb)
1417{
1418 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1419 struct pxp_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1420
1421 v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
1422}
1423
1424static int pxp_start_streaming(struct vb2_queue *q, unsigned int count)
1425{
1426 struct pxp_ctx *ctx = vb2_get_drv_priv(q);
1427 struct pxp_q_data *q_data = get_q_data(ctx, q->type);
1428
1429 q_data->sequence = 0;
1430 return 0;
1431}
1432
1433static void pxp_stop_streaming(struct vb2_queue *q)
1434{
1435 struct pxp_ctx *ctx = vb2_get_drv_priv(q);
1436 struct vb2_v4l2_buffer *vbuf;
1437 unsigned long flags;
1438
1439 for (;;) {
1440 if (V4L2_TYPE_IS_OUTPUT(q->type))
1441 vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
1442 else
1443 vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
1444 if (vbuf == NULL)
1445 return;
1446 spin_lock_irqsave(&ctx->dev->irqlock, flags);
1447 v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR);
1448 spin_unlock_irqrestore(&ctx->dev->irqlock, flags);
1449 }
1450}
1451
1452static const struct vb2_ops pxp_qops = {
1453 .queue_setup = pxp_queue_setup,
1454 .buf_prepare = pxp_buf_prepare,
1455 .buf_queue = pxp_buf_queue,
1456 .start_streaming = pxp_start_streaming,
1457 .stop_streaming = pxp_stop_streaming,
1458 .wait_prepare = vb2_ops_wait_prepare,
1459 .wait_finish = vb2_ops_wait_finish,
1460};
1461
1462static int queue_init(void *priv, struct vb2_queue *src_vq,
1463 struct vb2_queue *dst_vq)
1464{
1465 struct pxp_ctx *ctx = priv;
1466 int ret;
1467
1468 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
1469 src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
1470 src_vq->drv_priv = ctx;
1471 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1472 src_vq->ops = &pxp_qops;
1473 src_vq->mem_ops = &vb2_dma_contig_memops;
1474 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
1475 src_vq->lock = &ctx->dev->dev_mutex;
1476 src_vq->dev = ctx->dev->v4l2_dev.dev;
1477
1478 ret = vb2_queue_init(src_vq);
1479 if (ret)
1480 return ret;
1481
1482 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1483 dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
1484 dst_vq->drv_priv = ctx;
1485 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1486 dst_vq->ops = &pxp_qops;
1487 dst_vq->mem_ops = &vb2_dma_contig_memops;
1488 dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
1489 dst_vq->lock = &ctx->dev->dev_mutex;
1490 dst_vq->dev = ctx->dev->v4l2_dev.dev;
1491
1492 return vb2_queue_init(dst_vq);
1493}
1494
1495/*
1496 * File operations
1497 */
1498static int pxp_open(struct file *file)
1499{
1500 struct pxp_dev *dev = video_drvdata(file);
1501 struct pxp_ctx *ctx = NULL;
1502 struct v4l2_ctrl_handler *hdl;
1503 int rc = 0;
1504
1505 if (mutex_lock_interruptible(&dev->dev_mutex))
1506 return -ERESTARTSYS;
1507 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
1508 if (!ctx) {
1509 rc = -ENOMEM;
1510 goto open_unlock;
1511 }
1512
1513 v4l2_fh_init(&ctx->fh, video_devdata(file));
1514 file->private_data = &ctx->fh;
1515 ctx->dev = dev;
1516 hdl = &ctx->hdl;
1517 v4l2_ctrl_handler_init(hdl, 4);
1518 v4l2_ctrl_new_std(hdl, &pxp_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
1519 v4l2_ctrl_new_std(hdl, &pxp_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
1520 v4l2_ctrl_new_std(hdl, &pxp_ctrl_ops, V4L2_CID_ALPHA_COMPONENT,
1521 0, 255, 1, 255);
1522 if (hdl->error) {
1523 rc = hdl->error;
1524 v4l2_ctrl_handler_free(hdl);
1525 kfree(ctx);
1526 goto open_unlock;
1527 }
1528 ctx->fh.ctrl_handler = hdl;
1529 v4l2_ctrl_handler_setup(hdl);
1530
1531 ctx->q_data[V4L2_M2M_SRC].fmt = &formats[0];
1532 ctx->q_data[V4L2_M2M_SRC].width = 640;
1533 ctx->q_data[V4L2_M2M_SRC].height = 480;
1534 ctx->q_data[V4L2_M2M_SRC].bytesperline =
1535 pxp_bytesperline(&formats[0], 640);
1536 ctx->q_data[V4L2_M2M_SRC].sizeimage =
1537 pxp_sizeimage(&formats[0], 640, 480);
1538 ctx->q_data[V4L2_M2M_DST] = ctx->q_data[V4L2_M2M_SRC];
1539 ctx->colorspace = V4L2_COLORSPACE_REC709;
1540
1541 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx, &queue_init);
1542
1543 if (IS_ERR(ctx->fh.m2m_ctx)) {
1544 rc = PTR_ERR(ctx->fh.m2m_ctx);
1545
1546 v4l2_ctrl_handler_free(hdl);
1547 v4l2_fh_exit(&ctx->fh);
1548 kfree(ctx);
1549 goto open_unlock;
1550 }
1551
1552 v4l2_fh_add(&ctx->fh);
1553 atomic_inc(&dev->num_inst);
1554
1555 dprintk(dev, "Created instance: %p, m2m_ctx: %p\n",
1556 ctx, ctx->fh.m2m_ctx);
1557
1558open_unlock:
1559 mutex_unlock(&dev->dev_mutex);
1560 return rc;
1561}
1562
1563static int pxp_release(struct file *file)
1564{
1565 struct pxp_dev *dev = video_drvdata(file);
1566 struct pxp_ctx *ctx = file2ctx(file);
1567
1568 dprintk(dev, "Releasing instance %p\n", ctx);
1569
1570 v4l2_fh_del(&ctx->fh);
1571 v4l2_fh_exit(&ctx->fh);
1572 v4l2_ctrl_handler_free(&ctx->hdl);
1573 mutex_lock(&dev->dev_mutex);
1574 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
1575 mutex_unlock(&dev->dev_mutex);
1576 kfree(ctx);
1577
1578 atomic_dec(&dev->num_inst);
1579
1580 return 0;
1581}
1582
1583static const struct v4l2_file_operations pxp_fops = {
1584 .owner = THIS_MODULE,
1585 .open = pxp_open,
1586 .release = pxp_release,
1587 .poll = v4l2_m2m_fop_poll,
1588 .unlocked_ioctl = video_ioctl2,
1589 .mmap = v4l2_m2m_fop_mmap,
1590};
1591
1592static const struct video_device pxp_videodev = {
1593 .name = MEM2MEM_NAME,
1594 .vfl_dir = VFL_DIR_M2M,
1595 .fops = &pxp_fops,
1596 .device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING,
1597 .ioctl_ops = &pxp_ioctl_ops,
1598 .minor = -1,
1599 .release = video_device_release_empty,
1600};
1601
1602static const struct v4l2_m2m_ops m2m_ops = {
1603 .device_run = pxp_device_run,
1604 .job_ready = pxp_job_ready,
1605 .job_abort = pxp_job_abort,
1606};
1607
1608static void pxp_soft_reset(struct pxp_dev *dev)
1609{
1610 int ret;
1611 u32 val;
1612
1613 writel(BM_PXP_CTRL_SFTRST, dev->mmio + HW_PXP_CTRL_CLR);
1614 writel(BM_PXP_CTRL_CLKGATE, dev->mmio + HW_PXP_CTRL_CLR);
1615
1616 writel(BM_PXP_CTRL_SFTRST, dev->mmio + HW_PXP_CTRL_SET);
1617
1618 ret = readl_poll_timeout(dev->mmio + HW_PXP_CTRL, val,
1619 val & BM_PXP_CTRL_CLKGATE, 0, 100);
1620 if (ret < 0)
1621 pr_err("PXP reset timeout\n");
1622
1623 writel(BM_PXP_CTRL_SFTRST, dev->mmio + HW_PXP_CTRL_CLR);
1624 writel(BM_PXP_CTRL_CLKGATE, dev->mmio + HW_PXP_CTRL_CLR);
1625}
1626
1627static int pxp_probe(struct platform_device *pdev)
1628{
1629 struct pxp_dev *dev;
1630 struct resource *res;
1631 struct video_device *vfd;
1632 int irq;
1633 int ret;
1634
1635 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1636 if (!dev)
1637 return -ENOMEM;
1638
1639 dev->clk = devm_clk_get(&pdev->dev, "axi");
1640 if (IS_ERR(dev->clk)) {
1641 ret = PTR_ERR(dev->clk);
1642 dev_err(&pdev->dev, "Failed to get clk: %d\n", ret);
1643 return ret;
1644 }
1645
1646 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1647 dev->mmio = devm_ioremap_resource(&pdev->dev, res);
1648 if (IS_ERR(dev->mmio)) {
1649 ret = PTR_ERR(dev->mmio);
1650 dev_err(&pdev->dev, "Failed to map register space: %d\n", ret);
1651 return ret;
1652 }
1653
1654 irq = platform_get_irq(pdev, 0);
1655 if (irq < 0) {
1656 dev_err(&pdev->dev, "Failed to get irq resource: %d\n", irq);
1657 return irq;
1658 }
1659
1660 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, pxp_irq_handler,
1661 IRQF_ONESHOT, dev_name(&pdev->dev), dev);
1662 if (ret < 0) {
1663 dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
1664 return ret;
1665 }
1666
1667 clk_prepare_enable(dev->clk);
1668 pxp_soft_reset(dev);
1669
1670 spin_lock_init(&dev->irqlock);
1671
1672 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1673 if (ret)
1674 goto err_clk;
1675
1676 atomic_set(&dev->num_inst, 0);
1677 mutex_init(&dev->dev_mutex);
1678
1679 dev->vfd = pxp_videodev;
1680 vfd = &dev->vfd;
1681 vfd->lock = &dev->dev_mutex;
1682 vfd->v4l2_dev = &dev->v4l2_dev;
1683
1684 video_set_drvdata(vfd, dev);
1685 snprintf(vfd->name, sizeof(vfd->name), "%s", pxp_videodev.name);
1686 v4l2_info(&dev->v4l2_dev,
1687 "Device registered as /dev/video%d\n", vfd->num);
1688
1689 platform_set_drvdata(pdev, dev);
1690
1691 dev->m2m_dev = v4l2_m2m_init(&m2m_ops);
1692 if (IS_ERR(dev->m2m_dev)) {
1693 v4l2_err(&dev->v4l2_dev, "Failed to init mem2mem device\n");
1694 ret = PTR_ERR(dev->m2m_dev);
1695 goto err_v4l2;
1696 }
1697
1698 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1699 if (ret) {
1700 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1701 goto err_m2m;
1702 }
1703
1704 return 0;
1705
1706err_m2m:
1707 v4l2_m2m_release(dev->m2m_dev);
1708err_v4l2:
1709 v4l2_device_unregister(&dev->v4l2_dev);
1710err_clk:
1711 clk_disable_unprepare(dev->clk);
1712
1713 return ret;
1714}
1715
1716static int pxp_remove(struct platform_device *pdev)
1717{
1718 struct pxp_dev *dev = platform_get_drvdata(pdev);
1719
1720 writel(BM_PXP_CTRL_CLKGATE, dev->mmio + HW_PXP_CTRL_SET);
1721 writel(BM_PXP_CTRL_SFTRST, dev->mmio + HW_PXP_CTRL_SET);
1722
1723 clk_disable_unprepare(dev->clk);
1724
1725 v4l2_info(&dev->v4l2_dev, "Removing " MEM2MEM_NAME);
1726 video_unregister_device(&dev->vfd);
1727 v4l2_m2m_release(dev->m2m_dev);
1728 v4l2_device_unregister(&dev->v4l2_dev);
1729
1730 return 0;
1731}
1732
1733static const struct of_device_id pxp_dt_ids[] = {
1734 { .compatible = "fsl,imx6ull-pxp", .data = NULL },
1735 { },
1736};
1737MODULE_DEVICE_TABLE(of, pxp_dt_ids);
1738
1739static struct platform_driver pxp_driver = {
1740 .probe = pxp_probe,
1741 .remove = pxp_remove,
1742 .driver = {
1743 .name = MEM2MEM_NAME,
1744 .of_match_table = of_match_ptr(pxp_dt_ids),
1745 },
1746};
1747
1748module_platform_driver(pxp_driver);
1749
1750MODULE_DESCRIPTION("i.MX PXP mem2mem scaler/CSC/rotator");
1751MODULE_AUTHOR("Philipp Zabel <kernel@pengutronix.de>");
1752MODULE_LICENSE("GPL");
diff --git a/drivers/media/platform/imx-pxp.h b/drivers/media/platform/imx-pxp.h
new file mode 100644
index 000000000000..44f95c749d2e
--- /dev/null
+++ b/drivers/media/platform/imx-pxp.h
@@ -0,0 +1,1685 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Freescale PXP Register Definitions
4 *
5 * based on pxp_dma_v3.h, Xml Revision: 1.77, Template Revision: 1.3
6 *
7 * Copyright 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved.
8 */
9
10#ifndef __IMX_PXP_H__
11#define __IMX_PXP_H__
12
13#define HW_PXP_CTRL (0x00000000)
14#define HW_PXP_CTRL_SET (0x00000004)
15#define HW_PXP_CTRL_CLR (0x00000008)
16#define HW_PXP_CTRL_TOG (0x0000000c)
17
18#define BM_PXP_CTRL_SFTRST 0x80000000
19#define BF_PXP_CTRL_SFTRST(v) \
20 (((v) << 31) & BM_PXP_CTRL_SFTRST)
21#define BM_PXP_CTRL_CLKGATE 0x40000000
22#define BF_PXP_CTRL_CLKGATE(v) \
23 (((v) << 30) & BM_PXP_CTRL_CLKGATE)
24#define BM_PXP_CTRL_RSVD4 0x20000000
25#define BF_PXP_CTRL_RSVD4(v) \
26 (((v) << 29) & BM_PXP_CTRL_RSVD4)
27#define BM_PXP_CTRL_EN_REPEAT 0x10000000
28#define BF_PXP_CTRL_EN_REPEAT(v) \
29 (((v) << 28) & BM_PXP_CTRL_EN_REPEAT)
30#define BM_PXP_CTRL_ENABLE_ROTATE1 0x08000000
31#define BF_PXP_CTRL_ENABLE_ROTATE1(v) \
32 (((v) << 27) & BM_PXP_CTRL_ENABLE_ROTATE1)
33#define BM_PXP_CTRL_ENABLE_ROTATE0 0x04000000
34#define BF_PXP_CTRL_ENABLE_ROTATE0(v) \
35 (((v) << 26) & BM_PXP_CTRL_ENABLE_ROTATE0)
36#define BM_PXP_CTRL_ENABLE_LUT 0x02000000
37#define BF_PXP_CTRL_ENABLE_LUT(v) \
38 (((v) << 25) & BM_PXP_CTRL_ENABLE_LUT)
39#define BM_PXP_CTRL_ENABLE_CSC2 0x01000000
40#define BF_PXP_CTRL_ENABLE_CSC2(v) \
41 (((v) << 24) & BM_PXP_CTRL_ENABLE_CSC2)
42#define BM_PXP_CTRL_BLOCK_SIZE 0x00800000
43#define BF_PXP_CTRL_BLOCK_SIZE(v) \
44 (((v) << 23) & BM_PXP_CTRL_BLOCK_SIZE)
45#define BV_PXP_CTRL_BLOCK_SIZE__8X8 0x0
46#define BV_PXP_CTRL_BLOCK_SIZE__16X16 0x1
47#define BM_PXP_CTRL_RSVD1 0x00400000
48#define BF_PXP_CTRL_RSVD1(v) \
49 (((v) << 22) & BM_PXP_CTRL_RSVD1)
50#define BM_PXP_CTRL_ENABLE_ALPHA_B 0x00200000
51#define BF_PXP_CTRL_ENABLE_ALPHA_B(v) \
52 (((v) << 21) & BM_PXP_CTRL_ENABLE_ALPHA_B)
53#define BM_PXP_CTRL_ENABLE_INPUT_FETCH_STORE 0x00100000
54#define BF_PXP_CTRL_ENABLE_INPUT_FETCH_STORE(v) \
55 (((v) << 20) & BM_PXP_CTRL_ENABLE_INPUT_FETCH_STORE)
56#define BM_PXP_CTRL_ENABLE_WFE_B 0x00080000
57#define BF_PXP_CTRL_ENABLE_WFE_B(v) \
58 (((v) << 19) & BM_PXP_CTRL_ENABLE_WFE_B)
59#define BM_PXP_CTRL_ENABLE_WFE_A 0x00040000
60#define BF_PXP_CTRL_ENABLE_WFE_A(v) \
61 (((v) << 18) & BM_PXP_CTRL_ENABLE_WFE_A)
62#define BM_PXP_CTRL_ENABLE_DITHER 0x00020000
63#define BF_PXP_CTRL_ENABLE_DITHER(v) \
64 (((v) << 17) & BM_PXP_CTRL_ENABLE_DITHER)
65#define BM_PXP_CTRL_ENABLE_PS_AS_OUT 0x00010000
66#define BF_PXP_CTRL_ENABLE_PS_AS_OUT(v) \
67 (((v) << 16) & BM_PXP_CTRL_ENABLE_PS_AS_OUT)
68#define BM_PXP_CTRL_VFLIP1 0x00008000
69#define BF_PXP_CTRL_VFLIP1(v) \
70 (((v) << 15) & BM_PXP_CTRL_VFLIP1)
71#define BM_PXP_CTRL_HFLIP1 0x00004000
72#define BF_PXP_CTRL_HFLIP1(v) \
73 (((v) << 14) & BM_PXP_CTRL_HFLIP1)
74#define BP_PXP_CTRL_ROTATE1 12
75#define BM_PXP_CTRL_ROTATE1 0x00003000
76#define BF_PXP_CTRL_ROTATE1(v) \
77 (((v) << 12) & BM_PXP_CTRL_ROTATE1)
78#define BV_PXP_CTRL_ROTATE1__ROT_0 0x0
79#define BV_PXP_CTRL_ROTATE1__ROT_90 0x1
80#define BV_PXP_CTRL_ROTATE1__ROT_180 0x2
81#define BV_PXP_CTRL_ROTATE1__ROT_270 0x3
82#define BM_PXP_CTRL_VFLIP0 0x00000800
83#define BF_PXP_CTRL_VFLIP0(v) \
84 (((v) << 11) & BM_PXP_CTRL_VFLIP0)
85#define BM_PXP_CTRL_HFLIP0 0x00000400
86#define BF_PXP_CTRL_HFLIP0(v) \
87 (((v) << 10) & BM_PXP_CTRL_HFLIP0)
88#define BP_PXP_CTRL_ROTATE0 8
89#define BM_PXP_CTRL_ROTATE0 0x00000300
90#define BF_PXP_CTRL_ROTATE0(v) \
91 (((v) << 8) & BM_PXP_CTRL_ROTATE0)
92#define BV_PXP_CTRL_ROTATE0__ROT_0 0x0
93#define BV_PXP_CTRL_ROTATE0__ROT_90 0x1
94#define BV_PXP_CTRL_ROTATE0__ROT_180 0x2
95#define BV_PXP_CTRL_ROTATE0__ROT_270 0x3
96#define BP_PXP_CTRL_RSVD0 6
97#define BM_PXP_CTRL_RSVD0 0x000000C0
98#define BF_PXP_CTRL_RSVD0(v) \
99 (((v) << 6) & BM_PXP_CTRL_RSVD0)
100#define BM_PXP_CTRL_HANDSHAKE_ABORT_SKIP 0x00000020
101#define BF_PXP_CTRL_HANDSHAKE_ABORT_SKIP(v) \
102 (((v) << 5) & BM_PXP_CTRL_HANDSHAKE_ABORT_SKIP)
103#define BM_PXP_CTRL_ENABLE_LCD0_HANDSHAKE 0x00000010
104#define BF_PXP_CTRL_ENABLE_LCD0_HANDSHAKE(v) \
105 (((v) << 4) & BM_PXP_CTRL_ENABLE_LCD0_HANDSHAKE)
106#define BM_PXP_CTRL_LUT_DMA_IRQ_ENABLE 0x00000008
107#define BF_PXP_CTRL_LUT_DMA_IRQ_ENABLE(v) \
108 (((v) << 3) & BM_PXP_CTRL_LUT_DMA_IRQ_ENABLE)
109#define BM_PXP_CTRL_NEXT_IRQ_ENABLE 0x00000004
110#define BF_PXP_CTRL_NEXT_IRQ_ENABLE(v) \
111 (((v) << 2) & BM_PXP_CTRL_NEXT_IRQ_ENABLE)
112#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002
113#define BF_PXP_CTRL_IRQ_ENABLE(v) \
114 (((v) << 1) & BM_PXP_CTRL_IRQ_ENABLE)
115#define BM_PXP_CTRL_ENABLE 0x00000001
116#define BF_PXP_CTRL_ENABLE(v) \
117 (((v) << 0) & BM_PXP_CTRL_ENABLE)
118
119#define HW_PXP_STAT (0x00000010)
120#define HW_PXP_STAT_SET (0x00000014)
121#define HW_PXP_STAT_CLR (0x00000018)
122#define HW_PXP_STAT_TOG (0x0000001c)
123
124#define BP_PXP_STAT_BLOCKX 24
125#define BM_PXP_STAT_BLOCKX 0xFF000000
126#define BF_PXP_STAT_BLOCKX(v) \
127 (((v) << 24) & BM_PXP_STAT_BLOCKX)
128#define BP_PXP_STAT_BLOCKY 16
129#define BM_PXP_STAT_BLOCKY 0x00FF0000
130#define BF_PXP_STAT_BLOCKY(v) \
131 (((v) << 16) & BM_PXP_STAT_BLOCKY)
132#define BP_PXP_STAT_AXI_ERROR_ID_1 12
133#define BM_PXP_STAT_AXI_ERROR_ID_1 0x0000F000
134#define BF_PXP_STAT_AXI_ERROR_ID_1(v) \
135 (((v) << 12) & BM_PXP_STAT_AXI_ERROR_ID_1)
136#define BM_PXP_STAT_RSVD2 0x00000800
137#define BF_PXP_STAT_RSVD2(v) \
138 (((v) << 11) & BM_PXP_STAT_RSVD2)
139#define BM_PXP_STAT_AXI_READ_ERROR_1 0x00000400
140#define BF_PXP_STAT_AXI_READ_ERROR_1(v) \
141 (((v) << 10) & BM_PXP_STAT_AXI_READ_ERROR_1)
142#define BM_PXP_STAT_AXI_WRITE_ERROR_1 0x00000200
143#define BF_PXP_STAT_AXI_WRITE_ERROR_1(v) \
144 (((v) << 9) & BM_PXP_STAT_AXI_WRITE_ERROR_1)
145#define BM_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ 0x00000100
146#define BF_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(v) \
147 (((v) << 8) & BM_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ)
148#define BP_PXP_STAT_AXI_ERROR_ID_0 4
149#define BM_PXP_STAT_AXI_ERROR_ID_0 0x000000F0
150#define BF_PXP_STAT_AXI_ERROR_ID_0(v) \
151 (((v) << 4) & BM_PXP_STAT_AXI_ERROR_ID_0)
152#define BM_PXP_STAT_NEXT_IRQ 0x00000008
153#define BF_PXP_STAT_NEXT_IRQ(v) \
154 (((v) << 3) & BM_PXP_STAT_NEXT_IRQ)
155#define BM_PXP_STAT_AXI_READ_ERROR_0 0x00000004
156#define BF_PXP_STAT_AXI_READ_ERROR_0(v) \
157 (((v) << 2) & BM_PXP_STAT_AXI_READ_ERROR_0)
158#define BM_PXP_STAT_AXI_WRITE_ERROR_0 0x00000002
159#define BF_PXP_STAT_AXI_WRITE_ERROR_0(v) \
160 (((v) << 1) & BM_PXP_STAT_AXI_WRITE_ERROR_0)
161#define BM_PXP_STAT_IRQ0 0x00000001
162#define BF_PXP_STAT_IRQ0(v) \
163 (((v) << 0) & BM_PXP_STAT_IRQ0)
164
165#define HW_PXP_OUT_CTRL (0x00000020)
166#define HW_PXP_OUT_CTRL_SET (0x00000024)
167#define HW_PXP_OUT_CTRL_CLR (0x00000028)
168#define HW_PXP_OUT_CTRL_TOG (0x0000002c)
169
170#define BP_PXP_OUT_CTRL_ALPHA 24
171#define BM_PXP_OUT_CTRL_ALPHA 0xFF000000
172#define BF_PXP_OUT_CTRL_ALPHA(v) \
173 (((v) << 24) & BM_PXP_OUT_CTRL_ALPHA)
174#define BM_PXP_OUT_CTRL_ALPHA_OUTPUT 0x00800000
175#define BF_PXP_OUT_CTRL_ALPHA_OUTPUT(v) \
176 (((v) << 23) & BM_PXP_OUT_CTRL_ALPHA_OUTPUT)
177#define BP_PXP_OUT_CTRL_RSVD1 10
178#define BM_PXP_OUT_CTRL_RSVD1 0x007FFC00
179#define BF_PXP_OUT_CTRL_RSVD1(v) \
180 (((v) << 10) & BM_PXP_OUT_CTRL_RSVD1)
181#define BP_PXP_OUT_CTRL_INTERLACED_OUTPUT 8
182#define BM_PXP_OUT_CTRL_INTERLACED_OUTPUT 0x00000300
183#define BF_PXP_OUT_CTRL_INTERLACED_OUTPUT(v) \
184 (((v) << 8) & BM_PXP_OUT_CTRL_INTERLACED_OUTPUT)
185#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__PROGRESSIVE 0x0
186#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD0 0x1
187#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD1 0x2
188#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__INTERLACED 0x3
189#define BP_PXP_OUT_CTRL_RSVD0 5
190#define BM_PXP_OUT_CTRL_RSVD0 0x000000E0
191#define BF_PXP_OUT_CTRL_RSVD0(v) \
192 (((v) << 5) & BM_PXP_OUT_CTRL_RSVD0)
193#define BP_PXP_OUT_CTRL_FORMAT 0
194#define BM_PXP_OUT_CTRL_FORMAT 0x0000001F
195#define BF_PXP_OUT_CTRL_FORMAT(v) \
196 (((v) << 0) & BM_PXP_OUT_CTRL_FORMAT)
197#define BV_PXP_OUT_CTRL_FORMAT__ARGB8888 0x0
198#define BV_PXP_OUT_CTRL_FORMAT__RGB888 0x4
199#define BV_PXP_OUT_CTRL_FORMAT__RGB888P 0x5
200#define BV_PXP_OUT_CTRL_FORMAT__ARGB1555 0x8
201#define BV_PXP_OUT_CTRL_FORMAT__ARGB4444 0x9
202#define BV_PXP_OUT_CTRL_FORMAT__RGB555 0xC
203#define BV_PXP_OUT_CTRL_FORMAT__RGB444 0xD
204#define BV_PXP_OUT_CTRL_FORMAT__RGB565 0xE
205#define BV_PXP_OUT_CTRL_FORMAT__YUV1P444 0x10
206#define BV_PXP_OUT_CTRL_FORMAT__UYVY1P422 0x12
207#define BV_PXP_OUT_CTRL_FORMAT__VYUY1P422 0x13
208#define BV_PXP_OUT_CTRL_FORMAT__Y8 0x14
209#define BV_PXP_OUT_CTRL_FORMAT__Y4 0x15
210#define BV_PXP_OUT_CTRL_FORMAT__YUV2P422 0x18
211#define BV_PXP_OUT_CTRL_FORMAT__YUV2P420 0x19
212#define BV_PXP_OUT_CTRL_FORMAT__YVU2P422 0x1A
213#define BV_PXP_OUT_CTRL_FORMAT__YVU2P420 0x1B
214
215#define HW_PXP_OUT_BUF (0x00000030)
216
217#define BP_PXP_OUT_BUF_ADDR 0
218#define BM_PXP_OUT_BUF_ADDR 0xFFFFFFFF
219#define BF_PXP_OUT_BUF_ADDR(v) (v)
220
221#define HW_PXP_OUT_BUF2 (0x00000040)
222
223#define BP_PXP_OUT_BUF2_ADDR 0
224#define BM_PXP_OUT_BUF2_ADDR 0xFFFFFFFF
225#define BF_PXP_OUT_BUF2_ADDR(v) (v)
226
227#define HW_PXP_OUT_PITCH (0x00000050)
228
229#define BP_PXP_OUT_PITCH_RSVD 16
230#define BM_PXP_OUT_PITCH_RSVD 0xFFFF0000
231#define BF_PXP_OUT_PITCH_RSVD(v) \
232 (((v) << 16) & BM_PXP_OUT_PITCH_RSVD)
233#define BP_PXP_OUT_PITCH_PITCH 0
234#define BM_PXP_OUT_PITCH_PITCH 0x0000FFFF
235#define BF_PXP_OUT_PITCH_PITCH(v) \
236 (((v) << 0) & BM_PXP_OUT_PITCH_PITCH)
237
238#define HW_PXP_OUT_LRC (0x00000060)
239
240#define BP_PXP_OUT_LRC_RSVD1 30
241#define BM_PXP_OUT_LRC_RSVD1 0xC0000000
242#define BF_PXP_OUT_LRC_RSVD1(v) \
243 (((v) << 30) & BM_PXP_OUT_LRC_RSVD1)
244#define BP_PXP_OUT_LRC_X 16
245#define BM_PXP_OUT_LRC_X 0x3FFF0000
246#define BF_PXP_OUT_LRC_X(v) \
247 (((v) << 16) & BM_PXP_OUT_LRC_X)
248#define BP_PXP_OUT_LRC_RSVD0 14
249#define BM_PXP_OUT_LRC_RSVD0 0x0000C000
250#define BF_PXP_OUT_LRC_RSVD0(v) \
251 (((v) << 14) & BM_PXP_OUT_LRC_RSVD0)
252#define BP_PXP_OUT_LRC_Y 0
253#define BM_PXP_OUT_LRC_Y 0x00003FFF
254#define BF_PXP_OUT_LRC_Y(v) \
255 (((v) << 0) & BM_PXP_OUT_LRC_Y)
256
257#define HW_PXP_OUT_PS_ULC (0x00000070)
258
259#define BP_PXP_OUT_PS_ULC_RSVD1 30
260#define BM_PXP_OUT_PS_ULC_RSVD1 0xC0000000
261#define BF_PXP_OUT_PS_ULC_RSVD1(v) \
262 (((v) << 30) & BM_PXP_OUT_PS_ULC_RSVD1)
263#define BP_PXP_OUT_PS_ULC_X 16
264#define BM_PXP_OUT_PS_ULC_X 0x3FFF0000
265#define BF_PXP_OUT_PS_ULC_X(v) \
266 (((v) << 16) & BM_PXP_OUT_PS_ULC_X)
267#define BP_PXP_OUT_PS_ULC_RSVD0 14
268#define BM_PXP_OUT_PS_ULC_RSVD0 0x0000C000
269#define BF_PXP_OUT_PS_ULC_RSVD0(v) \
270 (((v) << 14) & BM_PXP_OUT_PS_ULC_RSVD0)
271#define BP_PXP_OUT_PS_ULC_Y 0
272#define BM_PXP_OUT_PS_ULC_Y 0x00003FFF
273#define BF_PXP_OUT_PS_ULC_Y(v) \
274 (((v) << 0) & BM_PXP_OUT_PS_ULC_Y)
275
276#define HW_PXP_OUT_PS_LRC (0x00000080)
277
278#define BP_PXP_OUT_PS_LRC_RSVD1 30
279#define BM_PXP_OUT_PS_LRC_RSVD1 0xC0000000
280#define BF_PXP_OUT_PS_LRC_RSVD1(v) \
281 (((v) << 30) & BM_PXP_OUT_PS_LRC_RSVD1)
282#define BP_PXP_OUT_PS_LRC_X 16
283#define BM_PXP_OUT_PS_LRC_X 0x3FFF0000
284#define BF_PXP_OUT_PS_LRC_X(v) \
285 (((v) << 16) & BM_PXP_OUT_PS_LRC_X)
286#define BP_PXP_OUT_PS_LRC_RSVD0 14
287#define BM_PXP_OUT_PS_LRC_RSVD0 0x0000C000
288#define BF_PXP_OUT_PS_LRC_RSVD0(v) \
289 (((v) << 14) & BM_PXP_OUT_PS_LRC_RSVD0)
290#define BP_PXP_OUT_PS_LRC_Y 0
291#define BM_PXP_OUT_PS_LRC_Y 0x00003FFF
292#define BF_PXP_OUT_PS_LRC_Y(v) \
293 (((v) << 0) & BM_PXP_OUT_PS_LRC_Y)
294
295#define HW_PXP_OUT_AS_ULC (0x00000090)
296
297#define BP_PXP_OUT_AS_ULC_RSVD1 30
298#define BM_PXP_OUT_AS_ULC_RSVD1 0xC0000000
299#define BF_PXP_OUT_AS_ULC_RSVD1(v) \
300 (((v) << 30) & BM_PXP_OUT_AS_ULC_RSVD1)
301#define BP_PXP_OUT_AS_ULC_X 16
302#define BM_PXP_OUT_AS_ULC_X 0x3FFF0000
303#define BF_PXP_OUT_AS_ULC_X(v) \
304 (((v) << 16) & BM_PXP_OUT_AS_ULC_X)
305#define BP_PXP_OUT_AS_ULC_RSVD0 14
306#define BM_PXP_OUT_AS_ULC_RSVD0 0x0000C000
307#define BF_PXP_OUT_AS_ULC_RSVD0(v) \
308 (((v) << 14) & BM_PXP_OUT_AS_ULC_RSVD0)
309#define BP_PXP_OUT_AS_ULC_Y 0
310#define BM_PXP_OUT_AS_ULC_Y 0x00003FFF
311#define BF_PXP_OUT_AS_ULC_Y(v) \
312 (((v) << 0) & BM_PXP_OUT_AS_ULC_Y)
313
314#define HW_PXP_OUT_AS_LRC (0x000000a0)
315
316#define BP_PXP_OUT_AS_LRC_RSVD1 30
317#define BM_PXP_OUT_AS_LRC_RSVD1 0xC0000000
318#define BF_PXP_OUT_AS_LRC_RSVD1(v) \
319 (((v) << 30) & BM_PXP_OUT_AS_LRC_RSVD1)
320#define BP_PXP_OUT_AS_LRC_X 16
321#define BM_PXP_OUT_AS_LRC_X 0x3FFF0000
322#define BF_PXP_OUT_AS_LRC_X(v) \
323 (((v) << 16) & BM_PXP_OUT_AS_LRC_X)
324#define BP_PXP_OUT_AS_LRC_RSVD0 14
325#define BM_PXP_OUT_AS_LRC_RSVD0 0x0000C000
326#define BF_PXP_OUT_AS_LRC_RSVD0(v) \
327 (((v) << 14) & BM_PXP_OUT_AS_LRC_RSVD0)
328#define BP_PXP_OUT_AS_LRC_Y 0
329#define BM_PXP_OUT_AS_LRC_Y 0x00003FFF
330#define BF_PXP_OUT_AS_LRC_Y(v) \
331 (((v) << 0) & BM_PXP_OUT_AS_LRC_Y)
332
333#define HW_PXP_PS_CTRL (0x000000b0)
334#define HW_PXP_PS_CTRL_SET (0x000000b4)
335#define HW_PXP_PS_CTRL_CLR (0x000000b8)
336#define HW_PXP_PS_CTRL_TOG (0x000000bc)
337
338#define BP_PXP_PS_CTRL_RSVD1 12
339#define BM_PXP_PS_CTRL_RSVD1 0xFFFFF000
340#define BF_PXP_PS_CTRL_RSVD1(v) \
341 (((v) << 12) & BM_PXP_PS_CTRL_RSVD1)
342#define BP_PXP_PS_CTRL_DECX 10
343#define BM_PXP_PS_CTRL_DECX 0x00000C00
344#define BF_PXP_PS_CTRL_DECX(v) \
345 (((v) << 10) & BM_PXP_PS_CTRL_DECX)
346#define BV_PXP_PS_CTRL_DECX__DISABLE 0x0
347#define BV_PXP_PS_CTRL_DECX__DECX2 0x1
348#define BV_PXP_PS_CTRL_DECX__DECX4 0x2
349#define BV_PXP_PS_CTRL_DECX__DECX8 0x3
350#define BP_PXP_PS_CTRL_DECY 8
351#define BM_PXP_PS_CTRL_DECY 0x00000300
352#define BF_PXP_PS_CTRL_DECY(v) \
353 (((v) << 8) & BM_PXP_PS_CTRL_DECY)
354#define BV_PXP_PS_CTRL_DECY__DISABLE 0x0
355#define BV_PXP_PS_CTRL_DECY__DECY2 0x1
356#define BV_PXP_PS_CTRL_DECY__DECY4 0x2
357#define BV_PXP_PS_CTRL_DECY__DECY8 0x3
358#define BM_PXP_PS_CTRL_RSVD0 0x00000080
359#define BF_PXP_PS_CTRL_RSVD0(v) \
360 (((v) << 7) & BM_PXP_PS_CTRL_RSVD0)
361#define BM_PXP_PS_CTRL_WB_SWAP 0x00000040
362#define BF_PXP_PS_CTRL_WB_SWAP(v) \
363 (((v) << 6) & BM_PXP_PS_CTRL_WB_SWAP)
364#define BP_PXP_PS_CTRL_FORMAT 0
365#define BM_PXP_PS_CTRL_FORMAT 0x0000003F
366#define BF_PXP_PS_CTRL_FORMAT(v) \
367 (((v) << 0) & BM_PXP_PS_CTRL_FORMAT)
368#define BV_PXP_PS_CTRL_FORMAT__RGB888 0x4
369#define BV_PXP_PS_CTRL_FORMAT__RGB555 0xC
370#define BV_PXP_PS_CTRL_FORMAT__RGB444 0xD
371#define BV_PXP_PS_CTRL_FORMAT__RGB565 0xE
372#define BV_PXP_PS_CTRL_FORMAT__YUV1P444 0x10
373#define BV_PXP_PS_CTRL_FORMAT__UYVY1P422 0x12
374#define BV_PXP_PS_CTRL_FORMAT__VYUY1P422 0x13
375#define BV_PXP_PS_CTRL_FORMAT__Y8 0x14
376#define BV_PXP_PS_CTRL_FORMAT__Y4 0x15
377#define BV_PXP_PS_CTRL_FORMAT__YUV2P422 0x18
378#define BV_PXP_PS_CTRL_FORMAT__YUV2P420 0x19
379#define BV_PXP_PS_CTRL_FORMAT__YVU2P422 0x1A
380#define BV_PXP_PS_CTRL_FORMAT__YVU2P420 0x1B
381#define BV_PXP_PS_CTRL_FORMAT__YUV422 0x1E
382#define BV_PXP_PS_CTRL_FORMAT__YUV420 0x1F
383
384#define HW_PXP_PS_BUF (0x000000c0)
385
386#define BP_PXP_PS_BUF_ADDR 0
387#define BM_PXP_PS_BUF_ADDR 0xFFFFFFFF
388#define BF_PXP_PS_BUF_ADDR(v) (v)
389
390#define HW_PXP_PS_UBUF (0x000000d0)
391
392#define BP_PXP_PS_UBUF_ADDR 0
393#define BM_PXP_PS_UBUF_ADDR 0xFFFFFFFF
394#define BF_PXP_PS_UBUF_ADDR(v) (v)
395
396#define HW_PXP_PS_VBUF (0x000000e0)
397
398#define BP_PXP_PS_VBUF_ADDR 0
399#define BM_PXP_PS_VBUF_ADDR 0xFFFFFFFF
400#define BF_PXP_PS_VBUF_ADDR(v) (v)
401
402#define HW_PXP_PS_PITCH (0x000000f0)
403
404#define BP_PXP_PS_PITCH_RSVD 16
405#define BM_PXP_PS_PITCH_RSVD 0xFFFF0000
406#define BF_PXP_PS_PITCH_RSVD(v) \
407 (((v) << 16) & BM_PXP_PS_PITCH_RSVD)
408#define BP_PXP_PS_PITCH_PITCH 0
409#define BM_PXP_PS_PITCH_PITCH 0x0000FFFF
410#define BF_PXP_PS_PITCH_PITCH(v) \
411 (((v) << 0) & BM_PXP_PS_PITCH_PITCH)
412
413#define HW_PXP_PS_BACKGROUND_0 (0x00000100)
414
415#define BP_PXP_PS_BACKGROUND_0_RSVD 24
416#define BM_PXP_PS_BACKGROUND_0_RSVD 0xFF000000
417#define BF_PXP_PS_BACKGROUND_0_RSVD(v) \
418 (((v) << 24) & BM_PXP_PS_BACKGROUND_0_RSVD)
419#define BP_PXP_PS_BACKGROUND_0_COLOR 0
420#define BM_PXP_PS_BACKGROUND_0_COLOR 0x00FFFFFF
421#define BF_PXP_PS_BACKGROUND_0_COLOR(v) \
422 (((v) << 0) & BM_PXP_PS_BACKGROUND_0_COLOR)
423
424#define HW_PXP_PS_SCALE (0x00000110)
425
426#define BM_PXP_PS_SCALE_RSVD2 0x80000000
427#define BF_PXP_PS_SCALE_RSVD2(v) \
428 (((v) << 31) & BM_PXP_PS_SCALE_RSVD2)
429#define BP_PXP_PS_SCALE_YSCALE 16
430#define BM_PXP_PS_SCALE_YSCALE 0x7FFF0000
431#define BF_PXP_PS_SCALE_YSCALE(v) \
432 (((v) << 16) & BM_PXP_PS_SCALE_YSCALE)
433#define BM_PXP_PS_SCALE_RSVD1 0x00008000
434#define BF_PXP_PS_SCALE_RSVD1(v) \
435 (((v) << 15) & BM_PXP_PS_SCALE_RSVD1)
436#define BP_PXP_PS_SCALE_XSCALE 0
437#define BM_PXP_PS_SCALE_XSCALE 0x00007FFF
438#define BF_PXP_PS_SCALE_XSCALE(v) \
439 (((v) << 0) & BM_PXP_PS_SCALE_XSCALE)
440
441#define HW_PXP_PS_OFFSET (0x00000120)
442
443#define BP_PXP_PS_OFFSET_RSVD2 28
444#define BM_PXP_PS_OFFSET_RSVD2 0xF0000000
445#define BF_PXP_PS_OFFSET_RSVD2(v) \
446 (((v) << 28) & BM_PXP_PS_OFFSET_RSVD2)
447#define BP_PXP_PS_OFFSET_YOFFSET 16
448#define BM_PXP_PS_OFFSET_YOFFSET 0x0FFF0000
449#define BF_PXP_PS_OFFSET_YOFFSET(v) \
450 (((v) << 16) & BM_PXP_PS_OFFSET_YOFFSET)
451#define BP_PXP_PS_OFFSET_RSVD1 12
452#define BM_PXP_PS_OFFSET_RSVD1 0x0000F000
453#define BF_PXP_PS_OFFSET_RSVD1(v) \
454 (((v) << 12) & BM_PXP_PS_OFFSET_RSVD1)
455#define BP_PXP_PS_OFFSET_XOFFSET 0
456#define BM_PXP_PS_OFFSET_XOFFSET 0x00000FFF
457#define BF_PXP_PS_OFFSET_XOFFSET(v) \
458 (((v) << 0) & BM_PXP_PS_OFFSET_XOFFSET)
459
460#define HW_PXP_PS_CLRKEYLOW_0 (0x00000130)
461
462#define BP_PXP_PS_CLRKEYLOW_0_RSVD1 24
463#define BM_PXP_PS_CLRKEYLOW_0_RSVD1 0xFF000000
464#define BF_PXP_PS_CLRKEYLOW_0_RSVD1(v) \
465 (((v) << 24) & BM_PXP_PS_CLRKEYLOW_0_RSVD1)
466#define BP_PXP_PS_CLRKEYLOW_0_PIXEL 0
467#define BM_PXP_PS_CLRKEYLOW_0_PIXEL 0x00FFFFFF
468#define BF_PXP_PS_CLRKEYLOW_0_PIXEL(v) \
469 (((v) << 0) & BM_PXP_PS_CLRKEYLOW_0_PIXEL)
470
471#define HW_PXP_PS_CLRKEYHIGH_0 (0x00000140)
472
473#define BP_PXP_PS_CLRKEYHIGH_0_RSVD1 24
474#define BM_PXP_PS_CLRKEYHIGH_0_RSVD1 0xFF000000
475#define BF_PXP_PS_CLRKEYHIGH_0_RSVD1(v) \
476 (((v) << 24) & BM_PXP_PS_CLRKEYHIGH_0_RSVD1)
477#define BP_PXP_PS_CLRKEYHIGH_0_PIXEL 0
478#define BM_PXP_PS_CLRKEYHIGH_0_PIXEL 0x00FFFFFF
479#define BF_PXP_PS_CLRKEYHIGH_0_PIXEL(v) \
480 (((v) << 0) & BM_PXP_PS_CLRKEYHIGH_0_PIXEL)
481
482#define HW_PXP_AS_CTRL (0x00000150)
483
484#define BP_PXP_AS_CTRL_RSVD1 22
485#define BM_PXP_AS_CTRL_RSVD1 0xFFC00000
486#define BF_PXP_AS_CTRL_RSVD1(v) \
487 (((v) << 22) & BM_PXP_AS_CTRL_RSVD1)
488#define BM_PXP_AS_CTRL_ALPHA1_INVERT 0x00200000
489#define BF_PXP_AS_CTRL_ALPHA1_INVERT(v) \
490 (((v) << 21) & BM_PXP_AS_CTRL_ALPHA1_INVERT)
491#define BM_PXP_AS_CTRL_ALPHA0_INVERT 0x00100000
492#define BF_PXP_AS_CTRL_ALPHA0_INVERT(v) \
493 (((v) << 20) & BM_PXP_AS_CTRL_ALPHA0_INVERT)
494#define BP_PXP_AS_CTRL_ROP 16
495#define BM_PXP_AS_CTRL_ROP 0x000F0000
496#define BF_PXP_AS_CTRL_ROP(v) \
497 (((v) << 16) & BM_PXP_AS_CTRL_ROP)
498#define BV_PXP_AS_CTRL_ROP__MASKAS 0x0
499#define BV_PXP_AS_CTRL_ROP__MASKNOTAS 0x1
500#define BV_PXP_AS_CTRL_ROP__MASKASNOT 0x2
501#define BV_PXP_AS_CTRL_ROP__MERGEAS 0x3
502#define BV_PXP_AS_CTRL_ROP__MERGENOTAS 0x4
503#define BV_PXP_AS_CTRL_ROP__MERGEASNOT 0x5
504#define BV_PXP_AS_CTRL_ROP__NOTCOPYAS 0x6
505#define BV_PXP_AS_CTRL_ROP__NOT 0x7
506#define BV_PXP_AS_CTRL_ROP__NOTMASKAS 0x8
507#define BV_PXP_AS_CTRL_ROP__NOTMERGEAS 0x9
508#define BV_PXP_AS_CTRL_ROP__XORAS 0xA
509#define BV_PXP_AS_CTRL_ROP__NOTXORAS 0xB
510#define BP_PXP_AS_CTRL_ALPHA 8
511#define BM_PXP_AS_CTRL_ALPHA 0x0000FF00
512#define BF_PXP_AS_CTRL_ALPHA(v) \
513 (((v) << 8) & BM_PXP_AS_CTRL_ALPHA)
514#define BP_PXP_AS_CTRL_FORMAT 4
515#define BM_PXP_AS_CTRL_FORMAT 0x000000F0
516#define BF_PXP_AS_CTRL_FORMAT(v) \
517 (((v) << 4) & BM_PXP_AS_CTRL_FORMAT)
518#define BV_PXP_AS_CTRL_FORMAT__ARGB8888 0x0
519#define BV_PXP_AS_CTRL_FORMAT__RGBA8888 0x1
520#define BV_PXP_AS_CTRL_FORMAT__RGB888 0x4
521#define BV_PXP_AS_CTRL_FORMAT__ARGB1555 0x8
522#define BV_PXP_AS_CTRL_FORMAT__ARGB4444 0x9
523#define BV_PXP_AS_CTRL_FORMAT__RGB555 0xC
524#define BV_PXP_AS_CTRL_FORMAT__RGB444 0xD
525#define BV_PXP_AS_CTRL_FORMAT__RGB565 0xE
526#define BM_PXP_AS_CTRL_ENABLE_COLORKEY 0x00000008
527#define BF_PXP_AS_CTRL_ENABLE_COLORKEY(v) \
528 (((v) << 3) & BM_PXP_AS_CTRL_ENABLE_COLORKEY)
529#define BP_PXP_AS_CTRL_ALPHA_CTRL 1
530#define BM_PXP_AS_CTRL_ALPHA_CTRL 0x00000006
531#define BF_PXP_AS_CTRL_ALPHA_CTRL(v) \
532 (((v) << 1) & BM_PXP_AS_CTRL_ALPHA_CTRL)
533#define BV_PXP_AS_CTRL_ALPHA_CTRL__Embedded 0x0
534#define BV_PXP_AS_CTRL_ALPHA_CTRL__Override 0x1
535#define BV_PXP_AS_CTRL_ALPHA_CTRL__Multiply 0x2
536#define BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs 0x3
537#define BM_PXP_AS_CTRL_RSVD0 0x00000001
538#define BF_PXP_AS_CTRL_RSVD0(v) \
539 (((v) << 0) & BM_PXP_AS_CTRL_RSVD0)
540
541#define HW_PXP_AS_BUF (0x00000160)
542
543#define BP_PXP_AS_BUF_ADDR 0
544#define BM_PXP_AS_BUF_ADDR 0xFFFFFFFF
545#define BF_PXP_AS_BUF_ADDR(v) (v)
546
547#define HW_PXP_AS_PITCH (0x00000170)
548
549#define BP_PXP_AS_PITCH_RSVD 16
550#define BM_PXP_AS_PITCH_RSVD 0xFFFF0000
551#define BF_PXP_AS_PITCH_RSVD(v) \
552 (((v) << 16) & BM_PXP_AS_PITCH_RSVD)
553#define BP_PXP_AS_PITCH_PITCH 0
554#define BM_PXP_AS_PITCH_PITCH 0x0000FFFF
555#define BF_PXP_AS_PITCH_PITCH(v) \
556 (((v) << 0) & BM_PXP_AS_PITCH_PITCH)
557
558#define HW_PXP_AS_CLRKEYLOW_0 (0x00000180)
559
560#define BP_PXP_AS_CLRKEYLOW_0_RSVD1 24
561#define BM_PXP_AS_CLRKEYLOW_0_RSVD1 0xFF000000
562#define BF_PXP_AS_CLRKEYLOW_0_RSVD1(v) \
563 (((v) << 24) & BM_PXP_AS_CLRKEYLOW_0_RSVD1)
564#define BP_PXP_AS_CLRKEYLOW_0_PIXEL 0
565#define BM_PXP_AS_CLRKEYLOW_0_PIXEL 0x00FFFFFF
566#define BF_PXP_AS_CLRKEYLOW_0_PIXEL(v) \
567 (((v) << 0) & BM_PXP_AS_CLRKEYLOW_0_PIXEL)
568
569#define HW_PXP_AS_CLRKEYHIGH_0 (0x00000190)
570
571#define BP_PXP_AS_CLRKEYHIGH_0_RSVD1 24
572#define BM_PXP_AS_CLRKEYHIGH_0_RSVD1 0xFF000000
573#define BF_PXP_AS_CLRKEYHIGH_0_RSVD1(v) \
574 (((v) << 24) & BM_PXP_AS_CLRKEYHIGH_0_RSVD1)
575#define BP_PXP_AS_CLRKEYHIGH_0_PIXEL 0
576#define BM_PXP_AS_CLRKEYHIGH_0_PIXEL 0x00FFFFFF
577#define BF_PXP_AS_CLRKEYHIGH_0_PIXEL(v) \
578 (((v) << 0) & BM_PXP_AS_CLRKEYHIGH_0_PIXEL)
579
580#define HW_PXP_CSC1_COEF0 (0x000001a0)
581
582#define BM_PXP_CSC1_COEF0_YCBCR_MODE 0x80000000
583#define BF_PXP_CSC1_COEF0_YCBCR_MODE(v) \
584 (((v) << 31) & BM_PXP_CSC1_COEF0_YCBCR_MODE)
585#define BM_PXP_CSC1_COEF0_BYPASS 0x40000000
586#define BF_PXP_CSC1_COEF0_BYPASS(v) \
587 (((v) << 30) & BM_PXP_CSC1_COEF0_BYPASS)
588#define BM_PXP_CSC1_COEF0_RSVD1 0x20000000
589#define BF_PXP_CSC1_COEF0_RSVD1(v) \
590 (((v) << 29) & BM_PXP_CSC1_COEF0_RSVD1)
591#define BP_PXP_CSC1_COEF0_C0 18
592#define BM_PXP_CSC1_COEF0_C0 0x1FFC0000
593#define BF_PXP_CSC1_COEF0_C0(v) \
594 (((v) << 18) & BM_PXP_CSC1_COEF0_C0)
595#define BP_PXP_CSC1_COEF0_UV_OFFSET 9
596#define BM_PXP_CSC1_COEF0_UV_OFFSET 0x0003FE00
597#define BF_PXP_CSC1_COEF0_UV_OFFSET(v) \
598 (((v) << 9) & BM_PXP_CSC1_COEF0_UV_OFFSET)
599#define BP_PXP_CSC1_COEF0_Y_OFFSET 0
600#define BM_PXP_CSC1_COEF0_Y_OFFSET 0x000001FF
601#define BF_PXP_CSC1_COEF0_Y_OFFSET(v) \
602 (((v) << 0) & BM_PXP_CSC1_COEF0_Y_OFFSET)
603
604#define HW_PXP_CSC1_COEF1 (0x000001b0)
605
606#define BP_PXP_CSC1_COEF1_RSVD1 27
607#define BM_PXP_CSC1_COEF1_RSVD1 0xF8000000
608#define BF_PXP_CSC1_COEF1_RSVD1(v) \
609 (((v) << 27) & BM_PXP_CSC1_COEF1_RSVD1)
610#define BP_PXP_CSC1_COEF1_C1 16
611#define BM_PXP_CSC1_COEF1_C1 0x07FF0000
612#define BF_PXP_CSC1_COEF1_C1(v) \
613 (((v) << 16) & BM_PXP_CSC1_COEF1_C1)
614#define BP_PXP_CSC1_COEF1_RSVD0 11
615#define BM_PXP_CSC1_COEF1_RSVD0 0x0000F800
616#define BF_PXP_CSC1_COEF1_RSVD0(v) \
617 (((v) << 11) & BM_PXP_CSC1_COEF1_RSVD0)
618#define BP_PXP_CSC1_COEF1_C4 0
619#define BM_PXP_CSC1_COEF1_C4 0x000007FF
620#define BF_PXP_CSC1_COEF1_C4(v) \
621 (((v) << 0) & BM_PXP_CSC1_COEF1_C4)
622
623#define HW_PXP_CSC1_COEF2 (0x000001c0)
624
625#define BP_PXP_CSC1_COEF2_RSVD1 27
626#define BM_PXP_CSC1_COEF2_RSVD1 0xF8000000
627#define BF_PXP_CSC1_COEF2_RSVD1(v) \
628 (((v) << 27) & BM_PXP_CSC1_COEF2_RSVD1)
629#define BP_PXP_CSC1_COEF2_C2 16
630#define BM_PXP_CSC1_COEF2_C2 0x07FF0000
631#define BF_PXP_CSC1_COEF2_C2(v) \
632 (((v) << 16) & BM_PXP_CSC1_COEF2_C2)
633#define BP_PXP_CSC1_COEF2_RSVD0 11
634#define BM_PXP_CSC1_COEF2_RSVD0 0x0000F800
635#define BF_PXP_CSC1_COEF2_RSVD0(v) \
636 (((v) << 11) & BM_PXP_CSC1_COEF2_RSVD0)
637#define BP_PXP_CSC1_COEF2_C3 0
638#define BM_PXP_CSC1_COEF2_C3 0x000007FF
639#define BF_PXP_CSC1_COEF2_C3(v) \
640 (((v) << 0) & BM_PXP_CSC1_COEF2_C3)
641
642#define HW_PXP_CSC2_CTRL (0x000001d0)
643
644#define BP_PXP_CSC2_CTRL_RSVD 3
645#define BM_PXP_CSC2_CTRL_RSVD 0xFFFFFFF8
646#define BF_PXP_CSC2_CTRL_RSVD(v) \
647 (((v) << 3) & BM_PXP_CSC2_CTRL_RSVD)
648#define BP_PXP_CSC2_CTRL_CSC_MODE 1
649#define BM_PXP_CSC2_CTRL_CSC_MODE 0x00000006
650#define BF_PXP_CSC2_CTRL_CSC_MODE(v) \
651 (((v) << 1) & BM_PXP_CSC2_CTRL_CSC_MODE)
652#define BV_PXP_CSC2_CTRL_CSC_MODE__YUV2RGB 0x0
653#define BV_PXP_CSC2_CTRL_CSC_MODE__YCbCr2RGB 0x1
654#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YUV 0x2
655#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YCbCr 0x3
656#define BM_PXP_CSC2_CTRL_BYPASS 0x00000001
657#define BF_PXP_CSC2_CTRL_BYPASS(v) \
658 (((v) << 0) & BM_PXP_CSC2_CTRL_BYPASS)
659
660#define HW_PXP_CSC2_COEF0 (0x000001e0)
661
662#define BP_PXP_CSC2_COEF0_RSVD1 27
663#define BM_PXP_CSC2_COEF0_RSVD1 0xF8000000
664#define BF_PXP_CSC2_COEF0_RSVD1(v) \
665 (((v) << 27) & BM_PXP_CSC2_COEF0_RSVD1)
666#define BP_PXP_CSC2_COEF0_A2 16
667#define BM_PXP_CSC2_COEF0_A2 0x07FF0000
668#define BF_PXP_CSC2_COEF0_A2(v) \
669 (((v) << 16) & BM_PXP_CSC2_COEF0_A2)
670#define BP_PXP_CSC2_COEF0_RSVD0 11
671#define BM_PXP_CSC2_COEF0_RSVD0 0x0000F800
672#define BF_PXP_CSC2_COEF0_RSVD0(v) \
673 (((v) << 11) & BM_PXP_CSC2_COEF0_RSVD0)
674#define BP_PXP_CSC2_COEF0_A1 0
675#define BM_PXP_CSC2_COEF0_A1 0x000007FF
676#define BF_PXP_CSC2_COEF0_A1(v) \
677 (((v) << 0) & BM_PXP_CSC2_COEF0_A1)
678
679#define HW_PXP_CSC2_COEF1 (0x000001f0)
680
681#define BP_PXP_CSC2_COEF1_RSVD1 27
682#define BM_PXP_CSC2_COEF1_RSVD1 0xF8000000
683#define BF_PXP_CSC2_COEF1_RSVD1(v) \
684 (((v) << 27) & BM_PXP_CSC2_COEF1_RSVD1)
685#define BP_PXP_CSC2_COEF1_B1 16
686#define BM_PXP_CSC2_COEF1_B1 0x07FF0000
687#define BF_PXP_CSC2_COEF1_B1(v) \
688 (((v) << 16) & BM_PXP_CSC2_COEF1_B1)
689#define BP_PXP_CSC2_COEF1_RSVD0 11
690#define BM_PXP_CSC2_COEF1_RSVD0 0x0000F800
691#define BF_PXP_CSC2_COEF1_RSVD0(v) \
692 (((v) << 11) & BM_PXP_CSC2_COEF1_RSVD0)
693#define BP_PXP_CSC2_COEF1_A3 0
694#define BM_PXP_CSC2_COEF1_A3 0x000007FF
695#define BF_PXP_CSC2_COEF1_A3(v) \
696 (((v) << 0) & BM_PXP_CSC2_COEF1_A3)
697
698#define HW_PXP_CSC2_COEF2 (0x00000200)
699
700#define BP_PXP_CSC2_COEF2_RSVD1 27
701#define BM_PXP_CSC2_COEF2_RSVD1 0xF8000000
702#define BF_PXP_CSC2_COEF2_RSVD1(v) \
703 (((v) << 27) & BM_PXP_CSC2_COEF2_RSVD1)
704#define BP_PXP_CSC2_COEF2_B3 16
705#define BM_PXP_CSC2_COEF2_B3 0x07FF0000
706#define BF_PXP_CSC2_COEF2_B3(v) \
707 (((v) << 16) & BM_PXP_CSC2_COEF2_B3)
708#define BP_PXP_CSC2_COEF2_RSVD0 11
709#define BM_PXP_CSC2_COEF2_RSVD0 0x0000F800
710#define BF_PXP_CSC2_COEF2_RSVD0(v) \
711 (((v) << 11) & BM_PXP_CSC2_COEF2_RSVD0)
712#define BP_PXP_CSC2_COEF2_B2 0
713#define BM_PXP_CSC2_COEF2_B2 0x000007FF
714#define BF_PXP_CSC2_COEF2_B2(v) \
715 (((v) << 0) & BM_PXP_CSC2_COEF2_B2)
716
717#define HW_PXP_CSC2_COEF3 (0x00000210)
718
719#define BP_PXP_CSC2_COEF3_RSVD1 27
720#define BM_PXP_CSC2_COEF3_RSVD1 0xF8000000
721#define BF_PXP_CSC2_COEF3_RSVD1(v) \
722 (((v) << 27) & BM_PXP_CSC2_COEF3_RSVD1)
723#define BP_PXP_CSC2_COEF3_C2 16
724#define BM_PXP_CSC2_COEF3_C2 0x07FF0000
725#define BF_PXP_CSC2_COEF3_C2(v) \
726 (((v) << 16) & BM_PXP_CSC2_COEF3_C2)
727#define BP_PXP_CSC2_COEF3_RSVD0 11
728#define BM_PXP_CSC2_COEF3_RSVD0 0x0000F800
729#define BF_PXP_CSC2_COEF3_RSVD0(v) \
730 (((v) << 11) & BM_PXP_CSC2_COEF3_RSVD0)
731#define BP_PXP_CSC2_COEF3_C1 0
732#define BM_PXP_CSC2_COEF3_C1 0x000007FF
733#define BF_PXP_CSC2_COEF3_C1(v) \
734 (((v) << 0) & BM_PXP_CSC2_COEF3_C1)
735
736#define HW_PXP_CSC2_COEF4 (0x00000220)
737
738#define BP_PXP_CSC2_COEF4_RSVD1 25
739#define BM_PXP_CSC2_COEF4_RSVD1 0xFE000000
740#define BF_PXP_CSC2_COEF4_RSVD1(v) \
741 (((v) << 25) & BM_PXP_CSC2_COEF4_RSVD1)
742#define BP_PXP_CSC2_COEF4_D1 16
743#define BM_PXP_CSC2_COEF4_D1 0x01FF0000
744#define BF_PXP_CSC2_COEF4_D1(v) \
745 (((v) << 16) & BM_PXP_CSC2_COEF4_D1)
746#define BP_PXP_CSC2_COEF4_RSVD0 11
747#define BM_PXP_CSC2_COEF4_RSVD0 0x0000F800
748#define BF_PXP_CSC2_COEF4_RSVD0(v) \
749 (((v) << 11) & BM_PXP_CSC2_COEF4_RSVD0)
750#define BP_PXP_CSC2_COEF4_C3 0
751#define BM_PXP_CSC2_COEF4_C3 0x000007FF
752#define BF_PXP_CSC2_COEF4_C3(v) \
753 (((v) << 0) & BM_PXP_CSC2_COEF4_C3)
754
755#define HW_PXP_CSC2_COEF5 (0x00000230)
756
757#define BP_PXP_CSC2_COEF5_RSVD1 25
758#define BM_PXP_CSC2_COEF5_RSVD1 0xFE000000
759#define BF_PXP_CSC2_COEF5_RSVD1(v) \
760 (((v) << 25) & BM_PXP_CSC2_COEF5_RSVD1)
761#define BP_PXP_CSC2_COEF5_D3 16
762#define BM_PXP_CSC2_COEF5_D3 0x01FF0000
763#define BF_PXP_CSC2_COEF5_D3(v) \
764 (((v) << 16) & BM_PXP_CSC2_COEF5_D3)
765#define BP_PXP_CSC2_COEF5_RSVD0 9
766#define BM_PXP_CSC2_COEF5_RSVD0 0x0000FE00
767#define BF_PXP_CSC2_COEF5_RSVD0(v) \
768 (((v) << 9) & BM_PXP_CSC2_COEF5_RSVD0)
769#define BP_PXP_CSC2_COEF5_D2 0
770#define BM_PXP_CSC2_COEF5_D2 0x000001FF
771#define BF_PXP_CSC2_COEF5_D2(v) \
772 (((v) << 0) & BM_PXP_CSC2_COEF5_D2)
773
774#define HW_PXP_LUT_CTRL (0x00000240)
775
776#define BM_PXP_LUT_CTRL_BYPASS 0x80000000
777#define BF_PXP_LUT_CTRL_BYPASS(v) \
778 (((v) << 31) & BM_PXP_LUT_CTRL_BYPASS)
779#define BP_PXP_LUT_CTRL_RSVD3 26
780#define BM_PXP_LUT_CTRL_RSVD3 0x7C000000
781#define BF_PXP_LUT_CTRL_RSVD3(v) \
782 (((v) << 26) & BM_PXP_LUT_CTRL_RSVD3)
783#define BP_PXP_LUT_CTRL_LOOKUP_MODE 24
784#define BM_PXP_LUT_CTRL_LOOKUP_MODE 0x03000000
785#define BF_PXP_LUT_CTRL_LOOKUP_MODE(v) \
786 (((v) << 24) & BM_PXP_LUT_CTRL_LOOKUP_MODE)
787#define BV_PXP_LUT_CTRL_LOOKUP_MODE__CACHE_RGB565 0x0
788#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8 0x1
789#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB444 0x2
790#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB454 0x3
791#define BP_PXP_LUT_CTRL_RSVD2 18
792#define BM_PXP_LUT_CTRL_RSVD2 0x00FC0000
793#define BF_PXP_LUT_CTRL_RSVD2(v) \
794 (((v) << 18) & BM_PXP_LUT_CTRL_RSVD2)
795#define BP_PXP_LUT_CTRL_OUT_MODE 16
796#define BM_PXP_LUT_CTRL_OUT_MODE 0x00030000
797#define BF_PXP_LUT_CTRL_OUT_MODE(v) \
798 (((v) << 16) & BM_PXP_LUT_CTRL_OUT_MODE)
799#define BV_PXP_LUT_CTRL_OUT_MODE__RESERVED 0x0
800#define BV_PXP_LUT_CTRL_OUT_MODE__Y8 0x1
801#define BV_PXP_LUT_CTRL_OUT_MODE__RGBW4444CFA 0x2
802#define BV_PXP_LUT_CTRL_OUT_MODE__RGB888 0x3
803#define BP_PXP_LUT_CTRL_RSVD1 11
804#define BM_PXP_LUT_CTRL_RSVD1 0x0000F800
805#define BF_PXP_LUT_CTRL_RSVD1(v) \
806 (((v) << 11) & BM_PXP_LUT_CTRL_RSVD1)
807#define BM_PXP_LUT_CTRL_SEL_8KB 0x00000400
808#define BF_PXP_LUT_CTRL_SEL_8KB(v) \
809 (((v) << 10) & BM_PXP_LUT_CTRL_SEL_8KB)
810#define BM_PXP_LUT_CTRL_LRU_UPD 0x00000200
811#define BF_PXP_LUT_CTRL_LRU_UPD(v) \
812 (((v) << 9) & BM_PXP_LUT_CTRL_LRU_UPD)
813#define BM_PXP_LUT_CTRL_INVALID 0x00000100
814#define BF_PXP_LUT_CTRL_INVALID(v) \
815 (((v) << 8) & BM_PXP_LUT_CTRL_INVALID)
816#define BP_PXP_LUT_CTRL_RSVD0 1
817#define BM_PXP_LUT_CTRL_RSVD0 0x000000FE
818#define BF_PXP_LUT_CTRL_RSVD0(v) \
819 (((v) << 1) & BM_PXP_LUT_CTRL_RSVD0)
820#define BM_PXP_LUT_CTRL_DMA_START 0x00000001
821#define BF_PXP_LUT_CTRL_DMA_START(v) \
822 (((v) << 0) & BM_PXP_LUT_CTRL_DMA_START)
823
824#define HW_PXP_LUT_ADDR (0x00000250)
825
826#define BM_PXP_LUT_ADDR_RSVD2 0x80000000
827#define BF_PXP_LUT_ADDR_RSVD2(v) \
828 (((v) << 31) & BM_PXP_LUT_ADDR_RSVD2)
829#define BP_PXP_LUT_ADDR_NUM_BYTES 16
830#define BM_PXP_LUT_ADDR_NUM_BYTES 0x7FFF0000
831#define BF_PXP_LUT_ADDR_NUM_BYTES(v) \
832 (((v) << 16) & BM_PXP_LUT_ADDR_NUM_BYTES)
833#define BP_PXP_LUT_ADDR_RSVD1 14
834#define BM_PXP_LUT_ADDR_RSVD1 0x0000C000
835#define BF_PXP_LUT_ADDR_RSVD1(v) \
836 (((v) << 14) & BM_PXP_LUT_ADDR_RSVD1)
837#define BP_PXP_LUT_ADDR_ADDR 0
838#define BM_PXP_LUT_ADDR_ADDR 0x00003FFF
839#define BF_PXP_LUT_ADDR_ADDR(v) \
840 (((v) << 0) & BM_PXP_LUT_ADDR_ADDR)
841
842#define HW_PXP_LUT_DATA (0x00000260)
843
844#define BP_PXP_LUT_DATA_DATA 0
845#define BM_PXP_LUT_DATA_DATA 0xFFFFFFFF
846#define BF_PXP_LUT_DATA_DATA(v) (v)
847
848#define HW_PXP_LUT_EXTMEM (0x00000270)
849
850#define BP_PXP_LUT_EXTMEM_ADDR 0
851#define BM_PXP_LUT_EXTMEM_ADDR 0xFFFFFFFF
852#define BF_PXP_LUT_EXTMEM_ADDR(v) (v)
853
854#define HW_PXP_CFA (0x00000280)
855
856#define BP_PXP_CFA_DATA 0
857#define BM_PXP_CFA_DATA 0xFFFFFFFF
858#define BF_PXP_CFA_DATA(v) (v)
859
860#define HW_PXP_ALPHA_A_CTRL (0x00000290)
861
862#define BP_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA 24
863#define BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA 0xFF000000
864#define BF_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA(v) \
865 (((v) << 24) & BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA)
866#define BP_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA 16
867#define BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA 0x00FF0000
868#define BF_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA(v) \
869 (((v) << 16) & BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA)
870#define BP_PXP_ALPHA_A_CTRL_RSVD0 14
871#define BM_PXP_ALPHA_A_CTRL_RSVD0 0x0000C000
872#define BF_PXP_ALPHA_A_CTRL_RSVD0(v) \
873 (((v) << 14) & BM_PXP_ALPHA_A_CTRL_RSVD0)
874#define BM_PXP_ALPHA_A_CTRL_S1_COLOR_MODE 0x00002000
875#define BF_PXP_ALPHA_A_CTRL_S1_COLOR_MODE(v) \
876 (((v) << 13) & BM_PXP_ALPHA_A_CTRL_S1_COLOR_MODE)
877#define BV_PXP_ALPHA_A_CTRL_S1_COLOR_MODE__0 0x0
878#define BV_PXP_ALPHA_A_CTRL_S1_COLOR_MODE__1 0x1
879#define BM_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE 0x00001000
880#define BF_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE(v) \
881 (((v) << 12) & BM_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE)
882#define BV_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE__0 0x0
883#define BV_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE__1 0x1
884#define BP_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE 10
885#define BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE 0x00000C00
886#define BF_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE(v) \
887 (((v) << 10) & BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE)
888#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__0 0x0
889#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__1 0x0
890#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__2 0x0
891#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__3 0x0
892#define BP_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE 8
893#define BM_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE 0x00000300
894#define BF_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE(v) \
895 (((v) << 8) & BM_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE)
896#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__0 0x0
897#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__1 0x1
898#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__2 0x2
899#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__3 0x3
900#define BM_PXP_ALPHA_A_CTRL_RSVD1 0x00000080
901#define BF_PXP_ALPHA_A_CTRL_RSVD1(v) \
902 (((v) << 7) & BM_PXP_ALPHA_A_CTRL_RSVD1)
903#define BM_PXP_ALPHA_A_CTRL_S0_COLOR_MODE 0x00000040
904#define BF_PXP_ALPHA_A_CTRL_S0_COLOR_MODE(v) \
905 (((v) << 6) & BM_PXP_ALPHA_A_CTRL_S0_COLOR_MODE)
906#define BV_PXP_ALPHA_A_CTRL_S0_COLOR_MODE__0 0x0
907#define BV_PXP_ALPHA_A_CTRL_S0_COLOR_MODE__1 0x1
908#define BM_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE 0x00000020
909#define BF_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE(v) \
910 (((v) << 5) & BM_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE)
911#define BV_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE__0 0x0
912#define BV_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE__1 0x1
913#define BP_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE 3
914#define BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE 0x00000018
915#define BF_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE(v) \
916 (((v) << 3) & BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE)
917#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__0 0x0
918#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__1 0x1
919#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__2 0x2
920#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__3 0x3
921#define BP_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE 1
922#define BM_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE 0x00000006
923#define BF_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE(v) \
924 (((v) << 1) & BM_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE)
925#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__0 0x0
926#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__1 0x1
927#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__2 0x2
928#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__3 0x3
929#define BM_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE 0x00000001
930#define BF_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE(v) \
931 (((v) << 0) & BM_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE)
932#define BV_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE__0 0x0
933#define BV_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE__1 0x1
934
935#define HW_PXP_ALPHA_B_CTRL (0x000002a0)
936
937#define BP_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA 24
938#define BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA 0xFF000000
939#define BF_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA(v) \
940 (((v) << 24) & BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA)
941#define BP_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA 16
942#define BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA 0x00FF0000
943#define BF_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA(v) \
944 (((v) << 16) & BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA)
945#define BP_PXP_ALPHA_B_CTRL_RSVD0 14
946#define BM_PXP_ALPHA_B_CTRL_RSVD0 0x0000C000
947#define BF_PXP_ALPHA_B_CTRL_RSVD0(v) \
948 (((v) << 14) & BM_PXP_ALPHA_B_CTRL_RSVD0)
949#define BM_PXP_ALPHA_B_CTRL_S1_COLOR_MODE 0x00002000
950#define BF_PXP_ALPHA_B_CTRL_S1_COLOR_MODE(v) \
951 (((v) << 13) & BM_PXP_ALPHA_B_CTRL_S1_COLOR_MODE)
952#define BV_PXP_ALPHA_B_CTRL_S1_COLOR_MODE__0 0x0
953#define BV_PXP_ALPHA_B_CTRL_S1_COLOR_MODE__1 0x1
954#define BM_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE 0x00001000
955#define BF_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE(v) \
956 (((v) << 12) & BM_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE)
957#define BV_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE__0 0x0
958#define BV_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE__1 0x1
959#define BP_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE 10
960#define BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE 0x00000C00
961#define BF_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE(v) \
962 (((v) << 10) & BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE)
963#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__0 0x0
964#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__1 0x1
965#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__2 0x2
966#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__3 0x3
967#define BP_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE 8
968#define BM_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE 0x00000300
969#define BF_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE(v) \
970 (((v) << 8) & BM_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE)
971#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__0 0x0
972#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__1 0x1
973#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__2 0x2
974#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__3 0x3
975#define BM_PXP_ALPHA_B_CTRL_RSVD1 0x00000080
976#define BF_PXP_ALPHA_B_CTRL_RSVD1(v) \
977 (((v) << 7) & BM_PXP_ALPHA_B_CTRL_RSVD1)
978#define BM_PXP_ALPHA_B_CTRL_S0_COLOR_MODE 0x00000040
979#define BF_PXP_ALPHA_B_CTRL_S0_COLOR_MODE(v) \
980 (((v) << 6) & BM_PXP_ALPHA_B_CTRL_S0_COLOR_MODE)
981#define BV_PXP_ALPHA_B_CTRL_S0_COLOR_MODE__0 0x0
982#define BV_PXP_ALPHA_B_CTRL_S0_COLOR_MODE__1 0x1
983#define BM_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE 0x00000020
984#define BF_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE(v) \
985 (((v) << 5) & BM_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE)
986#define BV_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE__0 0x0
987#define BV_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE__1 0x1
988#define BP_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE 3
989#define BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE 0x00000018
990#define BF_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE(v) \
991 (((v) << 3) & BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE)
992#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__0 0x0
993#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__1 0x1
994#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__2 0x2
995#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__3 0x3
996#define BP_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE 1
997#define BM_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE 0x00000006
998#define BF_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE(v) \
999 (((v) << 1) & BM_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE)
1000#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__0 0x0
1001#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__1 0x1
1002#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__2 0x2
1003#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__3 0x3
1004#define BM_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE 0x00000001
1005#define BF_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE(v) \
1006 (((v) << 0) & BM_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE)
1007#define BV_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE__0 0x0
1008#define BV_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE__1 0x1
1009
1010#define HW_PXP_ALPHA_B_CTRL_1 (0x000002b0)
1011
1012#define BP_PXP_ALPHA_B_CTRL_1_RSVD0 8
1013#define BM_PXP_ALPHA_B_CTRL_1_RSVD0 0xFFFFFF00
1014#define BF_PXP_ALPHA_B_CTRL_1_RSVD0(v) \
1015 (((v) << 8) & BM_PXP_ALPHA_B_CTRL_1_RSVD0)
1016#define BP_PXP_ALPHA_B_CTRL_1_ROP 4
1017#define BM_PXP_ALPHA_B_CTRL_1_ROP 0x000000F0
1018#define BF_PXP_ALPHA_B_CTRL_1_ROP(v) \
1019 (((v) << 4) & BM_PXP_ALPHA_B_CTRL_1_ROP)
1020#define BV_PXP_ALPHA_B_CTRL_1_ROP__MASKAS 0x0
1021#define BV_PXP_ALPHA_B_CTRL_1_ROP__MASKNOTAS 0x1
1022#define BV_PXP_ALPHA_B_CTRL_1_ROP__MASKASNOT 0x2
1023#define BV_PXP_ALPHA_B_CTRL_1_ROP__MERGEAS 0x3
1024#define BV_PXP_ALPHA_B_CTRL_1_ROP__MERGENOTAS 0x4
1025#define BV_PXP_ALPHA_B_CTRL_1_ROP__MERGEASNOT 0x5
1026#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTCOPYAS 0x6
1027#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOT 0x7
1028#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTMASKAS 0x8
1029#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTMERGEAS 0x9
1030#define BV_PXP_ALPHA_B_CTRL_1_ROP__XORAS 0xA
1031#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTXORAS 0xB
1032#define BP_PXP_ALPHA_B_CTRL_1_RSVD1 2
1033#define BM_PXP_ALPHA_B_CTRL_1_RSVD1 0x0000000C
1034#define BF_PXP_ALPHA_B_CTRL_1_RSVD1(v) \
1035 (((v) << 2) & BM_PXP_ALPHA_B_CTRL_1_RSVD1)
1036#define BM_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE 0x00000002
1037#define BF_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE(v) \
1038 (((v) << 1) & BM_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE)
1039#define BM_PXP_ALPHA_B_CTRL_1_ROP_ENABLE 0x00000001
1040#define BF_PXP_ALPHA_B_CTRL_1_ROP_ENABLE(v) \
1041 (((v) << 0) & BM_PXP_ALPHA_B_CTRL_1_ROP_ENABLE)
1042
1043#define HW_PXP_PS_BACKGROUND_1 (0x000002c0)
1044
1045#define BP_PXP_PS_BACKGROUND_1_RSVD 24
1046#define BM_PXP_PS_BACKGROUND_1_RSVD 0xFF000000
1047#define BF_PXP_PS_BACKGROUND_1_RSVD(v) \
1048 (((v) << 24) & BM_PXP_PS_BACKGROUND_1_RSVD)
1049#define BP_PXP_PS_BACKGROUND_1_COLOR 0
1050#define BM_PXP_PS_BACKGROUND_1_COLOR 0x00FFFFFF
1051#define BF_PXP_PS_BACKGROUND_1_COLOR(v) \
1052 (((v) << 0) & BM_PXP_PS_BACKGROUND_1_COLOR)
1053
1054#define HW_PXP_PS_CLRKEYLOW_1 (0x000002d0)
1055
1056#define BP_PXP_PS_CLRKEYLOW_1_RSVD1 24
1057#define BM_PXP_PS_CLRKEYLOW_1_RSVD1 0xFF000000
1058#define BF_PXP_PS_CLRKEYLOW_1_RSVD1(v) \
1059 (((v) << 24) & BM_PXP_PS_CLRKEYLOW_1_RSVD1)
1060#define BP_PXP_PS_CLRKEYLOW_1_PIXEL 0
1061#define BM_PXP_PS_CLRKEYLOW_1_PIXEL 0x00FFFFFF
1062#define BF_PXP_PS_CLRKEYLOW_1_PIXEL(v) \
1063 (((v) << 0) & BM_PXP_PS_CLRKEYLOW_1_PIXEL)
1064
1065#define HW_PXP_PS_CLRKEYHIGH_1 (0x000002e0)
1066
1067#define BP_PXP_PS_CLRKEYHIGH_1_RSVD1 24
1068#define BM_PXP_PS_CLRKEYHIGH_1_RSVD1 0xFF000000
1069#define BF_PXP_PS_CLRKEYHIGH_1_RSVD1(v) \
1070 (((v) << 24) & BM_PXP_PS_CLRKEYHIGH_1_RSVD1)
1071#define BP_PXP_PS_CLRKEYHIGH_1_PIXEL 0
1072#define BM_PXP_PS_CLRKEYHIGH_1_PIXEL 0x00FFFFFF
1073#define BF_PXP_PS_CLRKEYHIGH_1_PIXEL(v) \
1074 (((v) << 0) & BM_PXP_PS_CLRKEYHIGH_1_PIXEL)
1075
1076#define HW_PXP_AS_CLRKEYLOW_1 (0x000002f0)
1077
1078#define BP_PXP_AS_CLRKEYLOW_1_RSVD1 24
1079#define BM_PXP_AS_CLRKEYLOW_1_RSVD1 0xFF000000
1080#define BF_PXP_AS_CLRKEYLOW_1_RSVD1(v) \
1081 (((v) << 24) & BM_PXP_AS_CLRKEYLOW_1_RSVD1)
1082#define BP_PXP_AS_CLRKEYLOW_1_PIXEL 0
1083#define BM_PXP_AS_CLRKEYLOW_1_PIXEL 0x00FFFFFF
1084#define BF_PXP_AS_CLRKEYLOW_1_PIXEL(v) \
1085 (((v) << 0) & BM_PXP_AS_CLRKEYLOW_1_PIXEL)
1086
1087#define HW_PXP_AS_CLRKEYHIGH_1 (0x00000300)
1088
1089#define BP_PXP_AS_CLRKEYHIGH_1_RSVD1 24
1090#define BM_PXP_AS_CLRKEYHIGH_1_RSVD1 0xFF000000
1091#define BF_PXP_AS_CLRKEYHIGH_1_RSVD1(v) \
1092 (((v) << 24) & BM_PXP_AS_CLRKEYHIGH_1_RSVD1)
1093#define BP_PXP_AS_CLRKEYHIGH_1_PIXEL 0
1094#define BM_PXP_AS_CLRKEYHIGH_1_PIXEL 0x00FFFFFF
1095#define BF_PXP_AS_CLRKEYHIGH_1_PIXEL(v) \
1096 (((v) << 0) & BM_PXP_AS_CLRKEYHIGH_1_PIXEL)
1097
1098#define HW_PXP_CTRL2 (0x00000310)
1099#define HW_PXP_CTRL2_SET (0x00000314)
1100#define HW_PXP_CTRL2_CLR (0x00000318)
1101#define HW_PXP_CTRL2_TOG (0x0000031c)
1102
1103#define BP_PXP_CTRL2_RSVD3 28
1104#define BM_PXP_CTRL2_RSVD3 0xF0000000
1105#define BF_PXP_CTRL2_RSVD3(v) \
1106 (((v) << 28) & BM_PXP_CTRL2_RSVD3)
1107#define BM_PXP_CTRL2_ENABLE_ROTATE1 0x08000000
1108#define BF_PXP_CTRL2_ENABLE_ROTATE1(v) \
1109 (((v) << 27) & BM_PXP_CTRL2_ENABLE_ROTATE1)
1110#define BM_PXP_CTRL2_ENABLE_ROTATE0 0x04000000
1111#define BF_PXP_CTRL2_ENABLE_ROTATE0(v) \
1112 (((v) << 26) & BM_PXP_CTRL2_ENABLE_ROTATE0)
1113#define BM_PXP_CTRL2_ENABLE_LUT 0x02000000
1114#define BF_PXP_CTRL2_ENABLE_LUT(v) \
1115 (((v) << 25) & BM_PXP_CTRL2_ENABLE_LUT)
1116#define BM_PXP_CTRL2_ENABLE_CSC2 0x01000000
1117#define BF_PXP_CTRL2_ENABLE_CSC2(v) \
1118 (((v) << 24) & BM_PXP_CTRL2_ENABLE_CSC2)
1119#define BM_PXP_CTRL2_BLOCK_SIZE 0x00800000
1120#define BF_PXP_CTRL2_BLOCK_SIZE(v) \
1121 (((v) << 23) & BM_PXP_CTRL2_BLOCK_SIZE)
1122#define BV_PXP_CTRL2_BLOCK_SIZE__8X8 0x0
1123#define BV_PXP_CTRL2_BLOCK_SIZE__16X16 0x1
1124#define BM_PXP_CTRL2_RSVD2 0x00400000
1125#define BF_PXP_CTRL2_RSVD2(v) \
1126 (((v) << 22) & BM_PXP_CTRL2_RSVD2)
1127#define BM_PXP_CTRL2_ENABLE_ALPHA_B 0x00200000
1128#define BF_PXP_CTRL2_ENABLE_ALPHA_B(v) \
1129 (((v) << 21) & BM_PXP_CTRL2_ENABLE_ALPHA_B)
1130#define BM_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE 0x00100000
1131#define BF_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE(v) \
1132 (((v) << 20) & BM_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE)
1133#define BM_PXP_CTRL2_ENABLE_WFE_B 0x00080000
1134#define BF_PXP_CTRL2_ENABLE_WFE_B(v) \
1135 (((v) << 19) & BM_PXP_CTRL2_ENABLE_WFE_B)
1136#define BM_PXP_CTRL2_ENABLE_WFE_A 0x00040000
1137#define BF_PXP_CTRL2_ENABLE_WFE_A(v) \
1138 (((v) << 18) & BM_PXP_CTRL2_ENABLE_WFE_A)
1139#define BM_PXP_CTRL2_ENABLE_DITHER 0x00020000
1140#define BF_PXP_CTRL2_ENABLE_DITHER(v) \
1141 (((v) << 17) & BM_PXP_CTRL2_ENABLE_DITHER)
1142#define BM_PXP_CTRL2_RSVD1 0x00010000
1143#define BF_PXP_CTRL2_RSVD1(v) \
1144 (((v) << 16) & BM_PXP_CTRL2_RSVD1)
1145#define BM_PXP_CTRL2_VFLIP1 0x00008000
1146#define BF_PXP_CTRL2_VFLIP1(v) \
1147 (((v) << 15) & BM_PXP_CTRL2_VFLIP1)
1148#define BM_PXP_CTRL2_HFLIP1 0x00004000
1149#define BF_PXP_CTRL2_HFLIP1(v) \
1150 (((v) << 14) & BM_PXP_CTRL2_HFLIP1)
1151#define BP_PXP_CTRL2_ROTATE1 12
1152#define BM_PXP_CTRL2_ROTATE1 0x00003000
1153#define BF_PXP_CTRL2_ROTATE1(v) \
1154 (((v) << 12) & BM_PXP_CTRL2_ROTATE1)
1155#define BV_PXP_CTRL2_ROTATE1__ROT_0 0x0
1156#define BV_PXP_CTRL2_ROTATE1__ROT_90 0x1
1157#define BV_PXP_CTRL2_ROTATE1__ROT_180 0x2
1158#define BV_PXP_CTRL2_ROTATE1__ROT_270 0x3
1159#define BM_PXP_CTRL2_VFLIP0 0x00000800
1160#define BF_PXP_CTRL2_VFLIP0(v) \
1161 (((v) << 11) & BM_PXP_CTRL2_VFLIP0)
1162#define BM_PXP_CTRL2_HFLIP0 0x00000400
1163#define BF_PXP_CTRL2_HFLIP0(v) \
1164 (((v) << 10) & BM_PXP_CTRL2_HFLIP0)
1165#define BP_PXP_CTRL2_ROTATE0 8
1166#define BM_PXP_CTRL2_ROTATE0 0x00000300
1167#define BF_PXP_CTRL2_ROTATE0(v) \
1168 (((v) << 8) & BM_PXP_CTRL2_ROTATE0)
1169#define BV_PXP_CTRL2_ROTATE0__ROT_0 0x0
1170#define BV_PXP_CTRL2_ROTATE0__ROT_90 0x1
1171#define BV_PXP_CTRL2_ROTATE0__ROT_180 0x2
1172#define BV_PXP_CTRL2_ROTATE0__ROT_270 0x3
1173#define BP_PXP_CTRL2_RSVD0 1
1174#define BM_PXP_CTRL2_RSVD0 0x000000FE
1175#define BF_PXP_CTRL2_RSVD0(v) \
1176 (((v) << 1) & BM_PXP_CTRL2_RSVD0)
1177#define BM_PXP_CTRL2_ENABLE 0x00000001
1178#define BF_PXP_CTRL2_ENABLE(v) \
1179 (((v) << 0) & BM_PXP_CTRL2_ENABLE)
1180
1181#define HW_PXP_POWER_REG0 (0x00000320)
1182
1183#define BP_PXP_POWER_REG0_CTRL 12
1184#define BM_PXP_POWER_REG0_CTRL 0xFFFFF000
1185#define BF_PXP_POWER_REG0_CTRL(v) \
1186 (((v) << 12) & BM_PXP_POWER_REG0_CTRL)
1187#define BP_PXP_POWER_REG0_ROT0_MEM_LP_STATE 9
1188#define BM_PXP_POWER_REG0_ROT0_MEM_LP_STATE 0x00000E00
1189#define BF_PXP_POWER_REG0_ROT0_MEM_LP_STATE(v) \
1190 (((v) << 9) & BM_PXP_POWER_REG0_ROT0_MEM_LP_STATE)
1191#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__NONE 0x0
1192#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__LS 0x1
1193#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__DS 0x2
1194#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__SD 0x4
1195#define BP_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN 6
1196#define BM_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN 0x000001C0
1197#define BF_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN(v) \
1198 (((v) << 6) & BM_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN)
1199#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__NONE 0x0
1200#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__LS 0x1
1201#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__DS 0x2
1202#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__SD 0x4
1203#define BP_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN 3
1204#define BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN 0x00000038
1205#define BF_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN(v) \
1206 (((v) << 3) & BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN)
1207#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__NONE 0x0
1208#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__LS 0x1
1209#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__DS 0x2
1210#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__SD 0x4
1211#define BP_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0 0
1212#define BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0 0x00000007
1213#define BF_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0(v) \
1214 (((v) << 0) & BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0)
1215#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__NONE 0x0
1216#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__LS 0x1
1217#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__DS 0x2
1218#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__SD 0x4
1219
1220#define HW_PXP_POWER_REG1 (0x00000330)
1221
1222#define BP_PXP_POWER_REG1_RSVD0 24
1223#define BM_PXP_POWER_REG1_RSVD0 0xFF000000
1224#define BF_PXP_POWER_REG1_RSVD0(v) \
1225 (((v) << 24) & BM_PXP_POWER_REG1_RSVD0)
1226#define BP_PXP_POWER_REG1_ALU_B_MEM_LP_STATE 21
1227#define BM_PXP_POWER_REG1_ALU_B_MEM_LP_STATE 0x00E00000
1228#define BF_PXP_POWER_REG1_ALU_B_MEM_LP_STATE(v) \
1229 (((v) << 21) & BM_PXP_POWER_REG1_ALU_B_MEM_LP_STATE)
1230#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__NONE 0x0
1231#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__LS 0x1
1232#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__DS 0x2
1233#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__SD 0x4
1234#define BP_PXP_POWER_REG1_ALU_A_MEM_LP_STATE 18
1235#define BM_PXP_POWER_REG1_ALU_A_MEM_LP_STATE 0x001C0000
1236#define BF_PXP_POWER_REG1_ALU_A_MEM_LP_STATE(v) \
1237 (((v) << 18) & BM_PXP_POWER_REG1_ALU_A_MEM_LP_STATE)
1238#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__NONE 0x0
1239#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__LS 0x1
1240#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__DS 0x2
1241#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__SD 0x4
1242#define BP_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE 15
1243#define BM_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE 0x00038000
1244#define BF_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE(v) \
1245 (((v) << 15) & BM_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE)
1246#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__NONE 0x0
1247#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__LS 0x1
1248#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__DS 0x2
1249#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__SD 0x4
1250#define BP_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE 12
1251#define BM_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE 0x00007000
1252#define BF_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE(v) \
1253 (((v) << 12) & BM_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE)
1254#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__NONE 0x0
1255#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__LS 0x1
1256#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__DS 0x2
1257#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__SD 0x4
1258#define BP_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE 9
1259#define BM_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE 0x00000E00
1260#define BF_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE(v) \
1261 (((v) << 9) & BM_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE)
1262#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__NONE 0x0
1263#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__LS 0x1
1264#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__DS 0x2
1265#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__SD 0x4
1266#define BP_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE 6
1267#define BM_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE 0x000001C0
1268#define BF_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE(v) \
1269 (((v) << 6) & BM_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE)
1270#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__NONE 0x0
1271#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__LS 0x1
1272#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__DS 0x2
1273#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__SD 0x4
1274#define BP_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE 3
1275#define BM_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE 0x00000038
1276#define BF_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE(v) \
1277 (((v) << 3) & BM_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE)
1278#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__NONE 0x0
1279#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__LS 0x1
1280#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__DS 0x2
1281#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__SD 0x4
1282#define BP_PXP_POWER_REG1_ROT1_MEM_LP_STATE 0
1283#define BM_PXP_POWER_REG1_ROT1_MEM_LP_STATE 0x00000007
1284#define BF_PXP_POWER_REG1_ROT1_MEM_LP_STATE(v) \
1285 (((v) << 0) & BM_PXP_POWER_REG1_ROT1_MEM_LP_STATE)
1286#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__NONE 0x0
1287#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__LS 0x1
1288#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__DS 0x2
1289#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__SD 0x4
1290
1291#define HW_PXP_DATA_PATH_CTRL0 (0x00000340)
1292#define HW_PXP_DATA_PATH_CTRL0_SET (0x00000344)
1293#define HW_PXP_DATA_PATH_CTRL0_CLR (0x00000348)
1294#define HW_PXP_DATA_PATH_CTRL0_TOG (0x0000034c)
1295
1296#define BP_PXP_DATA_PATH_CTRL0_MUX15_SEL 30
1297#define BM_PXP_DATA_PATH_CTRL0_MUX15_SEL 0xC0000000
1298#define BF_PXP_DATA_PATH_CTRL0_MUX15_SEL(v) \
1299 (((v) << 30) & BM_PXP_DATA_PATH_CTRL0_MUX15_SEL)
1300#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__0 0x0
1301#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__1 0x1
1302#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__2 0x2
1303#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__3 0x3
1304#define BP_PXP_DATA_PATH_CTRL0_MUX14_SEL 28
1305#define BM_PXP_DATA_PATH_CTRL0_MUX14_SEL 0x30000000
1306#define BF_PXP_DATA_PATH_CTRL0_MUX14_SEL(v) \
1307 (((v) << 28) & BM_PXP_DATA_PATH_CTRL0_MUX14_SEL)
1308#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__0 0x0
1309#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__1 0x1
1310#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__2 0x2
1311#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__3 0x3
1312#define BP_PXP_DATA_PATH_CTRL0_MUX13_SEL 26
1313#define BM_PXP_DATA_PATH_CTRL0_MUX13_SEL 0x0C000000
1314#define BF_PXP_DATA_PATH_CTRL0_MUX13_SEL(v) \
1315 (((v) << 26) & BM_PXP_DATA_PATH_CTRL0_MUX13_SEL)
1316#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__0 0x0
1317#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__1 0x1
1318#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__2 0x2
1319#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__3 0x3
1320#define BP_PXP_DATA_PATH_CTRL0_MUX12_SEL 24
1321#define BM_PXP_DATA_PATH_CTRL0_MUX12_SEL 0x03000000
1322#define BF_PXP_DATA_PATH_CTRL0_MUX12_SEL(v) \
1323 (((v) << 24) & BM_PXP_DATA_PATH_CTRL0_MUX12_SEL)
1324#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__0 0x0
1325#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__1 0x1
1326#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__2 0x2
1327#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__3 0x3
1328#define BP_PXP_DATA_PATH_CTRL0_MUX11_SEL 22
1329#define BM_PXP_DATA_PATH_CTRL0_MUX11_SEL 0x00C00000
1330#define BF_PXP_DATA_PATH_CTRL0_MUX11_SEL(v) \
1331 (((v) << 22) & BM_PXP_DATA_PATH_CTRL0_MUX11_SEL)
1332#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__0 0x0
1333#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__1 0x1
1334#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__2 0x2
1335#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__3 0x3
1336#define BP_PXP_DATA_PATH_CTRL0_MUX10_SEL 20
1337#define BM_PXP_DATA_PATH_CTRL0_MUX10_SEL 0x00300000
1338#define BF_PXP_DATA_PATH_CTRL0_MUX10_SEL(v) \
1339 (((v) << 20) & BM_PXP_DATA_PATH_CTRL0_MUX10_SEL)
1340#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__0 0x0
1341#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__1 0x1
1342#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__2 0x2
1343#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__3 0x3
1344#define BP_PXP_DATA_PATH_CTRL0_MUX9_SEL 18
1345#define BM_PXP_DATA_PATH_CTRL0_MUX9_SEL 0x000C0000
1346#define BF_PXP_DATA_PATH_CTRL0_MUX9_SEL(v) \
1347 (((v) << 18) & BM_PXP_DATA_PATH_CTRL0_MUX9_SEL)
1348#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__0 0x0
1349#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__1 0x1
1350#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__2 0x2
1351#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__3 0x3
1352#define BP_PXP_DATA_PATH_CTRL0_MUX8_SEL 16
1353#define BM_PXP_DATA_PATH_CTRL0_MUX8_SEL 0x00030000
1354#define BF_PXP_DATA_PATH_CTRL0_MUX8_SEL(v) \
1355 (((v) << 16) & BM_PXP_DATA_PATH_CTRL0_MUX8_SEL)
1356#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__0 0x0
1357#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__1 0x1
1358#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__2 0x2
1359#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__3 0x3
1360#define BP_PXP_DATA_PATH_CTRL0_MUX7_SEL 14
1361#define BM_PXP_DATA_PATH_CTRL0_MUX7_SEL 0x0000C000
1362#define BF_PXP_DATA_PATH_CTRL0_MUX7_SEL(v) \
1363 (((v) << 14) & BM_PXP_DATA_PATH_CTRL0_MUX7_SEL)
1364#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__0 0x0
1365#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__1 0x1
1366#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__2 0x2
1367#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__3 0x3
1368#define BP_PXP_DATA_PATH_CTRL0_MUX6_SEL 12
1369#define BM_PXP_DATA_PATH_CTRL0_MUX6_SEL 0x00003000
1370#define BF_PXP_DATA_PATH_CTRL0_MUX6_SEL(v) \
1371 (((v) << 12) & BM_PXP_DATA_PATH_CTRL0_MUX6_SEL)
1372#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__0 0x0
1373#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__1 0x1
1374#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__2 0x2
1375#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__3 0x3
1376#define BP_PXP_DATA_PATH_CTRL0_MUX5_SEL 10
1377#define BM_PXP_DATA_PATH_CTRL0_MUX5_SEL 0x00000C00
1378#define BF_PXP_DATA_PATH_CTRL0_MUX5_SEL(v) \
1379 (((v) << 10) & BM_PXP_DATA_PATH_CTRL0_MUX5_SEL)
1380#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__0 0x0
1381#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__1 0x1
1382#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__2 0x2
1383#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__3 0x3
1384#define BP_PXP_DATA_PATH_CTRL0_MUX4_SEL 8
1385#define BM_PXP_DATA_PATH_CTRL0_MUX4_SEL 0x00000300
1386#define BF_PXP_DATA_PATH_CTRL0_MUX4_SEL(v) \
1387 (((v) << 8) & BM_PXP_DATA_PATH_CTRL0_MUX4_SEL)
1388#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__0 0x0
1389#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__1 0x1
1390#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__2 0x2
1391#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__3 0x3
1392#define BP_PXP_DATA_PATH_CTRL0_MUX3_SEL 6
1393#define BM_PXP_DATA_PATH_CTRL0_MUX3_SEL 0x000000C0
1394#define BF_PXP_DATA_PATH_CTRL0_MUX3_SEL(v) \
1395 (((v) << 6) & BM_PXP_DATA_PATH_CTRL0_MUX3_SEL)
1396#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__0 0x0
1397#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__1 0x1
1398#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__2 0x2
1399#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__3 0x3
1400#define BP_PXP_DATA_PATH_CTRL0_MUX2_SEL 4
1401#define BM_PXP_DATA_PATH_CTRL0_MUX2_SEL 0x00000030
1402#define BF_PXP_DATA_PATH_CTRL0_MUX2_SEL(v) \
1403 (((v) << 4) & BM_PXP_DATA_PATH_CTRL0_MUX2_SEL)
1404#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__0 0x0
1405#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__1 0x1
1406#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__2 0x2
1407#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__3 0x3
1408#define BP_PXP_DATA_PATH_CTRL0_MUX1_SEL 2
1409#define BM_PXP_DATA_PATH_CTRL0_MUX1_SEL 0x0000000C
1410#define BF_PXP_DATA_PATH_CTRL0_MUX1_SEL(v) \
1411 (((v) << 2) & BM_PXP_DATA_PATH_CTRL0_MUX1_SEL)
1412#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__0 0x0
1413#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__1 0x1
1414#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__2 0x2
1415#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__3 0x3
1416#define BP_PXP_DATA_PATH_CTRL0_MUX0_SEL 0
1417#define BM_PXP_DATA_PATH_CTRL0_MUX0_SEL 0x00000003
1418#define BF_PXP_DATA_PATH_CTRL0_MUX0_SEL(v) \
1419 (((v) << 0) & BM_PXP_DATA_PATH_CTRL0_MUX0_SEL)
1420#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__0 0x0
1421#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__1 0x1
1422#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__2 0x2
1423#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__3 0x3
1424
1425#define HW_PXP_DATA_PATH_CTRL1 (0x00000350)
1426#define HW_PXP_DATA_PATH_CTRL1_SET (0x00000354)
1427#define HW_PXP_DATA_PATH_CTRL1_CLR (0x00000358)
1428#define HW_PXP_DATA_PATH_CTRL1_TOG (0x0000035c)
1429
1430#define BP_PXP_DATA_PATH_CTRL1_RSVD0 4
1431#define BM_PXP_DATA_PATH_CTRL1_RSVD0 0xFFFFFFF0
1432#define BF_PXP_DATA_PATH_CTRL1_RSVD0(v) \
1433 (((v) << 4) & BM_PXP_DATA_PATH_CTRL1_RSVD0)
1434#define BP_PXP_DATA_PATH_CTRL1_MUX17_SEL 2
1435#define BM_PXP_DATA_PATH_CTRL1_MUX17_SEL 0x0000000C
1436#define BF_PXP_DATA_PATH_CTRL1_MUX17_SEL(v) \
1437 (((v) << 2) & BM_PXP_DATA_PATH_CTRL1_MUX17_SEL)
1438#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__0 0x0
1439#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__1 0x1
1440#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__2 0x2
1441#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__3 0x3
1442#define BP_PXP_DATA_PATH_CTRL1_MUX16_SEL 0
1443#define BM_PXP_DATA_PATH_CTRL1_MUX16_SEL 0x00000003
1444#define BF_PXP_DATA_PATH_CTRL1_MUX16_SEL(v) \
1445 (((v) << 0) & BM_PXP_DATA_PATH_CTRL1_MUX16_SEL)
1446#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__0 0x0
1447#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__1 0x1
1448#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__2 0x2
1449#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__3 0x3
1450
1451#define HW_PXP_INIT_MEM_CTRL (0x00000360)
1452#define HW_PXP_INIT_MEM_CTRL_SET (0x00000364)
1453#define HW_PXP_INIT_MEM_CTRL_CLR (0x00000368)
1454#define HW_PXP_INIT_MEM_CTRL_TOG (0x0000036c)
1455
1456#define BM_PXP_INIT_MEM_CTRL_START 0x80000000
1457#define BF_PXP_INIT_MEM_CTRL_START(v) \
1458 (((v) << 31) & BM_PXP_INIT_MEM_CTRL_START)
1459#define BP_PXP_INIT_MEM_CTRL_SELECT 27
1460#define BM_PXP_INIT_MEM_CTRL_SELECT 0x78000000
1461#define BF_PXP_INIT_MEM_CTRL_SELECT(v) \
1462 (((v) << 27) & BM_PXP_INIT_MEM_CTRL_SELECT)
1463#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_LUT 0x0
1464#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_ERR0 0x1
1465#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_ERR1 0x2
1466#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER1_LUT 0x3
1467#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER2_LUT 0x4
1468#define BV_PXP_INIT_MEM_CTRL_SELECT__ALU_A 0x5
1469#define BV_PXP_INIT_MEM_CTRL_SELECT__ALU_B 0x6
1470#define BV_PXP_INIT_MEM_CTRL_SELECT__WFE_A_FETCH 0x7
1471#define BV_PXP_INIT_MEM_CTRL_SELECT__WFE_B_FETCH 0x8
1472#define BV_PXP_INIT_MEM_CTRL_SELECT__RESERVED 0x15
1473#define BP_PXP_INIT_MEM_CTRL_RSVD0 16
1474#define BM_PXP_INIT_MEM_CTRL_RSVD0 0x07FF0000
1475#define BF_PXP_INIT_MEM_CTRL_RSVD0(v) \
1476 (((v) << 16) & BM_PXP_INIT_MEM_CTRL_RSVD0)
1477#define BP_PXP_INIT_MEM_CTRL_ADDR 0
1478#define BM_PXP_INIT_MEM_CTRL_ADDR 0x0000FFFF
1479#define BF_PXP_INIT_MEM_CTRL_ADDR(v) \
1480 (((v) << 0) & BM_PXP_INIT_MEM_CTRL_ADDR)
1481
1482#define HW_PXP_INIT_MEM_DATA (0x00000370)
1483
1484#define BP_PXP_INIT_MEM_DATA_DATA 0
1485#define BM_PXP_INIT_MEM_DATA_DATA 0xFFFFFFFF
1486#define BF_PXP_INIT_MEM_DATA_DATA(v) (v)
1487
1488#define HW_PXP_INIT_MEM_DATA_HIGH (0x00000380)
1489
1490#define BP_PXP_INIT_MEM_DATA_HIGH_DATA 0
1491#define BM_PXP_INIT_MEM_DATA_HIGH_DATA 0xFFFFFFFF
1492#define BF_PXP_INIT_MEM_DATA_HIGH_DATA(v) (v)
1493
1494#define HW_PXP_IRQ_MASK (0x00000390)
1495#define HW_PXP_IRQ_MASK_SET (0x00000394)
1496#define HW_PXP_IRQ_MASK_CLR (0x00000398)
1497#define HW_PXP_IRQ_MASK_TOG (0x0000039c)
1498
1499#define BM_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN 0x80000000
1500#define BF_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN(v) \
1501 (((v) << 31) & BM_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN)
1502#define BP_PXP_IRQ_MASK_RSVD1 16
1503#define BM_PXP_IRQ_MASK_RSVD1 0x7FFF0000
1504#define BF_PXP_IRQ_MASK_RSVD1(v) \
1505 (((v) << 16) & BM_PXP_IRQ_MASK_RSVD1)
1506#define BM_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN 0x00008000
1507#define BF_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN(v) \
1508 (((v) << 15) & BM_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN)
1509#define BM_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN 0x00004000
1510#define BF_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN(v) \
1511 (((v) << 14) & BM_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN)
1512#define BM_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN 0x00002000
1513#define BF_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN(v) \
1514 (((v) << 13) & BM_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN)
1515#define BM_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN 0x00001000
1516#define BF_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN(v) \
1517 (((v) << 12) & BM_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN)
1518#define BM_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN 0x00000800
1519#define BF_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN(v) \
1520 (((v) << 11) & BM_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN)
1521#define BM_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN 0x00000400
1522#define BF_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN(v) \
1523 (((v) << 10) & BM_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN)
1524#define BM_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN 0x00000200
1525#define BF_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN(v) \
1526 (((v) << 9) & BM_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN)
1527#define BM_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN 0x00000100
1528#define BF_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN(v) \
1529 (((v) << 8) & BM_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN)
1530#define BM_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN 0x00000080
1531#define BF_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN(v) \
1532 (((v) << 7) & BM_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN)
1533#define BM_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN 0x00000040
1534#define BF_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN(v) \
1535 (((v) << 6) & BM_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN)
1536#define BM_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN 0x00000020
1537#define BF_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN(v) \
1538 (((v) << 5) & BM_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN)
1539#define BM_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN 0x00000010
1540#define BF_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN(v) \
1541 (((v) << 4) & BM_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN)
1542#define BM_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN 0x00000008
1543#define BF_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN(v) \
1544 (((v) << 3) & BM_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN)
1545#define BM_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN 0x00000004
1546#define BF_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN(v) \
1547 (((v) << 2) & BM_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN)
1548#define BM_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN 0x00000002
1549#define BF_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN(v) \
1550 (((v) << 1) & BM_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN)
1551#define BM_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN 0x00000001
1552#define BF_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN(v) \
1553 (((v) << 0) & BM_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN)
1554
1555#define HW_PXP_IRQ (0x000003a0)
1556#define HW_PXP_IRQ_SET (0x000003a4)
1557#define HW_PXP_IRQ_CLR (0x000003a8)
1558#define HW_PXP_IRQ_TOG (0x000003ac)
1559
1560#define BM_PXP_IRQ_COMPRESS_DONE_IRQ 0x80000000
1561#define BF_PXP_IRQ_COMPRESS_DONE_IRQ(v) \
1562 (((v) << 31) & BM_PXP_IRQ_COMPRESS_DONE_IRQ)
1563#define BP_PXP_IRQ_RSVD1 16
1564#define BM_PXP_IRQ_RSVD1 0x7FFF0000
1565#define BF_PXP_IRQ_RSVD1(v) \
1566 (((v) << 16) & BM_PXP_IRQ_RSVD1)
1567#define BM_PXP_IRQ_WFE_B_STORE_IRQ 0x00008000
1568#define BF_PXP_IRQ_WFE_B_STORE_IRQ(v) \
1569 (((v) << 15) & BM_PXP_IRQ_WFE_B_STORE_IRQ)
1570#define BM_PXP_IRQ_WFE_A_STORE_IRQ 0x00004000
1571#define BF_PXP_IRQ_WFE_A_STORE_IRQ(v) \
1572 (((v) << 14) & BM_PXP_IRQ_WFE_A_STORE_IRQ)
1573#define BM_PXP_IRQ_DITHER_STORE_IRQ 0x00002000
1574#define BF_PXP_IRQ_DITHER_STORE_IRQ(v) \
1575 (((v) << 13) & BM_PXP_IRQ_DITHER_STORE_IRQ)
1576#define BM_PXP_IRQ_FIRST_STORE_IRQ 0x00001000
1577#define BF_PXP_IRQ_FIRST_STORE_IRQ(v) \
1578 (((v) << 12) & BM_PXP_IRQ_FIRST_STORE_IRQ)
1579#define BM_PXP_IRQ_WFE_B_CH1_STORE_IRQ 0x00000800
1580#define BF_PXP_IRQ_WFE_B_CH1_STORE_IRQ(v) \
1581 (((v) << 11) & BM_PXP_IRQ_WFE_B_CH1_STORE_IRQ)
1582#define BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ 0x00000400
1583#define BF_PXP_IRQ_WFE_B_CH0_STORE_IRQ(v) \
1584 (((v) << 10) & BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ)
1585#define BM_PXP_IRQ_WFE_A_CH1_STORE_IRQ 0x00000200
1586#define BF_PXP_IRQ_WFE_A_CH1_STORE_IRQ(v) \
1587 (((v) << 9) & BM_PXP_IRQ_WFE_A_CH1_STORE_IRQ)
1588#define BM_PXP_IRQ_WFE_A_CH0_STORE_IRQ 0x00000100
1589#define BF_PXP_IRQ_WFE_A_CH0_STORE_IRQ(v) \
1590 (((v) << 8) & BM_PXP_IRQ_WFE_A_CH0_STORE_IRQ)
1591#define BM_PXP_IRQ_DITHER_CH1_STORE_IRQ 0x00000080
1592#define BF_PXP_IRQ_DITHER_CH1_STORE_IRQ(v) \
1593 (((v) << 7) & BM_PXP_IRQ_DITHER_CH1_STORE_IRQ)
1594#define BM_PXP_IRQ_DITHER_CH0_STORE_IRQ 0x00000040
1595#define BF_PXP_IRQ_DITHER_CH0_STORE_IRQ(v) \
1596 (((v) << 6) & BM_PXP_IRQ_DITHER_CH0_STORE_IRQ)
1597#define BM_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ 0x00000020
1598#define BF_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ(v) \
1599 (((v) << 5) & BM_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ)
1600#define BM_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ 0x00000010
1601#define BF_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ(v) \
1602 (((v) << 4) & BM_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ)
1603#define BM_PXP_IRQ_FIRST_CH1_STORE_IRQ 0x00000008
1604#define BF_PXP_IRQ_FIRST_CH1_STORE_IRQ(v) \
1605 (((v) << 3) & BM_PXP_IRQ_FIRST_CH1_STORE_IRQ)
1606#define BM_PXP_IRQ_FIRST_CH0_STORE_IRQ 0x00000004
1607#define BF_PXP_IRQ_FIRST_CH0_STORE_IRQ(v) \
1608 (((v) << 2) & BM_PXP_IRQ_FIRST_CH0_STORE_IRQ)
1609#define BM_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ 0x00000002
1610#define BF_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ(v) \
1611 (((v) << 1) & BM_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ)
1612#define BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ 0x00000001
1613#define BF_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ(v) \
1614 (((v) << 0) & BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ)
1615
1616#define HW_PXP_NEXT (0x00000400)
1617
1618#define BP_PXP_NEXT_POINTER 2
1619#define BM_PXP_NEXT_POINTER 0xFFFFFFFC
1620#define BF_PXP_NEXT_POINTER(v) \
1621 (((v) << 2) & BM_PXP_NEXT_POINTER)
1622#define BM_PXP_NEXT_RSVD 0x00000002
1623#define BF_PXP_NEXT_RSVD(v) \
1624 (((v) << 1) & BM_PXP_NEXT_RSVD)
1625#define BM_PXP_NEXT_ENABLED 0x00000001
1626#define BF_PXP_NEXT_ENABLED(v) \
1627 (((v) << 0) & BM_PXP_NEXT_ENABLED)
1628
1629#define HW_PXP_DEBUGCTRL (0x00000410)
1630
1631#define BP_PXP_DEBUGCTRL_RSVD 12
1632#define BM_PXP_DEBUGCTRL_RSVD 0xFFFFF000
1633#define BF_PXP_DEBUGCTRL_RSVD(v) \
1634 (((v) << 12) & BM_PXP_DEBUGCTRL_RSVD)
1635#define BP_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 8
1636#define BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 0x00000F00
1637#define BF_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT(v) \
1638 (((v) << 8) & BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT)
1639#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__NONE 0x0
1640#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MISS_CNT 0x1
1641#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__HIT_CNT 0x2
1642#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__LAT_CNT 0x4
1643#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MAX_LAT 0x8
1644#define BP_PXP_DEBUGCTRL_SELECT 0
1645#define BM_PXP_DEBUGCTRL_SELECT 0x000000FF
1646#define BF_PXP_DEBUGCTRL_SELECT(v) \
1647 (((v) << 0) & BM_PXP_DEBUGCTRL_SELECT)
1648#define BV_PXP_DEBUGCTRL_SELECT__NONE 0x0
1649#define BV_PXP_DEBUGCTRL_SELECT__CTRL 0x1
1650#define BV_PXP_DEBUGCTRL_SELECT__PSBUF 0x2
1651#define BV_PXP_DEBUGCTRL_SELECT__PSBAX 0x3
1652#define BV_PXP_DEBUGCTRL_SELECT__PSBAY 0x4
1653#define BV_PXP_DEBUGCTRL_SELECT__ASBUF 0x5
1654#define BV_PXP_DEBUGCTRL_SELECT__ROTATION 0x6
1655#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF0 0x7
1656#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF1 0x8
1657#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF2 0x9
1658#define BV_PXP_DEBUGCTRL_SELECT__LUT_STAT 0x10
1659#define BV_PXP_DEBUGCTRL_SELECT__LUT_MISS 0x11
1660#define BV_PXP_DEBUGCTRL_SELECT__LUT_HIT 0x12
1661#define BV_PXP_DEBUGCTRL_SELECT__LUT_LAT 0x13
1662#define BV_PXP_DEBUGCTRL_SELECT__LUT_MAX_LAT 0x14
1663
1664#define HW_PXP_DEBUG (0x00000420)
1665
1666#define BP_PXP_DEBUG_DATA 0
1667#define BM_PXP_DEBUG_DATA 0xFFFFFFFF
1668#define BF_PXP_DEBUG_DATA(v) (v)
1669
1670#define HW_PXP_VERSION (0x00000430)
1671
1672#define BP_PXP_VERSION_MAJOR 24
1673#define BM_PXP_VERSION_MAJOR 0xFF000000
1674#define BF_PXP_VERSION_MAJOR(v) \
1675 (((v) << 24) & BM_PXP_VERSION_MAJOR)
1676#define BP_PXP_VERSION_MINOR 16
1677#define BM_PXP_VERSION_MINOR 0x00FF0000
1678#define BF_PXP_VERSION_MINOR(v) \
1679 (((v) << 16) & BM_PXP_VERSION_MINOR)
1680#define BP_PXP_VERSION_STEP 0
1681#define BM_PXP_VERSION_STEP 0x0000FFFF
1682#define BF_PXP_VERSION_STEP(v) \
1683 (((v) << 0) & BM_PXP_VERSION_STEP)
1684
1685#endif /* __IMX_PXP_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-30 07:01:53 -0400